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radeon/r200/r300: cleanup some of the renderbuffer code
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
36 */
37
38 #include <errno.h>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
44
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #include "radeon_common.h"
50 #include "radeon_span.h"
51 #if !RADEON_COMMON
52 #include "radeon_context.h"
53 #include "radeon_tex.h"
54 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
55 #include "r200_context.h"
56 #include "r200_ioctl.h"
57 #include "r200_tex.h"
58 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
59 #include "r300_context.h"
60 #include "r300_fragprog.h"
61 #include "r300_tex.h"
62 #endif
63
64 #include "utils.h"
65 #include "vblank.h"
66 #include "drirenderbuffer.h"
67
68 #include "radeon_bocs_wrapper.h"
69
70 #include "GL/internal/dri_interface.h"
71
72 /* Radeon configuration
73 */
74 #include "xmlpool.h"
75
76 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
77 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
78 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
79 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
80 DRI_CONF_OPT_END
81
82 #if !RADEON_COMMON /* R100 */
83 PUBLIC const char __driConfigOptions[] =
84 DRI_CONF_BEGIN
85 DRI_CONF_SECTION_PERFORMANCE
86 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
87 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
88 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
89 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
90 DRI_CONF_HYPERZ(false)
91 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
92 DRI_CONF_SECTION_END
93 DRI_CONF_SECTION_QUALITY
94 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
95 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
96 DRI_CONF_NO_NEG_LOD_BIAS(false)
97 DRI_CONF_FORCE_S3TC_ENABLE(false)
98 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
99 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
100 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
101 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
102 DRI_CONF_SECTION_END
103 DRI_CONF_SECTION_DEBUG
104 DRI_CONF_NO_RAST(false)
105 DRI_CONF_SECTION_END
106 DRI_CONF_END;
107 static const GLuint __driNConfigOptions = 15;
108
109 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
110
111 PUBLIC const char __driConfigOptions[] =
112 DRI_CONF_BEGIN
113 DRI_CONF_SECTION_PERFORMANCE
114 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
115 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
116 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
117 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
118 DRI_CONF_HYPERZ(false)
119 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
120 DRI_CONF_SECTION_END
121 DRI_CONF_SECTION_QUALITY
122 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
123 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
124 DRI_CONF_NO_NEG_LOD_BIAS(false)
125 DRI_CONF_FORCE_S3TC_ENABLE(false)
126 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
127 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
128 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
129 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
130 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
131 DRI_CONF_SECTION_END
132 DRI_CONF_SECTION_DEBUG
133 DRI_CONF_NO_RAST(false)
134 DRI_CONF_SECTION_END
135 DRI_CONF_SECTION_SOFTWARE
136 DRI_CONF_NV_VERTEX_PROGRAM(false)
137 DRI_CONF_SECTION_END
138 DRI_CONF_END;
139 static const GLuint __driNConfigOptions = 17;
140
141 extern const struct dri_extension blend_extensions[];
142 extern const struct dri_extension ARB_vp_extension[];
143 extern const struct dri_extension NV_vp_extension[];
144 extern const struct dri_extension ATI_fs_extension[];
145 extern const struct dri_extension point_extensions[];
146
147 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
148
149 /* TODO: integrate these into xmlpool.h! */
150 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
151 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
152 DRI_CONF_DESC(en,"Number of texture image units") \
153 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
154 DRI_CONF_OPT_END
155
156 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
157 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
158 DRI_CONF_DESC(en,"Number of texture coordinate units") \
159 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
160 DRI_CONF_OPT_END
161
162
163
164 #define DRI_CONF_DISABLE_S3TC(def) \
165 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
166 DRI_CONF_DESC(en,"Disable S3TC compression") \
167 DRI_CONF_OPT_END
168
169 #define DRI_CONF_DISABLE_FALLBACK(def) \
170 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
171 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
172 DRI_CONF_OPT_END
173
174 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
175 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
176 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
177 DRI_CONF_OPT_END
178
179 #define DRI_CONF_FP_OPTIMIZATION(def) \
180 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
181 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
182 DRI_CONF_ENUM(0,"Optimize for Speed") \
183 DRI_CONF_ENUM(1,"Optimize for Quality") \
184 DRI_CONF_DESC_END \
185 DRI_CONF_OPT_END
186
187 PUBLIC const char __driConfigOptions[] =
188 DRI_CONF_BEGIN
189 DRI_CONF_SECTION_PERFORMANCE
190 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
191 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
192 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
193 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
194 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
195 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
196 DRI_CONF_DISABLE_FALLBACK(true)
197 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
198 DRI_CONF_SECTION_END
199 DRI_CONF_SECTION_QUALITY
200 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
201 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
202 DRI_CONF_FORCE_S3TC_ENABLE(false)
203 DRI_CONF_DISABLE_S3TC(false)
204 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
205 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
206 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
207 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
208 DRI_CONF_SECTION_END
209 DRI_CONF_SECTION_DEBUG
210 DRI_CONF_NO_RAST(false)
211 DRI_CONF_SECTION_END
212 DRI_CONF_END;
213 static const GLuint __driNConfigOptions = 17;
214
215 extern const struct dri_extension gl_20_extension[];
216
217 #ifndef RADEON_DEBUG
218
219 static const struct dri_debug_control debug_control[] = {
220 {"fall", DEBUG_FALLBACKS},
221 {"tex", DEBUG_TEXTURE},
222 {"ioctl", DEBUG_IOCTL},
223 {"prim", DEBUG_PRIMS},
224 {"vert", DEBUG_VERTS},
225 {"state", DEBUG_STATE},
226 {"code", DEBUG_CODEGEN},
227 {"vfmt", DEBUG_VFMT},
228 {"vtxf", DEBUG_VFMT},
229 {"verb", DEBUG_VERBOSE},
230 {"dri", DEBUG_DRI},
231 {"dma", DEBUG_DMA},
232 {"san", DEBUG_SANITY},
233 {"sync", DEBUG_SYNC},
234 {"pix", DEBUG_PIXEL},
235 {"mem", DEBUG_MEMORY},
236 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
237 {NULL, 0}
238 };
239 #endif /* RADEON_DEBUG */
240
241 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
242
243 extern const struct dri_extension card_extensions[];
244
245 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
246
247 static int
248 radeonGetParam(int fd, int param, void *value)
249 {
250 int ret;
251 drm_radeon_getparam_t gp;
252
253 gp.param = param;
254 gp.value = value;
255
256 ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
257 return ret;
258 }
259
260 static const __DRIconfig **
261 radeonFillInModes( __DRIscreenPrivate *psp,
262 unsigned pixel_bits, unsigned depth_bits,
263 unsigned stencil_bits, GLboolean have_back_buffer )
264 {
265 __DRIconfig **configs;
266 __GLcontextModes *m;
267 unsigned depth_buffer_factor;
268 unsigned back_buffer_factor;
269 GLenum fb_format;
270 GLenum fb_type;
271 int i;
272
273 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
274 * enough to add support. Basically, if a context is created with an
275 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
276 * will never be used.
277 */
278 static const GLenum back_buffer_modes[] = {
279 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
280 };
281
282 uint8_t depth_bits_array[2];
283 uint8_t stencil_bits_array[2];
284 uint8_t msaa_samples_array[1];
285
286 depth_bits_array[0] = depth_bits;
287 depth_bits_array[1] = depth_bits;
288
289 /* Just like with the accumulation buffer, always provide some modes
290 * with a stencil buffer. It will be a sw fallback, but some apps won't
291 * care about that.
292 */
293 stencil_bits_array[0] = 0;
294 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
295
296 msaa_samples_array[0] = 0;
297
298 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
299 back_buffer_factor = (have_back_buffer) ? 2 : 1;
300
301 if ( pixel_bits == 16 ) {
302 fb_format = GL_RGB;
303 fb_type = GL_UNSIGNED_SHORT_5_6_5;
304 }
305 else {
306 fb_format = GL_BGRA;
307 fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
308 }
309
310 configs = driCreateConfigs(fb_format, fb_type,
311 depth_bits_array, stencil_bits_array,
312 depth_buffer_factor,
313 back_buffer_modes, back_buffer_factor,
314 msaa_samples_array, 1);
315 if (configs == NULL) {
316 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
317 __func__, __LINE__ );
318 return NULL;
319 }
320
321 /* Mark the visual as slow if there are "fake" stencil bits.
322 */
323 for (i = 0; configs[i]; i++) {
324 m = &configs[i]->modes;
325 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
326 m->visualRating = GLX_SLOW_CONFIG;
327 }
328 }
329
330 return (const __DRIconfig **) configs;
331 }
332
333 #if !RADEON_COMMON
334 static const __DRItexOffsetExtension radeonTexOffsetExtension = {
335 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
336 radeonSetTexOffset,
337 };
338
339 static const __DRItexBufferExtension radeonTexBufferExtension = {
340 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
341 radeonSetTexBuffer,
342 };
343 #endif
344
345 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
346 static const __DRIallocateExtension r200AllocateExtension = {
347 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
348 r200AllocateMemoryMESA,
349 r200FreeMemoryMESA,
350 r200GetMemoryOffsetMESA
351 };
352
353 static const __DRItexOffsetExtension r200texOffsetExtension = {
354 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
355 r200SetTexOffset,
356 };
357
358 static const __DRItexBufferExtension r200TexBufferExtension = {
359 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
360 r200SetTexBuffer,
361 };
362 #endif
363
364 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
365 static const __DRItexOffsetExtension r300texOffsetExtension = {
366 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
367 r300SetTexOffset,
368 };
369
370 static const __DRItexBufferExtension r300TexBufferExtension = {
371 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
372 r300SetTexBuffer,
373 };
374 #endif
375
376 static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
377 {
378 screen->chip_flags = 0;
379 switch ( device_id ) {
380 case PCI_CHIP_RADEON_LY:
381 case PCI_CHIP_RADEON_LZ:
382 case PCI_CHIP_RADEON_QY:
383 case PCI_CHIP_RADEON_QZ:
384 case PCI_CHIP_RN50_515E:
385 case PCI_CHIP_RN50_5969:
386 screen->chip_family = CHIP_FAMILY_RV100;
387 break;
388
389 case PCI_CHIP_RS100_4136:
390 case PCI_CHIP_RS100_4336:
391 screen->chip_family = CHIP_FAMILY_RS100;
392 break;
393
394 case PCI_CHIP_RS200_4137:
395 case PCI_CHIP_RS200_4337:
396 case PCI_CHIP_RS250_4237:
397 case PCI_CHIP_RS250_4437:
398 screen->chip_family = CHIP_FAMILY_RS200;
399 break;
400
401 case PCI_CHIP_RADEON_QD:
402 case PCI_CHIP_RADEON_QE:
403 case PCI_CHIP_RADEON_QF:
404 case PCI_CHIP_RADEON_QG:
405 /* all original radeons (7200) presumably have a stencil op bug */
406 screen->chip_family = CHIP_FAMILY_R100;
407 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
408 break;
409
410 case PCI_CHIP_RV200_QW:
411 case PCI_CHIP_RV200_QX:
412 case PCI_CHIP_RADEON_LW:
413 case PCI_CHIP_RADEON_LX:
414 screen->chip_family = CHIP_FAMILY_RV200;
415 screen->chip_flags = RADEON_CHIPSET_TCL;
416 break;
417
418 case PCI_CHIP_R200_BB:
419 case PCI_CHIP_R200_BC:
420 case PCI_CHIP_R200_QH:
421 case PCI_CHIP_R200_QL:
422 case PCI_CHIP_R200_QM:
423 screen->chip_family = CHIP_FAMILY_R200;
424 screen->chip_flags = RADEON_CHIPSET_TCL;
425 break;
426
427 case PCI_CHIP_RV250_If:
428 case PCI_CHIP_RV250_Ig:
429 case PCI_CHIP_RV250_Ld:
430 case PCI_CHIP_RV250_Lf:
431 case PCI_CHIP_RV250_Lg:
432 screen->chip_family = CHIP_FAMILY_RV250;
433 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
434 break;
435
436 case PCI_CHIP_RV280_5960:
437 case PCI_CHIP_RV280_5961:
438 case PCI_CHIP_RV280_5962:
439 case PCI_CHIP_RV280_5964:
440 case PCI_CHIP_RV280_5965:
441 case PCI_CHIP_RV280_5C61:
442 case PCI_CHIP_RV280_5C63:
443 screen->chip_family = CHIP_FAMILY_RV280;
444 screen->chip_flags = RADEON_CHIPSET_TCL;
445 break;
446
447 case PCI_CHIP_RS300_5834:
448 case PCI_CHIP_RS300_5835:
449 case PCI_CHIP_RS350_7834:
450 case PCI_CHIP_RS350_7835:
451 screen->chip_family = CHIP_FAMILY_RS300;
452 break;
453
454 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
455 case PCI_CHIP_R300_AD:
456 screen->chip_family = CHIP_FAMILY_RV350;
457 screen->chip_flags = RADEON_CHIPSET_TCL;
458 break;
459 case PCI_CHIP_R300_AE:
460 case PCI_CHIP_R300_AF:
461 case PCI_CHIP_R300_AG:
462 case PCI_CHIP_R300_ND:
463 case PCI_CHIP_R300_NE:
464 case PCI_CHIP_R300_NF:
465 case PCI_CHIP_R300_NG:
466 screen->chip_family = CHIP_FAMILY_R300;
467 screen->chip_flags = RADEON_CHIPSET_TCL;
468 break;
469
470 case PCI_CHIP_RV350_AP:
471 case PCI_CHIP_RV350_AQ:
472 case PCI_CHIP_RV350_AR:
473 case PCI_CHIP_RV350_AS:
474 case PCI_CHIP_RV350_AT:
475 case PCI_CHIP_RV350_AV:
476 case PCI_CHIP_RV350_AU:
477 case PCI_CHIP_RV350_NP:
478 case PCI_CHIP_RV350_NQ:
479 case PCI_CHIP_RV350_NR:
480 case PCI_CHIP_RV350_NS:
481 case PCI_CHIP_RV350_NT:
482 case PCI_CHIP_RV350_NV:
483 screen->chip_family = CHIP_FAMILY_RV350;
484 screen->chip_flags = RADEON_CHIPSET_TCL;
485 break;
486
487 case PCI_CHIP_R350_AH:
488 case PCI_CHIP_R350_AI:
489 case PCI_CHIP_R350_AJ:
490 case PCI_CHIP_R350_AK:
491 case PCI_CHIP_R350_NH:
492 case PCI_CHIP_R350_NI:
493 case PCI_CHIP_R360_NJ:
494 case PCI_CHIP_R350_NK:
495 screen->chip_family = CHIP_FAMILY_R350;
496 screen->chip_flags = RADEON_CHIPSET_TCL;
497 break;
498
499 case PCI_CHIP_RV370_5460:
500 case PCI_CHIP_RV370_5462:
501 case PCI_CHIP_RV370_5464:
502 case PCI_CHIP_RV370_5B60:
503 case PCI_CHIP_RV370_5B62:
504 case PCI_CHIP_RV370_5B63:
505 case PCI_CHIP_RV370_5B64:
506 case PCI_CHIP_RV370_5B65:
507 case PCI_CHIP_RV380_3150:
508 case PCI_CHIP_RV380_3152:
509 case PCI_CHIP_RV380_3154:
510 case PCI_CHIP_RV380_3E50:
511 case PCI_CHIP_RV380_3E54:
512 screen->chip_family = CHIP_FAMILY_RV380;
513 screen->chip_flags = RADEON_CHIPSET_TCL;
514 break;
515
516 case PCI_CHIP_R420_JN:
517 case PCI_CHIP_R420_JH:
518 case PCI_CHIP_R420_JI:
519 case PCI_CHIP_R420_JJ:
520 case PCI_CHIP_R420_JK:
521 case PCI_CHIP_R420_JL:
522 case PCI_CHIP_R420_JM:
523 case PCI_CHIP_R420_JO:
524 case PCI_CHIP_R420_JP:
525 case PCI_CHIP_R420_JT:
526 case PCI_CHIP_R481_4B49:
527 case PCI_CHIP_R481_4B4A:
528 case PCI_CHIP_R481_4B4B:
529 case PCI_CHIP_R481_4B4C:
530 case PCI_CHIP_R423_UH:
531 case PCI_CHIP_R423_UI:
532 case PCI_CHIP_R423_UJ:
533 case PCI_CHIP_R423_UK:
534 case PCI_CHIP_R430_554C:
535 case PCI_CHIP_R430_554D:
536 case PCI_CHIP_R430_554E:
537 case PCI_CHIP_R430_554F:
538 case PCI_CHIP_R423_5550:
539 case PCI_CHIP_R423_UQ:
540 case PCI_CHIP_R423_UR:
541 case PCI_CHIP_R423_UT:
542 case PCI_CHIP_R430_5D48:
543 case PCI_CHIP_R430_5D49:
544 case PCI_CHIP_R430_5D4A:
545 case PCI_CHIP_R480_5D4C:
546 case PCI_CHIP_R480_5D4D:
547 case PCI_CHIP_R480_5D4E:
548 case PCI_CHIP_R480_5D4F:
549 case PCI_CHIP_R480_5D50:
550 case PCI_CHIP_R480_5D52:
551 case PCI_CHIP_R423_5D57:
552 screen->chip_family = CHIP_FAMILY_R420;
553 screen->chip_flags = RADEON_CHIPSET_TCL;
554 break;
555
556 case PCI_CHIP_RV410_5E4C:
557 case PCI_CHIP_RV410_5E4F:
558 case PCI_CHIP_RV410_564A:
559 case PCI_CHIP_RV410_564B:
560 case PCI_CHIP_RV410_564F:
561 case PCI_CHIP_RV410_5652:
562 case PCI_CHIP_RV410_5653:
563 case PCI_CHIP_RV410_5657:
564 case PCI_CHIP_RV410_5E48:
565 case PCI_CHIP_RV410_5E4A:
566 case PCI_CHIP_RV410_5E4B:
567 case PCI_CHIP_RV410_5E4D:
568 screen->chip_family = CHIP_FAMILY_RV410;
569 screen->chip_flags = RADEON_CHIPSET_TCL;
570 break;
571
572 case PCI_CHIP_RS480_5954:
573 case PCI_CHIP_RS480_5955:
574 case PCI_CHIP_RS482_5974:
575 case PCI_CHIP_RS482_5975:
576 case PCI_CHIP_RS400_5A41:
577 case PCI_CHIP_RS400_5A42:
578 case PCI_CHIP_RC410_5A61:
579 case PCI_CHIP_RC410_5A62:
580 screen->chip_family = CHIP_FAMILY_RS400;
581 break;
582
583 case PCI_CHIP_RS600_793F:
584 case PCI_CHIP_RS600_7941:
585 case PCI_CHIP_RS600_7942:
586 screen->chip_family = CHIP_FAMILY_RS600;
587 break;
588
589 case PCI_CHIP_RS690_791E:
590 case PCI_CHIP_RS690_791F:
591 screen->chip_family = CHIP_FAMILY_RS690;
592 break;
593 case PCI_CHIP_RS740_796C:
594 case PCI_CHIP_RS740_796D:
595 case PCI_CHIP_RS740_796E:
596 case PCI_CHIP_RS740_796F:
597 screen->chip_family = CHIP_FAMILY_RS740;
598 break;
599
600 case PCI_CHIP_R520_7100:
601 case PCI_CHIP_R520_7101:
602 case PCI_CHIP_R520_7102:
603 case PCI_CHIP_R520_7103:
604 case PCI_CHIP_R520_7104:
605 case PCI_CHIP_R520_7105:
606 case PCI_CHIP_R520_7106:
607 case PCI_CHIP_R520_7108:
608 case PCI_CHIP_R520_7109:
609 case PCI_CHIP_R520_710A:
610 case PCI_CHIP_R520_710B:
611 case PCI_CHIP_R520_710C:
612 case PCI_CHIP_R520_710E:
613 case PCI_CHIP_R520_710F:
614 screen->chip_family = CHIP_FAMILY_R520;
615 screen->chip_flags = RADEON_CHIPSET_TCL;
616 break;
617
618 case PCI_CHIP_RV515_7140:
619 case PCI_CHIP_RV515_7141:
620 case PCI_CHIP_RV515_7142:
621 case PCI_CHIP_RV515_7143:
622 case PCI_CHIP_RV515_7144:
623 case PCI_CHIP_RV515_7145:
624 case PCI_CHIP_RV515_7146:
625 case PCI_CHIP_RV515_7147:
626 case PCI_CHIP_RV515_7149:
627 case PCI_CHIP_RV515_714A:
628 case PCI_CHIP_RV515_714B:
629 case PCI_CHIP_RV515_714C:
630 case PCI_CHIP_RV515_714D:
631 case PCI_CHIP_RV515_714E:
632 case PCI_CHIP_RV515_714F:
633 case PCI_CHIP_RV515_7151:
634 case PCI_CHIP_RV515_7152:
635 case PCI_CHIP_RV515_7153:
636 case PCI_CHIP_RV515_715E:
637 case PCI_CHIP_RV515_715F:
638 case PCI_CHIP_RV515_7180:
639 case PCI_CHIP_RV515_7181:
640 case PCI_CHIP_RV515_7183:
641 case PCI_CHIP_RV515_7186:
642 case PCI_CHIP_RV515_7187:
643 case PCI_CHIP_RV515_7188:
644 case PCI_CHIP_RV515_718A:
645 case PCI_CHIP_RV515_718B:
646 case PCI_CHIP_RV515_718C:
647 case PCI_CHIP_RV515_718D:
648 case PCI_CHIP_RV515_718F:
649 case PCI_CHIP_RV515_7193:
650 case PCI_CHIP_RV515_7196:
651 case PCI_CHIP_RV515_719B:
652 case PCI_CHIP_RV515_719F:
653 case PCI_CHIP_RV515_7200:
654 case PCI_CHIP_RV515_7210:
655 case PCI_CHIP_RV515_7211:
656 screen->chip_family = CHIP_FAMILY_RV515;
657 screen->chip_flags = RADEON_CHIPSET_TCL;
658 break;
659
660 case PCI_CHIP_RV530_71C0:
661 case PCI_CHIP_RV530_71C1:
662 case PCI_CHIP_RV530_71C2:
663 case PCI_CHIP_RV530_71C3:
664 case PCI_CHIP_RV530_71C4:
665 case PCI_CHIP_RV530_71C5:
666 case PCI_CHIP_RV530_71C6:
667 case PCI_CHIP_RV530_71C7:
668 case PCI_CHIP_RV530_71CD:
669 case PCI_CHIP_RV530_71CE:
670 case PCI_CHIP_RV530_71D2:
671 case PCI_CHIP_RV530_71D4:
672 case PCI_CHIP_RV530_71D5:
673 case PCI_CHIP_RV530_71D6:
674 case PCI_CHIP_RV530_71DA:
675 case PCI_CHIP_RV530_71DE:
676 screen->chip_family = CHIP_FAMILY_RV530;
677 screen->chip_flags = RADEON_CHIPSET_TCL;
678 break;
679
680 case PCI_CHIP_R580_7240:
681 case PCI_CHIP_R580_7243:
682 case PCI_CHIP_R580_7244:
683 case PCI_CHIP_R580_7245:
684 case PCI_CHIP_R580_7246:
685 case PCI_CHIP_R580_7247:
686 case PCI_CHIP_R580_7248:
687 case PCI_CHIP_R580_7249:
688 case PCI_CHIP_R580_724A:
689 case PCI_CHIP_R580_724B:
690 case PCI_CHIP_R580_724C:
691 case PCI_CHIP_R580_724D:
692 case PCI_CHIP_R580_724E:
693 case PCI_CHIP_R580_724F:
694 case PCI_CHIP_R580_7284:
695 screen->chip_family = CHIP_FAMILY_R580;
696 screen->chip_flags = RADEON_CHIPSET_TCL;
697 break;
698
699 case PCI_CHIP_RV570_7280:
700 case PCI_CHIP_RV560_7281:
701 case PCI_CHIP_RV560_7283:
702 case PCI_CHIP_RV560_7287:
703 case PCI_CHIP_RV570_7288:
704 case PCI_CHIP_RV570_7289:
705 case PCI_CHIP_RV570_728B:
706 case PCI_CHIP_RV570_728C:
707 case PCI_CHIP_RV560_7290:
708 case PCI_CHIP_RV560_7291:
709 case PCI_CHIP_RV560_7293:
710 case PCI_CHIP_RV560_7297:
711 screen->chip_family = CHIP_FAMILY_RV560;
712 screen->chip_flags = RADEON_CHIPSET_TCL;
713 break;
714
715 default:
716 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
717 device_id);
718 return -1;
719 }
720
721 return 0;
722 }
723
724
725 /* Create the device specific screen private data struct.
726 */
727 static radeonScreenPtr
728 radeonCreateScreen( __DRIscreenPrivate *sPriv )
729 {
730 radeonScreenPtr screen;
731 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
732 unsigned char *RADEONMMIO = NULL;
733 int i;
734 int ret;
735 uint32_t temp;
736
737 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
738 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
739 return GL_FALSE;
740 }
741
742 /* Allocate the private area */
743 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
744 if ( !screen ) {
745 __driUtilMessage("%s: Could not allocate memory for screen structure",
746 __FUNCTION__);
747 return NULL;
748 }
749
750 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
751 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
752 #endif
753
754 /* parse information in __driConfigOptions */
755 driParseOptionInfo (&screen->optionCache,
756 __driConfigOptions, __driNConfigOptions);
757
758 /* This is first since which regions we map depends on whether or
759 * not we are using a PCI card.
760 */
761 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
762 {
763 int ret;
764
765 #ifdef RADEON_PARAM_KERNEL_MM
766 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_KERNEL_MM,
767 &screen->kernel_mm);
768
769 if (ret && ret != -EINVAL) {
770 FREE( screen );
771 fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret);
772 return NULL;
773 }
774
775 if (ret == -EINVAL)
776 screen->kernel_mm = 0;
777 #endif
778
779 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET,
780 &screen->gart_buffer_offset);
781
782 if (ret) {
783 FREE( screen );
784 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
785 return NULL;
786 }
787
788 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE,
789 &screen->gart_base);
790 if (ret) {
791 FREE( screen );
792 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
793 return NULL;
794 }
795
796 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
797 &screen->irq);
798 if (ret) {
799 FREE( screen );
800 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
801 return NULL;
802 }
803 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
804 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
805 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
806 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
807 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
808 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
809 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
810 }
811
812 if (!screen->kernel_mm) {
813 screen->mmio.handle = dri_priv->registerHandle;
814 screen->mmio.size = dri_priv->registerSize;
815 if ( drmMap( sPriv->fd,
816 screen->mmio.handle,
817 screen->mmio.size,
818 &screen->mmio.map ) ) {
819 FREE( screen );
820 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
821 return NULL;
822 }
823
824 RADEONMMIO = screen->mmio.map;
825
826 screen->status.handle = dri_priv->statusHandle;
827 screen->status.size = dri_priv->statusSize;
828 if ( drmMap( sPriv->fd,
829 screen->status.handle,
830 screen->status.size,
831 &screen->status.map ) ) {
832 drmUnmap( screen->mmio.map, screen->mmio.size );
833 FREE( screen );
834 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
835 return NULL;
836 }
837 screen->scratch = (__volatile__ uint32_t *)
838 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
839
840 screen->buffers = drmMapBufs( sPriv->fd );
841 if ( !screen->buffers ) {
842 drmUnmap( screen->status.map, screen->status.size );
843 drmUnmap( screen->mmio.map, screen->mmio.size );
844 FREE( screen );
845 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
846 return NULL;
847 }
848
849 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
850 screen->gartTextures.handle = dri_priv->gartTexHandle;
851 screen->gartTextures.size = dri_priv->gartTexMapSize;
852 if ( drmMap( sPriv->fd,
853 screen->gartTextures.handle,
854 screen->gartTextures.size,
855 (drmAddressPtr)&screen->gartTextures.map ) ) {
856 drmUnmapBufs( screen->buffers );
857 drmUnmap( screen->status.map, screen->status.size );
858 drmUnmap( screen->mmio.map, screen->mmio.size );
859 FREE( screen );
860 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
861 return NULL;
862 }
863
864 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
865 }
866 }
867
868
869 ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
870 if (ret == -1)
871 return NULL;
872
873 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
874 sPriv->ddx_version.minor < 2) {
875 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
876 return NULL;
877 }
878
879 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
880 fprintf(stderr, "R500 support requires a newer drm.\n");
881 return NULL;
882 }
883
884 if (getenv("R300_NO_TCL"))
885 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
886
887 if (screen->chip_family <= CHIP_FAMILY_RS200)
888 screen->chip_flags |= RADEON_CLASS_R100;
889 else if (screen->chip_family <= CHIP_FAMILY_RV280)
890 screen->chip_flags |= RADEON_CLASS_R200;
891 else
892 screen->chip_flags |= RADEON_CLASS_R300;
893
894 screen->cpp = dri_priv->bpp / 8;
895 screen->AGPMode = dri_priv->AGPMode;
896
897 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION,
898 &temp);
899 if (ret) {
900 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm)
901 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
902 else {
903 FREE( screen );
904 fprintf(stderr, "Unable to get fb location need newer drm\n");
905 return NULL;
906 }
907 } else {
908 screen->fbLocation = (temp & 0xffff) << 16;
909 }
910
911 if (screen->chip_family >= CHIP_FAMILY_R300) {
912 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES,
913 &temp);
914 if (ret) {
915 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
916 switch (screen->chip_family) {
917 case CHIP_FAMILY_R300:
918 case CHIP_FAMILY_R350:
919 screen->num_gb_pipes = 2;
920 break;
921 case CHIP_FAMILY_R420:
922 case CHIP_FAMILY_R520:
923 case CHIP_FAMILY_R580:
924 case CHIP_FAMILY_RV560:
925 case CHIP_FAMILY_RV570:
926 screen->num_gb_pipes = 4;
927 break;
928 case CHIP_FAMILY_RV350:
929 case CHIP_FAMILY_RV515:
930 case CHIP_FAMILY_RV530:
931 case CHIP_FAMILY_RV410:
932 default:
933 screen->num_gb_pipes = 1;
934 break;
935 }
936 } else {
937 screen->num_gb_pipes = temp;
938 }
939 }
940
941 if ( sPriv->drm_version.minor >= 10 ) {
942 drm_radeon_setparam_t sp;
943
944 sp.param = RADEON_SETPARAM_FB_LOCATION;
945 sp.value = screen->fbLocation;
946
947 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
948 &sp, sizeof( sp ) );
949 }
950
951 screen->frontOffset = dri_priv->frontOffset;
952 screen->frontPitch = dri_priv->frontPitch;
953 screen->backOffset = dri_priv->backOffset;
954 screen->backPitch = dri_priv->backPitch;
955 screen->depthOffset = dri_priv->depthOffset;
956 screen->depthPitch = dri_priv->depthPitch;
957
958 /* Check if ddx has set up a surface reg to cover depth buffer */
959 screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
960 /* these chips don't use tiled z without hyperz. So always pretend
961 we have set up a surface which will cause linear reads/writes */
962 (IS_R100_CLASS(screen) &&
963 !(screen->chip_flags & RADEON_CHIPSET_TCL));
964
965 if ( dri_priv->textureSize == 0 ) {
966 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
967 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
968 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
969 dri_priv->log2GARTTexGran;
970 } else {
971 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
972 + screen->fbLocation;
973 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
974 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
975 dri_priv->log2TexGran;
976 }
977
978 if ( !screen->gartTextures.map || dri_priv->textureSize == 0
979 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
980 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
981 screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
982 screen->texSize[RADEON_GART_TEX_HEAP] = 0;
983 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
984 } else {
985 screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
986 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
987 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
988 screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
989 dri_priv->log2GARTTexGran;
990 }
991
992 i = 0;
993 screen->extensions[i++] = &driCopySubBufferExtension.base;
994 screen->extensions[i++] = &driFrameTrackingExtension.base;
995 screen->extensions[i++] = &driReadDrawableExtension;
996
997 if ( screen->irq != 0 ) {
998 screen->extensions[i++] = &driSwapControlExtension.base;
999 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1000 }
1001
1002 if (!screen->kernel_mm) {
1003 #if !RADEON_COMMON
1004 screen->extensions[i++] = &radeonTexOffsetExtension.base;
1005 #endif
1006
1007 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1008 if (IS_R200_CLASS(screen))
1009 screen->extensions[i++] = &r200AllocateExtension.base;
1010
1011 screen->extensions[i++] = &r200texOffsetExtension.base;
1012 #endif
1013
1014 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1015 screen->extensions[i++] = &r300texOffsetExtension.base;
1016 #endif
1017 }
1018
1019 screen->extensions[i++] = NULL;
1020 sPriv->extensions = screen->extensions;
1021
1022 screen->driScreen = sPriv;
1023 screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
1024 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
1025 screen->sarea_priv_offset);
1026
1027 if (screen->kernel_mm)
1028 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1029 else
1030 screen->bom = radeon_bo_manager_legacy_ctor(screen);
1031 if (screen->bom == NULL) {
1032 free(screen);
1033 return NULL;
1034 }
1035
1036 return screen;
1037 }
1038
1039 static radeonScreenPtr
1040 radeonCreateScreen2(__DRIscreenPrivate *sPriv)
1041 {
1042 radeonScreenPtr screen;
1043 int i;
1044 int ret;
1045 uint32_t device_id;
1046
1047 /* Allocate the private area */
1048 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1049 if ( !screen ) {
1050 __driUtilMessage("%s: Could not allocate memory for screen structure",
1051 __FUNCTION__);
1052 fprintf(stderr, "leaving here\n");
1053 return NULL;
1054 }
1055
1056 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1057 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
1058 #endif
1059
1060 /* parse information in __driConfigOptions */
1061 driParseOptionInfo (&screen->optionCache,
1062 __driConfigOptions, __driNConfigOptions);
1063
1064 screen->kernel_mm = 1;
1065 screen->chip_flags = 0;
1066
1067 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
1068 &screen->irq);
1069
1070 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_DEVICE_ID,
1071 &device_id);
1072 if (ret) {
1073 FREE( screen );
1074 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret);
1075 return NULL;
1076 }
1077
1078 ret = radeon_set_screen_flags(screen, device_id);
1079 if (ret == -1)
1080 return NULL;
1081
1082 if (screen->chip_family <= CHIP_FAMILY_RS200)
1083 screen->chip_flags |= RADEON_CLASS_R100;
1084 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1085 screen->chip_flags |= RADEON_CLASS_R200;
1086 else
1087 screen->chip_flags |= RADEON_CLASS_R300;
1088
1089 i = 0;
1090 screen->extensions[i++] = &driCopySubBufferExtension.base;
1091 screen->extensions[i++] = &driFrameTrackingExtension.base;
1092 screen->extensions[i++] = &driReadDrawableExtension;
1093
1094 if ( screen->irq != 0 ) {
1095 screen->extensions[i++] = &driSwapControlExtension.base;
1096 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1097 }
1098
1099 #if !RADEON_COMMON
1100 screen->extensions[i++] = &radeonTexBufferExtension.base;
1101 #endif
1102
1103 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1104 if (IS_R200_CLASS(screen))
1105 screen->extensions[i++] = &r200AllocateExtension.base;
1106
1107 screen->extensions[i++] = &r200TexBufferExtension.base;
1108 #endif
1109
1110 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1111 screen->extensions[i++] = &r300TexBufferExtension.base;
1112 #endif
1113
1114 screen->extensions[i++] = NULL;
1115 sPriv->extensions = screen->extensions;
1116
1117 screen->driScreen = sPriv;
1118 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1119 if (screen->bom == NULL) {
1120 free(screen);
1121 return NULL;
1122 }
1123 return screen;
1124 }
1125
1126 /* Destroy the device specific screen private data struct.
1127 */
1128 static void
1129 radeonDestroyScreen( __DRIscreenPrivate *sPriv )
1130 {
1131 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1132
1133 if (!screen)
1134 return;
1135
1136 if (screen->kernel_mm) {
1137 #ifdef RADEON_BO_TRACK
1138 radeon_tracker_print(&screen->bom->tracker, stderr);
1139 #endif
1140 radeon_bo_manager_gem_dtor(screen->bom);
1141 } else {
1142 radeon_bo_manager_legacy_dtor(screen->bom);
1143
1144 if ( screen->gartTextures.map ) {
1145 drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
1146 }
1147 drmUnmapBufs( screen->buffers );
1148 drmUnmap( screen->status.map, screen->status.size );
1149 drmUnmap( screen->mmio.map, screen->mmio.size );
1150 }
1151
1152 /* free all option information */
1153 driDestroyOptionInfo (&screen->optionCache);
1154
1155 FREE( screen );
1156 sPriv->private = NULL;
1157 }
1158
1159
1160 /* Initialize the driver specific screen private data.
1161 */
1162 static GLboolean
1163 radeonInitDriver( __DRIscreenPrivate *sPriv )
1164 {
1165 if (sPriv->dri2.enabled) {
1166 sPriv->private = (void *) radeonCreateScreen2( sPriv );
1167 } else {
1168 sPriv->private = (void *) radeonCreateScreen( sPriv );
1169 }
1170 if ( !sPriv->private ) {
1171 radeonDestroyScreen( sPriv );
1172 return GL_FALSE;
1173 }
1174
1175 return GL_TRUE;
1176 }
1177
1178 static GLboolean
1179 radeon_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb,
1180 GLenum intFormat, GLuint w, GLuint h)
1181 {
1182 rb->Width = w;
1183 rb->Height = h;
1184 rb->_ActualFormat = intFormat;
1185
1186 return GL_TRUE;
1187 }
1188
1189
1190 static struct radeon_renderbuffer *
1191 radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv)
1192 {
1193 struct radeon_renderbuffer *ret;
1194
1195 ret = CALLOC_STRUCT(radeon_renderbuffer);
1196 if (!ret)
1197 return NULL;
1198
1199 _mesa_init_renderbuffer(&ret->base, 0);
1200 ret->base.ClassID = RADEON_RB_CLASS;
1201
1202 /* XXX format junk */
1203 switch (format) {
1204 case GL_RGB5:
1205 ret->base._ActualFormat = GL_RGB5;
1206 ret->base._BaseFormat = GL_RGBA;
1207 ret->base.RedBits = 5;
1208 ret->base.GreenBits = 6;
1209 ret->base.BlueBits = 5;
1210 ret->base.DataType = GL_UNSIGNED_BYTE;
1211 break;
1212 case GL_RGBA8:
1213 ret->base._ActualFormat = GL_RGBA8;
1214 ret->base._BaseFormat = GL_RGBA;
1215 ret->base.RedBits = 8;
1216 ret->base.GreenBits = 8;
1217 ret->base.BlueBits = 8;
1218 ret->base.AlphaBits = 8;
1219 ret->base.DataType = GL_UNSIGNED_BYTE;
1220 break;
1221 case GL_STENCIL_INDEX8_EXT:
1222 ret->base._ActualFormat = GL_STENCIL_INDEX8_EXT;
1223 ret->base._BaseFormat = GL_STENCIL_INDEX;
1224 ret->base.StencilBits = 8;
1225 ret->base.DataType = GL_UNSIGNED_BYTE;
1226 break;
1227 case GL_DEPTH_COMPONENT16:
1228 ret->base._ActualFormat = GL_DEPTH_COMPONENT16;
1229 ret->base._BaseFormat = GL_DEPTH_COMPONENT;
1230 ret->base.DepthBits = 16;
1231 ret->base.DataType = GL_UNSIGNED_SHORT;
1232 break;
1233 case GL_DEPTH_COMPONENT24:
1234 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT;
1235 ret->base._BaseFormat = GL_DEPTH_COMPONENT;
1236 ret->base.DepthBits = 24;
1237 ret->base.DataType = GL_UNSIGNED_INT;
1238 break;
1239 case GL_DEPTH24_STENCIL8_EXT:
1240 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT;
1241 ret->base._BaseFormat = GL_DEPTH_STENCIL_EXT;
1242 ret->base.DepthBits = 24;
1243 ret->base.StencilBits = 8;
1244 ret->base.DataType = GL_UNSIGNED_INT_24_8_EXT;
1245 break;
1246 default:
1247 fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format);
1248 _mesa_delete_renderbuffer(&ret->base);
1249 return NULL;
1250 }
1251
1252 ret->dPriv = driDrawPriv;
1253 ret->base.InternalFormat = format;
1254
1255 ret->base.AllocStorage = radeon_alloc_window_storage;
1256
1257 radeonSetSpanFunctions(ret);
1258
1259 ret->bo = NULL;
1260 return ret;
1261 }
1262
1263 /**
1264 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1265 *
1266 * \todo This function (and its interface) will need to be updated to support
1267 * pbuffers.
1268 */
1269 static GLboolean
1270 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
1271 __DRIdrawablePrivate *driDrawPriv,
1272 const __GLcontextModes *mesaVis,
1273 GLboolean isPixmap )
1274 {
1275 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1276
1277 const GLboolean swDepth = GL_FALSE;
1278 const GLboolean swAlpha = GL_FALSE;
1279 const GLboolean swAccum = mesaVis->accumRedBits > 0;
1280 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1281 mesaVis->depthBits != 24;
1282 GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8);
1283 GLenum depthFormat = GL_NONE;
1284 struct radeon_framebuffer *rfb;
1285
1286 if (isPixmap)
1287 return GL_FALSE; /* not implemented */
1288
1289 rfb = CALLOC_STRUCT(radeon_framebuffer);
1290 if (!rfb)
1291 return GL_FALSE;
1292
1293 _mesa_initialize_framebuffer(&rfb->base, mesaVis);
1294
1295 if (mesaVis->depthBits == 16)
1296 depthFormat = GL_DEPTH_COMPONENT16;
1297 else if (mesaVis->depthBits == 24)
1298 depthFormat = GL_DEPTH_COMPONENT24;
1299
1300 /* front color renderbuffer */
1301 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1302 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base);
1303 rfb->color_rb[0]->has_surface = 1;
1304
1305 /* back color renderbuffer */
1306 if (mesaVis->doubleBufferMode) {
1307 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1308 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base);
1309 rfb->color_rb[1]->has_surface = 1;
1310 }
1311
1312 /* depth renderbuffer */
1313 if (depthFormat != GL_NONE) {
1314 struct radeon_renderbuffer *depth =
1315 radeon_create_renderbuffer(depthFormat, driDrawPriv);
1316 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1317 depth->has_surface = screen->depthHasSurface;
1318 }
1319
1320 /* stencil renderbuffer */
1321 if (mesaVis->stencilBits > 0 && !swStencil) {
1322 struct radeon_renderbuffer *stencil =
1323 radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv);
1324 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &stencil->base);
1325 stencil->has_surface = screen->depthHasSurface;
1326 }
1327
1328 _mesa_add_soft_renderbuffers(&rfb->base,
1329 GL_FALSE, /* color */
1330 swDepth,
1331 swStencil,
1332 swAccum,
1333 swAlpha,
1334 GL_FALSE /* aux */);
1335 driDrawPriv->driverPrivate = (void *) rfb;
1336
1337 return (driDrawPriv->driverPrivate != NULL);
1338 }
1339
1340 static void
1341 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
1342 {
1343 struct radeon_renderbuffer *rb;
1344 struct radeon_framebuffer *rfb;
1345
1346 rfb = (void*)driDrawPriv->driverPrivate;
1347 rb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
1348 if (rb && rb->bo) {
1349 radeon_bo_unref(rb->bo);
1350 rb->bo = NULL;
1351 }
1352 rb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
1353 if (rb && rb->bo) {
1354 radeon_bo_unref(rb->bo);
1355 rb->bo = NULL;
1356 }
1357 rb = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer;
1358 if (rb && rb->bo) {
1359 radeon_bo_unref(rb->bo);
1360 rb->bo = NULL;
1361 }
1362 _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)));
1363 }
1364
1365 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1366 /**
1367 * Choose the appropriate CreateContext function based on the chipset.
1368 * Eventually, all drivers will go through this process.
1369 */
1370 static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
1371 __DRIcontextPrivate * driContextPriv,
1372 void *sharedContextPriv)
1373 {
1374 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
1375 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
1376
1377 if (IS_R300_CLASS(screen))
1378 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
1379 return GL_FALSE;
1380 }
1381
1382 /**
1383 * Choose the appropriate DestroyContext function based on the chipset.
1384 */
1385 static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
1386 {
1387 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
1388
1389 if (IS_R300_CLASS(radeon->radeonScreen))
1390 return r300DestroyContext(driContextPriv);
1391 }
1392
1393
1394 #endif
1395
1396
1397 /**
1398 * This is the driver specific part of the createNewScreen entry point.
1399 *
1400 * \todo maybe fold this into intelInitDriver
1401 *
1402 * \return the __GLcontextModes supported by this driver
1403 */
1404 static const __DRIconfig **
1405 radeonInitScreen(__DRIscreenPrivate *psp)
1406 {
1407 #if !RADEON_COMMON
1408 static const char *driver_name = "Radeon";
1409 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1410 static const __DRIversion dri_expected = { 4, 0, 0 };
1411 static const __DRIversion drm_expected = { 1, 6, 0 };
1412 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1413 static const char *driver_name = "R200";
1414 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1415 static const __DRIversion dri_expected = { 4, 0, 0 };
1416 static const __DRIversion drm_expected = { 1, 6, 0 };
1417 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1418 static const char *driver_name = "R300";
1419 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1420 static const __DRIversion dri_expected = { 4, 0, 0 };
1421 static const __DRIversion drm_expected = { 1, 24, 0 };
1422 #endif
1423 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1424
1425 if ( ! driCheckDriDdxDrmVersions3( driver_name,
1426 &psp->dri_version, & dri_expected,
1427 &psp->ddx_version, & ddx_expected,
1428 &psp->drm_version, & drm_expected ) ) {
1429 return NULL;
1430 }
1431
1432 /* Calling driInitExtensions here, with a NULL context pointer,
1433 * does not actually enable the extensions. It just makes sure
1434 * that all the dispatch offsets for all the extensions that
1435 * *might* be enables are known. This is needed because the
1436 * dispatch offsets need to be known when _mesa_context_create
1437 * is called, but we can't enable the extensions until we have a
1438 * context pointer.
1439 *
1440 * Hello chicken. Hello egg. How are you two today?
1441 */
1442 driInitExtensions( NULL, card_extensions, GL_FALSE );
1443 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1444 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1445 driInitSingleExtension( NULL, ARB_vp_extension );
1446 driInitSingleExtension( NULL, NV_vp_extension );
1447 driInitSingleExtension( NULL, ATI_fs_extension );
1448 driInitExtensions( NULL, point_extensions, GL_FALSE );
1449 #elif defined(RADEON_COMMON_FOR_R300)
1450 driInitSingleExtension( NULL, gl_20_extension );
1451 #endif
1452
1453 if (!radeonInitDriver(psp))
1454 return NULL;
1455
1456 /* for now fill in all modes */
1457 return radeonFillInModes( psp,
1458 dri_priv->bpp,
1459 (dri_priv->bpp == 16) ? 16 : 24,
1460 (dri_priv->bpp == 16) ? 0 : 8, 1);
1461 }
1462 #define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
1463
1464 /**
1465 * This is the driver specific part of the createNewScreen entry point.
1466 * Called when using DRI2.
1467 *
1468 * \return the __GLcontextModes supported by this driver
1469 */
1470 static const
1471 __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp)
1472 {
1473 GLenum fb_format[3];
1474 GLenum fb_type[3];
1475 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
1476 * support pageflipping at all.
1477 */
1478 static const GLenum back_buffer_modes[] = {
1479 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/
1480 };
1481 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
1482 int color;
1483 __DRIconfig **configs = NULL;
1484
1485 /* Calling driInitExtensions here, with a NULL context pointer,
1486 * does not actually enable the extensions. It just makes sure
1487 * that all the dispatch offsets for all the extensions that
1488 * *might* be enables are known. This is needed because the
1489 * dispatch offsets need to be known when _mesa_context_create
1490 * is called, but we can't enable the extensions until we have a
1491 * context pointer.
1492 *
1493 * Hello chicken. Hello egg. How are you two today?
1494 */
1495 driInitExtensions( NULL, card_extensions, GL_FALSE );
1496 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1497 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1498 driInitSingleExtension( NULL, ARB_vp_extension );
1499 driInitSingleExtension( NULL, NV_vp_extension );
1500 driInitSingleExtension( NULL, ATI_fs_extension );
1501 driInitExtensions( NULL, point_extensions, GL_FALSE );
1502 #endif
1503
1504 if (!radeonInitDriver(psp)) {
1505 return NULL;
1506 }
1507 depth_bits[0] = 0;
1508 stencil_bits[0] = 0;
1509 depth_bits[1] = 16;
1510 stencil_bits[1] = 0;
1511 depth_bits[2] = 24;
1512 stencil_bits[2] = 0;
1513 depth_bits[3] = 24;
1514 stencil_bits[3] = 8;
1515
1516 msaa_samples_array[0] = 0;
1517
1518 fb_format[0] = GL_RGB;
1519 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5;
1520
1521 fb_format[1] = GL_BGR;
1522 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV;
1523
1524 fb_format[2] = GL_BGRA;
1525 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
1526
1527 for (color = 0; color < ARRAY_SIZE(fb_format); color++) {
1528 __DRIconfig **new_configs;
1529
1530 new_configs = driCreateConfigs(fb_format[color], fb_type[color],
1531 depth_bits,
1532 stencil_bits,
1533 ARRAY_SIZE(depth_bits),
1534 back_buffer_modes,
1535 ARRAY_SIZE(back_buffer_modes),
1536 msaa_samples_array,
1537 ARRAY_SIZE(msaa_samples_array));
1538 if (configs == NULL)
1539 configs = new_configs;
1540 else
1541 configs = driConcatConfigs(configs, new_configs);
1542 }
1543
1544 if (configs == NULL) {
1545 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
1546 __LINE__);
1547 return NULL;
1548 }
1549
1550 return (const __DRIconfig **)configs;
1551 }
1552
1553 /**
1554 * Get information about previous buffer swaps.
1555 */
1556 static int
1557 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1558 {
1559 struct radeon_framebuffer *rfb;
1560
1561 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1562 || (dPriv->driContextPriv->driverPrivate == NULL)
1563 || (sInfo == NULL) ) {
1564 return -1;
1565 }
1566
1567 rfb = dPriv->driverPrivate;
1568 sInfo->swap_count = rfb->swap_count;
1569 sInfo->swap_ust = rfb->swap_ust;
1570 sInfo->swap_missed_count = rfb->swap_missed_count;
1571
1572 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1573 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust )
1574 : 0.0;
1575
1576 return 0;
1577 }
1578
1579 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1580 const struct __DriverAPIRec driDriverAPI = {
1581 .InitScreen = radeonInitScreen,
1582 .DestroyScreen = radeonDestroyScreen,
1583 .CreateContext = radeonCreateContext,
1584 .DestroyContext = radeonDestroyContext,
1585 .CreateBuffer = radeonCreateBuffer,
1586 .DestroyBuffer = radeonDestroyBuffer,
1587 .SwapBuffers = radeonSwapBuffers,
1588 .MakeCurrent = radeonMakeCurrent,
1589 .UnbindContext = radeonUnbindContext,
1590 .GetSwapInfo = getSwapInfo,
1591 .GetDrawableMSC = driDrawableGetMSC32,
1592 .WaitForMSC = driWaitForMSC32,
1593 .WaitForSBC = NULL,
1594 .SwapBuffersMSC = NULL,
1595 .CopySubBuffer = radeonCopySubBuffer,
1596 /* DRI2 */
1597 .InitScreen2 = radeonInitScreen2,
1598 };
1599 #else
1600 const struct __DriverAPIRec driDriverAPI = {
1601 .InitScreen = radeonInitScreen,
1602 .DestroyScreen = radeonDestroyScreen,
1603 .CreateContext = r200CreateContext,
1604 .DestroyContext = r200DestroyContext,
1605 .CreateBuffer = radeonCreateBuffer,
1606 .DestroyBuffer = radeonDestroyBuffer,
1607 .SwapBuffers = radeonSwapBuffers,
1608 .MakeCurrent = radeonMakeCurrent,
1609 .UnbindContext = radeonUnbindContext,
1610 .GetSwapInfo = getSwapInfo,
1611 .GetDrawableMSC = driDrawableGetMSC32,
1612 .WaitForMSC = driWaitForMSC32,
1613 .WaitForSBC = NULL,
1614 .SwapBuffersMSC = NULL,
1615 .CopySubBuffer = radeonCopySubBuffer,
1616 .InitScreen2 = radeonInitScreen2,
1617 };
1618 #endif
1619