1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #include "radeon_buffer.h"
51 #include "radeon_context.h"
52 #include "radeon_span.h"
53 #include "radeon_tex.h"
54 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
55 #include "r200_context.h"
56 #include "r200_ioctl.h"
57 #include "r200_span.h"
59 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
60 #include "r300_context.h"
61 #include "r300_fragprog.h"
63 #include "radeon_span.h"
68 #include "drirenderbuffer.h"
70 #include "GL/internal/dri_interface.h"
72 /* Radeon configuration
75 #include "radeon_bo_legacy.h"
76 #include "radeon_bo_gem.h"
78 #if !RADEON_COMMON /* R100 */
79 PUBLIC
const char __driConfigOptions
[] =
81 DRI_CONF_SECTION_PERFORMANCE
82 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
83 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
84 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
85 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
86 DRI_CONF_HYPERZ(false)
88 DRI_CONF_SECTION_QUALITY
89 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
90 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
91 DRI_CONF_NO_NEG_LOD_BIAS(false)
92 DRI_CONF_FORCE_S3TC_ENABLE(false)
93 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
94 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
95 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
96 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
98 DRI_CONF_SECTION_DEBUG
99 DRI_CONF_NO_RAST(false)
102 static const GLuint __driNConfigOptions
= 14;
104 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
106 PUBLIC
const char __driConfigOptions
[] =
108 DRI_CONF_SECTION_PERFORMANCE
109 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
110 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
111 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
112 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
113 DRI_CONF_HYPERZ(false)
115 DRI_CONF_SECTION_QUALITY
116 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
117 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
118 DRI_CONF_NO_NEG_LOD_BIAS(false)
119 DRI_CONF_FORCE_S3TC_ENABLE(false)
120 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
121 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
122 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
123 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
124 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
126 DRI_CONF_SECTION_DEBUG
127 DRI_CONF_NO_RAST(false)
129 DRI_CONF_SECTION_SOFTWARE
130 DRI_CONF_NV_VERTEX_PROGRAM(false)
133 static const GLuint __driNConfigOptions
= 16;
135 extern const struct dri_extension blend_extensions
[];
136 extern const struct dri_extension ARB_vp_extension
[];
137 extern const struct dri_extension NV_vp_extension
[];
138 extern const struct dri_extension ATI_fs_extension
[];
139 extern const struct dri_extension point_extensions
[];
141 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
143 /* TODO: integrate these into xmlpool.h! */
144 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
145 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
146 DRI_CONF_DESC(en,"Number of texture image units") \
147 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
150 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
151 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
152 DRI_CONF_DESC(en,"Number of texture coordinate units") \
153 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
156 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
157 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
158 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
159 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
162 #define DRI_CONF_DISABLE_S3TC(def) \
163 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
164 DRI_CONF_DESC(en,"Disable S3TC compression") \
167 #define DRI_CONF_DISABLE_FALLBACK(def) \
168 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
169 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
172 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
173 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
174 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
177 #define DRI_CONF_FP_OPTIMIZATION(def) \
178 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
179 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
180 DRI_CONF_ENUM(0,"Optimize for Speed") \
181 DRI_CONF_ENUM(1,"Optimize for Quality") \
185 PUBLIC
const char __driConfigOptions
[] =
187 DRI_CONF_SECTION_PERFORMANCE
188 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
189 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
190 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
191 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
192 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
193 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
194 DRI_CONF_DISABLE_FALLBACK(true)
195 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
197 DRI_CONF_SECTION_QUALITY
198 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
199 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
200 DRI_CONF_FORCE_S3TC_ENABLE(false)
201 DRI_CONF_DISABLE_S3TC(false)
202 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
203 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
204 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
205 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED
)
207 DRI_CONF_SECTION_DEBUG
208 DRI_CONF_NO_RAST(false)
211 static const GLuint __driNConfigOptions
= 17;
214 int RADEON_DEBUG
= 0;
216 static const struct dri_debug_control debug_control
[] = {
217 {"fall", DEBUG_FALLBACKS
},
218 {"tex", DEBUG_TEXTURE
},
219 {"ioctl", DEBUG_IOCTL
},
220 {"prim", DEBUG_PRIMS
},
221 {"vert", DEBUG_VERTS
},
222 {"state", DEBUG_STATE
},
223 {"code", DEBUG_CODEGEN
},
224 {"vfmt", DEBUG_VFMT
},
225 {"vtxf", DEBUG_VFMT
},
226 {"verb", DEBUG_VERBOSE
},
229 {"san", DEBUG_SANITY
},
230 {"sync", DEBUG_SYNC
},
231 {"pix", DEBUG_PIXEL
},
232 {"mem", DEBUG_MEMORY
},
233 {"allmsg", ~DEBUG_SYNC
}, /* avoid the term "sync" because the parser uses strstr */
236 #endif /* RADEON_DEBUG */
238 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
240 extern const struct dri_extension card_extensions
[];
242 static int getSwapInfo( __DRIdrawablePrivate
*dPriv
, __DRIswapInfo
* sInfo
);
245 radeonGetParam(int fd
, int param
, void *value
)
248 drm_radeon_getparam_t gp
;
253 ret
= drmCommandWriteRead( fd
, DRM_RADEON_GETPARAM
, &gp
, sizeof(gp
));
257 static const __DRIconfig
**
258 radeonFillInModes( __DRIscreenPrivate
*psp
,
259 unsigned pixel_bits
, unsigned depth_bits
,
260 unsigned stencil_bits
, GLboolean have_back_buffer
)
262 __DRIconfig
**configs
;
264 unsigned depth_buffer_factor
;
265 unsigned back_buffer_factor
;
270 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
271 * enough to add support. Basically, if a context is created with an
272 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
273 * will never be used.
275 static const GLenum back_buffer_modes
[] = {
276 GLX_NONE
, GLX_SWAP_UNDEFINED_OML
/*, GLX_SWAP_COPY_OML */
279 uint8_t depth_bits_array
[2];
280 uint8_t stencil_bits_array
[2];
283 depth_bits_array
[0] = depth_bits
;
284 depth_bits_array
[1] = depth_bits
;
286 /* Just like with the accumulation buffer, always provide some modes
287 * with a stencil buffer. It will be a sw fallback, but some apps won't
290 stencil_bits_array
[0] = 0;
291 stencil_bits_array
[1] = (stencil_bits
== 0) ? 8 : stencil_bits
;
293 depth_buffer_factor
= ((depth_bits
!= 0) || (stencil_bits
!= 0)) ? 2 : 1;
294 back_buffer_factor
= (have_back_buffer
) ? 2 : 1;
296 if ( pixel_bits
== 16 ) {
298 fb_type
= GL_UNSIGNED_SHORT_5_6_5
;
302 fb_type
= GL_UNSIGNED_INT_8_8_8_8_REV
;
305 configs
= driCreateConfigs(fb_format
, fb_type
,
306 depth_bits_array
, stencil_bits_array
,
308 back_buffer_modes
, back_buffer_factor
);
309 if (configs
== NULL
) {
310 fprintf( stderr
, "[%s:%u] Error creating FBConfig!\n",
311 __func__
, __LINE__
);
315 /* Mark the visual as slow if there are "fake" stencil bits.
317 for (i
= 0; configs
[i
]; i
++) {
318 m
= &configs
[i
]->modes
;
319 if ((m
->stencilBits
!= 0) && (m
->stencilBits
!= stencil_bits
)) {
320 m
->visualRating
= GLX_SLOW_CONFIG
;
324 return (const __DRIconfig
**) configs
;
328 static const __DRItexOffsetExtension radeonTexOffsetExtension
= {
329 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
334 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
335 static const __DRIallocateExtension r200AllocateExtension
= {
336 { __DRI_ALLOCATE
, __DRI_ALLOCATE_VERSION
},
337 r200AllocateMemoryMESA
,
339 r200GetMemoryOffsetMESA
342 static const __DRItexOffsetExtension r200texOffsetExtension
= {
343 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
348 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
349 static const __DRItexOffsetExtension r300texOffsetExtension
= {
350 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
354 void r300SetTexBuffer(__DRIcontext
*pDRICtx
,
356 __DRIdrawable
*dPriv
);
357 static const __DRItexBufferExtension r300TexBufferExtension
= {
358 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
363 int radeon_set_screen_flags(radeonScreenPtr screen
, int device_id
)
365 screen
->chip_flags
= 0;
366 switch ( device_id
) {
367 case PCI_CHIP_RADEON_LY
:
368 case PCI_CHIP_RADEON_LZ
:
369 case PCI_CHIP_RADEON_QY
:
370 case PCI_CHIP_RADEON_QZ
:
371 case PCI_CHIP_RN50_515E
:
372 case PCI_CHIP_RN50_5969
:
373 screen
->chip_family
= CHIP_FAMILY_RV100
;
376 case PCI_CHIP_RS100_4136
:
377 case PCI_CHIP_RS100_4336
:
378 screen
->chip_family
= CHIP_FAMILY_RS100
;
381 case PCI_CHIP_RS200_4137
:
382 case PCI_CHIP_RS200_4337
:
383 case PCI_CHIP_RS250_4237
:
384 case PCI_CHIP_RS250_4437
:
385 screen
->chip_family
= CHIP_FAMILY_RS200
;
388 case PCI_CHIP_RADEON_QD
:
389 case PCI_CHIP_RADEON_QE
:
390 case PCI_CHIP_RADEON_QF
:
391 case PCI_CHIP_RADEON_QG
:
392 /* all original radeons (7200) presumably have a stencil op bug */
393 screen
->chip_family
= CHIP_FAMILY_R100
;
394 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_BROKEN_STENCIL
;
397 case PCI_CHIP_RV200_QW
:
398 case PCI_CHIP_RV200_QX
:
399 case PCI_CHIP_RADEON_LW
:
400 case PCI_CHIP_RADEON_LX
:
401 screen
->chip_family
= CHIP_FAMILY_RV200
;
402 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
405 case PCI_CHIP_R200_BB
:
406 case PCI_CHIP_R200_BC
:
407 case PCI_CHIP_R200_QH
:
408 case PCI_CHIP_R200_QL
:
409 case PCI_CHIP_R200_QM
:
410 screen
->chip_family
= CHIP_FAMILY_R200
;
411 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
414 case PCI_CHIP_RV250_If
:
415 case PCI_CHIP_RV250_Ig
:
416 case PCI_CHIP_RV250_Ld
:
417 case PCI_CHIP_RV250_Lf
:
418 case PCI_CHIP_RV250_Lg
:
419 screen
->chip_family
= CHIP_FAMILY_RV250
;
420 screen
->chip_flags
= R200_CHIPSET_YCBCR_BROKEN
| RADEON_CHIPSET_TCL
;
423 case PCI_CHIP_RV280_5960
:
424 case PCI_CHIP_RV280_5961
:
425 case PCI_CHIP_RV280_5962
:
426 case PCI_CHIP_RV280_5964
:
427 case PCI_CHIP_RV280_5965
:
428 case PCI_CHIP_RV280_5C61
:
429 case PCI_CHIP_RV280_5C63
:
430 screen
->chip_family
= CHIP_FAMILY_RV280
;
431 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
434 case PCI_CHIP_RS300_5834
:
435 case PCI_CHIP_RS300_5835
:
436 case PCI_CHIP_RS350_7834
:
437 case PCI_CHIP_RS350_7835
:
438 screen
->chip_family
= CHIP_FAMILY_RS300
;
441 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
442 case PCI_CHIP_R300_AD
:
443 screen
->chip_family
= CHIP_FAMILY_RV350
;
444 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
446 case PCI_CHIP_R300_AE
:
447 case PCI_CHIP_R300_AF
:
448 case PCI_CHIP_R300_AG
:
449 case PCI_CHIP_R300_ND
:
450 case PCI_CHIP_R300_NE
:
451 case PCI_CHIP_R300_NF
:
452 case PCI_CHIP_R300_NG
:
453 screen
->chip_family
= CHIP_FAMILY_R300
;
454 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
457 case PCI_CHIP_RV350_AP
:
458 case PCI_CHIP_RV350_AQ
:
459 case PCI_CHIP_RV350_AR
:
460 case PCI_CHIP_RV350_AS
:
461 case PCI_CHIP_RV350_AT
:
462 case PCI_CHIP_RV350_AV
:
463 case PCI_CHIP_RV350_AU
:
464 case PCI_CHIP_RV350_NP
:
465 case PCI_CHIP_RV350_NQ
:
466 case PCI_CHIP_RV350_NR
:
467 case PCI_CHIP_RV350_NS
:
468 case PCI_CHIP_RV350_NT
:
469 case PCI_CHIP_RV350_NV
:
470 screen
->chip_family
= CHIP_FAMILY_RV350
;
471 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
474 case PCI_CHIP_R350_AH
:
475 case PCI_CHIP_R350_AI
:
476 case PCI_CHIP_R350_AJ
:
477 case PCI_CHIP_R350_AK
:
478 case PCI_CHIP_R350_NH
:
479 case PCI_CHIP_R350_NI
:
480 case PCI_CHIP_R360_NJ
:
481 case PCI_CHIP_R350_NK
:
482 screen
->chip_family
= CHIP_FAMILY_R350
;
483 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
486 case PCI_CHIP_RV370_5460
:
487 case PCI_CHIP_RV370_5462
:
488 case PCI_CHIP_RV370_5464
:
489 case PCI_CHIP_RV370_5B60
:
490 case PCI_CHIP_RV370_5B62
:
491 case PCI_CHIP_RV370_5B63
:
492 case PCI_CHIP_RV370_5B64
:
493 case PCI_CHIP_RV370_5B65
:
494 case PCI_CHIP_RV380_3150
:
495 case PCI_CHIP_RV380_3152
:
496 case PCI_CHIP_RV380_3154
:
497 case PCI_CHIP_RV380_3E50
:
498 case PCI_CHIP_RV380_3E54
:
499 screen
->chip_family
= CHIP_FAMILY_RV380
;
500 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
503 case PCI_CHIP_R420_JN
:
504 case PCI_CHIP_R420_JH
:
505 case PCI_CHIP_R420_JI
:
506 case PCI_CHIP_R420_JJ
:
507 case PCI_CHIP_R420_JK
:
508 case PCI_CHIP_R420_JL
:
509 case PCI_CHIP_R420_JM
:
510 case PCI_CHIP_R420_JO
:
511 case PCI_CHIP_R420_JP
:
512 case PCI_CHIP_R420_JT
:
513 case PCI_CHIP_R481_4B49
:
514 case PCI_CHIP_R481_4B4A
:
515 case PCI_CHIP_R481_4B4B
:
516 case PCI_CHIP_R481_4B4C
:
517 case PCI_CHIP_R423_UH
:
518 case PCI_CHIP_R423_UI
:
519 case PCI_CHIP_R423_UJ
:
520 case PCI_CHIP_R423_UK
:
521 case PCI_CHIP_R430_554C
:
522 case PCI_CHIP_R430_554D
:
523 case PCI_CHIP_R430_554E
:
524 case PCI_CHIP_R430_554F
:
525 case PCI_CHIP_R423_5550
:
526 case PCI_CHIP_R423_UQ
:
527 case PCI_CHIP_R423_UR
:
528 case PCI_CHIP_R423_UT
:
529 case PCI_CHIP_R430_5D48
:
530 case PCI_CHIP_R430_5D49
:
531 case PCI_CHIP_R430_5D4A
:
532 case PCI_CHIP_R480_5D4C
:
533 case PCI_CHIP_R480_5D4D
:
534 case PCI_CHIP_R480_5D4E
:
535 case PCI_CHIP_R480_5D4F
:
536 case PCI_CHIP_R480_5D50
:
537 case PCI_CHIP_R480_5D52
:
538 case PCI_CHIP_R423_5D57
:
539 screen
->chip_family
= CHIP_FAMILY_R420
;
540 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
543 case PCI_CHIP_RV410_5E4C
:
544 case PCI_CHIP_RV410_5E4F
:
545 case PCI_CHIP_RV410_564A
:
546 case PCI_CHIP_RV410_564B
:
547 case PCI_CHIP_RV410_564F
:
548 case PCI_CHIP_RV410_5652
:
549 case PCI_CHIP_RV410_5653
:
550 case PCI_CHIP_RV410_5657
:
551 case PCI_CHIP_RV410_5E48
:
552 case PCI_CHIP_RV410_5E4A
:
553 case PCI_CHIP_RV410_5E4B
:
554 case PCI_CHIP_RV410_5E4D
:
555 screen
->chip_family
= CHIP_FAMILY_RV410
;
556 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
559 case PCI_CHIP_RS480_5954
:
560 case PCI_CHIP_RS480_5955
:
561 case PCI_CHIP_RS482_5974
:
562 case PCI_CHIP_RS482_5975
:
563 case PCI_CHIP_RS400_5A41
:
564 case PCI_CHIP_RS400_5A42
:
565 case PCI_CHIP_RC410_5A61
:
566 case PCI_CHIP_RC410_5A62
:
567 screen
->chip_family
= CHIP_FAMILY_RS400
;
570 case PCI_CHIP_RS690_791E
:
571 case PCI_CHIP_RS690_791F
:
572 screen
->chip_family
= CHIP_FAMILY_RS690
;
574 case PCI_CHIP_RS740_796C
:
575 case PCI_CHIP_RS740_796D
:
576 case PCI_CHIP_RS740_796E
:
577 case PCI_CHIP_RS740_796F
:
578 screen
->chip_family
= CHIP_FAMILY_RS740
;
581 case PCI_CHIP_R520_7100
:
582 case PCI_CHIP_R520_7101
:
583 case PCI_CHIP_R520_7102
:
584 case PCI_CHIP_R520_7103
:
585 case PCI_CHIP_R520_7104
:
586 case PCI_CHIP_R520_7105
:
587 case PCI_CHIP_R520_7106
:
588 case PCI_CHIP_R520_7108
:
589 case PCI_CHIP_R520_7109
:
590 case PCI_CHIP_R520_710A
:
591 case PCI_CHIP_R520_710B
:
592 case PCI_CHIP_R520_710C
:
593 case PCI_CHIP_R520_710E
:
594 case PCI_CHIP_R520_710F
:
595 screen
->chip_family
= CHIP_FAMILY_R520
;
596 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
599 case PCI_CHIP_RV515_7140
:
600 case PCI_CHIP_RV515_7141
:
601 case PCI_CHIP_RV515_7142
:
602 case PCI_CHIP_RV515_7143
:
603 case PCI_CHIP_RV515_7144
:
604 case PCI_CHIP_RV515_7145
:
605 case PCI_CHIP_RV515_7146
:
606 case PCI_CHIP_RV515_7147
:
607 case PCI_CHIP_RV515_7149
:
608 case PCI_CHIP_RV515_714A
:
609 case PCI_CHIP_RV515_714B
:
610 case PCI_CHIP_RV515_714C
:
611 case PCI_CHIP_RV515_714D
:
612 case PCI_CHIP_RV515_714E
:
613 case PCI_CHIP_RV515_714F
:
614 case PCI_CHIP_RV515_7151
:
615 case PCI_CHIP_RV515_7152
:
616 case PCI_CHIP_RV515_7153
:
617 case PCI_CHIP_RV515_715E
:
618 case PCI_CHIP_RV515_715F
:
619 case PCI_CHIP_RV515_7180
:
620 case PCI_CHIP_RV515_7181
:
621 case PCI_CHIP_RV515_7183
:
622 case PCI_CHIP_RV515_7186
:
623 case PCI_CHIP_RV515_7187
:
624 case PCI_CHIP_RV515_7188
:
625 case PCI_CHIP_RV515_718A
:
626 case PCI_CHIP_RV515_718B
:
627 case PCI_CHIP_RV515_718C
:
628 case PCI_CHIP_RV515_718D
:
629 case PCI_CHIP_RV515_718F
:
630 case PCI_CHIP_RV515_7193
:
631 case PCI_CHIP_RV515_7196
:
632 case PCI_CHIP_RV515_719B
:
633 case PCI_CHIP_RV515_719F
:
634 case PCI_CHIP_RV515_7200
:
635 case PCI_CHIP_RV515_7210
:
636 case PCI_CHIP_RV515_7211
:
637 screen
->chip_family
= CHIP_FAMILY_RV515
;
638 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
641 case PCI_CHIP_RV530_71C0
:
642 case PCI_CHIP_RV530_71C1
:
643 case PCI_CHIP_RV530_71C2
:
644 case PCI_CHIP_RV530_71C3
:
645 case PCI_CHIP_RV530_71C4
:
646 case PCI_CHIP_RV530_71C5
:
647 case PCI_CHIP_RV530_71C6
:
648 case PCI_CHIP_RV530_71C7
:
649 case PCI_CHIP_RV530_71CD
:
650 case PCI_CHIP_RV530_71CE
:
651 case PCI_CHIP_RV530_71D2
:
652 case PCI_CHIP_RV530_71D4
:
653 case PCI_CHIP_RV530_71D5
:
654 case PCI_CHIP_RV530_71D6
:
655 case PCI_CHIP_RV530_71DA
:
656 case PCI_CHIP_RV530_71DE
:
657 screen
->chip_family
= CHIP_FAMILY_RV530
;
658 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
661 case PCI_CHIP_R580_7240
:
662 case PCI_CHIP_R580_7243
:
663 case PCI_CHIP_R580_7244
:
664 case PCI_CHIP_R580_7245
:
665 case PCI_CHIP_R580_7246
:
666 case PCI_CHIP_R580_7247
:
667 case PCI_CHIP_R580_7248
:
668 case PCI_CHIP_R580_7249
:
669 case PCI_CHIP_R580_724A
:
670 case PCI_CHIP_R580_724B
:
671 case PCI_CHIP_R580_724C
:
672 case PCI_CHIP_R580_724D
:
673 case PCI_CHIP_R580_724E
:
674 case PCI_CHIP_R580_724F
:
675 case PCI_CHIP_R580_7284
:
676 screen
->chip_family
= CHIP_FAMILY_R580
;
677 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
680 case PCI_CHIP_RV570_7280
:
681 case PCI_CHIP_RV560_7281
:
682 case PCI_CHIP_RV560_7283
:
683 case PCI_CHIP_RV560_7287
:
684 case PCI_CHIP_RV570_7288
:
685 case PCI_CHIP_RV570_7289
:
686 case PCI_CHIP_RV570_728B
:
687 case PCI_CHIP_RV570_728C
:
688 case PCI_CHIP_RV560_7290
:
689 case PCI_CHIP_RV560_7291
:
690 case PCI_CHIP_RV560_7293
:
691 case PCI_CHIP_RV560_7297
:
692 screen
->chip_family
= CHIP_FAMILY_RV560
;
693 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
697 fprintf(stderr
, "unknown chip id 0x%x, can't guess.\n",
706 /* Create the device specific screen private data struct.
708 static radeonScreenPtr
709 radeonCreateScreen( __DRIscreenPrivate
*sPriv
)
711 radeonScreenPtr screen
;
712 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
)sPriv
->pDevPriv
;
713 unsigned char *RADEONMMIO
= NULL
;
718 if (sPriv
->devPrivSize
!= sizeof(RADEONDRIRec
)) {
719 fprintf(stderr
,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
723 /* Allocate the private area */
724 screen
= (radeonScreenPtr
) CALLOC( sizeof(*screen
) );
726 __driUtilMessage("%s: Could not allocate memory for screen structure",
731 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
732 RADEON_DEBUG
= driParseDebugString(getenv("RADEON_DEBUG"), debug_control
);
735 /* parse information in __driConfigOptions */
736 driParseOptionInfo (&screen
->optionCache
,
737 __driConfigOptions
, __driNConfigOptions
);
739 /* This is first since which regions we map depends on whether or
740 * not we are using a PCI card.
742 screen
->card_type
= (dri_priv
->IsPCI
? RADEON_CARD_PCI
: RADEON_CARD_AGP
);
746 #ifdef RADEON_PARAM_KERNEL_MM
747 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_KERNEL_MM
,
750 if (ret
&& ret
!= -EINVAL
) {
752 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret
);
757 screen
->kernel_mm
= 0;
760 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_GART_BUFFER_OFFSET
,
761 &screen
->gart_buffer_offset
);
765 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret
);
769 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_GART_BASE
,
773 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret
);
777 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_IRQ_NR
,
781 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret
);
784 screen
->drmSupportsCubeMapsR200
= (sPriv
->drm_version
.minor
>= 7);
785 screen
->drmSupportsBlendColor
= (sPriv
->drm_version
.minor
>= 11);
786 screen
->drmSupportsTriPerf
= (sPriv
->drm_version
.minor
>= 16);
787 screen
->drmSupportsFragShader
= (sPriv
->drm_version
.minor
>= 18);
788 screen
->drmSupportsPointSprites
= (sPriv
->drm_version
.minor
>= 13);
789 screen
->drmSupportsCubeMapsR100
= (sPriv
->drm_version
.minor
>= 15);
790 screen
->drmSupportsVertexProgram
= (sPriv
->drm_version
.minor
>= 25);
793 if (!screen
->kernel_mm
) {
794 screen
->mmio
.handle
= dri_priv
->registerHandle
;
795 screen
->mmio
.size
= dri_priv
->registerSize
;
796 if ( drmMap( sPriv
->fd
,
799 &screen
->mmio
.map
) ) {
801 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__
);
805 RADEONMMIO
= screen
->mmio
.map
;
807 screen
->status
.handle
= dri_priv
->statusHandle
;
808 screen
->status
.size
= dri_priv
->statusSize
;
809 if ( drmMap( sPriv
->fd
,
810 screen
->status
.handle
,
812 &screen
->status
.map
) ) {
813 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
815 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__
);
818 screen
->scratch
= (__volatile__
uint32_t *)
819 ((GLubyte
*)screen
->status
.map
+ RADEON_SCRATCH_REG_OFFSET
);
821 screen
->buffers
= drmMapBufs( sPriv
->fd
);
822 if ( !screen
->buffers
) {
823 drmUnmap( screen
->status
.map
, screen
->status
.size
);
824 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
826 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__
);
830 if ( dri_priv
->gartTexHandle
&& dri_priv
->gartTexMapSize
) {
831 screen
->gartTextures
.handle
= dri_priv
->gartTexHandle
;
832 screen
->gartTextures
.size
= dri_priv
->gartTexMapSize
;
833 if ( drmMap( sPriv
->fd
,
834 screen
->gartTextures
.handle
,
835 screen
->gartTextures
.size
,
836 (drmAddressPtr
)&screen
->gartTextures
.map
) ) {
837 drmUnmapBufs( screen
->buffers
);
838 drmUnmap( screen
->status
.map
, screen
->status
.size
);
839 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
841 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__
);
845 screen
->gart_texture_offset
= dri_priv
->gartTexOffset
+ screen
->gart_base
;
850 ret
= radeon_set_screen_flags(screen
, dri_priv
->deviceID
);
854 if ((screen
->chip_family
== CHIP_FAMILY_R350
|| screen
->chip_family
== CHIP_FAMILY_R300
) &&
855 sPriv
->ddx_version
.minor
< 2) {
856 fprintf(stderr
, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
860 if ((sPriv
->drm_version
.minor
< 29) && (screen
->chip_family
>= CHIP_FAMILY_RV515
)) {
861 fprintf(stderr
, "R500 support requires a newer drm.\n");
865 if (getenv("R300_NO_TCL"))
866 screen
->chip_flags
&= ~RADEON_CHIPSET_TCL
;
868 if (screen
->chip_family
<= CHIP_FAMILY_RS200
)
869 screen
->chip_flags
|= RADEON_CLASS_R100
;
870 else if (screen
->chip_family
<= CHIP_FAMILY_RV280
)
871 screen
->chip_flags
|= RADEON_CLASS_R200
;
873 screen
->chip_flags
|= RADEON_CLASS_R300
;
875 screen
->cpp
= dri_priv
->bpp
/ 8;
876 screen
->AGPMode
= dri_priv
->AGPMode
;
878 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_FB_LOCATION
,
881 if (screen
->chip_family
< CHIP_FAMILY_RS690
&& !screen
->kernel_mm
)
882 screen
->fbLocation
= ( INREG( RADEON_MC_FB_LOCATION
) & 0xffff) << 16;
885 fprintf(stderr
, "Unable to get fb location need newer drm\n");
889 screen
->fbLocation
= (temp
& 0xffff) << 16;
892 if (screen
->chip_family
>= CHIP_FAMILY_RV515
) {
893 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_NUM_GB_PIPES
,
896 fprintf(stderr
, "Unable to get num_pipes, need newer drm\n");
897 switch (screen
->chip_family
) {
898 case CHIP_FAMILY_R300
:
899 case CHIP_FAMILY_R350
:
900 screen
->num_gb_pipes
= 2;
902 case CHIP_FAMILY_R420
:
903 case CHIP_FAMILY_R520
:
904 case CHIP_FAMILY_R580
:
905 case CHIP_FAMILY_RV560
:
906 case CHIP_FAMILY_RV570
:
907 screen
->num_gb_pipes
= 4;
909 case CHIP_FAMILY_RV350
:
910 case CHIP_FAMILY_RV515
:
911 case CHIP_FAMILY_RV530
:
912 case CHIP_FAMILY_RV410
:
914 screen
->num_gb_pipes
= 1;
918 screen
->num_gb_pipes
= temp
;
922 if ( sPriv
->drm_version
.minor
>= 10 ) {
923 drm_radeon_setparam_t sp
;
925 sp
.param
= RADEON_SETPARAM_FB_LOCATION
;
926 sp
.value
= screen
->fbLocation
;
928 drmCommandWrite( sPriv
->fd
, DRM_RADEON_SETPARAM
,
932 screen
->frontOffset
= dri_priv
->frontOffset
;
933 screen
->frontPitch
= dri_priv
->frontPitch
;
934 screen
->backOffset
= dri_priv
->backOffset
;
935 screen
->backPitch
= dri_priv
->backPitch
;
936 screen
->depthOffset
= dri_priv
->depthOffset
;
937 screen
->depthPitch
= dri_priv
->depthPitch
;
939 /* Check if ddx has set up a surface reg to cover depth buffer */
940 screen
->depthHasSurface
= (sPriv
->ddx_version
.major
> 4) ||
941 /* these chips don't use tiled z without hyperz. So always pretend
942 we have set up a surface which will cause linear reads/writes */
943 (IS_R100_CLASS(screen
) &&
944 !(screen
->chip_flags
& RADEON_CHIPSET_TCL
));
946 if ( dri_priv
->textureSize
== 0 ) {
947 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = screen
->gart_texture_offset
;
948 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
949 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
950 dri_priv
->log2GARTTexGran
;
952 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureOffset
953 + screen
->fbLocation
;
954 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureSize
;
955 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
956 dri_priv
->log2TexGran
;
959 if ( !screen
->gartTextures
.map
|| dri_priv
->textureSize
== 0
960 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
961 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
- 1;
962 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = 0;
963 screen
->texSize
[RADEON_GART_TEX_HEAP
] = 0;
964 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] = 0;
966 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
;
967 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = screen
->gart_texture_offset
;
968 screen
->texSize
[RADEON_GART_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
969 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] =
970 dri_priv
->log2GARTTexGran
;
974 screen
->extensions
[i
++] = &driCopySubBufferExtension
.base
;
975 screen
->extensions
[i
++] = &driFrameTrackingExtension
.base
;
976 screen
->extensions
[i
++] = &driReadDrawableExtension
;
978 if ( screen
->irq
!= 0 ) {
979 screen
->extensions
[i
++] = &driSwapControlExtension
.base
;
980 screen
->extensions
[i
++] = &driMediaStreamCounterExtension
.base
;
984 screen
->extensions
[i
++] = &radeonTexOffsetExtension
.base
;
987 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
988 if (IS_R200_CLASS(screen
))
989 screen
->extensions
[i
++] = &r200AllocateExtension
.base
;
991 screen
->extensions
[i
++] = &r200texOffsetExtension
.base
;
994 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
995 //screen->extensions[i++] = &r300texOffsetExtension.base;
998 screen
->extensions
[i
++] = NULL
;
999 sPriv
->extensions
= screen
->extensions
;
1001 screen
->driScreen
= sPriv
;
1002 screen
->sarea_priv_offset
= dri_priv
->sarea_priv_offset
;
1003 screen
->sarea
= (drm_radeon_sarea_t
*) ((GLubyte
*) sPriv
->pSAREA
+
1004 screen
->sarea_priv_offset
);
1006 if (screen
->kernel_mm
)
1007 screen
->bom
= radeon_bo_manager_gem_ctor(sPriv
->fd
);
1009 screen
->bom
= radeon_bo_manager_legacy_ctor(screen
);
1010 if (screen
->bom
== NULL
) {
1017 static radeonScreenPtr
1018 radeonCreateScreen2(__DRIscreenPrivate
*sPriv
)
1020 radeonScreenPtr screen
;
1025 /* Allocate the private area */
1026 screen
= (radeonScreenPtr
) CALLOC( sizeof(*screen
) );
1028 __driUtilMessage("%s: Could not allocate memory for screen structure",
1030 fprintf(stderr
, "leaving here\n");
1034 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1035 RADEON_DEBUG
= driParseDebugString(getenv("RADEON_DEBUG"), debug_control
);
1038 /* parse information in __driConfigOptions */
1039 driParseOptionInfo (&screen
->optionCache
,
1040 __driConfigOptions
, __driNConfigOptions
);
1042 screen
->kernel_mm
= 1;
1043 screen
->chip_flags
= 0;
1045 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_IRQ_NR
,
1048 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_DEVICE_ID
,
1052 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret
);
1056 ret
= radeon_set_screen_flags(screen
, device_id
);
1060 if (screen
->chip_family
<= CHIP_FAMILY_RS200
)
1061 screen
->chip_flags
|= RADEON_CLASS_R100
;
1062 else if (screen
->chip_family
<= CHIP_FAMILY_RV280
)
1063 screen
->chip_flags
|= RADEON_CLASS_R200
;
1065 screen
->chip_flags
|= RADEON_CLASS_R300
;
1068 screen
->extensions
[i
++] = &driCopySubBufferExtension
.base
;
1069 screen
->extensions
[i
++] = &driFrameTrackingExtension
.base
;
1070 screen
->extensions
[i
++] = &driReadDrawableExtension
;
1072 if ( screen
->irq
!= 0 ) {
1073 screen
->extensions
[i
++] = &driSwapControlExtension
.base
;
1074 screen
->extensions
[i
++] = &driMediaStreamCounterExtension
.base
;
1078 screen
->extensions
[i
++] = &radeonTexOffsetExtension
.base
;
1081 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1082 if (IS_R200_CLASS(screen
))
1083 screen
->extensions
[i
++] = &r200AllocateExtension
.base
;
1085 screen
->extensions
[i
++] = &r200texOffsetExtension
.base
;
1088 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1089 screen
->extensions
[i
++] = &r300texOffsetExtension
.base
;
1090 screen
->extensions
[i
++] = &r300TexBufferExtension
.base
;
1093 screen
->extensions
[i
++] = NULL
;
1094 sPriv
->extensions
= screen
->extensions
;
1096 screen
->driScreen
= sPriv
;
1097 screen
->bom
= radeon_bo_manager_gem_ctor(sPriv
->fd
);
1098 if (screen
->bom
== NULL
) {
1105 /* Destroy the device specific screen private data struct.
1108 radeonDestroyScreen( __DRIscreenPrivate
*sPriv
)
1110 radeonScreenPtr screen
= (radeonScreenPtr
)sPriv
->private;
1115 if (screen
->kernel_mm
) {
1116 radeon_tracker_print(&screen
->bom
->tracker
, stderr
);
1117 radeon_bo_manager_gem_dtor(screen
->bom
);
1119 radeon_bo_manager_legacy_dtor(screen
->bom
);
1121 if ( screen
->gartTextures
.map
) {
1122 drmUnmap( screen
->gartTextures
.map
, screen
->gartTextures
.size
);
1124 drmUnmapBufs( screen
->buffers
);
1125 drmUnmap( screen
->status
.map
, screen
->status
.size
);
1126 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
1129 /* free all option information */
1130 driDestroyOptionInfo (&screen
->optionCache
);
1133 sPriv
->private = NULL
;
1137 /* Initialize the driver specific screen private data.
1140 radeonInitDriver( __DRIscreenPrivate
*sPriv
)
1142 if (sPriv
->dri2
.enabled
) {
1143 sPriv
->private = (void *) radeonCreateScreen2( sPriv
);
1145 sPriv
->private = (void *) radeonCreateScreen( sPriv
);
1147 if ( !sPriv
->private ) {
1148 radeonDestroyScreen( sPriv
);
1155 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1157 radeon_alloc_window_storage(GLcontext
*ctx
, struct gl_renderbuffer
*rb
,
1158 GLenum intFormat
, GLuint w
, GLuint h
)
1162 rb
->_ActualFormat
= intFormat
;
1168 static struct radeon_renderbuffer
*
1169 radeon_create_renderbuffer(GLenum format
, __DRIdrawablePrivate
*driDrawPriv
)
1171 struct radeon_renderbuffer
*ret
;
1173 ret
= CALLOC_STRUCT(radeon_renderbuffer
);
1177 _mesa_init_renderbuffer(&ret
->base
, 0);
1179 /* XXX format junk */
1182 ret
->base
._ActualFormat
= GL_RGB5
;
1183 ret
->base
._BaseFormat
= GL_RGBA
;
1184 ret
->base
.RedBits
= 5;
1185 ret
->base
.GreenBits
= 6;
1186 ret
->base
.BlueBits
= 5;
1187 ret
->base
.DataType
= GL_UNSIGNED_BYTE
;
1190 ret
->base
._ActualFormat
= GL_RGBA8
;
1191 ret
->base
._BaseFormat
= GL_RGBA
;
1192 ret
->base
.RedBits
= 8;
1193 ret
->base
.GreenBits
= 8;
1194 ret
->base
.BlueBits
= 8;
1195 ret
->base
.AlphaBits
= 8;
1196 ret
->base
.DataType
= GL_UNSIGNED_BYTE
;
1198 case GL_STENCIL_INDEX8_EXT
:
1199 ret
->base
._ActualFormat
= GL_STENCIL_INDEX8_EXT
;
1200 ret
->base
._BaseFormat
= GL_STENCIL_INDEX
;
1201 ret
->base
.StencilBits
= 8;
1202 ret
->base
.DataType
= GL_UNSIGNED_BYTE
;
1204 case GL_DEPTH_COMPONENT16
:
1205 ret
->base
._ActualFormat
= GL_DEPTH_COMPONENT16
;
1206 ret
->base
._BaseFormat
= GL_DEPTH_COMPONENT
;
1207 ret
->base
.DepthBits
= 16;
1208 ret
->base
.DataType
= GL_UNSIGNED_SHORT
;
1210 case GL_DEPTH_COMPONENT24
:
1211 ret
->base
._ActualFormat
= GL_DEPTH24_STENCIL8_EXT
;
1212 ret
->base
._BaseFormat
= GL_DEPTH_COMPONENT
;
1213 ret
->base
.DepthBits
= 24;
1214 ret
->base
.DataType
= GL_UNSIGNED_INT
;
1216 case GL_DEPTH24_STENCIL8_EXT
:
1217 ret
->base
._ActualFormat
= GL_DEPTH24_STENCIL8_EXT
;
1218 ret
->base
._BaseFormat
= GL_DEPTH_STENCIL_EXT
;
1219 ret
->base
.DepthBits
= 24;
1220 ret
->base
.StencilBits
= 8;
1221 ret
->base
.DataType
= GL_UNSIGNED_INT_24_8_EXT
;
1224 fprintf(stderr
, "%s: Unknown format 0x%04x\n", __FUNCTION__
, format
);
1225 _mesa_delete_renderbuffer(&ret
->base
);
1229 ret
->dPriv
= driDrawPriv
;
1230 ret
->base
.InternalFormat
= format
;
1232 ret
->base
.AllocStorage
= radeon_alloc_window_storage
;
1234 radeonSetSpanFunctions(ret
);
1241 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1243 * \todo This function (and its interface) will need to be updated to support
1247 radeonCreateBuffer( __DRIscreenPrivate
*driScrnPriv
,
1248 __DRIdrawablePrivate
*driDrawPriv
,
1249 const __GLcontextModes
*mesaVis
,
1250 GLboolean isPixmap
)
1252 radeonScreenPtr screen
= (radeonScreenPtr
) driScrnPriv
->private;
1254 const GLboolean swDepth
= GL_FALSE
;
1255 const GLboolean swAlpha
= GL_FALSE
;
1256 const GLboolean swAccum
= mesaVis
->accumRedBits
> 0;
1257 const GLboolean swStencil
= mesaVis
->stencilBits
> 0 &&
1258 mesaVis
->depthBits
!= 24;
1259 GLenum rgbFormat
= (mesaVis
->redBits
== 5 ? GL_RGB5
: GL_RGBA8
);
1260 GLenum depthFormat
= GL_NONE
;
1261 struct gl_framebuffer
*fb
= _mesa_create_framebuffer(mesaVis
);
1263 if (mesaVis
->depthBits
== 16)
1264 depthFormat
= GL_DEPTH_COMPONENT16
;
1265 else if (mesaVis
->depthBits
== 24)
1266 depthFormat
= GL_DEPTH_COMPONENT24
;
1268 /* front color renderbuffer */
1270 struct radeon_renderbuffer
*front
=
1271 radeon_create_renderbuffer(rgbFormat
, driDrawPriv
);
1272 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &front
->base
);
1273 front
->has_surface
= 1;
1276 /* back color renderbuffer */
1277 if (mesaVis
->doubleBufferMode
) {
1278 struct radeon_renderbuffer
*back
=
1279 radeon_create_renderbuffer(rgbFormat
, driDrawPriv
);
1280 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &back
->base
);
1281 back
->has_surface
= 1;
1284 /* depth renderbuffer */
1285 if (depthFormat
!= GL_NONE
) {
1286 struct radeon_renderbuffer
*depth
=
1287 radeon_create_renderbuffer(depthFormat
, driDrawPriv
);
1288 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &depth
->base
);
1289 depth
->has_surface
= screen
->depthHasSurface
;
1292 /* stencil renderbuffer */
1293 if (mesaVis
->stencilBits
> 0 && !swStencil
) {
1294 struct radeon_renderbuffer
*stencil
=
1295 radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT
, driDrawPriv
);
1296 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &stencil
->base
);
1297 stencil
->has_surface
= screen
->depthHasSurface
;
1300 _mesa_add_soft_renderbuffers(fb
,
1301 GL_FALSE
, /* color */
1306 GL_FALSE
/* aux */);
1307 driDrawPriv
->driverPrivate
= (void *) fb
;
1309 return (driDrawPriv
->driverPrivate
!= NULL
);
1314 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1316 * \todo This function (and its interface) will need to be updated to support
1320 radeonCreateBuffer( __DRIscreenPrivate
*driScrnPriv
,
1321 __DRIdrawablePrivate
*driDrawPriv
,
1322 const __GLcontextModes
*mesaVis
,
1323 GLboolean isPixmap
)
1325 radeonScreenPtr screen
= (radeonScreenPtr
) driScrnPriv
->private;
1328 return GL_FALSE
; /* not implemented */
1331 const GLboolean swDepth
= GL_FALSE
;
1332 const GLboolean swAlpha
= GL_FALSE
;
1333 const GLboolean swAccum
= mesaVis
->accumRedBits
> 0;
1334 const GLboolean swStencil
= mesaVis
->stencilBits
> 0 &&
1335 mesaVis
->depthBits
!= 24;
1336 struct gl_framebuffer
*fb
= _mesa_create_framebuffer(mesaVis
);
1338 /* front color renderbuffer */
1340 driRenderbuffer
*frontRb
1341 = driNewRenderbuffer(GL_RGBA
,
1342 driScrnPriv
->pFB
+ screen
->frontOffset
,
1344 screen
->frontOffset
, screen
->frontPitch
,
1346 radeonSetSpanFunctions(frontRb
, mesaVis
);
1347 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &frontRb
->Base
);
1350 /* back color renderbuffer */
1351 if (mesaVis
->doubleBufferMode
) {
1352 driRenderbuffer
*backRb
1353 = driNewRenderbuffer(GL_RGBA
,
1354 driScrnPriv
->pFB
+ screen
->backOffset
,
1356 screen
->backOffset
, screen
->backPitch
,
1358 radeonSetSpanFunctions(backRb
, mesaVis
);
1359 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &backRb
->Base
);
1362 /* depth renderbuffer */
1363 if (mesaVis
->depthBits
== 16) {
1364 driRenderbuffer
*depthRb
1365 = driNewRenderbuffer(GL_DEPTH_COMPONENT16
,
1366 driScrnPriv
->pFB
+ screen
->depthOffset
,
1368 screen
->depthOffset
, screen
->depthPitch
,
1370 radeonSetSpanFunctions(depthRb
, mesaVis
);
1371 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &depthRb
->Base
);
1372 // depthRb->has_surface = screen->depthHasSurface;
1374 else if (mesaVis
->depthBits
== 24) {
1375 driRenderbuffer
*depthRb
1376 = driNewRenderbuffer(GL_DEPTH_COMPONENT24
,
1377 driScrnPriv
->pFB
+ screen
->depthOffset
,
1379 screen
->depthOffset
, screen
->depthPitch
,
1381 radeonSetSpanFunctions(depthRb
, mesaVis
);
1382 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &depthRb
->Base
);
1383 // depthRb->has_surface = screen->depthHasSurface;
1386 /* stencil renderbuffer */
1387 if (mesaVis
->stencilBits
> 0 && !swStencil
) {
1388 driRenderbuffer
*stencilRb
1389 = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT
,
1390 driScrnPriv
->pFB
+ screen
->depthOffset
,
1392 screen
->depthOffset
, screen
->depthPitch
,
1394 radeonSetSpanFunctions(stencilRb
, mesaVis
);
1395 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &stencilRb
->Base
);
1396 //stencilRb->has_surface = screen->depthHasSurface;
1399 _mesa_add_soft_renderbuffers(fb
,
1400 GL_FALSE
, /* color */
1405 GL_FALSE
/* aux */);
1406 driDrawPriv
->driverPrivate
= (void *) fb
;
1408 return (driDrawPriv
->driverPrivate
!= NULL
);
1414 radeonDestroyBuffer(__DRIdrawablePrivate
*driDrawPriv
)
1416 struct radeon_renderbuffer
*rb
;
1419 fb
= (void*)driDrawPriv
->driverPrivate
;
1420 rb
= (void *)fb
->Attachment
[BUFFER_FRONT_LEFT
].Renderbuffer
;
1422 radeon_bo_unref(rb
->bo
);
1425 rb
= (void *)fb
->Attachment
[BUFFER_BACK_LEFT
].Renderbuffer
;
1427 radeon_bo_unref(rb
->bo
);
1430 rb
= (void *)fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
;
1432 radeon_bo_unref(rb
->bo
);
1435 _mesa_unreference_framebuffer((GLframebuffer
**)(&(driDrawPriv
->driverPrivate
)));
1438 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1440 * Choose the appropriate CreateContext function based on the chipset.
1441 * Eventually, all drivers will go through this process.
1443 static GLboolean
radeonCreateContext(const __GLcontextModes
* glVisual
,
1444 __DRIcontextPrivate
* driContextPriv
,
1445 void *sharedContextPriv
)
1447 __DRIscreenPrivate
*sPriv
= driContextPriv
->driScreenPriv
;
1448 radeonScreenPtr screen
= (radeonScreenPtr
) (sPriv
->private);
1450 if (IS_R300_CLASS(screen
))
1451 return r300CreateContext(glVisual
, driContextPriv
, sharedContextPriv
);
1456 * Choose the appropriate DestroyContext function based on the chipset.
1458 static void radeonDestroyContext(__DRIcontextPrivate
* driContextPriv
)
1460 radeonContextPtr radeon
= (radeonContextPtr
) driContextPriv
->driverPrivate
;
1462 if (IS_R300_CLASS(radeon
->radeonScreen
))
1463 return r300DestroyContext(driContextPriv
);
1470 * This is the driver specific part of the createNewScreen entry point.
1472 * \todo maybe fold this into intelInitDriver
1474 * \return the __GLcontextModes supported by this driver
1476 static const __DRIconfig
**
1477 radeonInitScreen(__DRIscreenPrivate
*psp
)
1480 static const char *driver_name
= "Radeon";
1481 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1482 static const __DRIversion dri_expected
= { 4, 0, 0 };
1483 static const __DRIversion drm_expected
= { 1, 6, 0 };
1484 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1485 static const char *driver_name
= "R200";
1486 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1487 static const __DRIversion dri_expected
= { 4, 0, 0 };
1488 static const __DRIversion drm_expected
= { 1, 6, 0 };
1489 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1490 static const char *driver_name
= "R300";
1491 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1492 static const __DRIversion dri_expected
= { 4, 0, 0 };
1493 static const __DRIversion drm_expected
= { 1, 24, 0 };
1495 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
) psp
->pDevPriv
;
1497 if ( ! driCheckDriDdxDrmVersions3( driver_name
,
1498 &psp
->dri_version
, & dri_expected
,
1499 &psp
->ddx_version
, & ddx_expected
,
1500 &psp
->drm_version
, & drm_expected
) ) {
1504 /* Calling driInitExtensions here, with a NULL context pointer,
1505 * does not actually enable the extensions. It just makes sure
1506 * that all the dispatch offsets for all the extensions that
1507 * *might* be enables are known. This is needed because the
1508 * dispatch offsets need to be known when _mesa_context_create
1509 * is called, but we can't enable the extensions until we have a
1512 * Hello chicken. Hello egg. How are you two today?
1514 driInitExtensions( NULL
, card_extensions
, GL_FALSE
);
1515 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1516 driInitExtensions( NULL
, blend_extensions
, GL_FALSE
);
1517 driInitSingleExtension( NULL
, ARB_vp_extension
);
1518 driInitSingleExtension( NULL
, NV_vp_extension
);
1519 driInitSingleExtension( NULL
, ATI_fs_extension
);
1520 driInitExtensions( NULL
, point_extensions
, GL_FALSE
);
1523 if (!radeonInitDriver(psp
))
1526 /* for now fill in all modes */
1527 return radeonFillInModes( psp
,
1529 (dri_priv
->bpp
== 16) ? 16 : 24,
1530 (dri_priv
->bpp
== 16) ? 0 : 8, 1);
1534 * This is the driver specific part of the createNewScreen entry point.
1535 * Called when using DRI2.
1537 * \return the __GLcontextModes supported by this driver
1540 __DRIconfig
**radeonInitScreen2(__DRIscreenPrivate
*psp
)
1542 /* Calling driInitExtensions here, with a NULL context pointer,
1543 * does not actually enable the extensions. It just makes sure
1544 * that all the dispatch offsets for all the extensions that
1545 * *might* be enables are known. This is needed because the
1546 * dispatch offsets need to be known when _mesa_context_create
1547 * is called, but we can't enable the extensions until we have a
1550 * Hello chicken. Hello egg. How are you two today?
1552 driInitExtensions( NULL
, card_extensions
, GL_FALSE
);
1553 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1554 driInitExtensions( NULL
, blend_extensions
, GL_FALSE
);
1555 driInitSingleExtension( NULL
, ARB_vp_extension
);
1556 driInitSingleExtension( NULL
, NV_vp_extension
);
1557 driInitSingleExtension( NULL
, ATI_fs_extension
);
1558 driInitExtensions( NULL
, point_extensions
, GL_FALSE
);
1561 if (!radeonInitDriver(psp
)) {
1565 /* for now fill in all modes */
1566 return radeonFillInModes( psp
, 24, 24, 8, 1);
1570 * Get information about previous buffer swaps.
1573 getSwapInfo( __DRIdrawablePrivate
*dPriv
, __DRIswapInfo
* sInfo
)
1575 radeonContextPtr rmesa
;
1577 if ( (dPriv
== NULL
) || (dPriv
->driContextPriv
== NULL
)
1578 || (dPriv
->driContextPriv
->driverPrivate
== NULL
)
1579 || (sInfo
== NULL
) ) {
1583 rmesa
= dPriv
->driContextPriv
->driverPrivate
;
1584 sInfo
->swap_count
= rmesa
->swap_count
;
1585 sInfo
->swap_ust
= rmesa
->swap_ust
;
1586 sInfo
->swap_missed_count
= rmesa
->swap_missed_count
;
1588 sInfo
->swap_missed_usage
= (sInfo
->swap_missed_count
!= 0)
1589 ? driCalculateSwapUsage( dPriv
, 0, rmesa
->swap_missed_ust
)
1595 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1596 const struct __DriverAPIRec driDriverAPI
= {
1597 .InitScreen
= radeonInitScreen
,
1598 .DestroyScreen
= radeonDestroyScreen
,
1599 .CreateContext
= radeonCreateContext
,
1600 .DestroyContext
= radeonDestroyContext
,
1601 .CreateBuffer
= radeonCreateBuffer
,
1602 .DestroyBuffer
= radeonDestroyBuffer
,
1603 .SwapBuffers
= radeonSwapBuffers
,
1604 .MakeCurrent
= radeonMakeCurrent
,
1605 .UnbindContext
= radeonUnbindContext
,
1606 .GetSwapInfo
= getSwapInfo
,
1607 .GetDrawableMSC
= driDrawableGetMSC32
,
1608 .WaitForMSC
= driWaitForMSC32
,
1610 .SwapBuffersMSC
= NULL
,
1611 .CopySubBuffer
= radeonCopySubBuffer
,
1613 .InitScreen2
= radeonInitScreen2
,
1616 const struct __DriverAPIRec driDriverAPI
= {
1617 .InitScreen
= radeonInitScreen
,
1618 .DestroyScreen
= radeonDestroyScreen
,
1619 .CreateContext
= r200CreateContext
,
1620 .DestroyContext
= r200DestroyContext
,
1621 .CreateBuffer
= radeonCreateBuffer
,
1622 .DestroyBuffer
= radeonDestroyBuffer
,
1623 .SwapBuffers
= r200SwapBuffers
,
1624 .MakeCurrent
= r200MakeCurrent
,
1625 .UnbindContext
= r200UnbindContext
,
1626 .GetSwapInfo
= getSwapInfo
,
1627 .GetDrawableMSC
= driDrawableGetMSC32
,
1628 .WaitForMSC
= driWaitForMSC32
,
1630 .SwapBuffersMSC
= NULL
,
1631 .CopySubBuffer
= r200CopySubBuffer
,