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r200: fix glean pixelFormats regression
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
36 */
37
38 #include <errno.h>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
44
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #include "radeon_common.h"
50 #include "radeon_span.h"
51 #if !RADEON_COMMON
52 #include "radeon_context.h"
53 #include "radeon_tex.h"
54 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
55 #include "r200_context.h"
56 #include "r200_ioctl.h"
57 #include "r200_tex.h"
58 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
59 #include "r300_context.h"
60 #include "r300_fragprog.h"
61 #include "r300_tex.h"
62 #endif
63
64 #include "utils.h"
65 #include "vblank.h"
66 #include "drirenderbuffer.h"
67
68 #include "radeon_bocs_wrapper.h"
69
70 #include "GL/internal/dri_interface.h"
71
72 /* Radeon configuration
73 */
74 #include "xmlpool.h"
75
76 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
77 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
78 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
79 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
80 DRI_CONF_OPT_END
81
82 #if !RADEON_COMMON /* R100 */
83 PUBLIC const char __driConfigOptions[] =
84 DRI_CONF_BEGIN
85 DRI_CONF_SECTION_PERFORMANCE
86 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
87 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
88 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
89 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
90 DRI_CONF_HYPERZ(false)
91 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
92 DRI_CONF_SECTION_END
93 DRI_CONF_SECTION_QUALITY
94 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
95 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
96 DRI_CONF_NO_NEG_LOD_BIAS(false)
97 DRI_CONF_FORCE_S3TC_ENABLE(false)
98 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
99 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
100 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
101 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
102 DRI_CONF_SECTION_END
103 DRI_CONF_SECTION_DEBUG
104 DRI_CONF_NO_RAST(false)
105 DRI_CONF_SECTION_END
106 DRI_CONF_END;
107 static const GLuint __driNConfigOptions = 15;
108
109 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
110
111 PUBLIC const char __driConfigOptions[] =
112 DRI_CONF_BEGIN
113 DRI_CONF_SECTION_PERFORMANCE
114 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
115 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
116 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
117 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
118 DRI_CONF_HYPERZ(false)
119 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
120 DRI_CONF_SECTION_END
121 DRI_CONF_SECTION_QUALITY
122 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
123 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
124 DRI_CONF_NO_NEG_LOD_BIAS(false)
125 DRI_CONF_FORCE_S3TC_ENABLE(false)
126 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
127 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
128 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
129 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
130 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
131 DRI_CONF_SECTION_END
132 DRI_CONF_SECTION_DEBUG
133 DRI_CONF_NO_RAST(false)
134 DRI_CONF_SECTION_END
135 DRI_CONF_SECTION_SOFTWARE
136 DRI_CONF_NV_VERTEX_PROGRAM(false)
137 DRI_CONF_SECTION_END
138 DRI_CONF_END;
139 static const GLuint __driNConfigOptions = 17;
140
141 extern const struct dri_extension blend_extensions[];
142 extern const struct dri_extension ARB_vp_extension[];
143 extern const struct dri_extension NV_vp_extension[];
144 extern const struct dri_extension ATI_fs_extension[];
145 extern const struct dri_extension point_extensions[];
146
147 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
148
149 /* TODO: integrate these into xmlpool.h! */
150 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
151 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
152 DRI_CONF_DESC(en,"Number of texture image units") \
153 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
154 DRI_CONF_OPT_END
155
156 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
157 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
158 DRI_CONF_DESC(en,"Number of texture coordinate units") \
159 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
160 DRI_CONF_OPT_END
161
162
163
164 #define DRI_CONF_DISABLE_S3TC(def) \
165 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
166 DRI_CONF_DESC(en,"Disable S3TC compression") \
167 DRI_CONF_OPT_END
168
169 #define DRI_CONF_DISABLE_FALLBACK(def) \
170 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
171 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
172 DRI_CONF_OPT_END
173
174 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
175 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
176 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
177 DRI_CONF_OPT_END
178
179 #define DRI_CONF_FP_OPTIMIZATION(def) \
180 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
181 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
182 DRI_CONF_ENUM(0,"Optimize for Speed") \
183 DRI_CONF_ENUM(1,"Optimize for Quality") \
184 DRI_CONF_DESC_END \
185 DRI_CONF_OPT_END
186
187 PUBLIC const char __driConfigOptions[] =
188 DRI_CONF_BEGIN
189 DRI_CONF_SECTION_PERFORMANCE
190 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
191 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
192 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
193 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
194 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
195 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
196 DRI_CONF_DISABLE_FALLBACK(true)
197 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
198 DRI_CONF_SECTION_END
199 DRI_CONF_SECTION_QUALITY
200 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
201 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
202 DRI_CONF_FORCE_S3TC_ENABLE(false)
203 DRI_CONF_DISABLE_S3TC(false)
204 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
205 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
206 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
207 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
208 DRI_CONF_SECTION_END
209 DRI_CONF_SECTION_DEBUG
210 DRI_CONF_NO_RAST(false)
211 DRI_CONF_SECTION_END
212 DRI_CONF_END;
213 static const GLuint __driNConfigOptions = 17;
214
215 extern const struct dri_extension gl_20_extension[];
216
217 #ifndef RADEON_DEBUG
218
219 static const struct dri_debug_control debug_control[] = {
220 {"fall", DEBUG_FALLBACKS},
221 {"tex", DEBUG_TEXTURE},
222 {"ioctl", DEBUG_IOCTL},
223 {"prim", DEBUG_PRIMS},
224 {"vert", DEBUG_VERTS},
225 {"state", DEBUG_STATE},
226 {"code", DEBUG_CODEGEN},
227 {"vfmt", DEBUG_VFMT},
228 {"vtxf", DEBUG_VFMT},
229 {"verb", DEBUG_VERBOSE},
230 {"dri", DEBUG_DRI},
231 {"dma", DEBUG_DMA},
232 {"san", DEBUG_SANITY},
233 {"sync", DEBUG_SYNC},
234 {"pix", DEBUG_PIXEL},
235 {"mem", DEBUG_MEMORY},
236 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
237 {NULL, 0}
238 };
239 #endif /* RADEON_DEBUG */
240
241 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
242
243 extern const struct dri_extension card_extensions[];
244 extern const struct dri_extension mm_extensions[];
245
246 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
247
248 static int
249 radeonGetParam(int fd, int param, void *value)
250 {
251 int ret;
252 drm_radeon_getparam_t gp;
253
254 gp.param = param;
255 gp.value = value;
256
257 ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
258 return ret;
259 }
260
261 static const __DRIconfig **
262 radeonFillInModes( __DRIscreenPrivate *psp,
263 unsigned pixel_bits, unsigned depth_bits,
264 unsigned stencil_bits, GLboolean have_back_buffer )
265 {
266 __DRIconfig **configs;
267 __GLcontextModes *m;
268 unsigned depth_buffer_factor;
269 unsigned back_buffer_factor;
270 GLenum fb_format;
271 GLenum fb_type;
272 int i;
273
274 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
275 * enough to add support. Basically, if a context is created with an
276 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
277 * will never be used.
278 */
279 static const GLenum back_buffer_modes[] = {
280 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
281 };
282
283 uint8_t depth_bits_array[2];
284 uint8_t stencil_bits_array[2];
285 uint8_t msaa_samples_array[1];
286
287 depth_bits_array[0] = depth_bits;
288 depth_bits_array[1] = depth_bits;
289
290 /* Just like with the accumulation buffer, always provide some modes
291 * with a stencil buffer. It will be a sw fallback, but some apps won't
292 * care about that.
293 */
294 stencil_bits_array[0] = 0;
295 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
296
297 msaa_samples_array[0] = 0;
298
299 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
300 back_buffer_factor = (have_back_buffer) ? 2 : 1;
301
302 if ( pixel_bits == 16 ) {
303 fb_format = GL_RGB;
304 fb_type = GL_UNSIGNED_SHORT_5_6_5;
305 }
306 else {
307 fb_format = GL_BGRA;
308 fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
309 }
310
311 configs = driCreateConfigs(fb_format, fb_type,
312 depth_bits_array, stencil_bits_array,
313 depth_buffer_factor,
314 back_buffer_modes, back_buffer_factor,
315 msaa_samples_array, 1);
316 if (configs == NULL) {
317 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
318 __func__, __LINE__ );
319 return NULL;
320 }
321
322 /* Mark the visual as slow if there are "fake" stencil bits.
323 */
324 for (i = 0; configs[i]; i++) {
325 m = &configs[i]->modes;
326 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
327 m->visualRating = GLX_SLOW_CONFIG;
328 }
329 }
330
331 return (const __DRIconfig **) configs;
332 }
333
334 #if !RADEON_COMMON
335 static const __DRItexOffsetExtension radeonTexOffsetExtension = {
336 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
337 radeonSetTexOffset,
338 };
339
340 static const __DRItexBufferExtension radeonTexBufferExtension = {
341 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
342 radeonSetTexBuffer,
343 radeonSetTexBuffer2,
344 };
345 #endif
346
347 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
348 static const __DRIallocateExtension r200AllocateExtension = {
349 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
350 r200AllocateMemoryMESA,
351 r200FreeMemoryMESA,
352 r200GetMemoryOffsetMESA
353 };
354
355 static const __DRItexOffsetExtension r200texOffsetExtension = {
356 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
357 r200SetTexOffset,
358 };
359
360 static const __DRItexBufferExtension r200TexBufferExtension = {
361 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
362 r200SetTexBuffer,
363 r200SetTexBuffer2,
364 };
365 #endif
366
367 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
368 static const __DRItexOffsetExtension r300texOffsetExtension = {
369 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
370 r300SetTexOffset,
371 };
372
373 static const __DRItexBufferExtension r300TexBufferExtension = {
374 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
375 r300SetTexBuffer,
376 r300SetTexBuffer2,
377 };
378 #endif
379
380 static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
381 {
382 screen->chip_flags = 0;
383 switch ( device_id ) {
384 case PCI_CHIP_RADEON_LY:
385 case PCI_CHIP_RADEON_LZ:
386 case PCI_CHIP_RADEON_QY:
387 case PCI_CHIP_RADEON_QZ:
388 case PCI_CHIP_RN50_515E:
389 case PCI_CHIP_RN50_5969:
390 screen->chip_family = CHIP_FAMILY_RV100;
391 break;
392
393 case PCI_CHIP_RS100_4136:
394 case PCI_CHIP_RS100_4336:
395 screen->chip_family = CHIP_FAMILY_RS100;
396 break;
397
398 case PCI_CHIP_RS200_4137:
399 case PCI_CHIP_RS200_4337:
400 case PCI_CHIP_RS250_4237:
401 case PCI_CHIP_RS250_4437:
402 screen->chip_family = CHIP_FAMILY_RS200;
403 break;
404
405 case PCI_CHIP_RADEON_QD:
406 case PCI_CHIP_RADEON_QE:
407 case PCI_CHIP_RADEON_QF:
408 case PCI_CHIP_RADEON_QG:
409 /* all original radeons (7200) presumably have a stencil op bug */
410 screen->chip_family = CHIP_FAMILY_R100;
411 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
412 break;
413
414 case PCI_CHIP_RV200_QW:
415 case PCI_CHIP_RV200_QX:
416 case PCI_CHIP_RADEON_LW:
417 case PCI_CHIP_RADEON_LX:
418 screen->chip_family = CHIP_FAMILY_RV200;
419 screen->chip_flags = RADEON_CHIPSET_TCL;
420 break;
421
422 case PCI_CHIP_R200_BB:
423 case PCI_CHIP_R200_BC:
424 case PCI_CHIP_R200_QH:
425 case PCI_CHIP_R200_QL:
426 case PCI_CHIP_R200_QM:
427 screen->chip_family = CHIP_FAMILY_R200;
428 screen->chip_flags = RADEON_CHIPSET_TCL;
429 break;
430
431 case PCI_CHIP_RV250_If:
432 case PCI_CHIP_RV250_Ig:
433 case PCI_CHIP_RV250_Ld:
434 case PCI_CHIP_RV250_Lf:
435 case PCI_CHIP_RV250_Lg:
436 screen->chip_family = CHIP_FAMILY_RV250;
437 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
438 break;
439
440 case PCI_CHIP_RV280_5960:
441 case PCI_CHIP_RV280_5961:
442 case PCI_CHIP_RV280_5962:
443 case PCI_CHIP_RV280_5964:
444 case PCI_CHIP_RV280_5965:
445 case PCI_CHIP_RV280_5C61:
446 case PCI_CHIP_RV280_5C63:
447 screen->chip_family = CHIP_FAMILY_RV280;
448 screen->chip_flags = RADEON_CHIPSET_TCL;
449 break;
450
451 case PCI_CHIP_RS300_5834:
452 case PCI_CHIP_RS300_5835:
453 case PCI_CHIP_RS350_7834:
454 case PCI_CHIP_RS350_7835:
455 screen->chip_family = CHIP_FAMILY_RS300;
456 break;
457
458 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
459 case PCI_CHIP_R300_AD:
460 screen->chip_family = CHIP_FAMILY_RV350;
461 screen->chip_flags = RADEON_CHIPSET_TCL;
462 break;
463 case PCI_CHIP_R300_AE:
464 case PCI_CHIP_R300_AF:
465 case PCI_CHIP_R300_AG:
466 case PCI_CHIP_R300_ND:
467 case PCI_CHIP_R300_NE:
468 case PCI_CHIP_R300_NF:
469 case PCI_CHIP_R300_NG:
470 screen->chip_family = CHIP_FAMILY_R300;
471 screen->chip_flags = RADEON_CHIPSET_TCL;
472 break;
473
474 case PCI_CHIP_RV350_AP:
475 case PCI_CHIP_RV350_AQ:
476 case PCI_CHIP_RV350_AR:
477 case PCI_CHIP_RV350_AS:
478 case PCI_CHIP_RV350_AT:
479 case PCI_CHIP_RV350_AV:
480 case PCI_CHIP_RV350_AU:
481 case PCI_CHIP_RV350_NP:
482 case PCI_CHIP_RV350_NQ:
483 case PCI_CHIP_RV350_NR:
484 case PCI_CHIP_RV350_NS:
485 case PCI_CHIP_RV350_NT:
486 case PCI_CHIP_RV350_NV:
487 screen->chip_family = CHIP_FAMILY_RV350;
488 screen->chip_flags = RADEON_CHIPSET_TCL;
489 break;
490
491 case PCI_CHIP_R350_AH:
492 case PCI_CHIP_R350_AI:
493 case PCI_CHIP_R350_AJ:
494 case PCI_CHIP_R350_AK:
495 case PCI_CHIP_R350_NH:
496 case PCI_CHIP_R350_NI:
497 case PCI_CHIP_R360_NJ:
498 case PCI_CHIP_R350_NK:
499 screen->chip_family = CHIP_FAMILY_R350;
500 screen->chip_flags = RADEON_CHIPSET_TCL;
501 break;
502
503 case PCI_CHIP_RV370_5460:
504 case PCI_CHIP_RV370_5462:
505 case PCI_CHIP_RV370_5464:
506 case PCI_CHIP_RV370_5B60:
507 case PCI_CHIP_RV370_5B62:
508 case PCI_CHIP_RV370_5B63:
509 case PCI_CHIP_RV370_5B64:
510 case PCI_CHIP_RV370_5B65:
511 case PCI_CHIP_RV380_3150:
512 case PCI_CHIP_RV380_3152:
513 case PCI_CHIP_RV380_3154:
514 case PCI_CHIP_RV380_3E50:
515 case PCI_CHIP_RV380_3E54:
516 screen->chip_family = CHIP_FAMILY_RV380;
517 screen->chip_flags = RADEON_CHIPSET_TCL;
518 break;
519
520 case PCI_CHIP_R420_JN:
521 case PCI_CHIP_R420_JH:
522 case PCI_CHIP_R420_JI:
523 case PCI_CHIP_R420_JJ:
524 case PCI_CHIP_R420_JK:
525 case PCI_CHIP_R420_JL:
526 case PCI_CHIP_R420_JM:
527 case PCI_CHIP_R420_JO:
528 case PCI_CHIP_R420_JP:
529 case PCI_CHIP_R420_JT:
530 case PCI_CHIP_R481_4B49:
531 case PCI_CHIP_R481_4B4A:
532 case PCI_CHIP_R481_4B4B:
533 case PCI_CHIP_R481_4B4C:
534 case PCI_CHIP_R423_UH:
535 case PCI_CHIP_R423_UI:
536 case PCI_CHIP_R423_UJ:
537 case PCI_CHIP_R423_UK:
538 case PCI_CHIP_R430_554C:
539 case PCI_CHIP_R430_554D:
540 case PCI_CHIP_R430_554E:
541 case PCI_CHIP_R430_554F:
542 case PCI_CHIP_R423_5550:
543 case PCI_CHIP_R423_UQ:
544 case PCI_CHIP_R423_UR:
545 case PCI_CHIP_R423_UT:
546 case PCI_CHIP_R430_5D48:
547 case PCI_CHIP_R430_5D49:
548 case PCI_CHIP_R430_5D4A:
549 case PCI_CHIP_R480_5D4C:
550 case PCI_CHIP_R480_5D4D:
551 case PCI_CHIP_R480_5D4E:
552 case PCI_CHIP_R480_5D4F:
553 case PCI_CHIP_R480_5D50:
554 case PCI_CHIP_R480_5D52:
555 case PCI_CHIP_R423_5D57:
556 screen->chip_family = CHIP_FAMILY_R420;
557 screen->chip_flags = RADEON_CHIPSET_TCL;
558 break;
559
560 case PCI_CHIP_RV410_5E4C:
561 case PCI_CHIP_RV410_5E4F:
562 case PCI_CHIP_RV410_564A:
563 case PCI_CHIP_RV410_564B:
564 case PCI_CHIP_RV410_564F:
565 case PCI_CHIP_RV410_5652:
566 case PCI_CHIP_RV410_5653:
567 case PCI_CHIP_RV410_5657:
568 case PCI_CHIP_RV410_5E48:
569 case PCI_CHIP_RV410_5E4A:
570 case PCI_CHIP_RV410_5E4B:
571 case PCI_CHIP_RV410_5E4D:
572 screen->chip_family = CHIP_FAMILY_RV410;
573 screen->chip_flags = RADEON_CHIPSET_TCL;
574 break;
575
576 case PCI_CHIP_RS480_5954:
577 case PCI_CHIP_RS480_5955:
578 case PCI_CHIP_RS482_5974:
579 case PCI_CHIP_RS482_5975:
580 case PCI_CHIP_RS400_5A41:
581 case PCI_CHIP_RS400_5A42:
582 case PCI_CHIP_RC410_5A61:
583 case PCI_CHIP_RC410_5A62:
584 screen->chip_family = CHIP_FAMILY_RS400;
585 break;
586
587 case PCI_CHIP_RS600_793F:
588 case PCI_CHIP_RS600_7941:
589 case PCI_CHIP_RS600_7942:
590 screen->chip_family = CHIP_FAMILY_RS600;
591 break;
592
593 case PCI_CHIP_RS690_791E:
594 case PCI_CHIP_RS690_791F:
595 screen->chip_family = CHIP_FAMILY_RS690;
596 break;
597 case PCI_CHIP_RS740_796C:
598 case PCI_CHIP_RS740_796D:
599 case PCI_CHIP_RS740_796E:
600 case PCI_CHIP_RS740_796F:
601 screen->chip_family = CHIP_FAMILY_RS740;
602 break;
603
604 case PCI_CHIP_R520_7100:
605 case PCI_CHIP_R520_7101:
606 case PCI_CHIP_R520_7102:
607 case PCI_CHIP_R520_7103:
608 case PCI_CHIP_R520_7104:
609 case PCI_CHIP_R520_7105:
610 case PCI_CHIP_R520_7106:
611 case PCI_CHIP_R520_7108:
612 case PCI_CHIP_R520_7109:
613 case PCI_CHIP_R520_710A:
614 case PCI_CHIP_R520_710B:
615 case PCI_CHIP_R520_710C:
616 case PCI_CHIP_R520_710E:
617 case PCI_CHIP_R520_710F:
618 screen->chip_family = CHIP_FAMILY_R520;
619 screen->chip_flags = RADEON_CHIPSET_TCL;
620 break;
621
622 case PCI_CHIP_RV515_7140:
623 case PCI_CHIP_RV515_7141:
624 case PCI_CHIP_RV515_7142:
625 case PCI_CHIP_RV515_7143:
626 case PCI_CHIP_RV515_7144:
627 case PCI_CHIP_RV515_7145:
628 case PCI_CHIP_RV515_7146:
629 case PCI_CHIP_RV515_7147:
630 case PCI_CHIP_RV515_7149:
631 case PCI_CHIP_RV515_714A:
632 case PCI_CHIP_RV515_714B:
633 case PCI_CHIP_RV515_714C:
634 case PCI_CHIP_RV515_714D:
635 case PCI_CHIP_RV515_714E:
636 case PCI_CHIP_RV515_714F:
637 case PCI_CHIP_RV515_7151:
638 case PCI_CHIP_RV515_7152:
639 case PCI_CHIP_RV515_7153:
640 case PCI_CHIP_RV515_715E:
641 case PCI_CHIP_RV515_715F:
642 case PCI_CHIP_RV515_7180:
643 case PCI_CHIP_RV515_7181:
644 case PCI_CHIP_RV515_7183:
645 case PCI_CHIP_RV515_7186:
646 case PCI_CHIP_RV515_7187:
647 case PCI_CHIP_RV515_7188:
648 case PCI_CHIP_RV515_718A:
649 case PCI_CHIP_RV515_718B:
650 case PCI_CHIP_RV515_718C:
651 case PCI_CHIP_RV515_718D:
652 case PCI_CHIP_RV515_718F:
653 case PCI_CHIP_RV515_7193:
654 case PCI_CHIP_RV515_7196:
655 case PCI_CHIP_RV515_719B:
656 case PCI_CHIP_RV515_719F:
657 case PCI_CHIP_RV515_7200:
658 case PCI_CHIP_RV515_7210:
659 case PCI_CHIP_RV515_7211:
660 screen->chip_family = CHIP_FAMILY_RV515;
661 screen->chip_flags = RADEON_CHIPSET_TCL;
662 break;
663
664 case PCI_CHIP_RV530_71C0:
665 case PCI_CHIP_RV530_71C1:
666 case PCI_CHIP_RV530_71C2:
667 case PCI_CHIP_RV530_71C3:
668 case PCI_CHIP_RV530_71C4:
669 case PCI_CHIP_RV530_71C5:
670 case PCI_CHIP_RV530_71C6:
671 case PCI_CHIP_RV530_71C7:
672 case PCI_CHIP_RV530_71CD:
673 case PCI_CHIP_RV530_71CE:
674 case PCI_CHIP_RV530_71D2:
675 case PCI_CHIP_RV530_71D4:
676 case PCI_CHIP_RV530_71D5:
677 case PCI_CHIP_RV530_71D6:
678 case PCI_CHIP_RV530_71DA:
679 case PCI_CHIP_RV530_71DE:
680 screen->chip_family = CHIP_FAMILY_RV530;
681 screen->chip_flags = RADEON_CHIPSET_TCL;
682 break;
683
684 case PCI_CHIP_R580_7240:
685 case PCI_CHIP_R580_7243:
686 case PCI_CHIP_R580_7244:
687 case PCI_CHIP_R580_7245:
688 case PCI_CHIP_R580_7246:
689 case PCI_CHIP_R580_7247:
690 case PCI_CHIP_R580_7248:
691 case PCI_CHIP_R580_7249:
692 case PCI_CHIP_R580_724A:
693 case PCI_CHIP_R580_724B:
694 case PCI_CHIP_R580_724C:
695 case PCI_CHIP_R580_724D:
696 case PCI_CHIP_R580_724E:
697 case PCI_CHIP_R580_724F:
698 case PCI_CHIP_R580_7284:
699 screen->chip_family = CHIP_FAMILY_R580;
700 screen->chip_flags = RADEON_CHIPSET_TCL;
701 break;
702
703 case PCI_CHIP_RV570_7280:
704 case PCI_CHIP_RV560_7281:
705 case PCI_CHIP_RV560_7283:
706 case PCI_CHIP_RV560_7287:
707 case PCI_CHIP_RV570_7288:
708 case PCI_CHIP_RV570_7289:
709 case PCI_CHIP_RV570_728B:
710 case PCI_CHIP_RV570_728C:
711 case PCI_CHIP_RV560_7290:
712 case PCI_CHIP_RV560_7291:
713 case PCI_CHIP_RV560_7293:
714 case PCI_CHIP_RV560_7297:
715 screen->chip_family = CHIP_FAMILY_RV560;
716 screen->chip_flags = RADEON_CHIPSET_TCL;
717 break;
718
719 default:
720 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
721 device_id);
722 return -1;
723 }
724
725 return 0;
726 }
727
728
729 /* Create the device specific screen private data struct.
730 */
731 static radeonScreenPtr
732 radeonCreateScreen( __DRIscreenPrivate *sPriv )
733 {
734 radeonScreenPtr screen;
735 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
736 unsigned char *RADEONMMIO = NULL;
737 int i;
738 int ret;
739 uint32_t temp = 0;
740
741 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
742 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
743 return GL_FALSE;
744 }
745
746 /* Allocate the private area */
747 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
748 if ( !screen ) {
749 __driUtilMessage("%s: Could not allocate memory for screen structure",
750 __FUNCTION__);
751 return NULL;
752 }
753
754 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
755 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
756 #endif
757
758 /* parse information in __driConfigOptions */
759 driParseOptionInfo (&screen->optionCache,
760 __driConfigOptions, __driNConfigOptions);
761
762 /* This is first since which regions we map depends on whether or
763 * not we are using a PCI card.
764 */
765 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
766 {
767 int ret;
768
769 #ifdef RADEON_PARAM_KERNEL_MM
770 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_KERNEL_MM,
771 &screen->kernel_mm);
772
773 if (ret && ret != -EINVAL) {
774 FREE( screen );
775 fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret);
776 return NULL;
777 }
778
779 if (ret == -EINVAL)
780 screen->kernel_mm = 0;
781 #endif
782
783 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET,
784 &screen->gart_buffer_offset);
785
786 if (ret) {
787 FREE( screen );
788 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
789 return NULL;
790 }
791
792 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE,
793 &screen->gart_base);
794 if (ret) {
795 FREE( screen );
796 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
797 return NULL;
798 }
799
800 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
801 &screen->irq);
802 if (ret) {
803 FREE( screen );
804 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
805 return NULL;
806 }
807 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
808 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
809 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
810 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
811 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
812 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
813 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
814 }
815
816 if (!screen->kernel_mm) {
817 screen->mmio.handle = dri_priv->registerHandle;
818 screen->mmio.size = dri_priv->registerSize;
819 if ( drmMap( sPriv->fd,
820 screen->mmio.handle,
821 screen->mmio.size,
822 &screen->mmio.map ) ) {
823 FREE( screen );
824 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
825 return NULL;
826 }
827
828 RADEONMMIO = screen->mmio.map;
829
830 screen->status.handle = dri_priv->statusHandle;
831 screen->status.size = dri_priv->statusSize;
832 if ( drmMap( sPriv->fd,
833 screen->status.handle,
834 screen->status.size,
835 &screen->status.map ) ) {
836 drmUnmap( screen->mmio.map, screen->mmio.size );
837 FREE( screen );
838 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
839 return NULL;
840 }
841 screen->scratch = (__volatile__ uint32_t *)
842 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
843
844 screen->buffers = drmMapBufs( sPriv->fd );
845 if ( !screen->buffers ) {
846 drmUnmap( screen->status.map, screen->status.size );
847 drmUnmap( screen->mmio.map, screen->mmio.size );
848 FREE( screen );
849 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
850 return NULL;
851 }
852
853 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
854 screen->gartTextures.handle = dri_priv->gartTexHandle;
855 screen->gartTextures.size = dri_priv->gartTexMapSize;
856 if ( drmMap( sPriv->fd,
857 screen->gartTextures.handle,
858 screen->gartTextures.size,
859 (drmAddressPtr)&screen->gartTextures.map ) ) {
860 drmUnmapBufs( screen->buffers );
861 drmUnmap( screen->status.map, screen->status.size );
862 drmUnmap( screen->mmio.map, screen->mmio.size );
863 FREE( screen );
864 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
865 return NULL;
866 }
867
868 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
869 }
870 }
871
872
873 ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
874 if (ret == -1)
875 return NULL;
876
877 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
878 sPriv->ddx_version.minor < 2) {
879 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
880 return NULL;
881 }
882
883 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
884 fprintf(stderr, "R500 support requires a newer drm.\n");
885 return NULL;
886 }
887
888 if (getenv("R300_NO_TCL"))
889 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
890
891 if (screen->chip_family <= CHIP_FAMILY_RS200)
892 screen->chip_flags |= RADEON_CLASS_R100;
893 else if (screen->chip_family <= CHIP_FAMILY_RV280)
894 screen->chip_flags |= RADEON_CLASS_R200;
895 else
896 screen->chip_flags |= RADEON_CLASS_R300;
897
898 screen->cpp = dri_priv->bpp / 8;
899 screen->AGPMode = dri_priv->AGPMode;
900
901 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION,
902 &temp);
903 if (ret) {
904 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm)
905 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
906 else {
907 FREE( screen );
908 fprintf(stderr, "Unable to get fb location need newer drm\n");
909 return NULL;
910 }
911 } else {
912 screen->fbLocation = (temp & 0xffff) << 16;
913 }
914
915 if (screen->chip_family >= CHIP_FAMILY_R300) {
916 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES,
917 &temp);
918 if (ret) {
919 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
920 switch (screen->chip_family) {
921 case CHIP_FAMILY_R300:
922 case CHIP_FAMILY_R350:
923 screen->num_gb_pipes = 2;
924 break;
925 case CHIP_FAMILY_R420:
926 case CHIP_FAMILY_R520:
927 case CHIP_FAMILY_R580:
928 case CHIP_FAMILY_RV560:
929 case CHIP_FAMILY_RV570:
930 screen->num_gb_pipes = 4;
931 break;
932 case CHIP_FAMILY_RV350:
933 case CHIP_FAMILY_RV515:
934 case CHIP_FAMILY_RV530:
935 case CHIP_FAMILY_RV410:
936 default:
937 screen->num_gb_pipes = 1;
938 break;
939 }
940 } else {
941 screen->num_gb_pipes = temp;
942 }
943 }
944
945 if ( sPriv->drm_version.minor >= 10 ) {
946 drm_radeon_setparam_t sp;
947
948 sp.param = RADEON_SETPARAM_FB_LOCATION;
949 sp.value = screen->fbLocation;
950
951 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
952 &sp, sizeof( sp ) );
953 }
954
955 screen->frontOffset = dri_priv->frontOffset;
956 screen->frontPitch = dri_priv->frontPitch;
957 screen->backOffset = dri_priv->backOffset;
958 screen->backPitch = dri_priv->backPitch;
959 screen->depthOffset = dri_priv->depthOffset;
960 screen->depthPitch = dri_priv->depthPitch;
961
962 /* Check if ddx has set up a surface reg to cover depth buffer */
963 screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
964 /* these chips don't use tiled z without hyperz. So always pretend
965 we have set up a surface which will cause linear reads/writes */
966 (IS_R100_CLASS(screen) &&
967 !(screen->chip_flags & RADEON_CHIPSET_TCL));
968
969 if ( dri_priv->textureSize == 0 ) {
970 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
971 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
972 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
973 dri_priv->log2GARTTexGran;
974 } else {
975 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
976 + screen->fbLocation;
977 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
978 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
979 dri_priv->log2TexGran;
980 }
981
982 if ( !screen->gartTextures.map || dri_priv->textureSize == 0
983 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
984 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
985 screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
986 screen->texSize[RADEON_GART_TEX_HEAP] = 0;
987 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
988 } else {
989 screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
990 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
991 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
992 screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
993 dri_priv->log2GARTTexGran;
994 }
995
996 i = 0;
997 screen->extensions[i++] = &driCopySubBufferExtension.base;
998 screen->extensions[i++] = &driFrameTrackingExtension.base;
999 screen->extensions[i++] = &driReadDrawableExtension;
1000
1001 if ( screen->irq != 0 ) {
1002 screen->extensions[i++] = &driSwapControlExtension.base;
1003 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1004 }
1005
1006 if (!screen->kernel_mm) {
1007 #if !RADEON_COMMON
1008 screen->extensions[i++] = &radeonTexOffsetExtension.base;
1009 #endif
1010
1011 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1012 if (IS_R200_CLASS(screen))
1013 screen->extensions[i++] = &r200AllocateExtension.base;
1014
1015 screen->extensions[i++] = &r200texOffsetExtension.base;
1016 #endif
1017
1018 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1019 screen->extensions[i++] = &r300texOffsetExtension.base;
1020 #endif
1021 }
1022
1023 screen->extensions[i++] = NULL;
1024 sPriv->extensions = screen->extensions;
1025
1026 screen->driScreen = sPriv;
1027 screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
1028 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
1029 screen->sarea_priv_offset);
1030
1031 if (screen->kernel_mm)
1032 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1033 else
1034 screen->bom = radeon_bo_manager_legacy_ctor(screen);
1035 if (screen->bom == NULL) {
1036 free(screen);
1037 return NULL;
1038 }
1039
1040 return screen;
1041 }
1042
1043 static radeonScreenPtr
1044 radeonCreateScreen2(__DRIscreenPrivate *sPriv)
1045 {
1046 radeonScreenPtr screen;
1047 int i;
1048 int ret;
1049 uint32_t device_id;
1050 uint32_t temp = 0;
1051
1052 /* Allocate the private area */
1053 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1054 if ( !screen ) {
1055 __driUtilMessage("%s: Could not allocate memory for screen structure",
1056 __FUNCTION__);
1057 fprintf(stderr, "leaving here\n");
1058 return NULL;
1059 }
1060
1061 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1062 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
1063 #endif
1064
1065 /* parse information in __driConfigOptions */
1066 driParseOptionInfo (&screen->optionCache,
1067 __driConfigOptions, __driNConfigOptions);
1068
1069 screen->kernel_mm = 1;
1070 screen->chip_flags = 0;
1071
1072 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
1073 &screen->irq);
1074
1075 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_DEVICE_ID,
1076 &device_id);
1077 if (ret) {
1078 FREE( screen );
1079 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret);
1080 return NULL;
1081 }
1082
1083 ret = radeon_set_screen_flags(screen, device_id);
1084 if (ret == -1)
1085 return NULL;
1086
1087 if (screen->chip_family >= CHIP_FAMILY_R300) {
1088 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES,
1089 &temp);
1090 if (ret) {
1091 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1092 switch (screen->chip_family) {
1093 case CHIP_FAMILY_R300:
1094 case CHIP_FAMILY_R350:
1095 screen->num_gb_pipes = 2;
1096 break;
1097 case CHIP_FAMILY_R420:
1098 case CHIP_FAMILY_R520:
1099 case CHIP_FAMILY_R580:
1100 case CHIP_FAMILY_RV560:
1101 case CHIP_FAMILY_RV570:
1102 screen->num_gb_pipes = 4;
1103 break;
1104 case CHIP_FAMILY_RV350:
1105 case CHIP_FAMILY_RV515:
1106 case CHIP_FAMILY_RV530:
1107 case CHIP_FAMILY_RV410:
1108 default:
1109 screen->num_gb_pipes = 1;
1110 break;
1111 }
1112 } else {
1113 screen->num_gb_pipes = temp;
1114 }
1115 }
1116
1117 if (screen->chip_family <= CHIP_FAMILY_RS200)
1118 screen->chip_flags |= RADEON_CLASS_R100;
1119 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1120 screen->chip_flags |= RADEON_CLASS_R200;
1121 else
1122 screen->chip_flags |= RADEON_CLASS_R300;
1123
1124 if (getenv("R300_NO_TCL"))
1125 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1126
1127 i = 0;
1128 screen->extensions[i++] = &driCopySubBufferExtension.base;
1129 screen->extensions[i++] = &driFrameTrackingExtension.base;
1130 screen->extensions[i++] = &driReadDrawableExtension;
1131
1132 if ( screen->irq != 0 ) {
1133 screen->extensions[i++] = &driSwapControlExtension.base;
1134 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1135 }
1136
1137 #if !RADEON_COMMON
1138 screen->extensions[i++] = &radeonTexBufferExtension.base;
1139 #endif
1140
1141 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1142 if (IS_R200_CLASS(screen))
1143 screen->extensions[i++] = &r200AllocateExtension.base;
1144
1145 screen->extensions[i++] = &r200TexBufferExtension.base;
1146 #endif
1147
1148 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1149 screen->extensions[i++] = &r300TexBufferExtension.base;
1150 #endif
1151
1152 screen->extensions[i++] = NULL;
1153 sPriv->extensions = screen->extensions;
1154
1155 screen->driScreen = sPriv;
1156 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1157 if (screen->bom == NULL) {
1158 free(screen);
1159 return NULL;
1160 }
1161 return screen;
1162 }
1163
1164 /* Destroy the device specific screen private data struct.
1165 */
1166 static void
1167 radeonDestroyScreen( __DRIscreenPrivate *sPriv )
1168 {
1169 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1170
1171 if (!screen)
1172 return;
1173
1174 if (screen->kernel_mm) {
1175 #ifdef RADEON_BO_TRACK
1176 radeon_tracker_print(&screen->bom->tracker, stderr);
1177 #endif
1178 radeon_bo_manager_gem_dtor(screen->bom);
1179 } else {
1180 radeon_bo_manager_legacy_dtor(screen->bom);
1181
1182 if ( screen->gartTextures.map ) {
1183 drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
1184 }
1185 drmUnmapBufs( screen->buffers );
1186 drmUnmap( screen->status.map, screen->status.size );
1187 drmUnmap( screen->mmio.map, screen->mmio.size );
1188 }
1189
1190 /* free all option information */
1191 driDestroyOptionInfo (&screen->optionCache);
1192
1193 FREE( screen );
1194 sPriv->private = NULL;
1195 }
1196
1197
1198 /* Initialize the driver specific screen private data.
1199 */
1200 static GLboolean
1201 radeonInitDriver( __DRIscreenPrivate *sPriv )
1202 {
1203 if (sPriv->dri2.enabled) {
1204 sPriv->private = (void *) radeonCreateScreen2( sPriv );
1205 } else {
1206 sPriv->private = (void *) radeonCreateScreen( sPriv );
1207 }
1208 if ( !sPriv->private ) {
1209 radeonDestroyScreen( sPriv );
1210 return GL_FALSE;
1211 }
1212
1213 return GL_TRUE;
1214 }
1215
1216
1217
1218 /**
1219 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1220 *
1221 * \todo This function (and its interface) will need to be updated to support
1222 * pbuffers.
1223 */
1224 static GLboolean
1225 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
1226 __DRIdrawablePrivate *driDrawPriv,
1227 const __GLcontextModes *mesaVis,
1228 GLboolean isPixmap )
1229 {
1230 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1231
1232 const GLboolean swDepth = GL_FALSE;
1233 const GLboolean swAlpha = GL_FALSE;
1234 const GLboolean swAccum = mesaVis->accumRedBits > 0;
1235 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1236 mesaVis->depthBits != 24;
1237 GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8);
1238 struct radeon_framebuffer *rfb;
1239
1240 if (isPixmap)
1241 return GL_FALSE; /* not implemented */
1242
1243 rfb = CALLOC_STRUCT(radeon_framebuffer);
1244 if (!rfb)
1245 return GL_FALSE;
1246
1247 _mesa_initialize_framebuffer(&rfb->base, mesaVis);
1248
1249 /* front color renderbuffer */
1250 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1251 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base);
1252 rfb->color_rb[0]->has_surface = 1;
1253
1254 /* back color renderbuffer */
1255 if (mesaVis->doubleBufferMode) {
1256 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1257 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base);
1258 rfb->color_rb[1]->has_surface = 1;
1259 }
1260
1261 if (mesaVis->depthBits == 24) {
1262 if (mesaVis->stencilBits == 8) {
1263 struct radeon_renderbuffer *depthStencilRb = radeon_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT, driDrawPriv);
1264 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base);
1265 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base);
1266 depthStencilRb->has_surface = screen->depthHasSurface;
1267 } else {
1268 /* depth renderbuffer */
1269 struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT24, driDrawPriv);
1270 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1271 depth->has_surface = screen->depthHasSurface;
1272 }
1273 } else if (mesaVis->depthBits == 16) {
1274 /* just 16-bit depth buffer, no hw stencil */
1275 struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT16, driDrawPriv);
1276 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1277 depth->has_surface = screen->depthHasSurface;
1278 }
1279
1280 _mesa_add_soft_renderbuffers(&rfb->base,
1281 GL_FALSE, /* color */
1282 swDepth,
1283 swStencil,
1284 swAccum,
1285 swAlpha,
1286 GL_FALSE /* aux */);
1287 driDrawPriv->driverPrivate = (void *) rfb;
1288
1289 return (driDrawPriv->driverPrivate != NULL);
1290 }
1291
1292 static void
1293 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
1294 {
1295 struct radeon_renderbuffer *rb;
1296 struct radeon_framebuffer *rfb;
1297
1298 rfb = (void*)driDrawPriv->driverPrivate;
1299 rb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
1300 if (rb && rb->bo) {
1301 radeon_bo_unref(rb->bo);
1302 rb->bo = NULL;
1303 }
1304 rb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
1305 if (rb && rb->bo) {
1306 radeon_bo_unref(rb->bo);
1307 rb->bo = NULL;
1308 }
1309 rb = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer;
1310 if (rb && rb->bo) {
1311 radeon_bo_unref(rb->bo);
1312 rb->bo = NULL;
1313 }
1314 _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL);
1315 }
1316
1317 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1318 /**
1319 * Choose the appropriate CreateContext function based on the chipset.
1320 * Eventually, all drivers will go through this process.
1321 */
1322 static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
1323 __DRIcontextPrivate * driContextPriv,
1324 void *sharedContextPriv)
1325 {
1326 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
1327 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
1328
1329 if (IS_R300_CLASS(screen))
1330 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
1331 return GL_FALSE;
1332 }
1333
1334 /**
1335 * Choose the appropriate DestroyContext function based on the chipset.
1336 */
1337 static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
1338 {
1339 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
1340
1341 if (IS_R300_CLASS(radeon->radeonScreen))
1342 return r300DestroyContext(driContextPriv);
1343 }
1344
1345
1346 #endif
1347
1348
1349 /**
1350 * This is the driver specific part of the createNewScreen entry point.
1351 *
1352 * \todo maybe fold this into intelInitDriver
1353 *
1354 * \return the __GLcontextModes supported by this driver
1355 */
1356 static const __DRIconfig **
1357 radeonInitScreen(__DRIscreenPrivate *psp)
1358 {
1359 #if !RADEON_COMMON
1360 static const char *driver_name = "Radeon";
1361 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1362 static const __DRIversion dri_expected = { 4, 0, 0 };
1363 static const __DRIversion drm_expected = { 1, 6, 0 };
1364 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1365 static const char *driver_name = "R200";
1366 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1367 static const __DRIversion dri_expected = { 4, 0, 0 };
1368 static const __DRIversion drm_expected = { 1, 6, 0 };
1369 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1370 static const char *driver_name = "R300";
1371 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1372 static const __DRIversion dri_expected = { 4, 0, 0 };
1373 static const __DRIversion drm_expected = { 1, 24, 0 };
1374 #endif
1375 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1376
1377 if ( ! driCheckDriDdxDrmVersions3( driver_name,
1378 &psp->dri_version, & dri_expected,
1379 &psp->ddx_version, & ddx_expected,
1380 &psp->drm_version, & drm_expected ) ) {
1381 return NULL;
1382 }
1383
1384 /* Calling driInitExtensions here, with a NULL context pointer,
1385 * does not actually enable the extensions. It just makes sure
1386 * that all the dispatch offsets for all the extensions that
1387 * *might* be enables are known. This is needed because the
1388 * dispatch offsets need to be known when _mesa_context_create
1389 * is called, but we can't enable the extensions until we have a
1390 * context pointer.
1391 *
1392 * Hello chicken. Hello egg. How are you two today?
1393 */
1394 driInitExtensions( NULL, card_extensions, GL_FALSE );
1395 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1396 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1397 driInitSingleExtension( NULL, ARB_vp_extension );
1398 driInitSingleExtension( NULL, NV_vp_extension );
1399 driInitSingleExtension( NULL, ATI_fs_extension );
1400 driInitExtensions( NULL, point_extensions, GL_FALSE );
1401 #elif defined(RADEON_COMMON_FOR_R300)
1402 driInitSingleExtension( NULL, gl_20_extension );
1403 #endif
1404
1405 if (!radeonInitDriver(psp))
1406 return NULL;
1407
1408 /* for now fill in all modes */
1409 return radeonFillInModes( psp,
1410 dri_priv->bpp,
1411 (dri_priv->bpp == 16) ? 16 : 24,
1412 (dri_priv->bpp == 16) ? 0 : 8, 1);
1413 }
1414 #define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
1415
1416 /**
1417 * This is the driver specific part of the createNewScreen entry point.
1418 * Called when using DRI2.
1419 *
1420 * \return the __GLcontextModes supported by this driver
1421 */
1422 static const
1423 __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp)
1424 {
1425 GLenum fb_format[3];
1426 GLenum fb_type[3];
1427 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
1428 * support pageflipping at all.
1429 */
1430 static const GLenum back_buffer_modes[] = {
1431 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/
1432 };
1433 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
1434 int color;
1435 __DRIconfig **configs = NULL;
1436
1437 /* Calling driInitExtensions here, with a NULL context pointer,
1438 * does not actually enable the extensions. It just makes sure
1439 * that all the dispatch offsets for all the extensions that
1440 * *might* be enables are known. This is needed because the
1441 * dispatch offsets need to be known when _mesa_context_create
1442 * is called, but we can't enable the extensions until we have a
1443 * context pointer.
1444 *
1445 * Hello chicken. Hello egg. How are you two today?
1446 */
1447 driInitExtensions( NULL, card_extensions, GL_FALSE );
1448 driInitExtensions( NULL, mm_extensions, GL_FALSE );
1449 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1450 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1451 driInitSingleExtension( NULL, ARB_vp_extension );
1452 driInitSingleExtension( NULL, NV_vp_extension );
1453 driInitSingleExtension( NULL, ATI_fs_extension );
1454 driInitExtensions( NULL, point_extensions, GL_FALSE );
1455 #endif
1456
1457 if (!radeonInitDriver(psp)) {
1458 return NULL;
1459 }
1460 depth_bits[0] = 0;
1461 stencil_bits[0] = 0;
1462 depth_bits[1] = 16;
1463 stencil_bits[1] = 0;
1464 depth_bits[2] = 24;
1465 stencil_bits[2] = 0;
1466 depth_bits[3] = 24;
1467 stencil_bits[3] = 8;
1468
1469 msaa_samples_array[0] = 0;
1470
1471 fb_format[0] = GL_RGB;
1472 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5;
1473
1474 fb_format[1] = GL_BGR;
1475 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV;
1476
1477 fb_format[2] = GL_BGRA;
1478 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
1479
1480 for (color = 0; color < ARRAY_SIZE(fb_format); color++) {
1481 __DRIconfig **new_configs;
1482
1483 new_configs = driCreateConfigs(fb_format[color], fb_type[color],
1484 depth_bits,
1485 stencil_bits,
1486 ARRAY_SIZE(depth_bits),
1487 back_buffer_modes,
1488 ARRAY_SIZE(back_buffer_modes),
1489 msaa_samples_array,
1490 ARRAY_SIZE(msaa_samples_array));
1491 if (configs == NULL)
1492 configs = new_configs;
1493 else
1494 configs = driConcatConfigs(configs, new_configs);
1495 }
1496
1497 if (configs == NULL) {
1498 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
1499 __LINE__);
1500 return NULL;
1501 }
1502
1503 return (const __DRIconfig **)configs;
1504 }
1505
1506 /**
1507 * Get information about previous buffer swaps.
1508 */
1509 static int
1510 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1511 {
1512 struct radeon_framebuffer *rfb;
1513
1514 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1515 || (dPriv->driContextPriv->driverPrivate == NULL)
1516 || (sInfo == NULL) ) {
1517 return -1;
1518 }
1519
1520 rfb = dPriv->driverPrivate;
1521 sInfo->swap_count = rfb->swap_count;
1522 sInfo->swap_ust = rfb->swap_ust;
1523 sInfo->swap_missed_count = rfb->swap_missed_count;
1524
1525 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1526 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust )
1527 : 0.0;
1528
1529 return 0;
1530 }
1531
1532 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1533 const struct __DriverAPIRec driDriverAPI = {
1534 .InitScreen = radeonInitScreen,
1535 .DestroyScreen = radeonDestroyScreen,
1536 .CreateContext = radeonCreateContext,
1537 .DestroyContext = radeonDestroyContext,
1538 .CreateBuffer = radeonCreateBuffer,
1539 .DestroyBuffer = radeonDestroyBuffer,
1540 .SwapBuffers = radeonSwapBuffers,
1541 .MakeCurrent = radeonMakeCurrent,
1542 .UnbindContext = radeonUnbindContext,
1543 .GetSwapInfo = getSwapInfo,
1544 .GetDrawableMSC = driDrawableGetMSC32,
1545 .WaitForMSC = driWaitForMSC32,
1546 .WaitForSBC = NULL,
1547 .SwapBuffersMSC = NULL,
1548 .CopySubBuffer = radeonCopySubBuffer,
1549 /* DRI2 */
1550 .InitScreen2 = radeonInitScreen2,
1551 };
1552 #else
1553 const struct __DriverAPIRec driDriverAPI = {
1554 .InitScreen = radeonInitScreen,
1555 .DestroyScreen = radeonDestroyScreen,
1556 .CreateContext = r200CreateContext,
1557 .DestroyContext = r200DestroyContext,
1558 .CreateBuffer = radeonCreateBuffer,
1559 .DestroyBuffer = radeonDestroyBuffer,
1560 .SwapBuffers = radeonSwapBuffers,
1561 .MakeCurrent = radeonMakeCurrent,
1562 .UnbindContext = radeonUnbindContext,
1563 .GetSwapInfo = getSwapInfo,
1564 .GetDrawableMSC = driDrawableGetMSC32,
1565 .WaitForMSC = driWaitForMSC32,
1566 .WaitForSBC = NULL,
1567 .SwapBuffersMSC = NULL,
1568 .CopySubBuffer = radeonCopySubBuffer,
1569 .InitScreen2 = radeonInitScreen2,
1570 };
1571 #endif
1572