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[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c
1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
2 /**************************************************************************
3
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
6
7 All Rights Reserved.
8
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
16
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
20
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28
29 **************************************************************************/
30
31 /**
32 * \file radeon_screen.c
33 * Screen initialization functions for the Radeon driver.
34 *
35 * \author Kevin E. Martin <martin@valinux.com>
36 * \author Gareth Hughes <gareth@valinux.com>
37 */
38
39 #include "glheader.h"
40 #include "imports.h"
41 #include "mtypes.h"
42 #include "framebuffer.h"
43 #include "renderbuffer.h"
44
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #if !RADEON_COMMON
50 #include "radeon_context.h"
51 #include "radeon_span.h"
52 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
53 #include "r200_context.h"
54 #include "r200_ioctl.h"
55 #include "r200_span.h"
56 #include "r200_tex.h"
57 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
58 #include "r300_context.h"
59 #include "r300_fragprog.h"
60 #include "r300_tex.h"
61 #include "radeon_span.h"
62 #endif
63
64 #include "utils.h"
65 #include "context.h"
66 #include "vblank.h"
67 #include "drirenderbuffer.h"
68
69 #include "GL/internal/dri_interface.h"
70
71 /* Radeon configuration
72 */
73 #include "xmlpool.h"
74
75 #if !RADEON_COMMON /* R100 */
76 PUBLIC const char __driConfigOptions[] =
77 DRI_CONF_BEGIN
78 DRI_CONF_SECTION_PERFORMANCE
79 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
80 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
81 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
82 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
83 DRI_CONF_HYPERZ(false)
84 DRI_CONF_SECTION_END
85 DRI_CONF_SECTION_QUALITY
86 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
87 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
88 DRI_CONF_NO_NEG_LOD_BIAS(false)
89 DRI_CONF_FORCE_S3TC_ENABLE(false)
90 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
91 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
92 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
93 DRI_CONF_ALLOW_LARGE_TEXTURES(1)
94 DRI_CONF_SECTION_END
95 DRI_CONF_SECTION_DEBUG
96 DRI_CONF_NO_RAST(false)
97 DRI_CONF_SECTION_END
98 DRI_CONF_END;
99 static const GLuint __driNConfigOptions = 14;
100
101 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
102
103 PUBLIC const char __driConfigOptions[] =
104 DRI_CONF_BEGIN
105 DRI_CONF_SECTION_PERFORMANCE
106 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
107 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
108 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
109 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
110 DRI_CONF_HYPERZ(false)
111 DRI_CONF_SECTION_END
112 DRI_CONF_SECTION_QUALITY
113 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
114 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
115 DRI_CONF_NO_NEG_LOD_BIAS(false)
116 DRI_CONF_FORCE_S3TC_ENABLE(false)
117 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
118 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
119 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
120 DRI_CONF_ALLOW_LARGE_TEXTURES(1)
121 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
122 DRI_CONF_SECTION_END
123 DRI_CONF_SECTION_DEBUG
124 DRI_CONF_NO_RAST(false)
125 DRI_CONF_SECTION_END
126 DRI_CONF_SECTION_SOFTWARE
127 DRI_CONF_NV_VERTEX_PROGRAM(false)
128 DRI_CONF_SECTION_END
129 DRI_CONF_END;
130 static const GLuint __driNConfigOptions = 16;
131
132 extern const struct dri_extension blend_extensions[];
133 extern const struct dri_extension ARB_vp_extension[];
134 extern const struct dri_extension NV_vp_extension[];
135 extern const struct dri_extension ATI_fs_extension[];
136 extern const struct dri_extension point_extensions[];
137
138 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
139
140 /* TODO: integrate these into xmlpool.h! */
141 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
142 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
143 DRI_CONF_DESC(en,"Number of texture image units") \
144 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
145 DRI_CONF_OPT_END
146
147 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
148 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
149 DRI_CONF_DESC(en,"Number of texture coordinate units") \
150 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
151 DRI_CONF_OPT_END
152
153 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
154 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
155 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
156 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
157 DRI_CONF_OPT_END
158
159 #define DRI_CONF_DISABLE_S3TC(def) \
160 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
161 DRI_CONF_DESC(en,"Disable S3TC compression") \
162 DRI_CONF_OPT_END
163
164 #define DRI_CONF_DISABLE_FALLBACK(def) \
165 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
166 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
167 DRI_CONF_OPT_END
168
169 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
170 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
171 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
172 DRI_CONF_OPT_END
173
174 #define DRI_CONF_FP_OPTIMIZATION(def) \
175 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
176 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
177 DRI_CONF_ENUM(0,"Optimize for Speed") \
178 DRI_CONF_ENUM(1,"Optimize for Quality") \
179 DRI_CONF_DESC_END \
180 DRI_CONF_OPT_END
181
182 PUBLIC const char __driConfigOptions[] =
183 DRI_CONF_BEGIN
184 DRI_CONF_SECTION_PERFORMANCE
185 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
186 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
187 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
188 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
189 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
190 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
191 DRI_CONF_DISABLE_FALLBACK(false)
192 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
193 DRI_CONF_SECTION_END
194 DRI_CONF_SECTION_QUALITY
195 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
196 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
197 DRI_CONF_NO_NEG_LOD_BIAS(false)
198 DRI_CONF_FORCE_S3TC_ENABLE(false)
199 DRI_CONF_DISABLE_S3TC(false)
200 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
201 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
202 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
203 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
204 DRI_CONF_SECTION_END
205 DRI_CONF_SECTION_DEBUG
206 DRI_CONF_NO_RAST(false)
207 DRI_CONF_SECTION_END
208 DRI_CONF_END;
209 static const GLuint __driNConfigOptions = 18;
210
211 #ifndef RADEON_DEBUG
212 int RADEON_DEBUG = 0;
213
214 static const struct dri_debug_control debug_control[] = {
215 {"fall", DEBUG_FALLBACKS},
216 {"tex", DEBUG_TEXTURE},
217 {"ioctl", DEBUG_IOCTL},
218 {"prim", DEBUG_PRIMS},
219 {"vert", DEBUG_VERTS},
220 {"state", DEBUG_STATE},
221 {"code", DEBUG_CODEGEN},
222 {"vfmt", DEBUG_VFMT},
223 {"vtxf", DEBUG_VFMT},
224 {"verb", DEBUG_VERBOSE},
225 {"dri", DEBUG_DRI},
226 {"dma", DEBUG_DMA},
227 {"san", DEBUG_SANITY},
228 {"sync", DEBUG_SYNC},
229 {"pix", DEBUG_PIXEL},
230 {"mem", DEBUG_MEMORY},
231 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
232 {NULL, 0}
233 };
234 #endif /* RADEON_DEBUG */
235
236 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
237
238 extern const struct dri_extension card_extensions[];
239
240 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
241
242 static int
243 radeonGetParam(int fd, int param, void *value)
244 {
245 int ret;
246 drm_radeon_getparam_t gp;
247
248 gp.param = param;
249 gp.value = value;
250
251 ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
252 return ret;
253 }
254
255 static __GLcontextModes *
256 radeonFillInModes( unsigned pixel_bits, unsigned depth_bits,
257 unsigned stencil_bits, GLboolean have_back_buffer )
258 {
259 __GLcontextModes * modes;
260 __GLcontextModes * m;
261 unsigned num_modes;
262 unsigned depth_buffer_factor;
263 unsigned back_buffer_factor;
264 GLenum fb_format;
265 GLenum fb_type;
266
267 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
268 * enough to add support. Basically, if a context is created with an
269 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
270 * will never be used.
271 */
272 static const GLenum back_buffer_modes[] = {
273 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
274 };
275
276 u_int8_t depth_bits_array[2];
277 u_int8_t stencil_bits_array[2];
278
279
280 depth_bits_array[0] = depth_bits;
281 depth_bits_array[1] = depth_bits;
282
283 /* Just like with the accumulation buffer, always provide some modes
284 * with a stencil buffer. It will be a sw fallback, but some apps won't
285 * care about that.
286 */
287 stencil_bits_array[0] = 0;
288 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
289
290 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
291 back_buffer_factor = (have_back_buffer) ? 2 : 1;
292
293 num_modes = depth_buffer_factor * back_buffer_factor * 4;
294
295 if ( pixel_bits == 16 ) {
296 fb_format = GL_RGB;
297 fb_type = GL_UNSIGNED_SHORT_5_6_5;
298 }
299 else {
300 fb_format = GL_BGRA;
301 fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
302 }
303
304 modes = (*dri_interface->createContextModes)( num_modes, sizeof( __GLcontextModes ) );
305 m = modes;
306 if ( ! driFillInModes( & m, fb_format, fb_type,
307 depth_bits_array, stencil_bits_array, depth_buffer_factor,
308 back_buffer_modes, back_buffer_factor,
309 GLX_TRUE_COLOR ) ) {
310 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
311 __func__, __LINE__ );
312 return NULL;
313 }
314
315 if ( ! driFillInModes( & m, fb_format, fb_type,
316 depth_bits_array, stencil_bits_array, depth_buffer_factor,
317 back_buffer_modes, back_buffer_factor,
318 GLX_DIRECT_COLOR ) ) {
319 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
320 __func__, __LINE__ );
321 return NULL;
322 }
323
324 /* Mark the visual as slow if there are "fake" stencil bits.
325 */
326 for ( m = modes ; m != NULL ; m = m->next ) {
327 if ( (m->stencilBits != 0) && (m->stencilBits != stencil_bits) ) {
328 m->visualRating = GLX_SLOW_CONFIG;
329 }
330 }
331
332 return modes;
333 }
334
335 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
336 static const __DRIallocateExtension r200AllocateExtension = {
337 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
338 r200AllocateMemoryMESA,
339 r200FreeMemoryMESA,
340 r200GetMemoryOffsetMESA
341 };
342
343 static const __DRItexOffsetExtension r200texOffsetExtension = {
344 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
345 r200SetTexOffset,
346 };
347 #endif
348
349 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
350 static const __DRItexOffsetExtension r300texOffsetExtension = {
351 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
352 r300SetTexOffset,
353 };
354 #endif
355
356 /* Create the device specific screen private data struct.
357 */
358 static radeonScreenPtr
359 radeonCreateScreen( __DRIscreenPrivate *sPriv )
360 {
361 radeonScreenPtr screen;
362 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
363 unsigned char *RADEONMMIO;
364 int i;
365 int ret;
366 uint32_t temp;
367
368 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
369 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
370 return GL_FALSE;
371 }
372
373 /* Allocate the private area */
374 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
375 if ( !screen ) {
376 __driUtilMessage("%s: Could not allocate memory for screen structure",
377 __FUNCTION__);
378 return NULL;
379 }
380
381 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
382 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
383 #endif
384
385 /* parse information in __driConfigOptions */
386 driParseOptionInfo (&screen->optionCache,
387 __driConfigOptions, __driNConfigOptions);
388
389 /* This is first since which regions we map depends on whether or
390 * not we are using a PCI card.
391 */
392 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
393 {
394 int ret;
395 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET,
396 &screen->gart_buffer_offset);
397
398 if (ret) {
399 FREE( screen );
400 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
401 return NULL;
402 }
403
404 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE,
405 &screen->gart_base);
406 if (ret) {
407 FREE( screen );
408 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
409 return NULL;
410 }
411
412 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
413 &screen->irq);
414 if (ret) {
415 FREE( screen );
416 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
417 return NULL;
418 }
419 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
420 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
421 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
422 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
423 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
424 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
425 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
426 }
427
428 screen->mmio.handle = dri_priv->registerHandle;
429 screen->mmio.size = dri_priv->registerSize;
430 if ( drmMap( sPriv->fd,
431 screen->mmio.handle,
432 screen->mmio.size,
433 &screen->mmio.map ) ) {
434 FREE( screen );
435 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
436 return NULL;
437 }
438
439 RADEONMMIO = screen->mmio.map;
440
441 screen->status.handle = dri_priv->statusHandle;
442 screen->status.size = dri_priv->statusSize;
443 if ( drmMap( sPriv->fd,
444 screen->status.handle,
445 screen->status.size,
446 &screen->status.map ) ) {
447 drmUnmap( screen->mmio.map, screen->mmio.size );
448 FREE( screen );
449 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
450 return NULL;
451 }
452 screen->scratch = (__volatile__ u_int32_t *)
453 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
454
455 screen->buffers = drmMapBufs( sPriv->fd );
456 if ( !screen->buffers ) {
457 drmUnmap( screen->status.map, screen->status.size );
458 drmUnmap( screen->mmio.map, screen->mmio.size );
459 FREE( screen );
460 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
461 return NULL;
462 }
463
464 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
465 screen->gartTextures.handle = dri_priv->gartTexHandle;
466 screen->gartTextures.size = dri_priv->gartTexMapSize;
467 if ( drmMap( sPriv->fd,
468 screen->gartTextures.handle,
469 screen->gartTextures.size,
470 (drmAddressPtr)&screen->gartTextures.map ) ) {
471 drmUnmapBufs( screen->buffers );
472 drmUnmap( screen->status.map, screen->status.size );
473 drmUnmap( screen->mmio.map, screen->mmio.size );
474 FREE( screen );
475 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
476 return NULL;
477 }
478
479 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
480 }
481
482 screen->chip_flags = 0;
483 /* XXX: add more chipsets */
484 switch ( dri_priv->deviceID ) {
485 case PCI_CHIP_RADEON_LY:
486 case PCI_CHIP_RADEON_LZ:
487 case PCI_CHIP_RADEON_QY:
488 case PCI_CHIP_RADEON_QZ:
489 case PCI_CHIP_RN50_515E:
490 case PCI_CHIP_RN50_5969:
491 screen->chip_family = CHIP_FAMILY_RV100;
492 break;
493
494 case PCI_CHIP_RS100_4136:
495 case PCI_CHIP_RS100_4336:
496 screen->chip_family = CHIP_FAMILY_RS100;
497 break;
498
499 case PCI_CHIP_RS200_4137:
500 case PCI_CHIP_RS200_4337:
501 case PCI_CHIP_RS250_4237:
502 case PCI_CHIP_RS250_4437:
503 screen->chip_family = CHIP_FAMILY_RS200;
504 break;
505
506 case PCI_CHIP_RADEON_QD:
507 case PCI_CHIP_RADEON_QE:
508 case PCI_CHIP_RADEON_QF:
509 case PCI_CHIP_RADEON_QG:
510 /* all original radeons (7200) presumably have a stencil op bug */
511 screen->chip_family = CHIP_FAMILY_R100;
512 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
513 break;
514
515 case PCI_CHIP_RV200_QW:
516 case PCI_CHIP_RV200_QX:
517 case PCI_CHIP_RADEON_LW:
518 case PCI_CHIP_RADEON_LX:
519 screen->chip_family = CHIP_FAMILY_RV200;
520 screen->chip_flags = RADEON_CHIPSET_TCL;
521 break;
522
523 case PCI_CHIP_R200_BB:
524 case PCI_CHIP_R200_BC:
525 case PCI_CHIP_R200_QH:
526 case PCI_CHIP_R200_QL:
527 case PCI_CHIP_R200_QM:
528 screen->chip_family = CHIP_FAMILY_R200;
529 screen->chip_flags = RADEON_CHIPSET_TCL;
530 break;
531
532 case PCI_CHIP_RV250_If:
533 case PCI_CHIP_RV250_Ig:
534 case PCI_CHIP_RV250_Ld:
535 case PCI_CHIP_RV250_Lf:
536 case PCI_CHIP_RV250_Lg:
537 screen->chip_family = CHIP_FAMILY_RV250;
538 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
539 break;
540
541 case PCI_CHIP_RV280_5960:
542 case PCI_CHIP_RV280_5961:
543 case PCI_CHIP_RV280_5962:
544 case PCI_CHIP_RV280_5964:
545 case PCI_CHIP_RV280_5965:
546 case PCI_CHIP_RV280_5C61:
547 case PCI_CHIP_RV280_5C63:
548 screen->chip_family = CHIP_FAMILY_RV280;
549 screen->chip_flags = RADEON_CHIPSET_TCL;
550 break;
551
552 case PCI_CHIP_RS300_5834:
553 case PCI_CHIP_RS300_5835:
554 case PCI_CHIP_RS350_7834:
555 case PCI_CHIP_RS350_7835:
556 screen->chip_family = CHIP_FAMILY_RS300;
557 break;
558
559 case PCI_CHIP_R300_AD:
560 case PCI_CHIP_R300_AE:
561 case PCI_CHIP_R300_AF:
562 case PCI_CHIP_R300_AG:
563 case PCI_CHIP_R300_ND:
564 case PCI_CHIP_R300_NE:
565 case PCI_CHIP_R300_NF:
566 case PCI_CHIP_R300_NG:
567 screen->chip_family = CHIP_FAMILY_R300;
568 screen->chip_flags = RADEON_CHIPSET_TCL;
569 break;
570
571 case PCI_CHIP_RV350_AP:
572 case PCI_CHIP_RV350_AQ:
573 case PCI_CHIP_RV350_AR:
574 case PCI_CHIP_RV350_AS:
575 case PCI_CHIP_RV350_AT:
576 case PCI_CHIP_RV350_AV:
577 case PCI_CHIP_RV350_AU:
578 case PCI_CHIP_RV350_NP:
579 case PCI_CHIP_RV350_NQ:
580 case PCI_CHIP_RV350_NR:
581 case PCI_CHIP_RV350_NS:
582 case PCI_CHIP_RV350_NT:
583 case PCI_CHIP_RV350_NV:
584 screen->chip_family = CHIP_FAMILY_RV350;
585 screen->chip_flags = RADEON_CHIPSET_TCL;
586 break;
587
588 case PCI_CHIP_R350_AH:
589 case PCI_CHIP_R350_AI:
590 case PCI_CHIP_R350_AJ:
591 case PCI_CHIP_R350_AK:
592 case PCI_CHIP_R350_NH:
593 case PCI_CHIP_R350_NI:
594 case PCI_CHIP_R360_NJ:
595 case PCI_CHIP_R350_NK:
596 screen->chip_family = CHIP_FAMILY_R350;
597 screen->chip_flags = RADEON_CHIPSET_TCL;
598 break;
599
600 case PCI_CHIP_RV370_5460:
601 case PCI_CHIP_RV370_5462:
602 case PCI_CHIP_RV370_5464:
603 case PCI_CHIP_RV370_5B60:
604 case PCI_CHIP_RV370_5B62:
605 case PCI_CHIP_RV370_5B63:
606 case PCI_CHIP_RV370_5B64:
607 case PCI_CHIP_RV370_5B65:
608 case PCI_CHIP_RV370_5657:
609 case PCI_CHIP_RV380_3150:
610 case PCI_CHIP_RV380_3152:
611 case PCI_CHIP_RV380_3154:
612 case PCI_CHIP_RV380_3E50:
613 case PCI_CHIP_RV380_3E54:
614 screen->chip_family = CHIP_FAMILY_RV380;
615 screen->chip_flags = RADEON_CHIPSET_TCL;
616 break;
617
618 case PCI_CHIP_R420_JN:
619 case PCI_CHIP_R420_JH:
620 case PCI_CHIP_R420_JI:
621 case PCI_CHIP_R420_JJ:
622 case PCI_CHIP_R420_JK:
623 case PCI_CHIP_R420_JL:
624 case PCI_CHIP_R420_JM:
625 case PCI_CHIP_R420_JO:
626 case PCI_CHIP_R420_JP:
627 case PCI_CHIP_R420_JT:
628 case PCI_CHIP_R481_4B49:
629 case PCI_CHIP_R481_4B4A:
630 case PCI_CHIP_R481_4B4B:
631 case PCI_CHIP_R481_4B4C:
632 case PCI_CHIP_R423_UH:
633 case PCI_CHIP_R423_UI:
634 case PCI_CHIP_R423_UJ:
635 case PCI_CHIP_R423_UK:
636 case PCI_CHIP_R430_554C:
637 case PCI_CHIP_R430_554D:
638 case PCI_CHIP_R430_554E:
639 case PCI_CHIP_R430_554F:
640 case PCI_CHIP_R423_5550:
641 case PCI_CHIP_R423_UQ:
642 case PCI_CHIP_R423_UR:
643 case PCI_CHIP_R423_UT:
644 case PCI_CHIP_R430_5D48:
645 case PCI_CHIP_R430_5D49:
646 case PCI_CHIP_R430_5D4A:
647 case PCI_CHIP_R480_5D4C:
648 case PCI_CHIP_R480_5D4D:
649 case PCI_CHIP_R480_5D4E:
650 case PCI_CHIP_R480_5D4F:
651 case PCI_CHIP_R480_5D50:
652 case PCI_CHIP_R480_5D52:
653 case PCI_CHIP_R423_5D57:
654 screen->chip_family = CHIP_FAMILY_R420;
655 screen->chip_flags = RADEON_CHIPSET_TCL;
656 break;
657
658 /* RV410 SE chips have half the pipes of regular RV410 */
659 case PCI_CHIP_RV410_5E4C:
660 case PCI_CHIP_RV410_5E4F:
661 screen->chip_family = CHIP_FAMILY_RV380;
662 screen->chip_flags = RADEON_CHIPSET_TCL;
663 break;
664
665 case PCI_CHIP_RV410_564A:
666 case PCI_CHIP_RV410_564B:
667 case PCI_CHIP_RV410_564F:
668 case PCI_CHIP_RV410_5652:
669 case PCI_CHIP_RV410_5653:
670 case PCI_CHIP_RV410_5E48:
671 case PCI_CHIP_RV410_5E4A:
672 case PCI_CHIP_RV410_5E4B:
673 case PCI_CHIP_RV410_5E4D:
674 screen->chip_family = CHIP_FAMILY_RV410;
675 screen->chip_flags = RADEON_CHIPSET_TCL;
676 break;
677
678 case PCI_CHIP_RS480_5954:
679 case PCI_CHIP_RS480_5955:
680 case PCI_CHIP_RS482_5974:
681 case PCI_CHIP_RS482_5975:
682 case PCI_CHIP_RS400_5A41:
683 case PCI_CHIP_RS400_5A42:
684 case PCI_CHIP_RC410_5A61:
685 case PCI_CHIP_RC410_5A62:
686 screen->chip_family = CHIP_FAMILY_RS400;
687 fprintf(stderr, "Warning, xpress200 detected.\n");
688 break;
689
690 case PCI_CHIP_RS690_791E:
691 screen->chip_family = CHIP_FAMILY_RS690;
692 fprintf(stderr, "Warning, RS690 detected, 3D support is incomplete.\n");
693 break;
694
695 default:
696 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
697 dri_priv->deviceID);
698 return NULL;
699 }
700 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
701 sPriv->ddx_version.minor < 2) {
702 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
703 return NULL;
704 }
705
706 if (screen->chip_family <= CHIP_FAMILY_RS200)
707 screen->chip_flags |= RADEON_CLASS_R100;
708 else if (screen->chip_family <= CHIP_FAMILY_RV280)
709 screen->chip_flags |= RADEON_CLASS_R200;
710 else
711 screen->chip_flags |= RADEON_CLASS_R300;
712
713 screen->cpp = dri_priv->bpp / 8;
714 screen->AGPMode = dri_priv->AGPMode;
715
716 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION,
717 &temp);
718 if (ret) {
719 if (screen->chip_family < CHIP_FAMILY_RS690)
720 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
721 else {
722 FREE( screen );
723 fprintf(stderr, "Unable to get fb location need newer drm\n");
724 return NULL;
725 }
726 } else {
727 screen->fbLocation = (temp & 0xffff) << 16;
728 }
729
730 if ( sPriv->drm_version.minor >= 10 ) {
731 drm_radeon_setparam_t sp;
732
733 sp.param = RADEON_SETPARAM_FB_LOCATION;
734 sp.value = screen->fbLocation;
735
736 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
737 &sp, sizeof( sp ) );
738 }
739
740 screen->frontOffset = dri_priv->frontOffset;
741 screen->frontPitch = dri_priv->frontPitch;
742 screen->backOffset = dri_priv->backOffset;
743 screen->backPitch = dri_priv->backPitch;
744 screen->depthOffset = dri_priv->depthOffset;
745 screen->depthPitch = dri_priv->depthPitch;
746
747 /* Check if ddx has set up a surface reg to cover depth buffer */
748 screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
749 /* these chips don't use tiled z without hyperz. So always pretend
750 we have set up a surface which will cause linear reads/writes */
751 ((screen->chip_family & RADEON_CLASS_R100) &&
752 !(screen->chip_flags & RADEON_CHIPSET_TCL));
753
754 if ( dri_priv->textureSize == 0 ) {
755 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
756 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
757 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
758 dri_priv->log2GARTTexGran;
759 } else {
760 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
761 + screen->fbLocation;
762 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
763 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
764 dri_priv->log2TexGran;
765 }
766
767 if ( !screen->gartTextures.map || dri_priv->textureSize == 0
768 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
769 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
770 screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
771 screen->texSize[RADEON_GART_TEX_HEAP] = 0;
772 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
773 } else {
774 screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
775 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
776 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
777 screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
778 dri_priv->log2GARTTexGran;
779 }
780
781 i = 0;
782 screen->extensions[i++] = &driCopySubBufferExtension.base;
783 screen->extensions[i++] = &driFrameTrackingExtension.base;
784 screen->extensions[i++] = &driReadDrawableExtension;
785
786 if ( screen->irq != 0 ) {
787 screen->extensions[i++] = &driSwapControlExtension.base;
788 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
789 }
790
791 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
792 if (IS_R200_CLASS(screen))
793 screen->extensions[i++] = &r200AllocateExtension.base;
794
795 screen->extensions[i++] = &r200texOffsetExtension.base;
796 #endif
797
798 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
799 screen->extensions[i++] = &r300texOffsetExtension.base;
800 #endif
801
802 screen->extensions[i++] = NULL;
803 sPriv->extensions = screen->extensions;
804
805 screen->driScreen = sPriv;
806 screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
807 return screen;
808 }
809
810 /* Destroy the device specific screen private data struct.
811 */
812 static void
813 radeonDestroyScreen( __DRIscreenPrivate *sPriv )
814 {
815 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
816
817 if (!screen)
818 return;
819
820 if ( screen->gartTextures.map ) {
821 drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
822 }
823 drmUnmapBufs( screen->buffers );
824 drmUnmap( screen->status.map, screen->status.size );
825 drmUnmap( screen->mmio.map, screen->mmio.size );
826
827 /* free all option information */
828 driDestroyOptionInfo (&screen->optionCache);
829
830 FREE( screen );
831 sPriv->private = NULL;
832 }
833
834
835 /* Initialize the driver specific screen private data.
836 */
837 static GLboolean
838 radeonInitDriver( __DRIscreenPrivate *sPriv )
839 {
840 sPriv->private = (void *) radeonCreateScreen( sPriv );
841 if ( !sPriv->private ) {
842 radeonDestroyScreen( sPriv );
843 return GL_FALSE;
844 }
845
846 return GL_TRUE;
847 }
848
849
850 /**
851 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
852 *
853 * \todo This function (and its interface) will need to be updated to support
854 * pbuffers.
855 */
856 static GLboolean
857 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
858 __DRIdrawablePrivate *driDrawPriv,
859 const __GLcontextModes *mesaVis,
860 GLboolean isPixmap )
861 {
862 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
863
864 if (isPixmap) {
865 return GL_FALSE; /* not implemented */
866 }
867 else {
868 const GLboolean swDepth = GL_FALSE;
869 const GLboolean swAlpha = GL_FALSE;
870 const GLboolean swAccum = mesaVis->accumRedBits > 0;
871 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
872 mesaVis->depthBits != 24;
873 struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
874
875 /* front color renderbuffer */
876 {
877 driRenderbuffer *frontRb
878 = driNewRenderbuffer(GL_RGBA,
879 driScrnPriv->pFB + screen->frontOffset,
880 screen->cpp,
881 screen->frontOffset, screen->frontPitch,
882 driDrawPriv);
883 radeonSetSpanFunctions(frontRb, mesaVis);
884 _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
885 }
886
887 /* back color renderbuffer */
888 if (mesaVis->doubleBufferMode) {
889 driRenderbuffer *backRb
890 = driNewRenderbuffer(GL_RGBA,
891 driScrnPriv->pFB + screen->backOffset,
892 screen->cpp,
893 screen->backOffset, screen->backPitch,
894 driDrawPriv);
895 radeonSetSpanFunctions(backRb, mesaVis);
896 _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
897 }
898
899 /* depth renderbuffer */
900 if (mesaVis->depthBits == 16) {
901 driRenderbuffer *depthRb
902 = driNewRenderbuffer(GL_DEPTH_COMPONENT16,
903 driScrnPriv->pFB + screen->depthOffset,
904 screen->cpp,
905 screen->depthOffset, screen->depthPitch,
906 driDrawPriv);
907 radeonSetSpanFunctions(depthRb, mesaVis);
908 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
909 depthRb->depthHasSurface = screen->depthHasSurface;
910 }
911 else if (mesaVis->depthBits == 24) {
912 driRenderbuffer *depthRb
913 = driNewRenderbuffer(GL_DEPTH_COMPONENT24,
914 driScrnPriv->pFB + screen->depthOffset,
915 screen->cpp,
916 screen->depthOffset, screen->depthPitch,
917 driDrawPriv);
918 radeonSetSpanFunctions(depthRb, mesaVis);
919 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
920 depthRb->depthHasSurface = screen->depthHasSurface;
921 }
922
923 /* stencil renderbuffer */
924 if (mesaVis->stencilBits > 0 && !swStencil) {
925 driRenderbuffer *stencilRb
926 = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT,
927 driScrnPriv->pFB + screen->depthOffset,
928 screen->cpp,
929 screen->depthOffset, screen->depthPitch,
930 driDrawPriv);
931 radeonSetSpanFunctions(stencilRb, mesaVis);
932 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
933 stencilRb->depthHasSurface = screen->depthHasSurface;
934 }
935
936 _mesa_add_soft_renderbuffers(fb,
937 GL_FALSE, /* color */
938 swDepth,
939 swStencil,
940 swAccum,
941 swAlpha,
942 GL_FALSE /* aux */);
943 driDrawPriv->driverPrivate = (void *) fb;
944
945 return (driDrawPriv->driverPrivate != NULL);
946 }
947 }
948
949
950 static void
951 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
952 {
953 _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)));
954 }
955
956 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
957 /**
958 * Choose the appropriate CreateContext function based on the chipset.
959 * Eventually, all drivers will go through this process.
960 */
961 static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
962 __DRIcontextPrivate * driContextPriv,
963 void *sharedContextPriv)
964 {
965 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
966 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
967
968 if (IS_R300_CLASS(screen))
969 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
970 return GL_FALSE;
971 }
972
973 /**
974 * Choose the appropriate DestroyContext function based on the chipset.
975 */
976 static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
977 {
978 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
979
980 if (IS_R300_CLASS(radeon->radeonScreen))
981 return r300DestroyContext(driContextPriv);
982 }
983
984
985 #endif
986
987 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
988 static struct __DriverAPIRec radeonAPI = {
989 .DestroyScreen = radeonDestroyScreen,
990 .CreateContext = radeonCreateContext,
991 .DestroyContext = radeonDestroyContext,
992 .CreateBuffer = radeonCreateBuffer,
993 .DestroyBuffer = radeonDestroyBuffer,
994 .SwapBuffers = radeonSwapBuffers,
995 .MakeCurrent = radeonMakeCurrent,
996 .UnbindContext = radeonUnbindContext,
997 .GetSwapInfo = getSwapInfo,
998 .GetMSC = driGetMSC32,
999 .GetDrawableMSC = driDrawableGetMSC32,
1000 .WaitForMSC = driWaitForMSC32,
1001 .WaitForSBC = NULL,
1002 .SwapBuffersMSC = NULL,
1003 .CopySubBuffer = radeonCopySubBuffer,
1004 };
1005 #else
1006 static const struct __DriverAPIRec r200API = {
1007 .DestroyScreen = radeonDestroyScreen,
1008 .CreateContext = r200CreateContext,
1009 .DestroyContext = r200DestroyContext,
1010 .CreateBuffer = radeonCreateBuffer,
1011 .DestroyBuffer = radeonDestroyBuffer,
1012 .SwapBuffers = r200SwapBuffers,
1013 .MakeCurrent = r200MakeCurrent,
1014 .UnbindContext = r200UnbindContext,
1015 .GetSwapInfo = getSwapInfo,
1016 .GetMSC = driGetMSC32,
1017 .GetDrawableMSC = driDrawableGetMSC32,
1018 .WaitForMSC = driWaitForMSC32,
1019 .WaitForSBC = NULL,
1020 .SwapBuffersMSC = NULL,
1021 .CopySubBuffer = r200CopySubBuffer,
1022 };
1023 #endif
1024
1025
1026 /**
1027 * This is the driver specific part of the createNewScreen entry point.
1028 *
1029 * \todo maybe fold this into intelInitDriver
1030 *
1031 * \return the __GLcontextModes supported by this driver
1032 */
1033 __GLcontextModes *__driDriverInitScreen(__DRIscreenPrivate *psp)
1034 {
1035 #if !RADEON_COMMON
1036 static const char *driver_name = "Radeon";
1037 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1038 static const __DRIversion dri_expected = { 4, 0, 0 };
1039 static const __DRIversion drm_expected = { 1, 6, 0 };
1040 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1041 static const char *driver_name = "R200";
1042 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1043 static const __DRIversion dri_expected = { 4, 0, 0 };
1044 static const __DRIversion drm_expected = { 1, 6, 0 };
1045 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1046 static const char *driver_name = "R300";
1047 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1048 static const __DRIversion dri_expected = { 4, 0, 0 };
1049 static const __DRIversion drm_expected = { 1, 24, 0 };
1050 #endif
1051 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1052
1053 if ( ! driCheckDriDdxDrmVersions3( driver_name,
1054 &psp->dri_version, & dri_expected,
1055 &psp->ddx_version, & ddx_expected,
1056 &psp->drm_version, & drm_expected ) ) {
1057 return NULL;
1058 }
1059 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1060 psp->DriverAPI = radeonAPI;
1061 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1062 psp->DriverAPI = r200API;
1063 #endif
1064
1065 /* Calling driInitExtensions here, with a NULL context pointer,
1066 * does not actually enable the extensions. It just makes sure
1067 * that all the dispatch offsets for all the extensions that
1068 * *might* be enables are known. This is needed because the
1069 * dispatch offsets need to be known when _mesa_context_create
1070 * is called, but we can't enable the extensions until we have a
1071 * context pointer.
1072 *
1073 * Hello chicken. Hello egg. How are you two today?
1074 */
1075 driInitExtensions( NULL, card_extensions, GL_FALSE );
1076 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1077 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1078 driInitSingleExtension( NULL, ARB_vp_extension );
1079 driInitSingleExtension( NULL, NV_vp_extension );
1080 driInitSingleExtension( NULL, ATI_fs_extension );
1081 driInitExtensions( NULL, point_extensions, GL_FALSE );
1082 #endif
1083
1084 if (!radeonInitDriver(psp))
1085 return NULL;
1086
1087 return radeonFillInModes( dri_priv->bpp,
1088 (dri_priv->bpp == 16) ? 16 : 24,
1089 (dri_priv->bpp == 16) ? 0 : 8,
1090 (dri_priv->backOffset != dri_priv->depthOffset) );
1091 }
1092
1093
1094 /**
1095 * Get information about previous buffer swaps.
1096 */
1097 static int
1098 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1099 {
1100 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1101 radeonContextPtr rmesa;
1102 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1103 r200ContextPtr rmesa;
1104 #endif
1105
1106 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1107 || (dPriv->driContextPriv->driverPrivate == NULL)
1108 || (sInfo == NULL) ) {
1109 return -1;
1110 }
1111
1112 rmesa = dPriv->driContextPriv->driverPrivate;
1113 sInfo->swap_count = rmesa->swap_count;
1114 sInfo->swap_ust = rmesa->swap_ust;
1115 sInfo->swap_missed_count = rmesa->swap_missed_count;
1116
1117 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1118 ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
1119 : 0.0;
1120
1121 return 0;
1122 }