src/mesa/drivers/dri/radeon/radeon_screen.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
   2 /**************************************************************************
   3
   4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   5                      VA Linux Systems Inc., Fremont, California.
   6
   7 All Rights Reserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining
  10 a copy of this software and associated documentation files (the
  11 "Software"), to deal in the Software without restriction, including
  12 without limitation the rights to use, copy, modify, merge, publish,
  13 distribute, sublicense, and/or sell copies of the Software, and to
  14 permit persons to whom the Software is furnished to do so, subject to
  15 the following conditions:
  16
  17 The above copyright notice and this permission notice (including the
  18 next paragraph) shall be included in all copies or substantial
  19 portions of the Software.
  20
  21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28
  29 **************************************************************************/
  30
  31 /**
  32  * \file radeon_screen.c
  33  * Screen initialization functions for the Radeon driver.
  34  *
  35  * \author Kevin E. Martin <martin@valinux.com>
  36  * \author  Gareth Hughes <gareth@valinux.com>
  37  */
  38
  39 #include "glheader.h"
  40 #include "imports.h"
  41
  42 #define STANDALONE_MMIO
  43 #include "radeon_context.h"
  44 #include "radeon_screen.h"
  45 #include "radeon_macros.h"
  46
  47 #include "utils.h"
  48 #include "context.h"
  49 #include "vblank.h"
  50
  51 #include "GL/internal/dri_interface.h"
  52
  53 /* Radeon configuration
  54  */
  55 #include "xmlpool.h"
  56
  57 PUBLIC const char __driConfigOptions[] =
  58 DRI_CONF_BEGIN
  59     DRI_CONF_SECTION_PERFORMANCE
  60         DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
  61         DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
  62         DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
  63         DRI_CONF_HYPERZ(false)
  64     DRI_CONF_SECTION_END
  65     DRI_CONF_SECTION_QUALITY
  66         DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
  67         DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
  68         DRI_CONF_NO_NEG_LOD_BIAS(false)
  69         DRI_CONF_FORCE_S3TC_ENABLE(false)
  70         DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
  71         DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
  72         DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
  73     DRI_CONF_SECTION_END
  74     DRI_CONF_SECTION_DEBUG
  75         DRI_CONF_NO_RAST(false)
  76     DRI_CONF_SECTION_END
  77 DRI_CONF_END;
  78 static const GLuint __driNConfigOptions = 12;
  79
  80 #if 1
  81 /* Including xf86PciInfo.h introduces a bunch of errors...
  82  */
  83 #define PCI_CHIP_RADEON_QD      0x5144
  84 #define PCI_CHIP_RADEON_QE      0x5145
  85 #define PCI_CHIP_RADEON_QF      0x5146
  86 #define PCI_CHIP_RADEON_QG      0x5147
  87
  88 #define PCI_CHIP_RADEON_QY      0x5159
  89 #define PCI_CHIP_RADEON_QZ      0x515A
  90
  91 #define PCI_CHIP_RADEON_LW      0x4C57 /* mobility 7 - has tcl */
  92 #define PCI_CHIP_RADEON_LX      0x4C58 /* mobility FireGL 7800 m7 */
  93
  94 #define PCI_CHIP_RADEON_LY      0x4C59
  95 #define PCI_CHIP_RADEON_LZ      0x4C5A
  96
  97 #define PCI_CHIP_RV200_QW       0x5157 /* Radeon 7500 - not an R200 at all */
  98 #define PCI_CHIP_RV200_QX       0x5158
  99
 100 /* IGP Chipsets */
 101 #define PCI_CHIP_RS100_4136     0x4136
 102 #define PCI_CHIP_RS200_4137     0x4137
 103 #define PCI_CHIP_RS250_4237     0x4237
 104 #define PCI_CHIP_RS100_4336     0x4336
 105 #define PCI_CHIP_RS200_4337     0x4337
 106 #define PCI_CHIP_RS250_4437     0x4437
 107 #endif
 108
 109 #ifdef USE_NEW_INTERFACE
 110 static PFNGLXCREATECONTEXTMODES create_context_modes = NULL;
 111 #endif /* USE_NEW_INTERFACE */
 112
 113 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
 114
 115 #ifdef USE_NEW_INTERFACE
 116 static __GLcontextModes *
 117 radeonFillInModes( unsigned pixel_bits, unsigned depth_bits,
 118                  unsigned stencil_bits, GLboolean have_back_buffer )
 119 {
 120     __GLcontextModes * modes;
 121     __GLcontextModes * m;
 122     unsigned num_modes;
 123     unsigned depth_buffer_factor;
 124     unsigned back_buffer_factor;
 125     GLenum fb_format;
 126     GLenum fb_type;
 127
 128     /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
 129      * enough to add support.  Basically, if a context is created with an
 130      * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
 131      * will never be used.
 132      */
 133     static const GLenum back_buffer_modes[] = {
 134         GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
 135     };
 136
 137     u_int8_t depth_bits_array[2];
 138     u_int8_t stencil_bits_array[2];
 139
 140
 141     depth_bits_array[0] = depth_bits;
 142     depth_bits_array[1] = depth_bits;
 143
 144     /* Just like with the accumulation buffer, always provide some modes
 145      * with a stencil buffer.  It will be a sw fallback, but some apps won't
 146      * care about that.
 147      */
 148     stencil_bits_array[0] = 0;
 149     stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
 150
 151     depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
 152     back_buffer_factor  = (have_back_buffer) ? 2 : 1;
 153
 154     num_modes = depth_buffer_factor * back_buffer_factor * 4;
 155
 156     if ( pixel_bits == 16 ) {
 157         fb_format = GL_RGB;
 158         fb_type = GL_UNSIGNED_SHORT_5_6_5;
 159     }
 160     else {
 161         fb_format = GL_BGRA;
 162         fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
 163     }
 164
 165     modes = (*create_context_modes)( num_modes, sizeof( __GLcontextModes ) );
 166     m = modes;
 167     if ( ! driFillInModes( & m, fb_format, fb_type,
 168                            depth_bits_array, stencil_bits_array, depth_buffer_factor,
 169                            back_buffer_modes, back_buffer_factor,
 170                            GLX_TRUE_COLOR ) ) {
 171         fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
 172                  __func__, __LINE__ );
 173         return NULL;
 174     }
 175
 176     if ( ! driFillInModes( & m, fb_format, fb_type,
 177                            depth_bits_array, stencil_bits_array, depth_buffer_factor,
 178                            back_buffer_modes, back_buffer_factor,
 179                            GLX_DIRECT_COLOR ) ) {
 180         fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
 181                  __func__, __LINE__ );
 182         return NULL;
 183     }
 184
 185     /* Mark the visual as slow if there are "fake" stencil bits.
 186      */
 187     for ( m = modes ; m != NULL ; m = m->next ) {
 188         if ( (m->stencilBits != 0) && (m->stencilBits != stencil_bits) ) {
 189             m->visualRating = GLX_SLOW_CONFIG;
 190         }
 191     }
 192
 193     return modes;
 194 }
 195 #endif /* USE_NEW_INTERFACE */
 196
 197 /* Create the device specific screen private data struct.
 198  */
 199 radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv )
 200 {
 201    radeonScreenPtr screen;
 202    RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
 203    unsigned char *RADEONMMIO;
 204
 205
 206    /* Allocate the private area */
 207    screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
 208    if ( !screen ) {
 209       __driUtilMessage("%s: Could not allocate memory for screen structure",
 210                        __FUNCTION__);
 211       return NULL;
 212    }
 213
 214    /* parse information in __driConfigOptions */
 215    driParseOptionInfo (&screen->optionCache,
 216                        __driConfigOptions, __driNConfigOptions);
 217
 218    /* This is first since which regions we map depends on whether or
 219     * not we are using a PCI card.
 220     */
 221    screen->IsPCI = dri_priv->IsPCI;
 222
 223    {
 224       int ret;
 225       drm_radeon_getparam_t gp;
 226
 227       gp.param = RADEON_PARAM_GART_BUFFER_OFFSET;
 228       gp.value = &screen->gart_buffer_offset;
 229
 230       ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
 231                                  &gp, sizeof(gp));
 232       if (ret) {
 233          FREE( screen );
 234          fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
 235          return NULL;
 236       }
 237
 238       if (sPriv->drmMinor >= 6) {
 239          gp.param = RADEON_PARAM_IRQ_NR;
 240          gp.value = &screen->irq;
 241
 242          ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
 243                                     &gp, sizeof(gp));
 244          if (ret) {
 245             FREE( screen );
 246             fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
 247             return NULL;
 248          }
 249       }
 250    }
 251
 252    screen->mmio.handle = dri_priv->registerHandle;
 253    screen->mmio.size   = dri_priv->registerSize;
 254    if ( drmMap( sPriv->fd,
 255                 screen->mmio.handle,
 256                 screen->mmio.size,
 257                 &screen->mmio.map ) ) {
 258       FREE( screen );
 259       __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
 260       return NULL;
 261    }
 262
 263    RADEONMMIO = screen->mmio.map;
 264
 265    screen->status.handle = dri_priv->statusHandle;
 266    screen->status.size   = dri_priv->statusSize;
 267    if ( drmMap( sPriv->fd,
 268                 screen->status.handle,
 269                 screen->status.size,
 270                 &screen->status.map ) ) {
 271       drmUnmap( screen->mmio.map, screen->mmio.size );
 272       FREE( screen );
 273       __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
 274       return NULL;
 275    }
 276    screen->scratch = (__volatile__ u_int32_t *)
 277       ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
 278
 279    screen->buffers = drmMapBufs( sPriv->fd );
 280    if ( !screen->buffers ) {
 281       drmUnmap( screen->status.map, screen->status.size );
 282       drmUnmap( screen->mmio.map, screen->mmio.size );
 283       FREE( screen );
 284       __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
 285       return NULL;
 286    }
 287
 288    if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
 289       screen->gartTextures.handle = dri_priv->gartTexHandle;
 290       screen->gartTextures.size   = dri_priv->gartTexMapSize;
 291       if ( drmMap( sPriv->fd,
 292                    screen->gartTextures.handle,
 293                    screen->gartTextures.size,
 294                    (drmAddressPtr)&screen->gartTextures.map ) ) {
 295          drmUnmapBufs( screen->buffers );
 296          drmUnmap( screen->status.map, screen->status.size );
 297          drmUnmap( screen->mmio.map, screen->mmio.size );
 298          FREE( screen );
 299          __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
 300          return NULL;
 301       }
 302
 303       screen->gart_texture_offset = dri_priv->gartTexOffset + ( screen->IsPCI
 304                 ? INREG( RADEON_AIC_LO_ADDR )
 305                 : ( ( INREG( RADEON_MC_AGP_LOCATION ) & 0x0ffffU ) << 16 ) );
 306    }
 307
 308    screen->chipset = 0;
 309    switch ( dri_priv->deviceID ) {
 310    default:
 311       fprintf(stderr, "unknown chip id, assuming full radeon support\n");
 312    case PCI_CHIP_RADEON_QD:
 313    case PCI_CHIP_RADEON_QE:
 314    case PCI_CHIP_RADEON_QF:
 315    case PCI_CHIP_RADEON_QG:
 316       /* all original radeons (7200) presumably have a stencil op bug */
 317       screen->chipset |= RADEON_CHIPSET_BROKEN_STENCIL;
 318    case PCI_CHIP_RV200_QW:
 319    case PCI_CHIP_RV200_QX:
 320    case PCI_CHIP_RADEON_LW:
 321    case PCI_CHIP_RADEON_LX:
 322       screen->chipset |= RADEON_CHIPSET_TCL;
 323    case PCI_CHIP_RADEON_QY:
 324    case PCI_CHIP_RADEON_QZ:
 325    case PCI_CHIP_RADEON_LY:
 326    case PCI_CHIP_RADEON_LZ:
 327    case PCI_CHIP_RS100_4136: /* IGPs don't have TCL */
 328    case PCI_CHIP_RS200_4137:
 329    case PCI_CHIP_RS250_4237:
 330    case PCI_CHIP_RS100_4336:
 331    case PCI_CHIP_RS200_4337:
 332    case PCI_CHIP_RS250_4437:
 333       break;
 334    }
 335
 336    screen->cpp = dri_priv->bpp / 8;
 337    screen->AGPMode = dri_priv->AGPMode;
 338
 339    screen->fbLocation   = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff ) << 16;
 340
 341    if ( sPriv->drmMinor >= 10 ) {
 342       drm_radeon_setparam_t sp;
 343
 344       sp.param = RADEON_SETPARAM_FB_LOCATION;
 345       sp.value = screen->fbLocation;
 346
 347       drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
 348                        &sp, sizeof( sp ) );
 349    }
 350
 351    screen->frontOffset  = dri_priv->frontOffset;
 352    screen->frontPitch   = dri_priv->frontPitch;
 353    screen->backOffset   = dri_priv->backOffset;
 354    screen->backPitch    = dri_priv->backPitch;
 355    screen->depthOffset  = dri_priv->depthOffset;
 356    screen->depthPitch   = dri_priv->depthPitch;
 357
 358    /* Check if ddx has set up a surface reg to cover depth buffer */
 359    screen->depthHasSurface = ((sPriv->ddxMajor > 4) &&
 360       (screen->chipset & RADEON_CHIPSET_TCL));
 361
 362    screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
 363                                        + screen->fbLocation;
 364    screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
 365    screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
 366       dri_priv->log2TexGran;
 367
 368    if ( !screen->gartTextures.map
 369         || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
 370       screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
 371       screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
 372       screen->texSize[RADEON_GART_TEX_HEAP] = 0;
 373       screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
 374    } else {
 375       screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
 376       screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
 377       screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
 378       screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
 379          dri_priv->log2GARTTexGran;
 380    }
 381
 382    if ( driCompareGLXAPIVersion( 20030813 ) >= 0 ) {
 383       PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension =
 384           (PFNGLXSCRENABLEEXTENSIONPROC) glXGetProcAddress( (const GLubyte *) "__glXScrEnableExtension" );
 385       void * const psc = sPriv->psc->screenConfigs;
 386
 387       if ( glx_enable_extension != NULL ) {
 388          if ( screen->irq != 0 ) {
 389             (*glx_enable_extension)( psc, "GLX_SGI_swap_control" );
 390             (*glx_enable_extension)( psc, "GLX_SGI_video_sync" );
 391             (*glx_enable_extension)( psc, "GLX_MESA_swap_control" );
 392          }
 393
 394          (*glx_enable_extension)( psc, "GLX_MESA_swap_frame_usage" );
 395
 396          if ( driCompareGLXAPIVersion( 20030915 ) >= 0 ) {
 397             (*glx_enable_extension)( psc, "GLX_SGIX_fbconfig" );
 398             (*glx_enable_extension)( psc, "GLX_OML_swap_method" );
 399          }
 400
 401       }
 402    }
 403
 404    screen->driScreen = sPriv;
 405    screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
 406    return screen;
 407 }
 408
 409 /* Destroy the device specific screen private data struct.
 410  */
 411 void radeonDestroyScreen( __DRIscreenPrivate *sPriv )
 412 {
 413    radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
 414
 415    if (!screen)
 416       return;
 417
 418    if ( screen->gartTextures.map ) {
 419       drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
 420    }
 421    drmUnmapBufs( screen->buffers );
 422    drmUnmap( screen->status.map, screen->status.size );
 423    drmUnmap( screen->mmio.map, screen->mmio.size );
 424
 425    /* free all option information */
 426    driDestroyOptionInfo (&screen->optionCache);
 427
 428    FREE( screen );
 429    sPriv->private = NULL;
 430 }
 431
 432
 433 /* Initialize the driver specific screen private data.
 434  */
 435 static GLboolean
 436 radeonInitDriver( __DRIscreenPrivate *sPriv )
 437 {
 438    sPriv->private = (void *) radeonCreateScreen( sPriv );
 439    if ( !sPriv->private ) {
 440       radeonDestroyScreen( sPriv );
 441       return GL_FALSE;
 442    }
 443
 444    return GL_TRUE;
 445 }
 446
 447
 448
 449 /**
 450  * Create and initialize the Mesa and driver specific pixmap buffer
 451  * data.
 452  *
 453  * \todo This function (and its interface) will need to be updated to support
 454  * pbuffers.
 455  */
 456 static GLboolean
 457 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
 458                     __DRIdrawablePrivate *driDrawPriv,
 459                     const __GLcontextModes *mesaVis,
 460                     GLboolean isPixmap )
 461 {
 462    if (isPixmap) {
 463       return GL_FALSE; /* not implemented */
 464    }
 465    else {
 466       const GLboolean swDepth = GL_FALSE;
 467       const GLboolean swAlpha = GL_FALSE;
 468       const GLboolean swAccum = mesaVis->accumRedBits > 0;
 469       const GLboolean swStencil = mesaVis->stencilBits > 0 &&
 470          mesaVis->depthBits != 24;
 471       driDrawPriv->driverPrivate = (void *)
 472          _mesa_create_framebuffer( mesaVis,
 473                                    swDepth,
 474                                    swStencil,
 475                                    swAccum,
 476                                    swAlpha );
 477       return (driDrawPriv->driverPrivate != NULL);
 478    }
 479 }
 480
 481
 482 static void
 483 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
 484 {
 485    _mesa_destroy_framebuffer((GLframebuffer *) (driDrawPriv->driverPrivate));
 486 }
 487
 488 static struct __DriverAPIRec radeonAPI = {
 489    .InitDriver      = radeonInitDriver,
 490    .DestroyScreen   = radeonDestroyScreen,
 491    .CreateContext   = radeonCreateContext,
 492    .DestroyContext  = radeonDestroyContext,
 493    .CreateBuffer    = radeonCreateBuffer,
 494    .DestroyBuffer   = radeonDestroyBuffer,
 495    .SwapBuffers     = radeonSwapBuffers,
 496    .MakeCurrent     = radeonMakeCurrent,
 497    .UnbindContext   = radeonUnbindContext,
 498    .GetSwapInfo     = getSwapInfo,
 499    .GetMSC          = driGetMSC32,
 500    .WaitForMSC      = driWaitForMSC32,
 501    .WaitForSBC      = NULL,
 502    .SwapBuffersMSC  = NULL
 503 };
 504
 505
 506 /*
 507  * This is the bootstrap function for the driver.
 508  * The __driCreateScreen name is the symbol that libGL.so fetches.
 509  * Return:  pointer to a __DRIscreenPrivate.
 510  */
 511 #if !defined(DRI_NEW_INTERFACE_ONLY)
 512 void *__driCreateScreen(Display *dpy, int scrn, __DRIscreen *psc,
 513                         int numConfigs, __GLXvisualConfig *config)
 514 {
 515    __DRIscreenPrivate *psp;
 516    psp = __driUtilCreateScreen(dpy, scrn, psc, numConfigs, config, &radeonAPI);
 517    return (void *) psp;
 518 }
 519 #endif /* !defined(DRI_NEW_INTERFACE_ONLY) */
 520
 521 /**
 522  * This is the bootstrap function for the driver.  libGL supplies all of the
 523  * requisite information about the system, and the driver initializes itself.
 524  * This routine also fills in the linked list pointed to by \c driver_modes
 525  * with the \c __GLcontextModes that the driver can support for windows or
 526  * pbuffers.
 527  *
 528  * \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on
 529  *         failure.
 530  */
 531 #ifdef USE_NEW_INTERFACE
 532 PUBLIC
 533 void * __driCreateNewScreen( __DRInativeDisplay *dpy, int scrn, __DRIscreen *psc,
 534                              const __GLcontextModes * modes,
 535                              const __DRIversion * ddx_version,
 536                              const __DRIversion * dri_version,
 537                              const __DRIversion * drm_version,
 538                              const __DRIframebuffer * frame_buffer,
 539                              drmAddress pSAREA, int fd,
 540                              int internal_api_version,
 541                              __GLcontextModes ** driver_modes )
 542
 543 {
 544    __DRIscreenPrivate *psp;
 545    static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
 546    static const __DRIversion dri_expected = { 4, 0, 0 };
 547    static const __DRIversion drm_expected = { 1, 3, 0 };
 548
 549    if ( ! driCheckDriDdxDrmVersions3( "Radeon",
 550                                       dri_version, & dri_expected,
 551                                       ddx_version, & ddx_expected,
 552                                       drm_version, & drm_expected ) ) {
 553       return NULL;
 554    }
 555
 556    psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
 557                                   ddx_version, dri_version, drm_version,
 558                                   frame_buffer, pSAREA, fd,
 559                                   internal_api_version, &radeonAPI);
 560    if ( psp != NULL ) {
 561       create_context_modes = (PFNGLXCREATECONTEXTMODES)
 562           glXGetProcAddress( (const GLubyte *) "__glXCreateContextModes" );
 563       if ( create_context_modes != NULL ) {
 564          RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
 565          *driver_modes = radeonFillInModes( dri_priv->bpp,
 566                                             (dri_priv->bpp == 16) ? 16 : 24,
 567                                             (dri_priv->bpp == 16) ? 0  : 8,
 568                                             (dri_priv->backOffset != dri_priv->depthOffset) );
 569       }
 570    }
 571
 572    return (void *) psp;
 573 }
 574 #endif /* USE_NEW_INTERFACE */
 575
 576 /**
 577  * Get information about previous buffer swaps.
 578  */
 579 static int
 580 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
 581 {
 582    radeonContextPtr  rmesa;
 583
 584    if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
 585         || (dPriv->driContextPriv->driverPrivate == NULL)
 586         || (sInfo == NULL) ) {
 587       return -1;
 588    }
 589
 590    rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
 591    sInfo->swap_count = rmesa->swap_count;
 592    sInfo->swap_ust = rmesa->swap_ust;
 593    sInfo->swap_missed_count = rmesa->swap_missed_count;
 594
 595    sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
 596        ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
 597        : 0.0;
 598
 599    return 0;
 600 }