src/mesa/drivers/dri/radeon/radeon_screen.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
   2 /**************************************************************************
   3
   4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   5                      VA Linux Systems Inc., Fremont, California.
   6
   7 All Rights Reserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining
  10 a copy of this software and associated documentation files (the
  11 "Software"), to deal in the Software without restriction, including
  12 without limitation the rights to use, copy, modify, merge, publish,
  13 distribute, sublicense, and/or sell copies of the Software, and to
  14 permit persons to whom the Software is furnished to do so, subject to
  15 the following conditions:
  16
  17 The above copyright notice and this permission notice (including the
  18 next paragraph) shall be included in all copies or substantial
  19 portions of the Software.
  20
  21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28
  29 **************************************************************************/
  30
  31 /**
  32  * \file radeon_screen.c
  33  * Screen initialization functions for the Radeon driver.
  34  *
  35  * \author Kevin E. Martin <martin@valinux.com>
  36  * \author  Gareth Hughes <gareth@valinux.com>
  37  */
  38
  39 #include "glheader.h"
  40 #include "imports.h"
  41 #include "mtypes.h"
  42 #include "framebuffer.h"
  43 #include "renderbuffer.h"
  44
  45 #define STANDALONE_MMIO
  46 #include "radeon_context.h"
  47 #include "radeon_screen.h"
  48 #include "radeon_macros.h"
  49 #include "radeon_span.h"
  50
  51 #include "utils.h"
  52 #include "context.h"
  53 #include "vblank.h"
  54 #include "drirenderbuffer.h"
  55
  56 #include "GL/internal/dri_interface.h"
  57
  58 /* Radeon configuration
  59  */
  60 #include "xmlpool.h"
  61
  62 PUBLIC const char __driConfigOptions[] =
  63 DRI_CONF_BEGIN
  64     DRI_CONF_SECTION_PERFORMANCE
  65         DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
  66         DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
  67         DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
  68         DRI_CONF_HYPERZ(false)
  69     DRI_CONF_SECTION_END
  70     DRI_CONF_SECTION_QUALITY
  71         DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
  72         DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
  73         DRI_CONF_NO_NEG_LOD_BIAS(false)
  74         DRI_CONF_FORCE_S3TC_ENABLE(false)
  75         DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
  76         DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
  77         DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
  78         DRI_CONF_TEXTURE_LEVEL_HACK(false)
  79     DRI_CONF_SECTION_END
  80     DRI_CONF_SECTION_DEBUG
  81         DRI_CONF_NO_RAST(false)
  82     DRI_CONF_SECTION_END
  83 DRI_CONF_END;
  84 static const GLuint __driNConfigOptions = 13;
  85
  86 extern const struct dri_extension card_extensions[];
  87
  88 #if 1
  89 /* Including xf86PciInfo.h introduces a bunch of errors...
  90  */
  91 #define PCI_CHIP_RADEON_QD      0x5144
  92 #define PCI_CHIP_RADEON_QE      0x5145
  93 #define PCI_CHIP_RADEON_QF      0x5146
  94 #define PCI_CHIP_RADEON_QG      0x5147
  95
  96 #define PCI_CHIP_RADEON_QY      0x5159
  97 #define PCI_CHIP_RADEON_QZ      0x515A
  98
  99 #define PCI_CHIP_RN50_515E      0x515E
 100 #define PCI_CHIP_RN50_5969      0x5969
 101
 102 #define PCI_CHIP_RADEON_LW      0x4C57 /* mobility 7 - has tcl */
 103 #define PCI_CHIP_RADEON_LX      0x4C58 /* mobility FireGL 7800 m7 */
 104
 105 #define PCI_CHIP_RADEON_LY      0x4C59
 106 #define PCI_CHIP_RADEON_LZ      0x4C5A
 107
 108 #define PCI_CHIP_RV200_QW       0x5157 /* Radeon 7500 - not an R200 at all */
 109 #define PCI_CHIP_RV200_QX       0x5158
 110
 111 /* IGP Chipsets */
 112 #define PCI_CHIP_RS100_4136     0x4136
 113 #define PCI_CHIP_RS200_4137     0x4137
 114 #define PCI_CHIP_RS250_4237     0x4237
 115 #define PCI_CHIP_RS100_4336     0x4336
 116 #define PCI_CHIP_RS200_4337     0x4337
 117 #define PCI_CHIP_RS250_4437     0x4437
 118 #endif
 119
 120
 121 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
 122
 123 static __GLcontextModes *
 124 radeonFillInModes( unsigned pixel_bits, unsigned depth_bits,
 125                  unsigned stencil_bits, GLboolean have_back_buffer )
 126 {
 127     __GLcontextModes * modes;
 128     __GLcontextModes * m;
 129     unsigned num_modes;
 130     unsigned depth_buffer_factor;
 131     unsigned back_buffer_factor;
 132     GLenum fb_format;
 133     GLenum fb_type;
 134
 135     /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
 136      * enough to add support.  Basically, if a context is created with an
 137      * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
 138      * will never be used.
 139      */
 140     static const GLenum back_buffer_modes[] = {
 141         GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
 142     };
 143
 144     u_int8_t depth_bits_array[2];
 145     u_int8_t stencil_bits_array[2];
 146
 147
 148     depth_bits_array[0] = depth_bits;
 149     depth_bits_array[1] = depth_bits;
 150
 151     /* Just like with the accumulation buffer, always provide some modes
 152      * with a stencil buffer.  It will be a sw fallback, but some apps won't
 153      * care about that.
 154      */
 155     stencil_bits_array[0] = 0;
 156     stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
 157
 158     depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
 159     back_buffer_factor  = (have_back_buffer) ? 2 : 1;
 160
 161     num_modes = depth_buffer_factor * back_buffer_factor * 4;
 162
 163     if ( pixel_bits == 16 ) {
 164         fb_format = GL_RGB;
 165         fb_type = GL_UNSIGNED_SHORT_5_6_5;
 166     }
 167     else {
 168         fb_format = GL_BGRA;
 169         fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
 170     }
 171
 172     modes = (*dri_interface->createContextModes)( num_modes, sizeof( __GLcontextModes ) );
 173     m = modes;
 174     if ( ! driFillInModes( & m, fb_format, fb_type,
 175                            depth_bits_array, stencil_bits_array, depth_buffer_factor,
 176                            back_buffer_modes, back_buffer_factor,
 177                            GLX_TRUE_COLOR ) ) {
 178         fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
 179                  __func__, __LINE__ );
 180         return NULL;
 181     }
 182
 183     if ( ! driFillInModes( & m, fb_format, fb_type,
 184                            depth_bits_array, stencil_bits_array, depth_buffer_factor,
 185                            back_buffer_modes, back_buffer_factor,
 186                            GLX_DIRECT_COLOR ) ) {
 187         fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
 188                  __func__, __LINE__ );
 189         return NULL;
 190     }
 191
 192     /* Mark the visual as slow if there are "fake" stencil bits.
 193      */
 194     for ( m = modes ; m != NULL ; m = m->next ) {
 195         if ( (m->stencilBits != 0) && (m->stencilBits != stencil_bits) ) {
 196             m->visualRating = GLX_SLOW_CONFIG;
 197         }
 198     }
 199
 200     return modes;
 201 }
 202
 203
 204 /* Create the device specific screen private data struct.
 205  */
 206 static radeonScreenPtr
 207 radeonCreateScreen( __DRIscreenPrivate *sPriv )
 208 {
 209    radeonScreenPtr screen;
 210    RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
 211    unsigned char *RADEONMMIO;
 212    PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension =
 213      (PFNGLXSCRENABLEEXTENSIONPROC) (*dri_interface->getProcAddress("glxEnableExtension"));
 214    void * const psc = sPriv->psc->screenConfigs;
 215
 216    if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
 217       fprintf(stderr,"\nERROR!  sizeof(RADEONDRIRec) does not match passed size from device driver\n");
 218       return GL_FALSE;
 219    }
 220
 221    /* Allocate the private area */
 222    screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
 223    if ( !screen ) {
 224       __driUtilMessage("%s: Could not allocate memory for screen structure",
 225                        __FUNCTION__);
 226       return NULL;
 227    }
 228
 229    /* parse information in __driConfigOptions */
 230    driParseOptionInfo (&screen->optionCache,
 231                        __driConfigOptions, __driNConfigOptions);
 232
 233    /* This is first since which regions we map depends on whether or
 234     * not we are using a PCI card.
 235     */
 236    screen->IsPCI = dri_priv->IsPCI;
 237
 238    {
 239       int ret;
 240       drm_radeon_getparam_t gp;
 241
 242       gp.param = RADEON_PARAM_GART_BUFFER_OFFSET;
 243       gp.value = &screen->gart_buffer_offset;
 244
 245       ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
 246                                  &gp, sizeof(gp));
 247       if (ret) {
 248          FREE( screen );
 249          fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
 250          return NULL;
 251       }
 252
 253       if (sPriv->drmMinor >= 6) {
 254          gp.param = RADEON_PARAM_IRQ_NR;
 255          gp.value = &screen->irq;
 256
 257          ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
 258                                     &gp, sizeof(gp));
 259          if (ret) {
 260             FREE( screen );
 261             fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
 262             return NULL;
 263          }
 264       }
 265    }
 266
 267    screen->mmio.handle = dri_priv->registerHandle;
 268    screen->mmio.size   = dri_priv->registerSize;
 269    if ( drmMap( sPriv->fd,
 270                 screen->mmio.handle,
 271                 screen->mmio.size,
 272                 &screen->mmio.map ) ) {
 273       FREE( screen );
 274       __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
 275       return NULL;
 276    }
 277
 278    RADEONMMIO = screen->mmio.map;
 279
 280    screen->status.handle = dri_priv->statusHandle;
 281    screen->status.size   = dri_priv->statusSize;
 282    if ( drmMap( sPriv->fd,
 283                 screen->status.handle,
 284                 screen->status.size,
 285                 &screen->status.map ) ) {
 286       drmUnmap( screen->mmio.map, screen->mmio.size );
 287       FREE( screen );
 288       __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
 289       return NULL;
 290    }
 291    screen->scratch = (__volatile__ u_int32_t *)
 292       ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
 293
 294    screen->buffers = drmMapBufs( sPriv->fd );
 295    if ( !screen->buffers ) {
 296       drmUnmap( screen->status.map, screen->status.size );
 297       drmUnmap( screen->mmio.map, screen->mmio.size );
 298       FREE( screen );
 299       __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
 300       return NULL;
 301    }
 302
 303    if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
 304       screen->gartTextures.handle = dri_priv->gartTexHandle;
 305       screen->gartTextures.size   = dri_priv->gartTexMapSize;
 306       if ( drmMap( sPriv->fd,
 307                    screen->gartTextures.handle,
 308                    screen->gartTextures.size,
 309                    (drmAddressPtr)&screen->gartTextures.map ) ) {
 310          drmUnmapBufs( screen->buffers );
 311          drmUnmap( screen->status.map, screen->status.size );
 312          drmUnmap( screen->mmio.map, screen->mmio.size );
 313          FREE( screen );
 314          __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
 315          return NULL;
 316       }
 317
 318       screen->gart_texture_offset = dri_priv->gartTexOffset + ( screen->IsPCI
 319                 ? INREG( RADEON_AIC_LO_ADDR )
 320                 : ( ( INREG( RADEON_MC_AGP_LOCATION ) & 0x0ffffU ) << 16 ) );
 321    }
 322
 323    screen->chipset = 0;
 324    switch ( dri_priv->deviceID ) {
 325    default:
 326       fprintf(stderr, "unknown chip id, assuming full radeon support\n");
 327    case PCI_CHIP_RADEON_QD:
 328    case PCI_CHIP_RADEON_QE:
 329    case PCI_CHIP_RADEON_QF:
 330    case PCI_CHIP_RADEON_QG:
 331       /* all original radeons (7200) presumably have a stencil op bug */
 332       screen->chipset |= RADEON_CHIPSET_BROKEN_STENCIL;
 333    case PCI_CHIP_RV200_QW:
 334    case PCI_CHIP_RV200_QX:
 335    case PCI_CHIP_RADEON_LW:
 336    case PCI_CHIP_RADEON_LX:
 337       screen->chipset |= RADEON_CHIPSET_TCL;
 338    case PCI_CHIP_RADEON_QY:
 339    case PCI_CHIP_RADEON_QZ:
 340    case PCI_CHIP_RN50_515E:
 341    case PCI_CHIP_RN50_5969:
 342    case PCI_CHIP_RADEON_LY:
 343    case PCI_CHIP_RADEON_LZ:
 344    case PCI_CHIP_RS100_4136: /* IGPs don't have TCL */
 345    case PCI_CHIP_RS200_4137:
 346    case PCI_CHIP_RS250_4237:
 347    case PCI_CHIP_RS100_4336:
 348    case PCI_CHIP_RS200_4337:
 349    case PCI_CHIP_RS250_4437:
 350       break;
 351    }
 352
 353    screen->cpp = dri_priv->bpp / 8;
 354    screen->AGPMode = dri_priv->AGPMode;
 355
 356    screen->fbLocation   = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff ) << 16;
 357
 358    if ( sPriv->drmMinor >= 10 ) {
 359       drm_radeon_setparam_t sp;
 360
 361       sp.param = RADEON_SETPARAM_FB_LOCATION;
 362       sp.value = screen->fbLocation;
 363
 364       drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
 365                        &sp, sizeof( sp ) );
 366    }
 367
 368    screen->frontOffset  = dri_priv->frontOffset;
 369    screen->frontPitch   = dri_priv->frontPitch;
 370    screen->backOffset   = dri_priv->backOffset;
 371    screen->backPitch    = dri_priv->backPitch;
 372    screen->depthOffset  = dri_priv->depthOffset;
 373    screen->depthPitch   = dri_priv->depthPitch;
 374
 375    /* Check if ddx has set up a surface reg to cover depth buffer */
 376    screen->depthHasSurface = ((sPriv->ddxMajor > 4) &&
 377       (screen->chipset & RADEON_CHIPSET_TCL));
 378
 379    screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
 380                                        + screen->fbLocation;
 381    screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
 382    screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
 383       dri_priv->log2TexGran;
 384
 385    if ( !screen->gartTextures.map
 386         || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
 387       screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
 388       screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
 389       screen->texSize[RADEON_GART_TEX_HEAP] = 0;
 390       screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
 391    } else {
 392       screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
 393       screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
 394       screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
 395       screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
 396          dri_priv->log2GARTTexGran;
 397    }
 398
 399    if ( glx_enable_extension != NULL ) {
 400       if ( screen->irq != 0 ) {
 401          (*glx_enable_extension)( psc, "GLX_SGI_swap_control" );
 402          (*glx_enable_extension)( psc, "GLX_SGI_video_sync" );
 403          (*glx_enable_extension)( psc, "GLX_MESA_swap_control" );
 404       }
 405
 406       (*glx_enable_extension)( psc, "GLX_MESA_swap_frame_usage" );
 407    }
 408
 409    screen->driScreen = sPriv;
 410    screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
 411    return screen;
 412 }
 413
 414 /* Destroy the device specific screen private data struct.
 415  */
 416 static void
 417 radeonDestroyScreen( __DRIscreenPrivate *sPriv )
 418 {
 419    radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
 420
 421    if (!screen)
 422       return;
 423
 424    if ( screen->gartTextures.map ) {
 425       drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
 426    }
 427    drmUnmapBufs( screen->buffers );
 428    drmUnmap( screen->status.map, screen->status.size );
 429    drmUnmap( screen->mmio.map, screen->mmio.size );
 430
 431    /* free all option information */
 432    driDestroyOptionInfo (&screen->optionCache);
 433
 434    FREE( screen );
 435    sPriv->private = NULL;
 436 }
 437
 438
 439 /* Initialize the driver specific screen private data.
 440  */
 441 static GLboolean
 442 radeonInitDriver( __DRIscreenPrivate *sPriv )
 443 {
 444    sPriv->private = (void *) radeonCreateScreen( sPriv );
 445    if ( !sPriv->private ) {
 446       radeonDestroyScreen( sPriv );
 447       return GL_FALSE;
 448    }
 449
 450    return GL_TRUE;
 451 }
 452
 453
 454 /**
 455  * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
 456  *
 457  * \todo This function (and its interface) will need to be updated to support
 458  * pbuffers.
 459  */
 460 static GLboolean
 461 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
 462                     __DRIdrawablePrivate *driDrawPriv,
 463                     const __GLcontextModes *mesaVis,
 464                     GLboolean isPixmap )
 465 {
 466    radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
 467
 468    if (isPixmap) {
 469       return GL_FALSE; /* not implemented */
 470    }
 471    else {
 472       const GLboolean swDepth = GL_FALSE;
 473       const GLboolean swAlpha = GL_FALSE;
 474       const GLboolean swAccum = mesaVis->accumRedBits > 0;
 475       const GLboolean swStencil = mesaVis->stencilBits > 0 &&
 476          mesaVis->depthBits != 24;
 477       struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
 478
 479       /* front color renderbuffer */
 480       {
 481          driRenderbuffer *frontRb
 482             = driNewRenderbuffer(GL_RGBA,
 483                                  driScrnPriv->pFB + screen->frontOffset,
 484                                  screen->cpp,
 485                                  screen->frontOffset, screen->frontPitch,
 486                                  driDrawPriv);
 487          radeonSetSpanFunctions(frontRb, mesaVis);
 488          _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
 489       }
 490
 491       /* back color renderbuffer */
 492       if (mesaVis->doubleBufferMode) {
 493          driRenderbuffer *backRb
 494             = driNewRenderbuffer(GL_RGBA,
 495                                  driScrnPriv->pFB + screen->backOffset,
 496                                  screen->cpp,
 497                                  screen->backOffset, screen->backPitch,
 498                                  driDrawPriv);
 499          radeonSetSpanFunctions(backRb, mesaVis);
 500          _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
 501       }
 502
 503       /* depth renderbuffer */
 504       if (mesaVis->depthBits == 16) {
 505          driRenderbuffer *depthRb
 506             = driNewRenderbuffer(GL_DEPTH_COMPONENT16,
 507                                  driScrnPriv->pFB + screen->depthOffset,
 508                                  screen->cpp,
 509                                  screen->depthOffset, screen->depthPitch,
 510                                  driDrawPriv);
 511          radeonSetSpanFunctions(depthRb, mesaVis);
 512          _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
 513          depthRb->depthHasSurface = screen->depthHasSurface;
 514       }
 515       else if (mesaVis->depthBits == 24) {
 516          driRenderbuffer *depthRb
 517             = driNewRenderbuffer(GL_DEPTH_COMPONENT24,
 518                                  driScrnPriv->pFB + screen->depthOffset,
 519                                  screen->cpp,
 520                                  screen->depthOffset, screen->depthPitch,
 521                                  driDrawPriv);
 522          radeonSetSpanFunctions(depthRb, mesaVis);
 523          _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
 524          depthRb->depthHasSurface = screen->depthHasSurface;
 525       }
 526
 527       /* stencil renderbuffer */
 528       if (mesaVis->stencilBits > 0 && !swStencil) {
 529          driRenderbuffer *stencilRb
 530             = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT,
 531                                  driScrnPriv->pFB + screen->depthOffset,
 532                                  screen->cpp,
 533                                  screen->depthOffset, screen->depthPitch,
 534                                  driDrawPriv);
 535          radeonSetSpanFunctions(stencilRb, mesaVis);
 536          _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
 537          stencilRb->depthHasSurface = screen->depthHasSurface;
 538       }
 539
 540       _mesa_add_soft_renderbuffers(fb,
 541                                    GL_FALSE, /* color */
 542                                    swDepth,
 543                                    swStencil,
 544                                    swAccum,
 545                                    swAlpha,
 546                                    GL_FALSE /* aux */);
 547       driDrawPriv->driverPrivate = (void *) fb;
 548
 549       return (driDrawPriv->driverPrivate != NULL);
 550    }
 551 }
 552
 553
 554 static void
 555 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
 556 {
 557    _mesa_destroy_framebuffer((GLframebuffer *) (driDrawPriv->driverPrivate));
 558 }
 559
 560 static struct __DriverAPIRec radeonAPI = {
 561    .InitDriver      = radeonInitDriver,
 562    .DestroyScreen   = radeonDestroyScreen,
 563    .CreateContext   = radeonCreateContext,
 564    .DestroyContext  = radeonDestroyContext,
 565    .CreateBuffer    = radeonCreateBuffer,
 566    .DestroyBuffer   = radeonDestroyBuffer,
 567    .SwapBuffers     = radeonSwapBuffers,
 568    .MakeCurrent     = radeonMakeCurrent,
 569    .UnbindContext   = radeonUnbindContext,
 570    .GetSwapInfo     = getSwapInfo,
 571    .GetMSC          = driGetMSC32,
 572    .WaitForMSC      = driWaitForMSC32,
 573    .WaitForSBC      = NULL,
 574    .SwapBuffersMSC  = NULL
 575 };
 576
 577
 578 /**
 579  * This is the bootstrap function for the driver.  libGL supplies all of the
 580  * requisite information about the system, and the driver initializes itself.
 581  * This routine also fills in the linked list pointed to by \c driver_modes
 582  * with the \c __GLcontextModes that the driver can support for windows or
 583  * pbuffers.
 584  *
 585  * \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on
 586  *         failure.
 587  */
 588 PUBLIC void *
 589 __driCreateNewScreen_20050727( __DRInativeDisplay *dpy,
 590                              int scrn, __DRIscreen *psc,
 591                              const __GLcontextModes * modes,
 592                              const __DRIversion * ddx_version,
 593                              const __DRIversion * dri_version,
 594                              const __DRIversion * drm_version,
 595                              const __DRIframebuffer * frame_buffer,
 596                              drmAddress pSAREA, int fd,
 597                              int internal_api_version,
 598                              const __DRIinterfaceMethods * interface,
 599                              __GLcontextModes ** driver_modes )
 600 {
 601    __DRIscreenPrivate *psp;
 602    static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
 603    static const __DRIversion dri_expected = { 4, 0, 0 };
 604    static const __DRIversion drm_expected = { 1, 3, 0 };
 605
 606    dri_interface = interface;
 607
 608    if ( ! driCheckDriDdxDrmVersions3( "Radeon",
 609                                       dri_version, & dri_expected,
 610                                       ddx_version, & ddx_expected,
 611                                       drm_version, & drm_expected ) ) {
 612       return NULL;
 613    }
 614
 615    psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
 616                                   ddx_version, dri_version, drm_version,
 617                                   frame_buffer, pSAREA, fd,
 618                                   internal_api_version, &radeonAPI);
 619    if ( psp != NULL ) {
 620       RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
 621       *driver_modes = radeonFillInModes( dri_priv->bpp,
 622                                          (dri_priv->bpp == 16) ? 16 : 24,
 623                                          (dri_priv->bpp == 16) ? 0  : 8,
 624                                          (dri_priv->backOffset != dri_priv->depthOffset) );
 625
 626       /* Calling driInitExtensions here, with a NULL context pointer,
 627        * does not actually enable the extensions.  It just makes sure
 628        * that all the dispatch offsets for all the extensions that
 629        * *might* be enables are known.  This is needed because the
 630        * dispatch offsets need to be known when _mesa_context_create
 631        * is called, but we can't enable the extensions until we have a
 632        * context pointer.
 633        *
 634        * Hello chicken.  Hello egg.  How are you two today?
 635        */
 636       driInitExtensions( NULL, card_extensions, GL_FALSE );
 637    }
 638
 639    return (void *) psp;
 640 }
 641
 642
 643 /**
 644  * Get information about previous buffer swaps.
 645  */
 646 static int
 647 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
 648 {
 649    radeonContextPtr  rmesa;
 650
 651    if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
 652         || (dPriv->driContextPriv->driverPrivate == NULL)
 653         || (sInfo == NULL) ) {
 654       return -1;
 655    }
 656
 657    rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
 658    sInfo->swap_count = rmesa->swap_count;
 659    sInfo->swap_ust = rmesa->swap_ust;
 660    sInfo->swap_missed_count = rmesa->swap_missed_count;
 661
 662    sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
 663        ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
 664        : 0.0;
 665
 666    return 0;
 667 }