1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
32 * \file radeon_screen.c
33 * Screen initialization functions for the Radeon driver.
35 * \author Kevin E. Martin <martin@valinux.com>
36 * \author Gareth Hughes <gareth@valinux.com>
42 #include "framebuffer.h"
43 #include "renderbuffer.h"
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
50 #include "radeon_context.h"
51 #include "radeon_span.h"
52 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
53 #include "r200_context.h"
54 #include "r200_ioctl.h"
55 #include "r200_span.h"
56 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
57 #include "r300_context.h"
58 #include "r300_fragprog.h"
60 #include "radeon_span.h"
66 #include "drirenderbuffer.h"
68 #include "GL/internal/dri_interface.h"
70 /* Radeon configuration
74 #if !RADEON_COMMON /* R100 */
75 PUBLIC
const char __driConfigOptions
[] =
77 DRI_CONF_SECTION_PERFORMANCE
78 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
79 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
80 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
81 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
82 DRI_CONF_HYPERZ(false)
84 DRI_CONF_SECTION_QUALITY
85 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
86 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
87 DRI_CONF_NO_NEG_LOD_BIAS(false)
88 DRI_CONF_FORCE_S3TC_ENABLE(false)
89 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
90 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
91 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
92 DRI_CONF_ALLOW_LARGE_TEXTURES(1)
94 DRI_CONF_SECTION_DEBUG
95 DRI_CONF_NO_RAST(false)
98 static const GLuint __driNConfigOptions
= 14;
100 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
102 PUBLIC
const char __driConfigOptions
[] =
104 DRI_CONF_SECTION_PERFORMANCE
105 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
106 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
107 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
108 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
109 DRI_CONF_HYPERZ(false)
111 DRI_CONF_SECTION_QUALITY
112 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
113 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
114 DRI_CONF_NO_NEG_LOD_BIAS(false)
115 DRI_CONF_FORCE_S3TC_ENABLE(false)
116 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
117 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
118 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
119 DRI_CONF_ALLOW_LARGE_TEXTURES(1)
120 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
122 DRI_CONF_SECTION_DEBUG
123 DRI_CONF_NO_RAST(false)
125 DRI_CONF_SECTION_SOFTWARE
126 DRI_CONF_NV_VERTEX_PROGRAM(false)
129 static const GLuint __driNConfigOptions
= 16;
131 extern const struct dri_extension blend_extensions
[];
132 extern const struct dri_extension ARB_vp_extension
[];
133 extern const struct dri_extension NV_vp_extension
[];
134 extern const struct dri_extension ATI_fs_extension
[];
135 extern const struct dri_extension point_extensions
[];
137 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
139 /* TODO: integrate these into xmlpool.h! */
140 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
141 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
142 DRI_CONF_DESC(en,"Number of texture image units") \
143 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
146 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
147 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
148 DRI_CONF_DESC(en,"Number of texture coordinate units") \
149 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
152 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
153 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
154 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
155 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
158 #define DRI_CONF_DISABLE_S3TC(def) \
159 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
160 DRI_CONF_DESC(en,"Disable S3TC compression") \
163 #define DRI_CONF_DISABLE_FALLBACK(def) \
164 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
165 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
168 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
169 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
170 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
173 #define DRI_CONF_FP_OPTIMIZATION(def) \
174 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
175 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
176 DRI_CONF_ENUM(0,"Optimize for Speed") \
177 DRI_CONF_ENUM(1,"Optimize for Quality") \
181 const char __driConfigOptions
[] =
183 DRI_CONF_SECTION_PERFORMANCE
184 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
185 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
186 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
187 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
188 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
189 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
190 DRI_CONF_DISABLE_FALLBACK(false)
191 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
193 DRI_CONF_SECTION_QUALITY
194 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
195 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
196 DRI_CONF_NO_NEG_LOD_BIAS(false)
197 DRI_CONF_FORCE_S3TC_ENABLE(false)
198 DRI_CONF_DISABLE_S3TC(false)
199 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
200 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
201 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
202 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED
)
204 DRI_CONF_SECTION_DEBUG
205 DRI_CONF_NO_RAST(false)
208 static const GLuint __driNConfigOptions
= 18;
211 int RADEON_DEBUG
= 0;
213 static const struct dri_debug_control debug_control
[] = {
214 {"fall", DEBUG_FALLBACKS
},
215 {"tex", DEBUG_TEXTURE
},
216 {"ioctl", DEBUG_IOCTL
},
217 {"prim", DEBUG_PRIMS
},
218 {"vert", DEBUG_VERTS
},
219 {"state", DEBUG_STATE
},
220 {"code", DEBUG_CODEGEN
},
221 {"vfmt", DEBUG_VFMT
},
222 {"vtxf", DEBUG_VFMT
},
223 {"verb", DEBUG_VERBOSE
},
226 {"san", DEBUG_SANITY
},
227 {"sync", DEBUG_SYNC
},
228 {"pix", DEBUG_PIXEL
},
229 {"mem", DEBUG_MEMORY
},
230 {"allmsg", ~DEBUG_SYNC
}, /* avoid the term "sync" because the parser uses strstr */
233 #endif /* RADEON_DEBUG */
235 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
237 extern const struct dri_extension card_extensions
[];
239 static int getSwapInfo( __DRIdrawablePrivate
*dPriv
, __DRIswapInfo
* sInfo
);
242 radeonGetParam(int fd
, int param
, void *value
)
245 drm_radeon_getparam_t gp
;
250 ret
= drmCommandWriteRead( fd
, DRM_RADEON_GETPARAM
, &gp
, sizeof(gp
));
254 static __GLcontextModes
*
255 radeonFillInModes( unsigned pixel_bits
, unsigned depth_bits
,
256 unsigned stencil_bits
, GLboolean have_back_buffer
)
258 __GLcontextModes
* modes
;
259 __GLcontextModes
* m
;
261 unsigned depth_buffer_factor
;
262 unsigned back_buffer_factor
;
266 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
267 * enough to add support. Basically, if a context is created with an
268 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
269 * will never be used.
271 static const GLenum back_buffer_modes
[] = {
272 GLX_NONE
, GLX_SWAP_UNDEFINED_OML
/*, GLX_SWAP_COPY_OML */
275 u_int8_t depth_bits_array
[2];
276 u_int8_t stencil_bits_array
[2];
279 depth_bits_array
[0] = depth_bits
;
280 depth_bits_array
[1] = depth_bits
;
282 /* Just like with the accumulation buffer, always provide some modes
283 * with a stencil buffer. It will be a sw fallback, but some apps won't
286 stencil_bits_array
[0] = 0;
287 stencil_bits_array
[1] = (stencil_bits
== 0) ? 8 : stencil_bits
;
289 depth_buffer_factor
= ((depth_bits
!= 0) || (stencil_bits
!= 0)) ? 2 : 1;
290 back_buffer_factor
= (have_back_buffer
) ? 2 : 1;
292 num_modes
= depth_buffer_factor
* back_buffer_factor
* 4;
294 if ( pixel_bits
== 16 ) {
296 fb_type
= GL_UNSIGNED_SHORT_5_6_5
;
300 fb_type
= GL_UNSIGNED_INT_8_8_8_8_REV
;
303 modes
= (*dri_interface
->createContextModes
)( num_modes
, sizeof( __GLcontextModes
) );
305 if ( ! driFillInModes( & m
, fb_format
, fb_type
,
306 depth_bits_array
, stencil_bits_array
, depth_buffer_factor
,
307 back_buffer_modes
, back_buffer_factor
,
309 fprintf( stderr
, "[%s:%u] Error creating FBConfig!\n",
310 __func__
, __LINE__
);
314 if ( ! driFillInModes( & m
, fb_format
, fb_type
,
315 depth_bits_array
, stencil_bits_array
, depth_buffer_factor
,
316 back_buffer_modes
, back_buffer_factor
,
317 GLX_DIRECT_COLOR
) ) {
318 fprintf( stderr
, "[%s:%u] Error creating FBConfig!\n",
319 __func__
, __LINE__
);
323 /* Mark the visual as slow if there are "fake" stencil bits.
325 for ( m
= modes
; m
!= NULL
; m
= m
->next
) {
326 if ( (m
->stencilBits
!= 0) && (m
->stencilBits
!= stencil_bits
) ) {
327 m
->visualRating
= GLX_SLOW_CONFIG
;
335 /* Create the device specific screen private data struct.
337 static radeonScreenPtr
338 radeonCreateScreen( __DRIscreenPrivate
*sPriv
)
340 radeonScreenPtr screen
;
341 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
)sPriv
->pDevPriv
;
342 unsigned char *RADEONMMIO
;
343 PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension
=
344 (PFNGLXSCRENABLEEXTENSIONPROC
) (*dri_interface
->getProcAddress("glxEnableExtension"));
345 void * const psc
= sPriv
->psc
->screenConfigs
;
347 if (sPriv
->devPrivSize
!= sizeof(RADEONDRIRec
)) {
348 fprintf(stderr
,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
352 /* Allocate the private area */
353 screen
= (radeonScreenPtr
) CALLOC( sizeof(*screen
) );
355 __driUtilMessage("%s: Could not allocate memory for screen structure",
360 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
361 RADEON_DEBUG
= driParseDebugString(getenv("RADEON_DEBUG"), debug_control
);
364 /* parse information in __driConfigOptions */
365 driParseOptionInfo (&screen
->optionCache
,
366 __driConfigOptions
, __driNConfigOptions
);
368 /* This is first since which regions we map depends on whether or
369 * not we are using a PCI card.
371 screen
->card_type
= (dri_priv
->IsPCI
? RADEON_CARD_PCI
: RADEON_CARD_AGP
);
374 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_GART_BUFFER_OFFSET
,
375 &screen
->gart_buffer_offset
);
379 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret
);
383 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_GART_BASE
,
387 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret
);
391 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_IRQ_NR
,
395 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret
);
398 screen
->drmSupportsCubeMapsR200
= (sPriv
->drmMinor
>= 7);
399 screen
->drmSupportsBlendColor
= (sPriv
->drmMinor
>= 11);
400 screen
->drmSupportsTriPerf
= (sPriv
->drmMinor
>= 16);
401 screen
->drmSupportsFragShader
= (sPriv
->drmMinor
>= 18);
402 screen
->drmSupportsPointSprites
= (sPriv
->drmMinor
>= 13);
403 screen
->drmSupportsCubeMapsR100
= (sPriv
->drmMinor
>= 15);
404 screen
->drmSupportsVertexProgram
= (sPriv
->drmMinor
>= 25);
407 screen
->mmio
.handle
= dri_priv
->registerHandle
;
408 screen
->mmio
.size
= dri_priv
->registerSize
;
409 if ( drmMap( sPriv
->fd
,
412 &screen
->mmio
.map
) ) {
414 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__
);
418 RADEONMMIO
= screen
->mmio
.map
;
420 screen
->status
.handle
= dri_priv
->statusHandle
;
421 screen
->status
.size
= dri_priv
->statusSize
;
422 if ( drmMap( sPriv
->fd
,
423 screen
->status
.handle
,
425 &screen
->status
.map
) ) {
426 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
428 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__
);
431 screen
->scratch
= (__volatile__ u_int32_t
*)
432 ((GLubyte
*)screen
->status
.map
+ RADEON_SCRATCH_REG_OFFSET
);
434 screen
->buffers
= drmMapBufs( sPriv
->fd
);
435 if ( !screen
->buffers
) {
436 drmUnmap( screen
->status
.map
, screen
->status
.size
);
437 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
439 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__
);
443 if ( dri_priv
->gartTexHandle
&& dri_priv
->gartTexMapSize
) {
444 screen
->gartTextures
.handle
= dri_priv
->gartTexHandle
;
445 screen
->gartTextures
.size
= dri_priv
->gartTexMapSize
;
446 if ( drmMap( sPriv
->fd
,
447 screen
->gartTextures
.handle
,
448 screen
->gartTextures
.size
,
449 (drmAddressPtr
)&screen
->gartTextures
.map
) ) {
450 drmUnmapBufs( screen
->buffers
);
451 drmUnmap( screen
->status
.map
, screen
->status
.size
);
452 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
454 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__
);
458 screen
->gart_texture_offset
= dri_priv
->gartTexOffset
+ screen
->gart_base
;
461 screen
->chip_flags
= 0;
462 /* XXX: add more chipsets */
463 switch ( dri_priv
->deviceID
) {
464 case PCI_CHIP_RADEON_LY
:
465 case PCI_CHIP_RADEON_LZ
:
466 case PCI_CHIP_RADEON_QY
:
467 case PCI_CHIP_RADEON_QZ
:
468 case PCI_CHIP_RN50_515E
:
469 case PCI_CHIP_RN50_5969
:
470 screen
->chip_family
= CHIP_FAMILY_RV100
;
473 case PCI_CHIP_RS100_4136
:
474 case PCI_CHIP_RS100_4336
:
475 screen
->chip_family
= CHIP_FAMILY_RS100
;
478 case PCI_CHIP_RS200_4137
:
479 case PCI_CHIP_RS200_4337
:
480 case PCI_CHIP_RS250_4237
:
481 case PCI_CHIP_RS250_4437
:
482 screen
->chip_family
= CHIP_FAMILY_RS200
;
485 case PCI_CHIP_RADEON_QD
:
486 case PCI_CHIP_RADEON_QE
:
487 case PCI_CHIP_RADEON_QF
:
488 case PCI_CHIP_RADEON_QG
:
489 /* all original radeons (7200) presumably have a stencil op bug */
490 screen
->chip_family
= CHIP_FAMILY_R100
;
491 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_BROKEN_STENCIL
;
494 case PCI_CHIP_RV200_QW
:
495 case PCI_CHIP_RV200_QX
:
496 case PCI_CHIP_RADEON_LW
:
497 case PCI_CHIP_RADEON_LX
:
498 screen
->chip_family
= CHIP_FAMILY_RV200
;
499 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
502 case PCI_CHIP_R200_BB
:
503 case PCI_CHIP_R200_BC
:
504 case PCI_CHIP_R200_QH
:
505 case PCI_CHIP_R200_QL
:
506 case PCI_CHIP_R200_QM
:
507 screen
->chip_family
= CHIP_FAMILY_R200
;
508 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
511 case PCI_CHIP_RV250_If
:
512 case PCI_CHIP_RV250_Ig
:
513 case PCI_CHIP_RV250_Ld
:
514 case PCI_CHIP_RV250_Lf
:
515 case PCI_CHIP_RV250_Lg
:
516 screen
->chip_family
= CHIP_FAMILY_RV250
;
517 screen
->chip_flags
= R200_CHIPSET_YCBCR_BROKEN
| RADEON_CHIPSET_TCL
;
520 case PCI_CHIP_RV280_5960
:
521 case PCI_CHIP_RV280_5961
:
522 case PCI_CHIP_RV280_5962
:
523 case PCI_CHIP_RV280_5964
:
524 case PCI_CHIP_RV280_5965
:
525 case PCI_CHIP_RV280_5C61
:
526 case PCI_CHIP_RV280_5C63
:
527 screen
->chip_family
= CHIP_FAMILY_RV280
;
528 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
531 case PCI_CHIP_RS300_5834
:
532 case PCI_CHIP_RS300_5835
:
533 case PCI_CHIP_RS350_7834
:
534 case PCI_CHIP_RS350_7835
:
535 screen
->chip_family
= CHIP_FAMILY_RS300
;
538 case PCI_CHIP_R300_AD
:
539 case PCI_CHIP_R300_AE
:
540 case PCI_CHIP_R300_AF
:
541 case PCI_CHIP_R300_AG
:
542 case PCI_CHIP_R300_ND
:
543 case PCI_CHIP_R300_NE
:
544 case PCI_CHIP_R300_NF
:
545 case PCI_CHIP_R300_NG
:
546 screen
->chip_family
= CHIP_FAMILY_R300
;
547 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
550 case PCI_CHIP_RV350_AP
:
551 case PCI_CHIP_RV350_AQ
:
552 case PCI_CHIP_RV350_AR
:
553 case PCI_CHIP_RV350_AS
:
554 case PCI_CHIP_RV350_AT
:
555 case PCI_CHIP_RV350_AV
:
556 case PCI_CHIP_RV350_AU
:
557 case PCI_CHIP_RV350_NP
:
558 case PCI_CHIP_RV350_NQ
:
559 case PCI_CHIP_RV350_NR
:
560 case PCI_CHIP_RV350_NS
:
561 case PCI_CHIP_RV350_NT
:
562 case PCI_CHIP_RV350_NV
:
563 screen
->chip_family
= CHIP_FAMILY_RV350
;
564 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
567 case PCI_CHIP_R350_AH
:
568 case PCI_CHIP_R350_AI
:
569 case PCI_CHIP_R350_AJ
:
570 case PCI_CHIP_R350_AK
:
571 case PCI_CHIP_R350_NH
:
572 case PCI_CHIP_R350_NI
:
573 case PCI_CHIP_R360_NJ
:
574 case PCI_CHIP_R350_NK
:
575 screen
->chip_family
= CHIP_FAMILY_R350
;
576 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
579 case PCI_CHIP_RV370_5460
:
580 case PCI_CHIP_RV370_5462
:
581 case PCI_CHIP_RV370_5464
:
582 case PCI_CHIP_RV370_5B60
:
583 case PCI_CHIP_RV370_5B62
:
584 case PCI_CHIP_RV370_5B63
:
585 case PCI_CHIP_RV370_5B64
:
586 case PCI_CHIP_RV370_5B65
:
587 case PCI_CHIP_RV380_3150
:
588 case PCI_CHIP_RV380_3152
:
589 case PCI_CHIP_RV380_3154
:
590 case PCI_CHIP_RV380_3E50
:
591 case PCI_CHIP_RV380_3E54
:
592 screen
->chip_family
= CHIP_FAMILY_RV380
;
593 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
596 case PCI_CHIP_R420_JN
:
597 case PCI_CHIP_R420_JH
:
598 case PCI_CHIP_R420_JI
:
599 case PCI_CHIP_R420_JJ
:
600 case PCI_CHIP_R420_JK
:
601 case PCI_CHIP_R420_JL
:
602 case PCI_CHIP_R420_JM
:
603 case PCI_CHIP_R420_JO
:
604 case PCI_CHIP_R420_JP
:
605 case PCI_CHIP_R420_JT
:
606 case PCI_CHIP_R481_4B49
:
607 case PCI_CHIP_R481_4B4A
:
608 case PCI_CHIP_R481_4B4B
:
609 case PCI_CHIP_R481_4B4C
:
610 case PCI_CHIP_R423_UH
:
611 case PCI_CHIP_R423_UI
:
612 case PCI_CHIP_R423_UJ
:
613 case PCI_CHIP_R423_UK
:
614 case PCI_CHIP_R430_554C
:
615 case PCI_CHIP_R430_554D
:
616 case PCI_CHIP_R430_554E
:
617 case PCI_CHIP_R430_554F
:
618 case PCI_CHIP_R423_5550
:
619 case PCI_CHIP_R423_UQ
:
620 case PCI_CHIP_R423_UR
:
621 case PCI_CHIP_R423_UT
:
622 case PCI_CHIP_R430_5D48
:
623 case PCI_CHIP_R430_5D49
:
624 case PCI_CHIP_R430_5D4A
:
625 case PCI_CHIP_R480_5D4C
:
626 case PCI_CHIP_R480_5D4D
:
627 case PCI_CHIP_R480_5D4E
:
628 case PCI_CHIP_R480_5D4F
:
629 case PCI_CHIP_R480_5D50
:
630 case PCI_CHIP_R480_5D52
:
631 case PCI_CHIP_R423_5D57
:
632 screen
->chip_family
= CHIP_FAMILY_R420
;
633 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
636 case PCI_CHIP_RV410_564A
:
637 case PCI_CHIP_RV410_564B
:
638 case PCI_CHIP_RV410_564F
:
639 case PCI_CHIP_RV410_5652
:
640 case PCI_CHIP_RV410_5653
:
641 case PCI_CHIP_RV410_5E48
:
642 case PCI_CHIP_RV410_5E4A
:
643 case PCI_CHIP_RV410_5E4B
:
644 case PCI_CHIP_RV410_5E4C
:
645 case PCI_CHIP_RV410_5E4D
:
646 case PCI_CHIP_RV410_5E4F
:
647 screen
->chip_family
= CHIP_FAMILY_RV410
;
648 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
651 case PCI_CHIP_RS480_5954
:
652 case PCI_CHIP_RS480_5955
:
653 case PCI_CHIP_RS482_5974
:
654 case PCI_CHIP_RS482_5975
:
655 case PCI_CHIP_RS400_5A41
:
656 case PCI_CHIP_RS400_5A42
:
657 case PCI_CHIP_RC410_5A61
:
658 case PCI_CHIP_RC410_5A62
:
659 screen
->chip_family
= CHIP_FAMILY_RS400
;
660 fprintf(stderr
, "Warning, xpress200 detected.\n");
664 fprintf(stderr
, "unknown chip id 0x%x, can't guess.\n",
668 if ((screen
->chip_family
== CHIP_FAMILY_R350
|| screen
->chip_family
== CHIP_FAMILY_R300
) &&
669 sPriv
->ddxMinor
< 2) {
670 fprintf(stderr
, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
674 if (screen
->chip_family
<= CHIP_FAMILY_RS200
)
675 screen
->chip_flags
|= RADEON_CLASS_R100
;
676 else if (screen
->chip_family
<= CHIP_FAMILY_RV280
)
677 screen
->chip_flags
|= RADEON_CLASS_R200
;
679 screen
->chip_flags
|= RADEON_CLASS_R300
;
681 screen
->cpp
= dri_priv
->bpp
/ 8;
682 screen
->AGPMode
= dri_priv
->AGPMode
;
684 screen
->fbLocation
= ( INREG( RADEON_MC_FB_LOCATION
) & 0xffff ) << 16;
686 if ( sPriv
->drmMinor
>= 10 ) {
687 drm_radeon_setparam_t sp
;
689 sp
.param
= RADEON_SETPARAM_FB_LOCATION
;
690 sp
.value
= screen
->fbLocation
;
692 drmCommandWrite( sPriv
->fd
, DRM_RADEON_SETPARAM
,
696 screen
->frontOffset
= dri_priv
->frontOffset
;
697 screen
->frontPitch
= dri_priv
->frontPitch
;
698 screen
->backOffset
= dri_priv
->backOffset
;
699 screen
->backPitch
= dri_priv
->backPitch
;
700 screen
->depthOffset
= dri_priv
->depthOffset
;
701 screen
->depthPitch
= dri_priv
->depthPitch
;
703 /* Check if ddx has set up a surface reg to cover depth buffer */
704 screen
->depthHasSurface
= ((sPriv
->ddxMajor
> 4) &&
705 (screen
->chip_flags
& RADEON_CHIPSET_TCL
));
707 if ( dri_priv
->textureSize
== 0 ) {
708 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = screen
->gart_texture_offset
;
709 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
710 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
711 dri_priv
->log2GARTTexGran
;
713 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureOffset
714 + screen
->fbLocation
;
715 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureSize
;
716 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
717 dri_priv
->log2TexGran
;
720 if ( !screen
->gartTextures
.map
|| dri_priv
->textureSize
== 0
721 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
722 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
- 1;
723 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = 0;
724 screen
->texSize
[RADEON_GART_TEX_HEAP
] = 0;
725 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] = 0;
727 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
;
728 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = screen
->gart_texture_offset
;
729 screen
->texSize
[RADEON_GART_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
730 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] =
731 dri_priv
->log2GARTTexGran
;
734 if ( glx_enable_extension
!= NULL
) {
735 if ( screen
->irq
!= 0 ) {
736 (*glx_enable_extension
)( psc
, "GLX_SGI_swap_control" );
737 (*glx_enable_extension
)( psc
, "GLX_SGI_video_sync" );
738 (*glx_enable_extension
)( psc
, "GLX_MESA_swap_control" );
741 (*glx_enable_extension
)( psc
, "GLX_MESA_swap_frame_usage" );
742 if (IS_R200_CLASS(screen
))
743 (*glx_enable_extension
)( psc
, "GLX_MESA_allocate_memory" );
745 (*glx_enable_extension
)( psc
, "GLX_MESA_copy_sub_buffer" );
746 (*glx_enable_extension
)( psc
, "GLX_SGI_make_current_read" );
749 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
750 if (IS_R200_CLASS(screen
)) {
751 sPriv
->psc
->allocateMemory
= (void *) r200AllocateMemoryMESA
;
752 sPriv
->psc
->freeMemory
= (void *) r200FreeMemoryMESA
;
753 sPriv
->psc
->memoryOffset
= (void *) r200GetMemoryOffsetMESA
;
757 screen
->driScreen
= sPriv
;
758 screen
->sarea_priv_offset
= dri_priv
->sarea_priv_offset
;
762 /* Destroy the device specific screen private data struct.
765 radeonDestroyScreen( __DRIscreenPrivate
*sPriv
)
767 radeonScreenPtr screen
= (radeonScreenPtr
)sPriv
->private;
772 if ( screen
->gartTextures
.map
) {
773 drmUnmap( screen
->gartTextures
.map
, screen
->gartTextures
.size
);
775 drmUnmapBufs( screen
->buffers
);
776 drmUnmap( screen
->status
.map
, screen
->status
.size
);
777 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
779 /* free all option information */
780 driDestroyOptionInfo (&screen
->optionCache
);
783 sPriv
->private = NULL
;
787 /* Initialize the driver specific screen private data.
790 radeonInitDriver( __DRIscreenPrivate
*sPriv
)
792 sPriv
->private = (void *) radeonCreateScreen( sPriv
);
793 if ( !sPriv
->private ) {
794 radeonDestroyScreen( sPriv
);
803 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
805 * \todo This function (and its interface) will need to be updated to support
809 radeonCreateBuffer( __DRIscreenPrivate
*driScrnPriv
,
810 __DRIdrawablePrivate
*driDrawPriv
,
811 const __GLcontextModes
*mesaVis
,
814 radeonScreenPtr screen
= (radeonScreenPtr
) driScrnPriv
->private;
817 return GL_FALSE
; /* not implemented */
820 const GLboolean swDepth
= GL_FALSE
;
821 const GLboolean swAlpha
= GL_FALSE
;
822 const GLboolean swAccum
= mesaVis
->accumRedBits
> 0;
823 const GLboolean swStencil
= mesaVis
->stencilBits
> 0 &&
824 mesaVis
->depthBits
!= 24;
825 struct gl_framebuffer
*fb
= _mesa_create_framebuffer(mesaVis
);
827 /* front color renderbuffer */
829 driRenderbuffer
*frontRb
830 = driNewRenderbuffer(GL_RGBA
,
831 driScrnPriv
->pFB
+ screen
->frontOffset
,
833 screen
->frontOffset
, screen
->frontPitch
,
835 radeonSetSpanFunctions(frontRb
, mesaVis
);
836 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &frontRb
->Base
);
839 /* back color renderbuffer */
840 if (mesaVis
->doubleBufferMode
) {
841 driRenderbuffer
*backRb
842 = driNewRenderbuffer(GL_RGBA
,
843 driScrnPriv
->pFB
+ screen
->backOffset
,
845 screen
->backOffset
, screen
->backPitch
,
847 radeonSetSpanFunctions(backRb
, mesaVis
);
848 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &backRb
->Base
);
851 /* depth renderbuffer */
852 if (mesaVis
->depthBits
== 16) {
853 driRenderbuffer
*depthRb
854 = driNewRenderbuffer(GL_DEPTH_COMPONENT16
,
855 driScrnPriv
->pFB
+ screen
->depthOffset
,
857 screen
->depthOffset
, screen
->depthPitch
,
859 radeonSetSpanFunctions(depthRb
, mesaVis
);
860 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &depthRb
->Base
);
861 depthRb
->depthHasSurface
= screen
->depthHasSurface
;
863 else if (mesaVis
->depthBits
== 24) {
864 driRenderbuffer
*depthRb
865 = driNewRenderbuffer(GL_DEPTH_COMPONENT24
,
866 driScrnPriv
->pFB
+ screen
->depthOffset
,
868 screen
->depthOffset
, screen
->depthPitch
,
870 radeonSetSpanFunctions(depthRb
, mesaVis
);
871 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &depthRb
->Base
);
872 depthRb
->depthHasSurface
= screen
->depthHasSurface
;
875 /* stencil renderbuffer */
876 if (mesaVis
->stencilBits
> 0 && !swStencil
) {
877 driRenderbuffer
*stencilRb
878 = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT
,
879 driScrnPriv
->pFB
+ screen
->depthOffset
,
881 screen
->depthOffset
, screen
->depthPitch
,
883 radeonSetSpanFunctions(stencilRb
, mesaVis
);
884 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &stencilRb
->Base
);
885 stencilRb
->depthHasSurface
= screen
->depthHasSurface
;
888 _mesa_add_soft_renderbuffers(fb
,
889 GL_FALSE
, /* color */
895 driDrawPriv
->driverPrivate
= (void *) fb
;
897 return (driDrawPriv
->driverPrivate
!= NULL
);
903 radeonDestroyBuffer(__DRIdrawablePrivate
*driDrawPriv
)
905 _mesa_unreference_framebuffer((GLframebuffer
**)(&(driDrawPriv
->driverPrivate
)));
908 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
910 * Choose the appropriate CreateContext function based on the chipset.
911 * Eventually, all drivers will go through this process.
913 static GLboolean
radeonCreateContext(const __GLcontextModes
* glVisual
,
914 __DRIcontextPrivate
* driContextPriv
,
915 void *sharedContextPriv
)
917 __DRIscreenPrivate
*sPriv
= driContextPriv
->driScreenPriv
;
918 radeonScreenPtr screen
= (radeonScreenPtr
) (sPriv
->private);
920 if (IS_R300_CLASS(screen
))
921 return r300CreateContext(glVisual
, driContextPriv
, sharedContextPriv
);
926 * Choose the appropriate DestroyContext function based on the chipset.
928 static void radeonDestroyContext(__DRIcontextPrivate
* driContextPriv
)
930 radeonContextPtr radeon
= (radeonContextPtr
) driContextPriv
->driverPrivate
;
932 if (IS_R300_CLASS(radeon
->radeonScreen
))
933 return r300DestroyContext(driContextPriv
);
939 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
940 static struct __DriverAPIRec radeonAPI
= {
941 .InitDriver
= radeonInitDriver
,
942 .DestroyScreen
= radeonDestroyScreen
,
943 .CreateContext
= radeonCreateContext
,
944 .DestroyContext
= radeonDestroyContext
,
945 .CreateBuffer
= radeonCreateBuffer
,
946 .DestroyBuffer
= radeonDestroyBuffer
,
947 .SwapBuffers
= radeonSwapBuffers
,
948 .MakeCurrent
= radeonMakeCurrent
,
949 .UnbindContext
= radeonUnbindContext
,
950 .GetSwapInfo
= getSwapInfo
,
951 .GetMSC
= driGetMSC32
,
952 .WaitForMSC
= driWaitForMSC32
,
954 .SwapBuffersMSC
= NULL
,
955 .CopySubBuffer
= radeonCopySubBuffer
,
956 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
957 .setTexOffset
= r300SetTexOffset
,
961 static const struct __DriverAPIRec r200API
= {
962 .InitDriver
= radeonInitDriver
,
963 .DestroyScreen
= radeonDestroyScreen
,
964 .CreateContext
= r200CreateContext
,
965 .DestroyContext
= r200DestroyContext
,
966 .CreateBuffer
= radeonCreateBuffer
,
967 .DestroyBuffer
= radeonDestroyBuffer
,
968 .SwapBuffers
= r200SwapBuffers
,
969 .MakeCurrent
= r200MakeCurrent
,
970 .UnbindContext
= r200UnbindContext
,
971 .GetSwapInfo
= getSwapInfo
,
972 .GetMSC
= driGetMSC32
,
973 .WaitForMSC
= driWaitForMSC32
,
975 .SwapBuffersMSC
= NULL
,
976 .CopySubBuffer
= r200CopySubBuffer
981 * This is the bootstrap function for the driver. libGL supplies all of the
982 * requisite information about the system, and the driver initializes itself.
983 * This routine also fills in the linked list pointed to by \c driver_modes
984 * with the \c __GLcontextModes that the driver can support for windows or
987 * \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on
991 __driCreateNewScreen_20050727( __DRInativeDisplay
*dpy
,
992 int scrn
, __DRIscreen
*psc
,
993 const __GLcontextModes
* modes
,
994 const __DRIversion
* ddx_version
,
995 const __DRIversion
* dri_version
,
996 const __DRIversion
* drm_version
,
997 const __DRIframebuffer
* frame_buffer
,
998 drmAddress pSAREA
, int fd
,
999 int internal_api_version
,
1000 const __DRIinterfaceMethods
* interface
,
1001 __GLcontextModes
** driver_modes
)
1003 __DRIscreenPrivate
*psp
;
1005 static const char *driver_name
= "Radeon";
1006 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1007 static const __DRIversion dri_expected
= { 4, 0, 0 };
1008 static const __DRIversion drm_expected
= { 1, 6, 0 };
1009 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1010 static const char *driver_name
= "R200";
1011 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1012 static const __DRIversion dri_expected
= { 4, 0, 0 };
1013 static const __DRIversion drm_expected
= { 1, 6, 0 };
1014 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1015 static const char *driver_name
= "R300";
1016 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1017 static const __DRIversion dri_expected
= { 4, 0, 0 };
1018 static const __DRIversion drm_expected
= { 1, 24, 0 };
1021 dri_interface
= interface
;
1023 if ( ! driCheckDriDdxDrmVersions3( driver_name
,
1024 dri_version
, & dri_expected
,
1025 ddx_version
, & ddx_expected
,
1026 drm_version
, & drm_expected
) ) {
1029 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1030 psp
= __driUtilCreateNewScreen(dpy
, scrn
, psc
, NULL
,
1031 ddx_version
, dri_version
, drm_version
,
1032 frame_buffer
, pSAREA
, fd
,
1033 internal_api_version
, &radeonAPI
);
1034 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1035 psp
= __driUtilCreateNewScreen(dpy
, scrn
, psc
, NULL
,
1036 ddx_version
, dri_version
, drm_version
,
1037 frame_buffer
, pSAREA
, fd
,
1038 internal_api_version
, &r200API
);
1041 if ( psp
!= NULL
) {
1042 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
) psp
->pDevPriv
;
1044 *driver_modes
= radeonFillInModes( dri_priv
->bpp
,
1045 (dri_priv
->bpp
== 16) ? 16 : 24,
1046 (dri_priv
->bpp
== 16) ? 0 : 8,
1047 (dri_priv
->backOffset
!= dri_priv
->depthOffset
) );
1050 /* Calling driInitExtensions here, with a NULL context pointer,
1051 * does not actually enable the extensions. It just makes sure
1052 * that all the dispatch offsets for all the extensions that
1053 * *might* be enables are known. This is needed because the
1054 * dispatch offsets need to be known when _mesa_context_create
1055 * is called, but we can't enable the extensions until we have a
1058 * Hello chicken. Hello egg. How are you two today?
1060 driInitExtensions( NULL
, card_extensions
, GL_FALSE
);
1061 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1062 driInitExtensions( NULL
, blend_extensions
, GL_FALSE
);
1063 driInitSingleExtension( NULL
, ARB_vp_extension
);
1064 driInitSingleExtension( NULL
, NV_vp_extension
);
1065 driInitSingleExtension( NULL
, ATI_fs_extension
);
1066 driInitExtensions( NULL
, point_extensions
, GL_FALSE
);
1070 return (void *) psp
;
1075 * Get information about previous buffer swaps.
1078 getSwapInfo( __DRIdrawablePrivate
*dPriv
, __DRIswapInfo
* sInfo
)
1080 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1081 radeonContextPtr rmesa
;
1082 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1083 r200ContextPtr rmesa
;
1086 if ( (dPriv
== NULL
) || (dPriv
->driContextPriv
== NULL
)
1087 || (dPriv
->driContextPriv
->driverPrivate
== NULL
)
1088 || (sInfo
== NULL
) ) {
1092 rmesa
= dPriv
->driContextPriv
->driverPrivate
;
1093 sInfo
->swap_count
= rmesa
->swap_count
;
1094 sInfo
->swap_ust
= rmesa
->swap_ust
;
1095 sInfo
->swap_missed_count
= rmesa
->swap_missed_count
;
1097 sInfo
->swap_missed_usage
= (sInfo
->swap_missed_count
!= 0)
1098 ? driCalculateSwapUsage( dPriv
, 0, rmesa
->swap_missed_ust
)