1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
32 * \file radeon_screen.c
33 * Screen initialization functions for the Radeon driver.
35 * \author Kevin E. Martin <martin@valinux.com>
36 * \author Gareth Hughes <gareth@valinux.com>
42 #include "framebuffer.h"
43 #include "renderbuffer.h"
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
50 #include "radeon_context.h"
51 #include "radeon_span.h"
52 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
53 #include "r200_context.h"
54 #include "r200_ioctl.h"
55 #include "r200_span.h"
56 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
57 #include "r300_context.h"
58 #include "r300_fragprog.h"
59 #include "radeon_span.h"
65 #include "drirenderbuffer.h"
67 #include "GL/internal/dri_interface.h"
69 /* Radeon configuration
73 #if !RADEON_COMMON /* R100 */
74 PUBLIC
const char __driConfigOptions
[] =
76 DRI_CONF_SECTION_PERFORMANCE
77 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
78 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
79 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
80 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
81 DRI_CONF_HYPERZ(false)
83 DRI_CONF_SECTION_QUALITY
84 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
85 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
86 DRI_CONF_NO_NEG_LOD_BIAS(false)
87 DRI_CONF_FORCE_S3TC_ENABLE(false)
88 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
89 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
90 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
91 DRI_CONF_ALLOW_LARGE_TEXTURES(1)
93 DRI_CONF_SECTION_DEBUG
94 DRI_CONF_NO_RAST(false)
97 static const GLuint __driNConfigOptions
= 14;
99 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
101 PUBLIC
const char __driConfigOptions
[] =
103 DRI_CONF_SECTION_PERFORMANCE
104 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
105 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
106 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
107 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
108 DRI_CONF_HYPERZ(false)
110 DRI_CONF_SECTION_QUALITY
111 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
112 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
113 DRI_CONF_NO_NEG_LOD_BIAS(false)
114 DRI_CONF_FORCE_S3TC_ENABLE(false)
115 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
116 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
117 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
118 DRI_CONF_ALLOW_LARGE_TEXTURES(1)
119 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
121 DRI_CONF_SECTION_DEBUG
122 DRI_CONF_NO_RAST(false)
124 DRI_CONF_SECTION_SOFTWARE
125 DRI_CONF_NV_VERTEX_PROGRAM(false)
128 static const GLuint __driNConfigOptions
= 16;
130 extern const struct dri_extension blend_extensions
[];
131 extern const struct dri_extension ARB_vp_extension
[];
132 extern const struct dri_extension NV_vp_extension
[];
133 extern const struct dri_extension ATI_fs_extension
[];
134 extern const struct dri_extension point_extensions
[];
136 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
138 /* TODO: integrate these into xmlpool.h! */
139 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
140 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
141 DRI_CONF_DESC(en,"Number of texture image units") \
142 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
145 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
146 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
147 DRI_CONF_DESC(en,"Number of texture coordinate units") \
148 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
151 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
152 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
153 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
154 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
157 #define DRI_CONF_DISABLE_S3TC(def) \
158 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
159 DRI_CONF_DESC(en,"Disable S3TC compression") \
162 #define DRI_CONF_DISABLE_FALLBACK(def) \
163 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
164 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
167 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
168 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
169 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
172 #define DRI_CONF_FP_OPTIMIZATION(def) \
173 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
174 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
175 DRI_CONF_ENUM(0,"Optimize for Speed") \
176 DRI_CONF_ENUM(1,"Optimize for Quality") \
180 const char __driConfigOptions
[] =
182 DRI_CONF_SECTION_PERFORMANCE
183 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
184 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
185 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
186 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
187 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
188 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
189 DRI_CONF_DISABLE_FALLBACK(false)
190 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
192 DRI_CONF_SECTION_QUALITY
193 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
194 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
195 DRI_CONF_NO_NEG_LOD_BIAS(false)
196 DRI_CONF_FORCE_S3TC_ENABLE(false)
197 DRI_CONF_DISABLE_S3TC(false)
198 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
199 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
200 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
201 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED
)
203 DRI_CONF_SECTION_DEBUG
204 DRI_CONF_NO_RAST(false)
207 static const GLuint __driNConfigOptions
= 18;
210 int RADEON_DEBUG
= 0;
212 static const struct dri_debug_control debug_control
[] = {
213 {"fall", DEBUG_FALLBACKS
},
214 {"tex", DEBUG_TEXTURE
},
215 {"ioctl", DEBUG_IOCTL
},
216 {"prim", DEBUG_PRIMS
},
217 {"vert", DEBUG_VERTS
},
218 {"state", DEBUG_STATE
},
219 {"code", DEBUG_CODEGEN
},
220 {"vfmt", DEBUG_VFMT
},
221 {"vtxf", DEBUG_VFMT
},
222 {"verb", DEBUG_VERBOSE
},
225 {"san", DEBUG_SANITY
},
226 {"sync", DEBUG_SYNC
},
227 {"pix", DEBUG_PIXEL
},
228 {"mem", DEBUG_MEMORY
},
229 {"allmsg", ~DEBUG_SYNC
}, /* avoid the term "sync" because the parser uses strstr */
232 #endif /* RADEON_DEBUG */
234 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
236 extern const struct dri_extension card_extensions
[];
238 static int getSwapInfo( __DRIdrawablePrivate
*dPriv
, __DRIswapInfo
* sInfo
);
241 radeonGetParam(int fd
, int param
, void *value
)
244 drm_radeon_getparam_t gp
;
249 ret
= drmCommandWriteRead( fd
, DRM_RADEON_GETPARAM
, &gp
, sizeof(gp
));
253 static __GLcontextModes
*
254 radeonFillInModes( unsigned pixel_bits
, unsigned depth_bits
,
255 unsigned stencil_bits
, GLboolean have_back_buffer
)
257 __GLcontextModes
* modes
;
258 __GLcontextModes
* m
;
260 unsigned depth_buffer_factor
;
261 unsigned back_buffer_factor
;
265 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
266 * enough to add support. Basically, if a context is created with an
267 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
268 * will never be used.
270 static const GLenum back_buffer_modes
[] = {
271 GLX_NONE
, GLX_SWAP_UNDEFINED_OML
/*, GLX_SWAP_COPY_OML */
274 u_int8_t depth_bits_array
[2];
275 u_int8_t stencil_bits_array
[2];
278 depth_bits_array
[0] = depth_bits
;
279 depth_bits_array
[1] = depth_bits
;
281 /* Just like with the accumulation buffer, always provide some modes
282 * with a stencil buffer. It will be a sw fallback, but some apps won't
285 stencil_bits_array
[0] = 0;
286 stencil_bits_array
[1] = (stencil_bits
== 0) ? 8 : stencil_bits
;
288 depth_buffer_factor
= ((depth_bits
!= 0) || (stencil_bits
!= 0)) ? 2 : 1;
289 back_buffer_factor
= (have_back_buffer
) ? 2 : 1;
291 num_modes
= depth_buffer_factor
* back_buffer_factor
* 4;
293 if ( pixel_bits
== 16 ) {
295 fb_type
= GL_UNSIGNED_SHORT_5_6_5
;
299 fb_type
= GL_UNSIGNED_INT_8_8_8_8_REV
;
302 modes
= (*dri_interface
->createContextModes
)( num_modes
, sizeof( __GLcontextModes
) );
304 if ( ! driFillInModes( & m
, fb_format
, fb_type
,
305 depth_bits_array
, stencil_bits_array
, depth_buffer_factor
,
306 back_buffer_modes
, back_buffer_factor
,
308 fprintf( stderr
, "[%s:%u] Error creating FBConfig!\n",
309 __func__
, __LINE__
);
313 if ( ! driFillInModes( & m
, fb_format
, fb_type
,
314 depth_bits_array
, stencil_bits_array
, depth_buffer_factor
,
315 back_buffer_modes
, back_buffer_factor
,
316 GLX_DIRECT_COLOR
) ) {
317 fprintf( stderr
, "[%s:%u] Error creating FBConfig!\n",
318 __func__
, __LINE__
);
322 /* Mark the visual as slow if there are "fake" stencil bits.
324 for ( m
= modes
; m
!= NULL
; m
= m
->next
) {
325 if ( (m
->stencilBits
!= 0) && (m
->stencilBits
!= stencil_bits
) ) {
326 m
->visualRating
= GLX_SLOW_CONFIG
;
334 /* Create the device specific screen private data struct.
336 static radeonScreenPtr
337 radeonCreateScreen( __DRIscreenPrivate
*sPriv
)
339 radeonScreenPtr screen
;
340 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
)sPriv
->pDevPriv
;
341 unsigned char *RADEONMMIO
;
342 PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension
=
343 (PFNGLXSCRENABLEEXTENSIONPROC
) (*dri_interface
->getProcAddress("glxEnableExtension"));
344 void * const psc
= sPriv
->psc
->screenConfigs
;
346 if (sPriv
->devPrivSize
!= sizeof(RADEONDRIRec
)) {
347 fprintf(stderr
,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
351 /* Allocate the private area */
352 screen
= (radeonScreenPtr
) CALLOC( sizeof(*screen
) );
354 __driUtilMessage("%s: Could not allocate memory for screen structure",
359 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
360 RADEON_DEBUG
= driParseDebugString(getenv("RADEON_DEBUG"), debug_control
);
363 /* parse information in __driConfigOptions */
364 driParseOptionInfo (&screen
->optionCache
,
365 __driConfigOptions
, __driNConfigOptions
);
367 /* This is first since which regions we map depends on whether or
368 * not we are using a PCI card.
370 screen
->card_type
= (dri_priv
->IsPCI
? RADEON_CARD_PCI
: RADEON_CARD_AGP
);
373 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_GART_BUFFER_OFFSET
,
374 &screen
->gart_buffer_offset
);
378 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret
);
382 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_GART_BASE
,
386 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret
);
390 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_IRQ_NR
,
394 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret
);
397 screen
->drmSupportsCubeMapsR200
= (sPriv
->drmMinor
>= 7);
398 screen
->drmSupportsBlendColor
= (sPriv
->drmMinor
>= 11);
399 screen
->drmSupportsTriPerf
= (sPriv
->drmMinor
>= 16);
400 screen
->drmSupportsFragShader
= (sPriv
->drmMinor
>= 18);
401 screen
->drmSupportsPointSprites
= (sPriv
->drmMinor
>= 13);
402 screen
->drmSupportsCubeMapsR100
= (sPriv
->drmMinor
>= 15);
403 screen
->drmSupportsVertexProgram
= (sPriv
->drmMinor
>= 25);
406 screen
->mmio
.handle
= dri_priv
->registerHandle
;
407 screen
->mmio
.size
= dri_priv
->registerSize
;
408 if ( drmMap( sPriv
->fd
,
411 &screen
->mmio
.map
) ) {
413 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__
);
417 RADEONMMIO
= screen
->mmio
.map
;
419 screen
->status
.handle
= dri_priv
->statusHandle
;
420 screen
->status
.size
= dri_priv
->statusSize
;
421 if ( drmMap( sPriv
->fd
,
422 screen
->status
.handle
,
424 &screen
->status
.map
) ) {
425 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
427 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__
);
430 screen
->scratch
= (__volatile__ u_int32_t
*)
431 ((GLubyte
*)screen
->status
.map
+ RADEON_SCRATCH_REG_OFFSET
);
433 screen
->buffers
= drmMapBufs( sPriv
->fd
);
434 if ( !screen
->buffers
) {
435 drmUnmap( screen
->status
.map
, screen
->status
.size
);
436 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
438 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__
);
442 if ( dri_priv
->gartTexHandle
&& dri_priv
->gartTexMapSize
) {
443 screen
->gartTextures
.handle
= dri_priv
->gartTexHandle
;
444 screen
->gartTextures
.size
= dri_priv
->gartTexMapSize
;
445 if ( drmMap( sPriv
->fd
,
446 screen
->gartTextures
.handle
,
447 screen
->gartTextures
.size
,
448 (drmAddressPtr
)&screen
->gartTextures
.map
) ) {
449 drmUnmapBufs( screen
->buffers
);
450 drmUnmap( screen
->status
.map
, screen
->status
.size
);
451 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
453 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__
);
457 screen
->gart_texture_offset
= dri_priv
->gartTexOffset
+ screen
->gart_base
;
460 screen
->chip_flags
= 0;
461 /* XXX: add more chipsets */
462 switch ( dri_priv
->deviceID
) {
463 case PCI_CHIP_RADEON_LY
:
464 case PCI_CHIP_RADEON_LZ
:
465 case PCI_CHIP_RADEON_QY
:
466 case PCI_CHIP_RADEON_QZ
:
467 case PCI_CHIP_RN50_515E
:
468 case PCI_CHIP_RN50_5969
:
469 screen
->chip_family
= CHIP_FAMILY_RV100
;
472 case PCI_CHIP_RS100_4136
:
473 case PCI_CHIP_RS100_4336
:
474 screen
->chip_family
= CHIP_FAMILY_RS100
;
477 case PCI_CHIP_RS200_4137
:
478 case PCI_CHIP_RS200_4337
:
479 case PCI_CHIP_RS250_4237
:
480 case PCI_CHIP_RS250_4437
:
481 screen
->chip_family
= CHIP_FAMILY_RS200
;
484 case PCI_CHIP_RADEON_QD
:
485 case PCI_CHIP_RADEON_QE
:
486 case PCI_CHIP_RADEON_QF
:
487 case PCI_CHIP_RADEON_QG
:
488 /* all original radeons (7200) presumably have a stencil op bug */
489 screen
->chip_family
= CHIP_FAMILY_R100
;
490 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_BROKEN_STENCIL
;
493 case PCI_CHIP_RV200_QW
:
494 case PCI_CHIP_RV200_QX
:
495 case PCI_CHIP_RADEON_LW
:
496 case PCI_CHIP_RADEON_LX
:
497 screen
->chip_family
= CHIP_FAMILY_RV200
;
498 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
501 case PCI_CHIP_R200_BB
:
502 case PCI_CHIP_R200_BC
:
503 case PCI_CHIP_R200_QH
:
504 case PCI_CHIP_R200_QL
:
505 case PCI_CHIP_R200_QM
:
506 screen
->chip_family
= CHIP_FAMILY_R200
;
507 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
510 case PCI_CHIP_RV250_If
:
511 case PCI_CHIP_RV250_Ig
:
512 case PCI_CHIP_RV250_Ld
:
513 case PCI_CHIP_RV250_Lf
:
514 case PCI_CHIP_RV250_Lg
:
515 screen
->chip_family
= CHIP_FAMILY_RV250
;
516 screen
->chip_flags
= R200_CHIPSET_YCBCR_BROKEN
| RADEON_CHIPSET_TCL
;
519 case PCI_CHIP_RV280_5960
:
520 case PCI_CHIP_RV280_5961
:
521 case PCI_CHIP_RV280_5962
:
522 case PCI_CHIP_RV280_5964
:
523 case PCI_CHIP_RV280_5965
:
524 case PCI_CHIP_RV280_5C61
:
525 case PCI_CHIP_RV280_5C63
:
526 screen
->chip_family
= CHIP_FAMILY_RV280
;
527 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
530 case PCI_CHIP_RS300_5834
:
531 case PCI_CHIP_RS300_5835
:
532 case PCI_CHIP_RS350_7834
:
533 case PCI_CHIP_RS350_7835
:
534 screen
->chip_family
= CHIP_FAMILY_RS300
;
537 case PCI_CHIP_R300_AD
:
538 case PCI_CHIP_R300_AE
:
539 case PCI_CHIP_R300_AF
:
540 case PCI_CHIP_R300_AG
:
541 case PCI_CHIP_R300_ND
:
542 case PCI_CHIP_R300_NE
:
543 case PCI_CHIP_R300_NF
:
544 case PCI_CHIP_R300_NG
:
545 screen
->chip_family
= CHIP_FAMILY_R300
;
546 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
549 case PCI_CHIP_RV350_AP
:
550 case PCI_CHIP_RV350_AQ
:
551 case PCI_CHIP_RV350_AR
:
552 case PCI_CHIP_RV350_AS
:
553 case PCI_CHIP_RV350_AT
:
554 case PCI_CHIP_RV350_AV
:
555 case PCI_CHIP_RV350_AU
:
556 case PCI_CHIP_RV350_NP
:
557 case PCI_CHIP_RV350_NQ
:
558 case PCI_CHIP_RV350_NR
:
559 case PCI_CHIP_RV350_NS
:
560 case PCI_CHIP_RV350_NT
:
561 case PCI_CHIP_RV350_NV
:
562 screen
->chip_family
= CHIP_FAMILY_RV350
;
563 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
566 case PCI_CHIP_R350_AH
:
567 case PCI_CHIP_R350_AI
:
568 case PCI_CHIP_R350_AJ
:
569 case PCI_CHIP_R350_AK
:
570 case PCI_CHIP_R350_NH
:
571 case PCI_CHIP_R350_NI
:
572 case PCI_CHIP_R360_NJ
:
573 case PCI_CHIP_R350_NK
:
574 screen
->chip_family
= CHIP_FAMILY_R350
;
575 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
578 case PCI_CHIP_RV370_5460
:
579 case PCI_CHIP_RV370_5462
:
580 case PCI_CHIP_RV370_5464
:
581 case PCI_CHIP_RV370_5B60
:
582 case PCI_CHIP_RV370_5B62
:
583 case PCI_CHIP_RV370_5B63
:
584 case PCI_CHIP_RV370_5B64
:
585 case PCI_CHIP_RV370_5B65
:
586 case PCI_CHIP_RV380_3150
:
587 case PCI_CHIP_RV380_3152
:
588 case PCI_CHIP_RV380_3154
:
589 case PCI_CHIP_RV380_3E50
:
590 case PCI_CHIP_RV380_3E54
:
591 screen
->chip_family
= CHIP_FAMILY_RV380
;
592 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
595 case PCI_CHIP_R420_JN
:
596 case PCI_CHIP_R420_JH
:
597 case PCI_CHIP_R420_JI
:
598 case PCI_CHIP_R420_JJ
:
599 case PCI_CHIP_R420_JK
:
600 case PCI_CHIP_R420_JL
:
601 case PCI_CHIP_R420_JM
:
602 case PCI_CHIP_R420_JO
:
603 case PCI_CHIP_R420_JP
:
604 case PCI_CHIP_R420_JT
:
605 case PCI_CHIP_R481_4B49
:
606 case PCI_CHIP_R481_4B4A
:
607 case PCI_CHIP_R481_4B4B
:
608 case PCI_CHIP_R481_4B4C
:
609 case PCI_CHIP_R423_UH
:
610 case PCI_CHIP_R423_UI
:
611 case PCI_CHIP_R423_UJ
:
612 case PCI_CHIP_R423_UK
:
613 case PCI_CHIP_R430_554C
:
614 case PCI_CHIP_R430_554D
:
615 case PCI_CHIP_R430_554E
:
616 case PCI_CHIP_R430_554F
:
617 case PCI_CHIP_R423_5550
:
618 case PCI_CHIP_R423_UQ
:
619 case PCI_CHIP_R423_UR
:
620 case PCI_CHIP_R423_UT
:
621 case PCI_CHIP_R430_5D48
:
622 case PCI_CHIP_R430_5D49
:
623 case PCI_CHIP_R430_5D4A
:
624 case PCI_CHIP_R480_5D4C
:
625 case PCI_CHIP_R480_5D4D
:
626 case PCI_CHIP_R480_5D4E
:
627 case PCI_CHIP_R480_5D4F
:
628 case PCI_CHIP_R480_5D50
:
629 case PCI_CHIP_R480_5D52
:
630 case PCI_CHIP_R423_5D57
:
631 screen
->chip_family
= CHIP_FAMILY_R420
;
632 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
635 case PCI_CHIP_RV410_564A
:
636 case PCI_CHIP_RV410_564B
:
637 case PCI_CHIP_RV410_564F
:
638 case PCI_CHIP_RV410_5652
:
639 case PCI_CHIP_RV410_5653
:
640 case PCI_CHIP_RV410_5E48
:
641 case PCI_CHIP_RV410_5E4A
:
642 case PCI_CHIP_RV410_5E4B
:
643 case PCI_CHIP_RV410_5E4C
:
644 case PCI_CHIP_RV410_5E4D
:
645 case PCI_CHIP_RV410_5E4F
:
646 screen
->chip_family
= CHIP_FAMILY_RV410
;
647 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
650 case PCI_CHIP_RS480_5954
:
651 case PCI_CHIP_RS480_5955
:
652 case PCI_CHIP_RS482_5974
:
653 case PCI_CHIP_RS482_5975
:
654 case PCI_CHIP_RS400_5A41
:
655 case PCI_CHIP_RS400_5A42
:
656 case PCI_CHIP_RC410_5A61
:
657 case PCI_CHIP_RC410_5A62
:
658 screen
->chip_family
= CHIP_FAMILY_RS400
;
659 fprintf(stderr
, "Warning, xpress200 detected.\n");
663 fprintf(stderr
, "unknown chip id 0x%x, can't guess.\n",
667 if ((screen
->chip_family
== CHIP_FAMILY_R350
|| screen
->chip_family
== CHIP_FAMILY_R300
) &&
668 sPriv
->ddxMinor
< 2) {
669 fprintf(stderr
, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
673 if (screen
->chip_family
<= CHIP_FAMILY_RS200
)
674 screen
->chip_flags
|= RADEON_CLASS_R100
;
675 else if (screen
->chip_family
<= CHIP_FAMILY_RV280
)
676 screen
->chip_flags
|= RADEON_CLASS_R200
;
678 screen
->chip_flags
|= RADEON_CLASS_R300
;
680 screen
->cpp
= dri_priv
->bpp
/ 8;
681 screen
->AGPMode
= dri_priv
->AGPMode
;
683 screen
->fbLocation
= ( INREG( RADEON_MC_FB_LOCATION
) & 0xffff ) << 16;
685 if ( sPriv
->drmMinor
>= 10 ) {
686 drm_radeon_setparam_t sp
;
688 sp
.param
= RADEON_SETPARAM_FB_LOCATION
;
689 sp
.value
= screen
->fbLocation
;
691 drmCommandWrite( sPriv
->fd
, DRM_RADEON_SETPARAM
,
695 screen
->frontOffset
= dri_priv
->frontOffset
;
696 screen
->frontPitch
= dri_priv
->frontPitch
;
697 screen
->backOffset
= dri_priv
->backOffset
;
698 screen
->backPitch
= dri_priv
->backPitch
;
699 screen
->depthOffset
= dri_priv
->depthOffset
;
700 screen
->depthPitch
= dri_priv
->depthPitch
;
702 /* Check if ddx has set up a surface reg to cover depth buffer */
703 screen
->depthHasSurface
= ((sPriv
->ddxMajor
> 4) &&
704 (screen
->chip_flags
& RADEON_CHIPSET_TCL
));
706 if ( dri_priv
->textureSize
== 0 ) {
707 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = screen
->gart_texture_offset
;
708 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
709 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
710 dri_priv
->log2GARTTexGran
;
712 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureOffset
713 + screen
->fbLocation
;
714 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureSize
;
715 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
716 dri_priv
->log2TexGran
;
719 if ( !screen
->gartTextures
.map
|| dri_priv
->textureSize
== 0
720 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
721 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
- 1;
722 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = 0;
723 screen
->texSize
[RADEON_GART_TEX_HEAP
] = 0;
724 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] = 0;
726 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
;
727 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = screen
->gart_texture_offset
;
728 screen
->texSize
[RADEON_GART_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
729 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] =
730 dri_priv
->log2GARTTexGran
;
733 if ( glx_enable_extension
!= NULL
) {
734 if ( screen
->irq
!= 0 ) {
735 (*glx_enable_extension
)( psc
, "GLX_SGI_swap_control" );
736 (*glx_enable_extension
)( psc
, "GLX_SGI_video_sync" );
737 (*glx_enable_extension
)( psc
, "GLX_MESA_swap_control" );
740 (*glx_enable_extension
)( psc
, "GLX_MESA_swap_frame_usage" );
741 if (IS_R200_CLASS(screen
))
742 (*glx_enable_extension
)( psc
, "GLX_MESA_allocate_memory" );
744 (*glx_enable_extension
)( psc
, "GLX_MESA_copy_sub_buffer" );
745 (*glx_enable_extension
)( psc
, "GLX_SGI_make_current_read" );
748 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
749 if (IS_R200_CLASS(screen
)) {
750 sPriv
->psc
->allocateMemory
= (void *) r200AllocateMemoryMESA
;
751 sPriv
->psc
->freeMemory
= (void *) r200FreeMemoryMESA
;
752 sPriv
->psc
->memoryOffset
= (void *) r200GetMemoryOffsetMESA
;
756 screen
->driScreen
= sPriv
;
757 screen
->sarea_priv_offset
= dri_priv
->sarea_priv_offset
;
761 /* Destroy the device specific screen private data struct.
764 radeonDestroyScreen( __DRIscreenPrivate
*sPriv
)
766 radeonScreenPtr screen
= (radeonScreenPtr
)sPriv
->private;
771 if ( screen
->gartTextures
.map
) {
772 drmUnmap( screen
->gartTextures
.map
, screen
->gartTextures
.size
);
774 drmUnmapBufs( screen
->buffers
);
775 drmUnmap( screen
->status
.map
, screen
->status
.size
);
776 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
778 /* free all option information */
779 driDestroyOptionInfo (&screen
->optionCache
);
782 sPriv
->private = NULL
;
786 /* Initialize the driver specific screen private data.
789 radeonInitDriver( __DRIscreenPrivate
*sPriv
)
791 sPriv
->private = (void *) radeonCreateScreen( sPriv
);
792 if ( !sPriv
->private ) {
793 radeonDestroyScreen( sPriv
);
802 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
804 * \todo This function (and its interface) will need to be updated to support
808 radeonCreateBuffer( __DRIscreenPrivate
*driScrnPriv
,
809 __DRIdrawablePrivate
*driDrawPriv
,
810 const __GLcontextModes
*mesaVis
,
813 radeonScreenPtr screen
= (radeonScreenPtr
) driScrnPriv
->private;
816 return GL_FALSE
; /* not implemented */
819 const GLboolean swDepth
= GL_FALSE
;
820 const GLboolean swAlpha
= GL_FALSE
;
821 const GLboolean swAccum
= mesaVis
->accumRedBits
> 0;
822 const GLboolean swStencil
= mesaVis
->stencilBits
> 0 &&
823 mesaVis
->depthBits
!= 24;
824 struct gl_framebuffer
*fb
= _mesa_create_framebuffer(mesaVis
);
826 /* front color renderbuffer */
828 driRenderbuffer
*frontRb
829 = driNewRenderbuffer(GL_RGBA
,
830 driScrnPriv
->pFB
+ screen
->frontOffset
,
832 screen
->frontOffset
, screen
->frontPitch
,
834 radeonSetSpanFunctions(frontRb
, mesaVis
);
835 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &frontRb
->Base
);
838 /* back color renderbuffer */
839 if (mesaVis
->doubleBufferMode
) {
840 driRenderbuffer
*backRb
841 = driNewRenderbuffer(GL_RGBA
,
842 driScrnPriv
->pFB
+ screen
->backOffset
,
844 screen
->backOffset
, screen
->backPitch
,
846 radeonSetSpanFunctions(backRb
, mesaVis
);
847 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &backRb
->Base
);
850 /* depth renderbuffer */
851 if (mesaVis
->depthBits
== 16) {
852 driRenderbuffer
*depthRb
853 = driNewRenderbuffer(GL_DEPTH_COMPONENT16
,
854 driScrnPriv
->pFB
+ screen
->depthOffset
,
856 screen
->depthOffset
, screen
->depthPitch
,
858 radeonSetSpanFunctions(depthRb
, mesaVis
);
859 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &depthRb
->Base
);
860 depthRb
->depthHasSurface
= screen
->depthHasSurface
;
862 else if (mesaVis
->depthBits
== 24) {
863 driRenderbuffer
*depthRb
864 = driNewRenderbuffer(GL_DEPTH_COMPONENT24
,
865 driScrnPriv
->pFB
+ screen
->depthOffset
,
867 screen
->depthOffset
, screen
->depthPitch
,
869 radeonSetSpanFunctions(depthRb
, mesaVis
);
870 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &depthRb
->Base
);
871 depthRb
->depthHasSurface
= screen
->depthHasSurface
;
874 /* stencil renderbuffer */
875 if (mesaVis
->stencilBits
> 0 && !swStencil
) {
876 driRenderbuffer
*stencilRb
877 = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT
,
878 driScrnPriv
->pFB
+ screen
->depthOffset
,
880 screen
->depthOffset
, screen
->depthPitch
,
882 radeonSetSpanFunctions(stencilRb
, mesaVis
);
883 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &stencilRb
->Base
);
884 stencilRb
->depthHasSurface
= screen
->depthHasSurface
;
887 _mesa_add_soft_renderbuffers(fb
,
888 GL_FALSE
, /* color */
894 driDrawPriv
->driverPrivate
= (void *) fb
;
896 return (driDrawPriv
->driverPrivate
!= NULL
);
902 radeonDestroyBuffer(__DRIdrawablePrivate
*driDrawPriv
)
904 _mesa_unreference_framebuffer((GLframebuffer
**)(&(driDrawPriv
->driverPrivate
)));
907 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
909 * Choose the appropriate CreateContext function based on the chipset.
910 * Eventually, all drivers will go through this process.
912 static GLboolean
radeonCreateContext(const __GLcontextModes
* glVisual
,
913 __DRIcontextPrivate
* driContextPriv
,
914 void *sharedContextPriv
)
916 __DRIscreenPrivate
*sPriv
= driContextPriv
->driScreenPriv
;
917 radeonScreenPtr screen
= (radeonScreenPtr
) (sPriv
->private);
919 if (IS_R300_CLASS(screen
))
920 return r300CreateContext(glVisual
, driContextPriv
, sharedContextPriv
);
925 * Choose the appropriate DestroyContext function based on the chipset.
927 static void radeonDestroyContext(__DRIcontextPrivate
* driContextPriv
)
929 radeonContextPtr radeon
= (radeonContextPtr
) driContextPriv
->driverPrivate
;
931 if (IS_R300_CLASS(radeon
->radeonScreen
))
932 return r300DestroyContext(driContextPriv
);
938 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
939 static struct __DriverAPIRec radeonAPI
= {
940 .InitDriver
= radeonInitDriver
,
941 .DestroyScreen
= radeonDestroyScreen
,
942 .CreateContext
= radeonCreateContext
,
943 .DestroyContext
= radeonDestroyContext
,
944 .CreateBuffer
= radeonCreateBuffer
,
945 .DestroyBuffer
= radeonDestroyBuffer
,
946 .SwapBuffers
= radeonSwapBuffers
,
947 .MakeCurrent
= radeonMakeCurrent
,
948 .UnbindContext
= radeonUnbindContext
,
949 .GetSwapInfo
= getSwapInfo
,
950 .GetMSC
= driGetMSC32
,
951 .WaitForMSC
= driWaitForMSC32
,
953 .SwapBuffersMSC
= NULL
,
954 .CopySubBuffer
= radeonCopySubBuffer
,
957 static const struct __DriverAPIRec r200API
= {
958 .InitDriver
= radeonInitDriver
,
959 .DestroyScreen
= radeonDestroyScreen
,
960 .CreateContext
= r200CreateContext
,
961 .DestroyContext
= r200DestroyContext
,
962 .CreateBuffer
= radeonCreateBuffer
,
963 .DestroyBuffer
= radeonDestroyBuffer
,
964 .SwapBuffers
= r200SwapBuffers
,
965 .MakeCurrent
= r200MakeCurrent
,
966 .UnbindContext
= r200UnbindContext
,
967 .GetSwapInfo
= getSwapInfo
,
968 .GetMSC
= driGetMSC32
,
969 .WaitForMSC
= driWaitForMSC32
,
971 .SwapBuffersMSC
= NULL
,
972 .CopySubBuffer
= r200CopySubBuffer
977 * This is the bootstrap function for the driver. libGL supplies all of the
978 * requisite information about the system, and the driver initializes itself.
979 * This routine also fills in the linked list pointed to by \c driver_modes
980 * with the \c __GLcontextModes that the driver can support for windows or
983 * \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on
987 __driCreateNewScreen_20050727( __DRInativeDisplay
*dpy
,
988 int scrn
, __DRIscreen
*psc
,
989 const __GLcontextModes
* modes
,
990 const __DRIversion
* ddx_version
,
991 const __DRIversion
* dri_version
,
992 const __DRIversion
* drm_version
,
993 const __DRIframebuffer
* frame_buffer
,
994 drmAddress pSAREA
, int fd
,
995 int internal_api_version
,
996 const __DRIinterfaceMethods
* interface
,
997 __GLcontextModes
** driver_modes
)
999 __DRIscreenPrivate
*psp
;
1001 static const char *driver_name
= "Radeon";
1002 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1003 static const __DRIversion dri_expected
= { 4, 0, 0 };
1004 static const __DRIversion drm_expected
= { 1, 6, 0 };
1005 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1006 static const char *driver_name
= "R200";
1007 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1008 static const __DRIversion dri_expected
= { 4, 0, 0 };
1009 static const __DRIversion drm_expected
= { 1, 6, 0 };
1010 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1011 static const char *driver_name
= "R300";
1012 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1013 static const __DRIversion dri_expected
= { 4, 0, 0 };
1014 static const __DRIversion drm_expected
= { 1, 24, 0 };
1017 dri_interface
= interface
;
1019 if ( ! driCheckDriDdxDrmVersions3( driver_name
,
1020 dri_version
, & dri_expected
,
1021 ddx_version
, & ddx_expected
,
1022 drm_version
, & drm_expected
) ) {
1025 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1026 psp
= __driUtilCreateNewScreen(dpy
, scrn
, psc
, NULL
,
1027 ddx_version
, dri_version
, drm_version
,
1028 frame_buffer
, pSAREA
, fd
,
1029 internal_api_version
, &radeonAPI
);
1030 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1031 psp
= __driUtilCreateNewScreen(dpy
, scrn
, psc
, NULL
,
1032 ddx_version
, dri_version
, drm_version
,
1033 frame_buffer
, pSAREA
, fd
,
1034 internal_api_version
, &r200API
);
1037 if ( psp
!= NULL
) {
1038 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
) psp
->pDevPriv
;
1040 *driver_modes
= radeonFillInModes( dri_priv
->bpp
,
1041 (dri_priv
->bpp
== 16) ? 16 : 24,
1042 (dri_priv
->bpp
== 16) ? 0 : 8,
1043 (dri_priv
->backOffset
!= dri_priv
->depthOffset
) );
1046 /* Calling driInitExtensions here, with a NULL context pointer,
1047 * does not actually enable the extensions. It just makes sure
1048 * that all the dispatch offsets for all the extensions that
1049 * *might* be enables are known. This is needed because the
1050 * dispatch offsets need to be known when _mesa_context_create
1051 * is called, but we can't enable the extensions until we have a
1054 * Hello chicken. Hello egg. How are you two today?
1056 driInitExtensions( NULL
, card_extensions
, GL_FALSE
);
1057 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1058 driInitExtensions( NULL
, blend_extensions
, GL_FALSE
);
1059 driInitSingleExtension( NULL
, ARB_vp_extension
);
1060 driInitSingleExtension( NULL
, NV_vp_extension
);
1061 driInitSingleExtension( NULL
, ATI_fs_extension
);
1062 driInitExtensions( NULL
, point_extensions
, GL_FALSE
);
1066 return (void *) psp
;
1071 * Get information about previous buffer swaps.
1074 getSwapInfo( __DRIdrawablePrivate
*dPriv
, __DRIswapInfo
* sInfo
)
1076 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1077 radeonContextPtr rmesa
;
1078 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1079 r200ContextPtr rmesa
;
1082 if ( (dPriv
== NULL
) || (dPriv
->driContextPriv
== NULL
)
1083 || (dPriv
->driContextPriv
->driverPrivate
== NULL
)
1084 || (sInfo
== NULL
) ) {
1088 rmesa
= dPriv
->driContextPriv
->driverPrivate
;
1089 sInfo
->swap_count
= rmesa
->swap_count
;
1090 sInfo
->swap_ust
= rmesa
->swap_ust
;
1091 sInfo
->swap_missed_count
= rmesa
->swap_missed_count
;
1093 sInfo
->swap_missed_usage
= (sInfo
->swap_missed_count
!= 0)
1094 ? driCalculateSwapUsage( dPriv
, 0, rmesa
->swap_missed_ust
)