1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
32 * \file radeon_screen.c
33 * Screen initialization functions for the Radeon driver.
35 * \author Kevin E. Martin <martin@valinux.com>
36 * \author Gareth Hughes <gareth@valinux.com>
42 #include "framebuffer.h"
43 #include "renderbuffer.h"
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
50 #include "radeon_context.h"
51 #include "radeon_span.h"
52 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
53 #include "r200_context.h"
54 #include "r200_ioctl.h"
55 #include "r200_span.h"
56 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
57 #include "r300_context.h"
58 #include "radeon_span.h"
64 #include "drirenderbuffer.h"
66 #include "GL/internal/dri_interface.h"
68 /* Radeon configuration
72 #if !RADEON_COMMON /* R100 */
73 PUBLIC
const char __driConfigOptions
[] =
75 DRI_CONF_SECTION_PERFORMANCE
76 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
77 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
78 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
79 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
80 DRI_CONF_HYPERZ(false)
82 DRI_CONF_SECTION_QUALITY
83 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
84 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
85 DRI_CONF_NO_NEG_LOD_BIAS(false)
86 DRI_CONF_FORCE_S3TC_ENABLE(false)
87 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
88 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
89 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
90 DRI_CONF_ALLOW_LARGE_TEXTURES(1)
92 DRI_CONF_SECTION_DEBUG
93 DRI_CONF_NO_RAST(false)
96 static const GLuint __driNConfigOptions
= 14;
98 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
100 PUBLIC
const char __driConfigOptions
[] =
102 DRI_CONF_SECTION_PERFORMANCE
103 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
104 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
105 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
106 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
107 DRI_CONF_HYPERZ(false)
109 DRI_CONF_SECTION_QUALITY
110 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
111 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
112 DRI_CONF_NO_NEG_LOD_BIAS(false)
113 DRI_CONF_FORCE_S3TC_ENABLE(false)
114 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
115 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
116 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
117 DRI_CONF_ALLOW_LARGE_TEXTURES(1)
118 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
120 DRI_CONF_SECTION_DEBUG
121 DRI_CONF_NO_RAST(false)
123 DRI_CONF_SECTION_SOFTWARE
124 DRI_CONF_NV_VERTEX_PROGRAM(false)
127 static const GLuint __driNConfigOptions
= 16;
129 extern const struct dri_extension blend_extensions
[];
130 extern const struct dri_extension ARB_vp_extension
[];
131 extern const struct dri_extension NV_vp_extension
[];
132 extern const struct dri_extension ATI_fs_extension
[];
134 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
136 /* TODO: integrate these into xmlpool.h! */
137 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
138 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
139 DRI_CONF_DESC(en,"Number of texture image units") \
140 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
143 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
144 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
145 DRI_CONF_DESC(en,"Number of texture coordinate units") \
146 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
149 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
150 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
151 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
152 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
155 const char __driConfigOptions
[] =
157 DRI_CONF_SECTION_PERFORMANCE
158 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
159 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
160 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
161 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
162 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
163 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
165 DRI_CONF_SECTION_QUALITY
166 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
167 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
168 DRI_CONF_NO_NEG_LOD_BIAS(false)
169 DRI_CONF_FORCE_S3TC_ENABLE(false)
170 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
171 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
172 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
174 DRI_CONF_SECTION_DEBUG
175 DRI_CONF_NO_RAST(false)
178 static const GLuint __driNConfigOptions
= 14;
181 int RADEON_DEBUG
= 0;
183 static const struct dri_debug_control debug_control
[] = {
184 {"fall", DEBUG_FALLBACKS
},
185 {"tex", DEBUG_TEXTURE
},
186 {"ioctl", DEBUG_IOCTL
},
187 {"prim", DEBUG_PRIMS
},
188 {"vert", DEBUG_VERTS
},
189 {"state", DEBUG_STATE
},
190 {"code", DEBUG_CODEGEN
},
191 {"vfmt", DEBUG_VFMT
},
192 {"vtxf", DEBUG_VFMT
},
193 {"verb", DEBUG_VERBOSE
},
196 {"san", DEBUG_SANITY
},
197 {"sync", DEBUG_SYNC
},
198 {"pix", DEBUG_PIXEL
},
199 {"mem", DEBUG_MEMORY
},
200 {"allmsg", ~DEBUG_SYNC
}, /* avoid the term "sync" because the parser uses strstr */
203 #endif /* RADEON_DEBUG */
205 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
207 extern const struct dri_extension card_extensions
[];
209 static int getSwapInfo( __DRIdrawablePrivate
*dPriv
, __DRIswapInfo
* sInfo
);
212 radeonGetParam(int fd
, int param
, void *value
)
215 drm_radeon_getparam_t gp
;
220 ret
= drmCommandWriteRead( fd
, DRM_RADEON_GETPARAM
, &gp
, sizeof(gp
));
224 static __GLcontextModes
*
225 radeonFillInModes( unsigned pixel_bits
, unsigned depth_bits
,
226 unsigned stencil_bits
, GLboolean have_back_buffer
)
228 __GLcontextModes
* modes
;
229 __GLcontextModes
* m
;
231 unsigned depth_buffer_factor
;
232 unsigned back_buffer_factor
;
236 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
237 * enough to add support. Basically, if a context is created with an
238 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
239 * will never be used.
241 static const GLenum back_buffer_modes
[] = {
242 GLX_NONE
, GLX_SWAP_UNDEFINED_OML
/*, GLX_SWAP_COPY_OML */
245 u_int8_t depth_bits_array
[2];
246 u_int8_t stencil_bits_array
[2];
249 depth_bits_array
[0] = depth_bits
;
250 depth_bits_array
[1] = depth_bits
;
252 /* Just like with the accumulation buffer, always provide some modes
253 * with a stencil buffer. It will be a sw fallback, but some apps won't
256 stencil_bits_array
[0] = 0;
257 stencil_bits_array
[1] = (stencil_bits
== 0) ? 8 : stencil_bits
;
259 depth_buffer_factor
= ((depth_bits
!= 0) || (stencil_bits
!= 0)) ? 2 : 1;
260 back_buffer_factor
= (have_back_buffer
) ? 2 : 1;
262 num_modes
= depth_buffer_factor
* back_buffer_factor
* 4;
264 if ( pixel_bits
== 16 ) {
266 fb_type
= GL_UNSIGNED_SHORT_5_6_5
;
270 fb_type
= GL_UNSIGNED_INT_8_8_8_8_REV
;
273 modes
= (*dri_interface
->createContextModes
)( num_modes
, sizeof( __GLcontextModes
) );
275 if ( ! driFillInModes( & m
, fb_format
, fb_type
,
276 depth_bits_array
, stencil_bits_array
, depth_buffer_factor
,
277 back_buffer_modes
, back_buffer_factor
,
279 fprintf( stderr
, "[%s:%u] Error creating FBConfig!\n",
280 __func__
, __LINE__
);
284 if ( ! driFillInModes( & m
, fb_format
, fb_type
,
285 depth_bits_array
, stencil_bits_array
, depth_buffer_factor
,
286 back_buffer_modes
, back_buffer_factor
,
287 GLX_DIRECT_COLOR
) ) {
288 fprintf( stderr
, "[%s:%u] Error creating FBConfig!\n",
289 __func__
, __LINE__
);
293 /* Mark the visual as slow if there are "fake" stencil bits.
295 for ( m
= modes
; m
!= NULL
; m
= m
->next
) {
296 if ( (m
->stencilBits
!= 0) && (m
->stencilBits
!= stencil_bits
) ) {
297 m
->visualRating
= GLX_SLOW_CONFIG
;
305 /* Create the device specific screen private data struct.
307 static radeonScreenPtr
308 radeonCreateScreen( __DRIscreenPrivate
*sPriv
)
310 radeonScreenPtr screen
;
311 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
)sPriv
->pDevPriv
;
312 unsigned char *RADEONMMIO
;
313 PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension
=
314 (PFNGLXSCRENABLEEXTENSIONPROC
) (*dri_interface
->getProcAddress("glxEnableExtension"));
315 void * const psc
= sPriv
->psc
->screenConfigs
;
317 if (sPriv
->devPrivSize
!= sizeof(RADEONDRIRec
)) {
318 fprintf(stderr
,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
322 /* Allocate the private area */
323 screen
= (radeonScreenPtr
) CALLOC( sizeof(*screen
) );
325 __driUtilMessage("%s: Could not allocate memory for screen structure",
330 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
331 RADEON_DEBUG
= driParseDebugString(getenv("RADEON_DEBUG"), debug_control
);
334 /* parse information in __driConfigOptions */
335 driParseOptionInfo (&screen
->optionCache
,
336 __driConfigOptions
, __driNConfigOptions
);
338 /* This is first since which regions we map depends on whether or
339 * not we are using a PCI card.
341 screen
->card_type
= (dri_priv
->IsPCI
? RADEON_CARD_PCI
: RADEON_CARD_AGP
);
344 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_GART_BUFFER_OFFSET
,
345 &screen
->gart_buffer_offset
);
349 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret
);
353 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_GART_BASE
,
357 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret
);
361 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_IRQ_NR
,
365 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret
);
368 screen
->drmSupportsCubeMapsR200
= (sPriv
->drmMinor
>= 7);
369 screen
->drmSupportsBlendColor
= (sPriv
->drmMinor
>= 11);
370 screen
->drmSupportsTriPerf
= (sPriv
->drmMinor
>= 16);
371 screen
->drmSupportsFragShader
= (sPriv
->drmMinor
>= 18);
372 screen
->drmSupportsPointSprites
= (sPriv
->drmMinor
>= 13);
373 screen
->drmSupportsCubeMapsR100
= (sPriv
->drmMinor
>= 15);
374 screen
->drmSupportsVertexProgram
= (sPriv
->drmMinor
>= 25);
377 screen
->mmio
.handle
= dri_priv
->registerHandle
;
378 screen
->mmio
.size
= dri_priv
->registerSize
;
379 if ( drmMap( sPriv
->fd
,
382 &screen
->mmio
.map
) ) {
384 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__
);
388 RADEONMMIO
= screen
->mmio
.map
;
390 screen
->status
.handle
= dri_priv
->statusHandle
;
391 screen
->status
.size
= dri_priv
->statusSize
;
392 if ( drmMap( sPriv
->fd
,
393 screen
->status
.handle
,
395 &screen
->status
.map
) ) {
396 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
398 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__
);
401 screen
->scratch
= (__volatile__ u_int32_t
*)
402 ((GLubyte
*)screen
->status
.map
+ RADEON_SCRATCH_REG_OFFSET
);
404 screen
->buffers
= drmMapBufs( sPriv
->fd
);
405 if ( !screen
->buffers
) {
406 drmUnmap( screen
->status
.map
, screen
->status
.size
);
407 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
409 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__
);
413 if ( dri_priv
->gartTexHandle
&& dri_priv
->gartTexMapSize
) {
414 screen
->gartTextures
.handle
= dri_priv
->gartTexHandle
;
415 screen
->gartTextures
.size
= dri_priv
->gartTexMapSize
;
416 if ( drmMap( sPriv
->fd
,
417 screen
->gartTextures
.handle
,
418 screen
->gartTextures
.size
,
419 (drmAddressPtr
)&screen
->gartTextures
.map
) ) {
420 drmUnmapBufs( screen
->buffers
);
421 drmUnmap( screen
->status
.map
, screen
->status
.size
);
422 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
424 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__
);
428 screen
->gart_texture_offset
= dri_priv
->gartTexOffset
+ screen
->gart_base
;
431 screen
->chip_flags
= 0;
432 /* XXX: add more chipsets */
433 switch ( dri_priv
->deviceID
) {
434 case PCI_CHIP_RADEON_LY
:
435 case PCI_CHIP_RADEON_LZ
:
436 case PCI_CHIP_RADEON_QY
:
437 case PCI_CHIP_RADEON_QZ
:
438 case PCI_CHIP_RN50_515E
:
439 case PCI_CHIP_RN50_5969
:
440 screen
->chip_family
= CHIP_FAMILY_RV100
;
443 case PCI_CHIP_RS100_4136
:
444 case PCI_CHIP_RS100_4336
:
445 screen
->chip_family
= CHIP_FAMILY_RS100
;
448 case PCI_CHIP_RS200_4137
:
449 case PCI_CHIP_RS200_4337
:
450 case PCI_CHIP_RS250_4237
:
451 case PCI_CHIP_RS250_4437
:
452 screen
->chip_family
= CHIP_FAMILY_RS200
;
455 case PCI_CHIP_RADEON_QD
:
456 case PCI_CHIP_RADEON_QE
:
457 case PCI_CHIP_RADEON_QF
:
458 case PCI_CHIP_RADEON_QG
:
459 /* all original radeons (7200) presumably have a stencil op bug */
460 screen
->chip_family
= CHIP_FAMILY_R100
;
461 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_BROKEN_STENCIL
;
464 case PCI_CHIP_RV200_QW
:
465 case PCI_CHIP_RV200_QX
:
466 case PCI_CHIP_RADEON_LW
:
467 case PCI_CHIP_RADEON_LX
:
468 screen
->chip_family
= CHIP_FAMILY_RV200
;
469 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
472 case PCI_CHIP_R200_BB
:
473 case PCI_CHIP_R200_BC
:
474 case PCI_CHIP_R200_QH
:
475 case PCI_CHIP_R200_QL
:
476 case PCI_CHIP_R200_QM
:
477 screen
->chip_family
= CHIP_FAMILY_R200
;
478 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
481 case PCI_CHIP_RV250_If
:
482 case PCI_CHIP_RV250_Ig
:
483 case PCI_CHIP_RV250_Ld
:
484 case PCI_CHIP_RV250_Lf
:
485 case PCI_CHIP_RV250_Lg
:
486 screen
->chip_family
= CHIP_FAMILY_RV250
;
487 screen
->chip_flags
= R200_CHIPSET_YCBCR_BROKEN
| RADEON_CHIPSET_TCL
;
490 case PCI_CHIP_RV280_5960
:
491 case PCI_CHIP_RV280_5961
:
492 case PCI_CHIP_RV280_5962
:
493 case PCI_CHIP_RV280_5964
:
494 case PCI_CHIP_RV280_5965
:
495 case PCI_CHIP_RV280_5C61
:
496 case PCI_CHIP_RV280_5C63
:
497 screen
->chip_family
= CHIP_FAMILY_RV280
;
498 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
501 case PCI_CHIP_RS300_5834
:
502 case PCI_CHIP_RS300_5835
:
503 case PCI_CHIP_RS350_7834
:
504 case PCI_CHIP_RS350_7835
:
505 screen
->chip_family
= CHIP_FAMILY_RS300
;
508 case PCI_CHIP_R300_AD
:
509 case PCI_CHIP_R300_AE
:
510 case PCI_CHIP_R300_AF
:
511 case PCI_CHIP_R300_AG
:
512 case PCI_CHIP_R300_ND
:
513 case PCI_CHIP_R300_NE
:
514 case PCI_CHIP_R300_NF
:
515 case PCI_CHIP_R300_NG
:
516 screen
->chip_family
= CHIP_FAMILY_R300
;
517 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
520 case PCI_CHIP_RV350_AP
:
521 case PCI_CHIP_RV350_AQ
:
522 case PCI_CHIP_RV350_AR
:
523 case PCI_CHIP_RV350_AS
:
524 case PCI_CHIP_RV350_AT
:
525 case PCI_CHIP_RV350_AV
:
526 case PCI_CHIP_RV350_AU
:
527 case PCI_CHIP_RV350_NP
:
528 case PCI_CHIP_RV350_NQ
:
529 case PCI_CHIP_RV350_NR
:
530 case PCI_CHIP_RV350_NS
:
531 case PCI_CHIP_RV350_NT
:
532 case PCI_CHIP_RV350_NV
:
533 screen
->chip_family
= CHIP_FAMILY_RV350
;
534 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
537 case PCI_CHIP_R350_AH
:
538 case PCI_CHIP_R350_AI
:
539 case PCI_CHIP_R350_AJ
:
540 case PCI_CHIP_R350_AK
:
541 case PCI_CHIP_R350_NH
:
542 case PCI_CHIP_R350_NI
:
543 case PCI_CHIP_R360_NJ
:
544 case PCI_CHIP_R350_NK
:
545 screen
->chip_family
= CHIP_FAMILY_R350
;
546 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
549 case PCI_CHIP_RV370_5460
:
550 case PCI_CHIP_RV370_5462
:
551 case PCI_CHIP_RV370_5464
:
552 case PCI_CHIP_RV370_5B60
:
553 case PCI_CHIP_RV370_5B62
:
554 case PCI_CHIP_RV370_5B63
:
555 case PCI_CHIP_RV370_5B64
:
556 case PCI_CHIP_RV370_5B65
:
557 case PCI_CHIP_RV380_3150
:
558 case PCI_CHIP_RV380_3152
:
559 case PCI_CHIP_RV380_3154
:
560 case PCI_CHIP_RV380_3E50
:
561 case PCI_CHIP_RV380_3E54
:
562 screen
->chip_family
= CHIP_FAMILY_RV380
;
563 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
566 case PCI_CHIP_R420_JN
:
567 case PCI_CHIP_R420_JH
:
568 case PCI_CHIP_R420_JI
:
569 case PCI_CHIP_R420_JJ
:
570 case PCI_CHIP_R420_JK
:
571 case PCI_CHIP_R420_JL
:
572 case PCI_CHIP_R420_JM
:
573 case PCI_CHIP_R420_JO
:
574 case PCI_CHIP_R420_JP
:
575 case PCI_CHIP_R420_JT
:
576 case PCI_CHIP_R481_4B49
:
577 case PCI_CHIP_R481_4B4A
:
578 case PCI_CHIP_R481_4B4B
:
579 case PCI_CHIP_R481_4B4C
:
580 case PCI_CHIP_R423_UH
:
581 case PCI_CHIP_R423_UI
:
582 case PCI_CHIP_R423_UJ
:
583 case PCI_CHIP_R423_UK
:
584 case PCI_CHIP_R430_554C
:
585 case PCI_CHIP_R430_554D
:
586 case PCI_CHIP_R430_554E
:
587 case PCI_CHIP_R430_554F
:
588 case PCI_CHIP_R423_5550
:
589 case PCI_CHIP_R423_UQ
:
590 case PCI_CHIP_R423_UR
:
591 case PCI_CHIP_R423_UT
:
592 case PCI_CHIP_R430_5D48
:
593 case PCI_CHIP_R430_5D49
:
594 case PCI_CHIP_R430_5D4A
:
595 case PCI_CHIP_R480_5D4C
:
596 case PCI_CHIP_R480_5D4D
:
597 case PCI_CHIP_R480_5D4E
:
598 case PCI_CHIP_R480_5D4F
:
599 case PCI_CHIP_R480_5D50
:
600 case PCI_CHIP_R480_5D52
:
601 case PCI_CHIP_R423_5D57
:
602 screen
->chip_family
= CHIP_FAMILY_R420
;
603 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
606 case PCI_CHIP_RV410_564A
:
607 case PCI_CHIP_RV410_564B
:
608 case PCI_CHIP_RV410_564F
:
609 case PCI_CHIP_RV410_5652
:
610 case PCI_CHIP_RV410_5653
:
611 case PCI_CHIP_RV410_5E48
:
612 case PCI_CHIP_RV410_5E4A
:
613 case PCI_CHIP_RV410_5E4B
:
614 case PCI_CHIP_RV410_5E4C
:
615 case PCI_CHIP_RV410_5E4D
:
616 case PCI_CHIP_RV410_5E4F
:
617 screen
->chip_family
= CHIP_FAMILY_RV410
;
618 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
621 case PCI_CHIP_RS480_5954
:
622 case PCI_CHIP_RS480_5955
:
623 case PCI_CHIP_RS482_5974
:
624 case PCI_CHIP_RS482_5975
:
625 case PCI_CHIP_RS400_5A41
:
626 case PCI_CHIP_RS400_5A42
:
627 case PCI_CHIP_RC410_5A61
:
628 case PCI_CHIP_RC410_5A62
:
629 screen
->chip_family
= CHIP_FAMILY_RS400
;
630 fprintf(stderr
, "Warning, xpress200 detected. Probably won't work.\n");
634 fprintf(stderr
, "unknown chip id 0x%x, can't guess.\n",
638 if ((screen
->chip_family
== CHIP_FAMILY_R350
|| screen
->chip_family
== CHIP_FAMILY_R300
) &&
639 sPriv
->ddxMinor
< 2) {
640 fprintf(stderr
, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
644 if (screen
->chip_family
<= CHIP_FAMILY_RS200
)
645 screen
->chip_flags
|= RADEON_CLASS_R100
;
646 else if (screen
->chip_family
<= CHIP_FAMILY_RV280
)
647 screen
->chip_flags
|= RADEON_CLASS_R200
;
649 screen
->chip_flags
|= RADEON_CLASS_R300
;
651 screen
->cpp
= dri_priv
->bpp
/ 8;
652 screen
->AGPMode
= dri_priv
->AGPMode
;
654 screen
->fbLocation
= ( INREG( RADEON_MC_FB_LOCATION
) & 0xffff ) << 16;
656 if ( sPriv
->drmMinor
>= 10 ) {
657 drm_radeon_setparam_t sp
;
659 sp
.param
= RADEON_SETPARAM_FB_LOCATION
;
660 sp
.value
= screen
->fbLocation
;
662 drmCommandWrite( sPriv
->fd
, DRM_RADEON_SETPARAM
,
666 screen
->frontOffset
= dri_priv
->frontOffset
;
667 screen
->frontPitch
= dri_priv
->frontPitch
;
668 screen
->backOffset
= dri_priv
->backOffset
;
669 screen
->backPitch
= dri_priv
->backPitch
;
670 screen
->depthOffset
= dri_priv
->depthOffset
;
671 screen
->depthPitch
= dri_priv
->depthPitch
;
673 /* Check if ddx has set up a surface reg to cover depth buffer */
674 screen
->depthHasSurface
= ((sPriv
->ddxMajor
> 4) &&
675 (screen
->chip_flags
& RADEON_CHIPSET_TCL
));
677 if ( dri_priv
->textureSize
== 0 ) {
678 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = screen
->gart_texture_offset
;
679 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
680 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
681 dri_priv
->log2GARTTexGran
;
683 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureOffset
684 + screen
->fbLocation
;
685 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureSize
;
686 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
687 dri_priv
->log2TexGran
;
690 if ( !screen
->gartTextures
.map
|| dri_priv
->textureSize
== 0
691 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
692 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
- 1;
693 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = 0;
694 screen
->texSize
[RADEON_GART_TEX_HEAP
] = 0;
695 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] = 0;
697 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
;
698 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = screen
->gart_texture_offset
;
699 screen
->texSize
[RADEON_GART_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
700 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] =
701 dri_priv
->log2GARTTexGran
;
704 if ( glx_enable_extension
!= NULL
) {
705 if ( screen
->irq
!= 0 ) {
706 (*glx_enable_extension
)( psc
, "GLX_SGI_swap_control" );
707 (*glx_enable_extension
)( psc
, "GLX_SGI_video_sync" );
708 (*glx_enable_extension
)( psc
, "GLX_MESA_swap_control" );
711 (*glx_enable_extension
)( psc
, "GLX_MESA_swap_frame_usage" );
712 if (IS_R200_CLASS(screen
))
713 (*glx_enable_extension
)( psc
, "GLX_MESA_allocate_memory" );
715 (*glx_enable_extension
)( psc
, "GLX_MESA_copy_sub_buffer" );
718 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
719 if (IS_R200_CLASS(screen
)) {
720 sPriv
->psc
->allocateMemory
= (void *) r200AllocateMemoryMESA
;
721 sPriv
->psc
->freeMemory
= (void *) r200FreeMemoryMESA
;
722 sPriv
->psc
->memoryOffset
= (void *) r200GetMemoryOffsetMESA
;
726 screen
->driScreen
= sPriv
;
727 screen
->sarea_priv_offset
= dri_priv
->sarea_priv_offset
;
731 /* Destroy the device specific screen private data struct.
734 radeonDestroyScreen( __DRIscreenPrivate
*sPriv
)
736 radeonScreenPtr screen
= (radeonScreenPtr
)sPriv
->private;
741 if ( screen
->gartTextures
.map
) {
742 drmUnmap( screen
->gartTextures
.map
, screen
->gartTextures
.size
);
744 drmUnmapBufs( screen
->buffers
);
745 drmUnmap( screen
->status
.map
, screen
->status
.size
);
746 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
748 /* free all option information */
749 driDestroyOptionInfo (&screen
->optionCache
);
752 sPriv
->private = NULL
;
756 /* Initialize the driver specific screen private data.
759 radeonInitDriver( __DRIscreenPrivate
*sPriv
)
761 sPriv
->private = (void *) radeonCreateScreen( sPriv
);
762 if ( !sPriv
->private ) {
763 radeonDestroyScreen( sPriv
);
772 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
774 * \todo This function (and its interface) will need to be updated to support
778 radeonCreateBuffer( __DRIscreenPrivate
*driScrnPriv
,
779 __DRIdrawablePrivate
*driDrawPriv
,
780 const __GLcontextModes
*mesaVis
,
783 radeonScreenPtr screen
= (radeonScreenPtr
) driScrnPriv
->private;
786 return GL_FALSE
; /* not implemented */
789 const GLboolean swDepth
= GL_FALSE
;
790 const GLboolean swAlpha
= GL_FALSE
;
791 const GLboolean swAccum
= mesaVis
->accumRedBits
> 0;
792 const GLboolean swStencil
= mesaVis
->stencilBits
> 0 &&
793 mesaVis
->depthBits
!= 24;
794 struct gl_framebuffer
*fb
= _mesa_create_framebuffer(mesaVis
);
796 /* front color renderbuffer */
798 driRenderbuffer
*frontRb
799 = driNewRenderbuffer(GL_RGBA
,
800 driScrnPriv
->pFB
+ screen
->frontOffset
,
802 screen
->frontOffset
, screen
->frontPitch
,
804 radeonSetSpanFunctions(frontRb
, mesaVis
);
805 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &frontRb
->Base
);
808 /* back color renderbuffer */
809 if (mesaVis
->doubleBufferMode
) {
810 driRenderbuffer
*backRb
811 = driNewRenderbuffer(GL_RGBA
,
812 driScrnPriv
->pFB
+ screen
->backOffset
,
814 screen
->backOffset
, screen
->backPitch
,
816 radeonSetSpanFunctions(backRb
, mesaVis
);
817 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &backRb
->Base
);
820 /* depth renderbuffer */
821 if (mesaVis
->depthBits
== 16) {
822 driRenderbuffer
*depthRb
823 = driNewRenderbuffer(GL_DEPTH_COMPONENT16
,
824 driScrnPriv
->pFB
+ screen
->depthOffset
,
826 screen
->depthOffset
, screen
->depthPitch
,
828 radeonSetSpanFunctions(depthRb
, mesaVis
);
829 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &depthRb
->Base
);
830 depthRb
->depthHasSurface
= screen
->depthHasSurface
;
832 else if (mesaVis
->depthBits
== 24) {
833 driRenderbuffer
*depthRb
834 = driNewRenderbuffer(GL_DEPTH_COMPONENT24
,
835 driScrnPriv
->pFB
+ screen
->depthOffset
,
837 screen
->depthOffset
, screen
->depthPitch
,
839 radeonSetSpanFunctions(depthRb
, mesaVis
);
840 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &depthRb
->Base
);
841 depthRb
->depthHasSurface
= screen
->depthHasSurface
;
844 /* stencil renderbuffer */
845 if (mesaVis
->stencilBits
> 0 && !swStencil
) {
846 driRenderbuffer
*stencilRb
847 = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT
,
848 driScrnPriv
->pFB
+ screen
->depthOffset
,
850 screen
->depthOffset
, screen
->depthPitch
,
852 radeonSetSpanFunctions(stencilRb
, mesaVis
);
853 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &stencilRb
->Base
);
854 stencilRb
->depthHasSurface
= screen
->depthHasSurface
;
857 _mesa_add_soft_renderbuffers(fb
,
858 GL_FALSE
, /* color */
864 driDrawPriv
->driverPrivate
= (void *) fb
;
866 return (driDrawPriv
->driverPrivate
!= NULL
);
872 radeonDestroyBuffer(__DRIdrawablePrivate
*driDrawPriv
)
874 _mesa_destroy_framebuffer((GLframebuffer
*) (driDrawPriv
->driverPrivate
));
877 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
879 * Choose the appropriate CreateContext function based on the chipset.
880 * Eventually, all drivers will go through this process.
882 static GLboolean
radeonCreateContext(const __GLcontextModes
* glVisual
,
883 __DRIcontextPrivate
* driContextPriv
,
884 void *sharedContextPriv
)
886 __DRIscreenPrivate
*sPriv
= driContextPriv
->driScreenPriv
;
887 radeonScreenPtr screen
= (radeonScreenPtr
) (sPriv
->private);
889 if (IS_R300_CLASS(screen
))
890 return r300CreateContext(glVisual
, driContextPriv
, sharedContextPriv
);
895 * Choose the appropriate DestroyContext function based on the chipset.
897 static void radeonDestroyContext(__DRIcontextPrivate
* driContextPriv
)
899 radeonContextPtr radeon
= (radeonContextPtr
) driContextPriv
->driverPrivate
;
901 if (IS_R300_CLASS(radeon
->radeonScreen
))
902 return r300DestroyContext(driContextPriv
);
908 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
909 static struct __DriverAPIRec radeonAPI
= {
910 .InitDriver
= radeonInitDriver
,
911 .DestroyScreen
= radeonDestroyScreen
,
912 .CreateContext
= radeonCreateContext
,
913 .DestroyContext
= radeonDestroyContext
,
914 .CreateBuffer
= radeonCreateBuffer
,
915 .DestroyBuffer
= radeonDestroyBuffer
,
916 .SwapBuffers
= radeonSwapBuffers
,
917 .MakeCurrent
= radeonMakeCurrent
,
918 .UnbindContext
= radeonUnbindContext
,
919 .GetSwapInfo
= getSwapInfo
,
920 .GetMSC
= driGetMSC32
,
921 .WaitForMSC
= driWaitForMSC32
,
923 .SwapBuffersMSC
= NULL
,
924 .CopySubBuffer
= radeonCopySubBuffer
,
927 static const struct __DriverAPIRec r200API
= {
928 .InitDriver
= radeonInitDriver
,
929 .DestroyScreen
= radeonDestroyScreen
,
930 .CreateContext
= r200CreateContext
,
931 .DestroyContext
= r200DestroyContext
,
932 .CreateBuffer
= radeonCreateBuffer
,
933 .DestroyBuffer
= radeonDestroyBuffer
,
934 .SwapBuffers
= r200SwapBuffers
,
935 .MakeCurrent
= r200MakeCurrent
,
936 .UnbindContext
= r200UnbindContext
,
937 .GetSwapInfo
= getSwapInfo
,
938 .GetMSC
= driGetMSC32
,
939 .WaitForMSC
= driWaitForMSC32
,
941 .SwapBuffersMSC
= NULL
,
942 .CopySubBuffer
= r200CopySubBuffer
947 * This is the bootstrap function for the driver. libGL supplies all of the
948 * requisite information about the system, and the driver initializes itself.
949 * This routine also fills in the linked list pointed to by \c driver_modes
950 * with the \c __GLcontextModes that the driver can support for windows or
953 * \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on
957 __driCreateNewScreen_20050727( __DRInativeDisplay
*dpy
,
958 int scrn
, __DRIscreen
*psc
,
959 const __GLcontextModes
* modes
,
960 const __DRIversion
* ddx_version
,
961 const __DRIversion
* dri_version
,
962 const __DRIversion
* drm_version
,
963 const __DRIframebuffer
* frame_buffer
,
964 drmAddress pSAREA
, int fd
,
965 int internal_api_version
,
966 const __DRIinterfaceMethods
* interface
,
967 __GLcontextModes
** driver_modes
)
969 __DRIscreenPrivate
*psp
;
971 static const char *driver_name
= "Radeon";
972 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
973 static const __DRIversion dri_expected
= { 4, 0, 0 };
974 static const __DRIversion drm_expected
= { 1, 6, 0 };
975 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
976 static const char *driver_name
= "R200";
977 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
978 static const __DRIversion dri_expected
= { 4, 0, 0 };
979 static const __DRIversion drm_expected
= { 1, 6, 0 };
980 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
981 static const char *driver_name
= "R300";
982 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
983 static const __DRIversion dri_expected
= { 4, 0, 0 };
984 static const __DRIversion drm_expected
= { 1, 24, 0 };
987 dri_interface
= interface
;
989 if ( ! driCheckDriDdxDrmVersions3( driver_name
,
990 dri_version
, & dri_expected
,
991 ddx_version
, & ddx_expected
,
992 drm_version
, & drm_expected
) ) {
995 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
996 psp
= __driUtilCreateNewScreen(dpy
, scrn
, psc
, NULL
,
997 ddx_version
, dri_version
, drm_version
,
998 frame_buffer
, pSAREA
, fd
,
999 internal_api_version
, &radeonAPI
);
1000 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1001 psp
= __driUtilCreateNewScreen(dpy
, scrn
, psc
, NULL
,
1002 ddx_version
, dri_version
, drm_version
,
1003 frame_buffer
, pSAREA
, fd
,
1004 internal_api_version
, &r200API
);
1007 if ( psp
!= NULL
) {
1008 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
) psp
->pDevPriv
;
1010 *driver_modes
= radeonFillInModes( dri_priv
->bpp
,
1011 (dri_priv
->bpp
== 16) ? 16 : 24,
1012 (dri_priv
->bpp
== 16) ? 0 : 8,
1013 (dri_priv
->backOffset
!= dri_priv
->depthOffset
) );
1016 /* Calling driInitExtensions here, with a NULL context pointer,
1017 * does not actually enable the extensions. It just makes sure
1018 * that all the dispatch offsets for all the extensions that
1019 * *might* be enables are known. This is needed because the
1020 * dispatch offsets need to be known when _mesa_context_create
1021 * is called, but we can't enable the extensions until we have a
1024 * Hello chicken. Hello egg. How are you two today?
1026 driInitExtensions( NULL
, card_extensions
, GL_FALSE
);
1027 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1028 driInitExtensions( NULL
, blend_extensions
, GL_FALSE
);
1029 driInitSingleExtension( NULL
, ARB_vp_extension
);
1030 driInitSingleExtension( NULL
, NV_vp_extension
);
1031 driInitSingleExtension( NULL
, ATI_fs_extension
);
1035 return (void *) psp
;
1040 * Get information about previous buffer swaps.
1043 getSwapInfo( __DRIdrawablePrivate
*dPriv
, __DRIswapInfo
* sInfo
)
1045 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1046 radeonContextPtr rmesa
;
1047 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1048 r200ContextPtr rmesa
;
1051 if ( (dPriv
== NULL
) || (dPriv
->driContextPriv
== NULL
)
1052 || (dPriv
->driContextPriv
->driverPrivate
== NULL
)
1053 || (sInfo
== NULL
) ) {
1057 rmesa
= dPriv
->driContextPriv
->driverPrivate
;
1058 sInfo
->swap_count
= rmesa
->swap_count
;
1059 sInfo
->swap_ust
= rmesa
->swap_ust
;
1060 sInfo
->swap_missed_count
= rmesa
->swap_missed_count
;
1062 sInfo
->swap_missed_usage
= (sInfo
->swap_missed_count
!= 0)
1063 ? driCalculateSwapUsage( dPriv
, 0, rmesa
->swap_missed_ust
)