src/mesa/drivers/dri/radeon/radeon_screen.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
   2 /**************************************************************************
   3
   4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   5                      VA Linux Systems Inc., Fremont, California.
   6
   7 All Rights Reserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining
  10 a copy of this software and associated documentation files (the
  11 "Software"), to deal in the Software without restriction, including
  12 without limitation the rights to use, copy, modify, merge, publish,
  13 distribute, sublicense, and/or sell copies of the Software, and to
  14 permit persons to whom the Software is furnished to do so, subject to
  15 the following conditions:
  16
  17 The above copyright notice and this permission notice (including the
  18 next paragraph) shall be included in all copies or substantial
  19 portions of the Software.
  20
  21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28
  29 **************************************************************************/
  30
  31 /**
  32  * \file radeon_screen.c
  33  * Screen initialization functions for the Radeon driver.
  34  *
  35  * \author Kevin E. Martin <martin@valinux.com>
  36  * \author  Gareth Hughes <gareth@valinux.com>
  37  */
  38
  39 #include "glheader.h"
  40 #include "imports.h"
  41
  42 #define STANDALONE_MMIO
  43 #include "radeon_context.h"
  44 #include "radeon_screen.h"
  45 #include "radeon_macros.h"
  46
  47 #include "utils.h"
  48 #include "context.h"
  49 #include "vblank.h"
  50
  51 #include "GL/internal/dri_interface.h"
  52
  53 /* Radeon configuration
  54  */
  55 #include "xmlpool.h"
  56
  57 PUBLIC const char __driConfigOptions[] =
  58 DRI_CONF_BEGIN
  59     DRI_CONF_SECTION_PERFORMANCE
  60         DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
  61         DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
  62         DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
  63         DRI_CONF_HYPERZ(false)
  64     DRI_CONF_SECTION_END
  65     DRI_CONF_SECTION_QUALITY
  66         DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
  67         DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
  68         DRI_CONF_NO_NEG_LOD_BIAS(false)
  69         DRI_CONF_FORCE_S3TC_ENABLE(false)
  70         DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
  71         DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
  72         DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
  73         DRI_CONF_TEXTURE_LEVEL_HACK(false)
  74     DRI_CONF_SECTION_END
  75     DRI_CONF_SECTION_DEBUG
  76         DRI_CONF_NO_RAST(false)
  77     DRI_CONF_SECTION_END
  78 DRI_CONF_END;
  79 static const GLuint __driNConfigOptions = 13;
  80
  81 #if 1
  82 /* Including xf86PciInfo.h introduces a bunch of errors...
  83  */
  84 #define PCI_CHIP_RADEON_QD      0x5144
  85 #define PCI_CHIP_RADEON_QE      0x5145
  86 #define PCI_CHIP_RADEON_QF      0x5146
  87 #define PCI_CHIP_RADEON_QG      0x5147
  88
  89 #define PCI_CHIP_RADEON_QY      0x5159
  90 #define PCI_CHIP_RADEON_QZ      0x515A
  91
  92 #define PCI_CHIP_RN50_515E      0x515E
  93 #define PCI_CHIP_RN50_5969      0x5969
  94
  95 #define PCI_CHIP_RADEON_LW      0x4C57 /* mobility 7 - has tcl */
  96 #define PCI_CHIP_RADEON_LX      0x4C58 /* mobility FireGL 7800 m7 */
  97
  98 #define PCI_CHIP_RADEON_LY      0x4C59
  99 #define PCI_CHIP_RADEON_LZ      0x4C5A
 100
 101 #define PCI_CHIP_RV200_QW       0x5157 /* Radeon 7500 - not an R200 at all */
 102 #define PCI_CHIP_RV200_QX       0x5158
 103
 104 /* IGP Chipsets */
 105 #define PCI_CHIP_RS100_4136     0x4136
 106 #define PCI_CHIP_RS200_4137     0x4137
 107 #define PCI_CHIP_RS250_4237     0x4237
 108 #define PCI_CHIP_RS100_4336     0x4336
 109 #define PCI_CHIP_RS200_4337     0x4337
 110 #define PCI_CHIP_RS250_4437     0x4437
 111 #endif
 112
 113 #ifdef USE_NEW_INTERFACE
 114 static PFNGLXCREATECONTEXTMODES create_context_modes = NULL;
 115 #endif /* USE_NEW_INTERFACE */
 116
 117 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
 118
 119 #ifdef USE_NEW_INTERFACE
 120 static __GLcontextModes *
 121 radeonFillInModes( unsigned pixel_bits, unsigned depth_bits,
 122                  unsigned stencil_bits, GLboolean have_back_buffer )
 123 {
 124     __GLcontextModes * modes;
 125     __GLcontextModes * m;
 126     unsigned num_modes;
 127     unsigned depth_buffer_factor;
 128     unsigned back_buffer_factor;
 129     GLenum fb_format;
 130     GLenum fb_type;
 131
 132     /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
 133      * enough to add support.  Basically, if a context is created with an
 134      * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
 135      * will never be used.
 136      */
 137     static const GLenum back_buffer_modes[] = {
 138         GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
 139     };
 140
 141     u_int8_t depth_bits_array[2];
 142     u_int8_t stencil_bits_array[2];
 143
 144
 145     depth_bits_array[0] = depth_bits;
 146     depth_bits_array[1] = depth_bits;
 147
 148     /* Just like with the accumulation buffer, always provide some modes
 149      * with a stencil buffer.  It will be a sw fallback, but some apps won't
 150      * care about that.
 151      */
 152     stencil_bits_array[0] = 0;
 153     stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
 154
 155     depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
 156     back_buffer_factor  = (have_back_buffer) ? 2 : 1;
 157
 158     num_modes = depth_buffer_factor * back_buffer_factor * 4;
 159
 160     if ( pixel_bits == 16 ) {
 161         fb_format = GL_RGB;
 162         fb_type = GL_UNSIGNED_SHORT_5_6_5;
 163     }
 164     else {
 165         fb_format = GL_BGRA;
 166         fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
 167     }
 168
 169     modes = (*create_context_modes)( num_modes, sizeof( __GLcontextModes ) );
 170     m = modes;
 171     if ( ! driFillInModes( & m, fb_format, fb_type,
 172                            depth_bits_array, stencil_bits_array, depth_buffer_factor,
 173                            back_buffer_modes, back_buffer_factor,
 174                            GLX_TRUE_COLOR ) ) {
 175         fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
 176                  __func__, __LINE__ );
 177         return NULL;
 178     }
 179
 180     if ( ! driFillInModes( & m, fb_format, fb_type,
 181                            depth_bits_array, stencil_bits_array, depth_buffer_factor,
 182                            back_buffer_modes, back_buffer_factor,
 183                            GLX_DIRECT_COLOR ) ) {
 184         fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
 185                  __func__, __LINE__ );
 186         return NULL;
 187     }
 188
 189     /* Mark the visual as slow if there are "fake" stencil bits.
 190      */
 191     for ( m = modes ; m != NULL ; m = m->next ) {
 192         if ( (m->stencilBits != 0) && (m->stencilBits != stencil_bits) ) {
 193             m->visualRating = GLX_SLOW_CONFIG;
 194         }
 195     }
 196
 197     return modes;
 198 }
 199 #endif /* USE_NEW_INTERFACE */
 200
 201 /* Create the device specific screen private data struct.
 202  */
 203 radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv )
 204 {
 205    radeonScreenPtr screen;
 206    RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
 207    unsigned char *RADEONMMIO;
 208
 209
 210    /* Allocate the private area */
 211    screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
 212    if ( !screen ) {
 213       __driUtilMessage("%s: Could not allocate memory for screen structure",
 214                        __FUNCTION__);
 215       return NULL;
 216    }
 217
 218    /* parse information in __driConfigOptions */
 219    driParseOptionInfo (&screen->optionCache,
 220                        __driConfigOptions, __driNConfigOptions);
 221
 222    /* This is first since which regions we map depends on whether or
 223     * not we are using a PCI card.
 224     */
 225    screen->IsPCI = dri_priv->IsPCI;
 226
 227    {
 228       int ret;
 229       drm_radeon_getparam_t gp;
 230
 231       gp.param = RADEON_PARAM_GART_BUFFER_OFFSET;
 232       gp.value = &screen->gart_buffer_offset;
 233
 234       ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
 235                                  &gp, sizeof(gp));
 236       if (ret) {
 237          FREE( screen );
 238          fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
 239          return NULL;
 240       }
 241
 242       if (sPriv->drmMinor >= 6) {
 243          gp.param = RADEON_PARAM_IRQ_NR;
 244          gp.value = &screen->irq;
 245
 246          ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
 247                                     &gp, sizeof(gp));
 248          if (ret) {
 249             FREE( screen );
 250             fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
 251             return NULL;
 252          }
 253       }
 254    }
 255
 256    screen->mmio.handle = dri_priv->registerHandle;
 257    screen->mmio.size   = dri_priv->registerSize;
 258    if ( drmMap( sPriv->fd,
 259                 screen->mmio.handle,
 260                 screen->mmio.size,
 261                 &screen->mmio.map ) ) {
 262       FREE( screen );
 263       __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
 264       return NULL;
 265    }
 266
 267    RADEONMMIO = screen->mmio.map;
 268
 269    screen->status.handle = dri_priv->statusHandle;
 270    screen->status.size   = dri_priv->statusSize;
 271    if ( drmMap( sPriv->fd,
 272                 screen->status.handle,
 273                 screen->status.size,
 274                 &screen->status.map ) ) {
 275       drmUnmap( screen->mmio.map, screen->mmio.size );
 276       FREE( screen );
 277       __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
 278       return NULL;
 279    }
 280    screen->scratch = (__volatile__ u_int32_t *)
 281       ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
 282
 283    screen->buffers = drmMapBufs( sPriv->fd );
 284    if ( !screen->buffers ) {
 285       drmUnmap( screen->status.map, screen->status.size );
 286       drmUnmap( screen->mmio.map, screen->mmio.size );
 287       FREE( screen );
 288       __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
 289       return NULL;
 290    }
 291
 292    if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
 293       screen->gartTextures.handle = dri_priv->gartTexHandle;
 294       screen->gartTextures.size   = dri_priv->gartTexMapSize;
 295       if ( drmMap( sPriv->fd,
 296                    screen->gartTextures.handle,
 297                    screen->gartTextures.size,
 298                    (drmAddressPtr)&screen->gartTextures.map ) ) {
 299          drmUnmapBufs( screen->buffers );
 300          drmUnmap( screen->status.map, screen->status.size );
 301          drmUnmap( screen->mmio.map, screen->mmio.size );
 302          FREE( screen );
 303          __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
 304          return NULL;
 305       }
 306
 307       screen->gart_texture_offset = dri_priv->gartTexOffset + ( screen->IsPCI
 308                 ? INREG( RADEON_AIC_LO_ADDR )
 309                 : ( ( INREG( RADEON_MC_AGP_LOCATION ) & 0x0ffffU ) << 16 ) );
 310    }
 311
 312    screen->chipset = 0;
 313    switch ( dri_priv->deviceID ) {
 314    default:
 315       fprintf(stderr, "unknown chip id, assuming full radeon support\n");
 316    case PCI_CHIP_RADEON_QD:
 317    case PCI_CHIP_RADEON_QE:
 318    case PCI_CHIP_RADEON_QF:
 319    case PCI_CHIP_RADEON_QG:
 320       /* all original radeons (7200) presumably have a stencil op bug */
 321       screen->chipset |= RADEON_CHIPSET_BROKEN_STENCIL;
 322    case PCI_CHIP_RV200_QW:
 323    case PCI_CHIP_RV200_QX:
 324    case PCI_CHIP_RADEON_LW:
 325    case PCI_CHIP_RADEON_LX:
 326       screen->chipset |= RADEON_CHIPSET_TCL;
 327    case PCI_CHIP_RADEON_QY:
 328    case PCI_CHIP_RADEON_QZ:
 329    case PCI_CHIP_RN50_515E:
 330    case PCI_CHIP_RN50_5969:
 331    case PCI_CHIP_RADEON_LY:
 332    case PCI_CHIP_RADEON_LZ:
 333    case PCI_CHIP_RS100_4136: /* IGPs don't have TCL */
 334    case PCI_CHIP_RS200_4137:
 335    case PCI_CHIP_RS250_4237:
 336    case PCI_CHIP_RS100_4336:
 337    case PCI_CHIP_RS200_4337:
 338    case PCI_CHIP_RS250_4437:
 339       break;
 340    }
 341
 342    screen->cpp = dri_priv->bpp / 8;
 343    screen->AGPMode = dri_priv->AGPMode;
 344
 345    screen->fbLocation   = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff ) << 16;
 346
 347    if ( sPriv->drmMinor >= 10 ) {
 348       drm_radeon_setparam_t sp;
 349
 350       sp.param = RADEON_SETPARAM_FB_LOCATION;
 351       sp.value = screen->fbLocation;
 352
 353       drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
 354                        &sp, sizeof( sp ) );
 355    }
 356
 357    screen->frontOffset  = dri_priv->frontOffset;
 358    screen->frontPitch   = dri_priv->frontPitch;
 359    screen->backOffset   = dri_priv->backOffset;
 360    screen->backPitch    = dri_priv->backPitch;
 361    screen->depthOffset  = dri_priv->depthOffset;
 362    screen->depthPitch   = dri_priv->depthPitch;
 363
 364    /* Check if ddx has set up a surface reg to cover depth buffer */
 365    screen->depthHasSurface = ((sPriv->ddxMajor > 4) &&
 366       (screen->chipset & RADEON_CHIPSET_TCL));
 367
 368    screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
 369                                        + screen->fbLocation;
 370    screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
 371    screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
 372       dri_priv->log2TexGran;
 373
 374    if ( !screen->gartTextures.map
 375         || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
 376       screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
 377       screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
 378       screen->texSize[RADEON_GART_TEX_HEAP] = 0;
 379       screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
 380    } else {
 381       screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
 382       screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
 383       screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
 384       screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
 385          dri_priv->log2GARTTexGran;
 386    }
 387
 388    if ( driCompareGLXAPIVersion( 20030813 ) >= 0 ) {
 389       PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension =
 390           (PFNGLXSCRENABLEEXTENSIONPROC) glXGetProcAddress( (const GLubyte *) "__glXScrEnableExtension" );
 391       void * const psc = sPriv->psc->screenConfigs;
 392
 393       if ( glx_enable_extension != NULL ) {
 394          if ( screen->irq != 0 ) {
 395             (*glx_enable_extension)( psc, "GLX_SGI_swap_control" );
 396             (*glx_enable_extension)( psc, "GLX_SGI_video_sync" );
 397             (*glx_enable_extension)( psc, "GLX_MESA_swap_control" );
 398          }
 399
 400          (*glx_enable_extension)( psc, "GLX_MESA_swap_frame_usage" );
 401
 402          if ( driCompareGLXAPIVersion( 20030915 ) >= 0 ) {
 403             (*glx_enable_extension)( psc, "GLX_SGIX_fbconfig" );
 404             (*glx_enable_extension)( psc, "GLX_OML_swap_method" );
 405          }
 406
 407       }
 408    }
 409
 410    screen->driScreen = sPriv;
 411    screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
 412    return screen;
 413 }
 414
 415 /* Destroy the device specific screen private data struct.
 416  */
 417 void radeonDestroyScreen( __DRIscreenPrivate *sPriv )
 418 {
 419    radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
 420
 421    if (!screen)
 422       return;
 423
 424    if ( screen->gartTextures.map ) {
 425       drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
 426    }
 427    drmUnmapBufs( screen->buffers );
 428    drmUnmap( screen->status.map, screen->status.size );
 429    drmUnmap( screen->mmio.map, screen->mmio.size );
 430
 431    /* free all option information */
 432    driDestroyOptionInfo (&screen->optionCache);
 433
 434    FREE( screen );
 435    sPriv->private = NULL;
 436 }
 437
 438
 439 /* Initialize the driver specific screen private data.
 440  */
 441 static GLboolean
 442 radeonInitDriver( __DRIscreenPrivate *sPriv )
 443 {
 444    sPriv->private = (void *) radeonCreateScreen( sPriv );
 445    if ( !sPriv->private ) {
 446       radeonDestroyScreen( sPriv );
 447       return GL_FALSE;
 448    }
 449
 450    return GL_TRUE;
 451 }
 452
 453
 454
 455 /**
 456  * Create and initialize the Mesa and driver specific pixmap buffer
 457  * data.
 458  *
 459  * \todo This function (and its interface) will need to be updated to support
 460  * pbuffers.
 461  */
 462 static GLboolean
 463 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
 464                     __DRIdrawablePrivate *driDrawPriv,
 465                     const __GLcontextModes *mesaVis,
 466                     GLboolean isPixmap )
 467 {
 468    if (isPixmap) {
 469       return GL_FALSE; /* not implemented */
 470    }
 471    else {
 472       const GLboolean swDepth = GL_FALSE;
 473       const GLboolean swAlpha = GL_FALSE;
 474       const GLboolean swAccum = mesaVis->accumRedBits > 0;
 475       const GLboolean swStencil = mesaVis->stencilBits > 0 &&
 476          mesaVis->depthBits != 24;
 477       driDrawPriv->driverPrivate = (void *)
 478          _mesa_create_framebuffer( mesaVis,
 479                                    swDepth,
 480                                    swStencil,
 481                                    swAccum,
 482                                    swAlpha );
 483       return (driDrawPriv->driverPrivate != NULL);
 484    }
 485 }
 486
 487
 488 static void
 489 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
 490 {
 491    _mesa_destroy_framebuffer((GLframebuffer *) (driDrawPriv->driverPrivate));
 492 }
 493
 494 static struct __DriverAPIRec radeonAPI = {
 495    .InitDriver      = radeonInitDriver,
 496    .DestroyScreen   = radeonDestroyScreen,
 497    .CreateContext   = radeonCreateContext,
 498    .DestroyContext  = radeonDestroyContext,
 499    .CreateBuffer    = radeonCreateBuffer,
 500    .DestroyBuffer   = radeonDestroyBuffer,
 501    .SwapBuffers     = radeonSwapBuffers,
 502    .MakeCurrent     = radeonMakeCurrent,
 503    .UnbindContext   = radeonUnbindContext,
 504    .GetSwapInfo     = getSwapInfo,
 505    .GetMSC          = driGetMSC32,
 506    .WaitForMSC      = driWaitForMSC32,
 507    .WaitForSBC      = NULL,
 508    .SwapBuffersMSC  = NULL
 509 };
 510
 511
 512 /*
 513  * This is the bootstrap function for the driver.
 514  * The __driCreateScreen name is the symbol that libGL.so fetches.
 515  * Return:  pointer to a __DRIscreenPrivate.
 516  */
 517 #if !defined(DRI_NEW_INTERFACE_ONLY)
 518 void *__driCreateScreen(Display *dpy, int scrn, __DRIscreen *psc,
 519                         int numConfigs, __GLXvisualConfig *config)
 520 {
 521    __DRIscreenPrivate *psp;
 522    psp = __driUtilCreateScreen(dpy, scrn, psc, numConfigs, config, &radeonAPI);
 523    return (void *) psp;
 524 }
 525 #endif /* !defined(DRI_NEW_INTERFACE_ONLY) */
 526
 527 /**
 528  * This is the bootstrap function for the driver.  libGL supplies all of the
 529  * requisite information about the system, and the driver initializes itself.
 530  * This routine also fills in the linked list pointed to by \c driver_modes
 531  * with the \c __GLcontextModes that the driver can support for windows or
 532  * pbuffers.
 533  *
 534  * \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on
 535  *         failure.
 536  */
 537 #ifdef USE_NEW_INTERFACE
 538 PUBLIC
 539 void * __driCreateNewScreen( __DRInativeDisplay *dpy, int scrn, __DRIscreen *psc,
 540                              const __GLcontextModes * modes,
 541                              const __DRIversion * ddx_version,
 542                              const __DRIversion * dri_version,
 543                              const __DRIversion * drm_version,
 544                              const __DRIframebuffer * frame_buffer,
 545                              drmAddress pSAREA, int fd,
 546                              int internal_api_version,
 547                              __GLcontextModes ** driver_modes )
 548
 549 {
 550    __DRIscreenPrivate *psp;
 551    static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
 552    static const __DRIversion dri_expected = { 4, 0, 0 };
 553    static const __DRIversion drm_expected = { 1, 3, 0 };
 554
 555    if ( ! driCheckDriDdxDrmVersions3( "Radeon",
 556                                       dri_version, & dri_expected,
 557                                       ddx_version, & ddx_expected,
 558                                       drm_version, & drm_expected ) ) {
 559       return NULL;
 560    }
 561
 562    psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
 563                                   ddx_version, dri_version, drm_version,
 564                                   frame_buffer, pSAREA, fd,
 565                                   internal_api_version, &radeonAPI);
 566    if ( psp != NULL ) {
 567       create_context_modes = (PFNGLXCREATECONTEXTMODES)
 568           glXGetProcAddress( (const GLubyte *) "__glXCreateContextModes" );
 569       if ( create_context_modes != NULL ) {
 570          RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
 571          *driver_modes = radeonFillInModes( dri_priv->bpp,
 572                                             (dri_priv->bpp == 16) ? 16 : 24,
 573                                             (dri_priv->bpp == 16) ? 0  : 8,
 574                                             (dri_priv->backOffset != dri_priv->depthOffset) );
 575       }
 576    }
 577
 578    return (void *) psp;
 579 }
 580 #endif /* USE_NEW_INTERFACE */
 581
 582 /**
 583  * Get information about previous buffer swaps.
 584  */
 585 static int
 586 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
 587 {
 588    radeonContextPtr  rmesa;
 589
 590    if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
 591         || (dPriv->driContextPriv->driverPrivate == NULL)
 592         || (sInfo == NULL) ) {
 593       return -1;
 594    }
 595
 596    rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
 597    sInfo->swap_count = rmesa->swap_count;
 598    sInfo->swap_ust = rmesa->swap_ust;
 599    sInfo->swap_missed_count = rmesa->swap_missed_count;
 600
 601    sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
 602        ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
 603        : 0.0;
 604
 605    return 0;
 606 }