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Reinstate vertex format after a rasterization fallback for both r200 and radeon drive...
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c
1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
2 /**************************************************************************
3
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
6
7 All Rights Reserved.
8
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
16
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
20
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28
29 **************************************************************************/
30
31 /**
32 * \file radeon_screen.c
33 * Screen initialization functions for the Radeon driver.
34 *
35 * \author Kevin E. Martin <martin@valinux.com>
36 * \author Gareth Hughes <gareth@valinux.com>
37 */
38
39 #include "glheader.h"
40 #include "imports.h"
41 #include "mtypes.h"
42 #include "framebuffer.h"
43 #include "renderbuffer.h"
44
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #if !RADEON_COMMON
50 #include "radeon_context.h"
51 #include "radeon_span.h"
52 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
53 #include "r200_context.h"
54 #include "r200_ioctl.h"
55 #include "r200_span.h"
56 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
57 #include "r300_context.h"
58 #include "radeon_span.h"
59 #endif
60
61 #include "utils.h"
62 #include "context.h"
63 #include "vblank.h"
64 #include "drirenderbuffer.h"
65
66 #include "GL/internal/dri_interface.h"
67
68 /* Radeon configuration
69 */
70 #include "xmlpool.h"
71
72 #if !RADEON_COMMON /* R100 */
73 PUBLIC const char __driConfigOptions[] =
74 DRI_CONF_BEGIN
75 DRI_CONF_SECTION_PERFORMANCE
76 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
77 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
78 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
79 DRI_CONF_MAX_TEXTURE_UNITS(2,2,3)
80 DRI_CONF_HYPERZ(false)
81 DRI_CONF_SECTION_END
82 DRI_CONF_SECTION_QUALITY
83 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
84 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
85 DRI_CONF_NO_NEG_LOD_BIAS(false)
86 DRI_CONF_FORCE_S3TC_ENABLE(false)
87 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
88 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
89 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
90 DRI_CONF_ALLOW_LARGE_TEXTURES(0)
91 DRI_CONF_SECTION_END
92 DRI_CONF_SECTION_DEBUG
93 DRI_CONF_NO_RAST(false)
94 DRI_CONF_SECTION_END
95 DRI_CONF_END;
96 static const GLuint __driNConfigOptions = 14;
97
98 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
99
100 PUBLIC const char __driConfigOptions[] =
101 DRI_CONF_BEGIN
102 DRI_CONF_SECTION_PERFORMANCE
103 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
104 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
105 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
106 DRI_CONF_MAX_TEXTURE_UNITS(4,2,6)
107 DRI_CONF_HYPERZ(false)
108 DRI_CONF_SECTION_END
109 DRI_CONF_SECTION_QUALITY
110 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
111 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
112 DRI_CONF_NO_NEG_LOD_BIAS(false)
113 DRI_CONF_FORCE_S3TC_ENABLE(false)
114 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
115 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
116 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
117 DRI_CONF_ALLOW_LARGE_TEXTURES(0)
118 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
119 DRI_CONF_SECTION_END
120 DRI_CONF_SECTION_DEBUG
121 DRI_CONF_NO_RAST(false)
122 DRI_CONF_SECTION_END
123 DRI_CONF_SECTION_SOFTWARE
124 DRI_CONF_ARB_VERTEX_PROGRAM(false)
125 DRI_CONF_NV_VERTEX_PROGRAM(false)
126 DRI_CONF_SECTION_END
127 DRI_CONF_END;
128 static const GLuint __driNConfigOptions = 17;
129
130 extern const struct dri_extension blend_extensions[];
131 extern const struct dri_extension ARB_vp_extension[];
132 extern const struct dri_extension NV_vp_extension[];
133 extern const struct dri_extension ATI_fs_extension[];
134
135 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
136
137 /* TODO: integrate these into xmlpool.h! */
138 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
139 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
140 DRI_CONF_DESC(en,"Number of texture image units") \
141 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
142 DRI_CONF_OPT_END
143
144 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
145 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
146 DRI_CONF_DESC(en,"Number of texture coordinate units") \
147 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
148 DRI_CONF_OPT_END
149
150 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
151 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
152 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
153 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
154 DRI_CONF_OPT_END
155
156 const char __driConfigOptions[] =
157 DRI_CONF_BEGIN
158 DRI_CONF_SECTION_PERFORMANCE
159 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
160 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
161 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
162 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(16, 2, 16)
163 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
164 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
165 DRI_CONF_SECTION_END
166 DRI_CONF_SECTION_QUALITY
167 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
168 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
169 DRI_CONF_NO_NEG_LOD_BIAS(false)
170 DRI_CONF_FORCE_S3TC_ENABLE(false)
171 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
172 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
173 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
174 DRI_CONF_SECTION_END
175 DRI_CONF_SECTION_DEBUG
176 DRI_CONF_NO_RAST(false)
177 DRI_CONF_SECTION_END
178 DRI_CONF_END;
179 static const GLuint __driNConfigOptions = 14;
180
181 #ifndef RADEON_DEBUG
182 int RADEON_DEBUG = 0;
183
184 static const struct dri_debug_control debug_control[] = {
185 {"fall", DEBUG_FALLBACKS},
186 {"tex", DEBUG_TEXTURE},
187 {"ioctl", DEBUG_IOCTL},
188 {"prim", DEBUG_PRIMS},
189 {"vert", DEBUG_VERTS},
190 {"state", DEBUG_STATE},
191 {"code", DEBUG_CODEGEN},
192 {"vfmt", DEBUG_VFMT},
193 {"vtxf", DEBUG_VFMT},
194 {"verb", DEBUG_VERBOSE},
195 {"dri", DEBUG_DRI},
196 {"dma", DEBUG_DMA},
197 {"san", DEBUG_SANITY},
198 {"sync", DEBUG_SYNC},
199 {"pix", DEBUG_PIXEL},
200 {"mem", DEBUG_MEMORY},
201 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
202 {NULL, 0}
203 };
204 #endif /* RADEON_DEBUG */
205
206 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
207
208 extern const struct dri_extension card_extensions[];
209
210 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
211
212 static __GLcontextModes *
213 radeonFillInModes( unsigned pixel_bits, unsigned depth_bits,
214 unsigned stencil_bits, GLboolean have_back_buffer )
215 {
216 __GLcontextModes * modes;
217 __GLcontextModes * m;
218 unsigned num_modes;
219 unsigned depth_buffer_factor;
220 unsigned back_buffer_factor;
221 GLenum fb_format;
222 GLenum fb_type;
223
224 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
225 * enough to add support. Basically, if a context is created with an
226 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
227 * will never be used.
228 */
229 static const GLenum back_buffer_modes[] = {
230 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
231 };
232
233 u_int8_t depth_bits_array[2];
234 u_int8_t stencil_bits_array[2];
235
236
237 depth_bits_array[0] = depth_bits;
238 depth_bits_array[1] = depth_bits;
239
240 /* Just like with the accumulation buffer, always provide some modes
241 * with a stencil buffer. It will be a sw fallback, but some apps won't
242 * care about that.
243 */
244 stencil_bits_array[0] = 0;
245 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
246
247 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
248 back_buffer_factor = (have_back_buffer) ? 2 : 1;
249
250 num_modes = depth_buffer_factor * back_buffer_factor * 4;
251
252 if ( pixel_bits == 16 ) {
253 fb_format = GL_RGB;
254 fb_type = GL_UNSIGNED_SHORT_5_6_5;
255 }
256 else {
257 fb_format = GL_BGRA;
258 fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
259 }
260
261 modes = (*dri_interface->createContextModes)( num_modes, sizeof( __GLcontextModes ) );
262 m = modes;
263 if ( ! driFillInModes( & m, fb_format, fb_type,
264 depth_bits_array, stencil_bits_array, depth_buffer_factor,
265 back_buffer_modes, back_buffer_factor,
266 GLX_TRUE_COLOR ) ) {
267 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
268 __func__, __LINE__ );
269 return NULL;
270 }
271
272 if ( ! driFillInModes( & m, fb_format, fb_type,
273 depth_bits_array, stencil_bits_array, depth_buffer_factor,
274 back_buffer_modes, back_buffer_factor,
275 GLX_DIRECT_COLOR ) ) {
276 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
277 __func__, __LINE__ );
278 return NULL;
279 }
280
281 /* Mark the visual as slow if there are "fake" stencil bits.
282 */
283 for ( m = modes ; m != NULL ; m = m->next ) {
284 if ( (m->stencilBits != 0) && (m->stencilBits != stencil_bits) ) {
285 m->visualRating = GLX_SLOW_CONFIG;
286 }
287 }
288
289 return modes;
290 }
291
292
293 /* Create the device specific screen private data struct.
294 */
295 static radeonScreenPtr
296 radeonCreateScreen( __DRIscreenPrivate *sPriv )
297 {
298 radeonScreenPtr screen;
299 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
300 unsigned char *RADEONMMIO;
301 PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension =
302 (PFNGLXSCRENABLEEXTENSIONPROC) (*dri_interface->getProcAddress("glxEnableExtension"));
303 void * const psc = sPriv->psc->screenConfigs;
304
305 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
306 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
307 return GL_FALSE;
308 }
309
310 /* Allocate the private area */
311 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
312 if ( !screen ) {
313 __driUtilMessage("%s: Could not allocate memory for screen structure",
314 __FUNCTION__);
315 return NULL;
316 }
317
318 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
319 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
320 #endif
321
322 /* parse information in __driConfigOptions */
323 driParseOptionInfo (&screen->optionCache,
324 __driConfigOptions, __driNConfigOptions);
325
326 /* This is first since which regions we map depends on whether or
327 * not we are using a PCI card.
328 */
329 screen->IsPCI = dri_priv->IsPCI;
330
331 {
332 int ret;
333 drm_radeon_getparam_t gp;
334
335 gp.param = RADEON_PARAM_GART_BUFFER_OFFSET;
336 gp.value = &screen->gart_buffer_offset;
337
338 ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
339 &gp, sizeof(gp));
340 if (ret) {
341 FREE( screen );
342 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
343 return NULL;
344 }
345
346 if (sPriv->drmMinor >= 6) {
347 gp.param = RADEON_PARAM_GART_BASE;
348 gp.value = &screen->gart_base;
349
350 ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
351 &gp, sizeof(gp));
352 if (ret) {
353 FREE( screen );
354 fprintf(stderr, "drmR200GetParam (RADEON_PARAM_GART_BASE): %d\n", ret);
355 return NULL;
356 }
357
358 gp.param = RADEON_PARAM_IRQ_NR;
359 gp.value = &screen->irq;
360
361 ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
362 &gp, sizeof(gp));
363 if (ret) {
364 FREE( screen );
365 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
366 return NULL;
367 }
368 screen->drmSupportsCubeMapsR200 = (sPriv->drmMinor >= 7);
369 screen->drmSupportsBlendColor = (sPriv->drmMinor >= 11);
370 screen->drmSupportsTriPerf = (sPriv->drmMinor >= 16);
371 screen->drmSupportsFragShader = (sPriv->drmMinor >= 18);
372 screen->drmSupportsPointSprites = (sPriv->drmMinor >= 13);
373 screen->drmSupportsCubeMapsR100 = (sPriv->drmMinor >= 15);
374 }
375 }
376
377 screen->mmio.handle = dri_priv->registerHandle;
378 screen->mmio.size = dri_priv->registerSize;
379 if ( drmMap( sPriv->fd,
380 screen->mmio.handle,
381 screen->mmio.size,
382 &screen->mmio.map ) ) {
383 FREE( screen );
384 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
385 return NULL;
386 }
387
388 RADEONMMIO = screen->mmio.map;
389
390 screen->status.handle = dri_priv->statusHandle;
391 screen->status.size = dri_priv->statusSize;
392 if ( drmMap( sPriv->fd,
393 screen->status.handle,
394 screen->status.size,
395 &screen->status.map ) ) {
396 drmUnmap( screen->mmio.map, screen->mmio.size );
397 FREE( screen );
398 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
399 return NULL;
400 }
401 screen->scratch = (__volatile__ u_int32_t *)
402 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
403
404 screen->buffers = drmMapBufs( sPriv->fd );
405 if ( !screen->buffers ) {
406 drmUnmap( screen->status.map, screen->status.size );
407 drmUnmap( screen->mmio.map, screen->mmio.size );
408 FREE( screen );
409 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
410 return NULL;
411 }
412
413 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
414 screen->gartTextures.handle = dri_priv->gartTexHandle;
415 screen->gartTextures.size = dri_priv->gartTexMapSize;
416 if ( drmMap( sPriv->fd,
417 screen->gartTextures.handle,
418 screen->gartTextures.size,
419 (drmAddressPtr)&screen->gartTextures.map ) ) {
420 drmUnmapBufs( screen->buffers );
421 drmUnmap( screen->status.map, screen->status.size );
422 drmUnmap( screen->mmio.map, screen->mmio.size );
423 FREE( screen );
424 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
425 return NULL;
426 }
427
428 screen->gart_texture_offset = dri_priv->gartTexOffset + ( screen->IsPCI
429 ? INREG( RADEON_AIC_LO_ADDR )
430 : ( ( INREG( RADEON_MC_AGP_LOCATION ) & 0x0ffffU ) << 16 ) );
431 }
432
433 screen->chip_flags = 0;
434 /* XXX: add more chipsets */
435 switch ( dri_priv->deviceID ) {
436 case PCI_CHIP_RADEON_LY:
437 case PCI_CHIP_RADEON_LZ:
438 case PCI_CHIP_RADEON_QY:
439 case PCI_CHIP_RADEON_QZ:
440 case PCI_CHIP_RN50_515E:
441 case PCI_CHIP_RN50_5969:
442 screen->chip_family = CHIP_FAMILY_RV100;
443 break;
444
445 case PCI_CHIP_RS100_4136:
446 case PCI_CHIP_RS100_4336:
447 screen->chip_family = CHIP_FAMILY_RS100;
448 break;
449
450 case PCI_CHIP_RS200_4137:
451 case PCI_CHIP_RS200_4337:
452 case PCI_CHIP_RS250_4237:
453 case PCI_CHIP_RS250_4437:
454 screen->chip_family = CHIP_FAMILY_RS200;
455 break;
456
457 case PCI_CHIP_RADEON_QD:
458 case PCI_CHIP_RADEON_QE:
459 case PCI_CHIP_RADEON_QF:
460 case PCI_CHIP_RADEON_QG:
461 /* all original radeons (7200) presumably have a stencil op bug */
462 screen->chip_family = CHIP_FAMILY_R100;
463 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
464 break;
465
466 case PCI_CHIP_RV200_QW:
467 case PCI_CHIP_RV200_QX:
468 case PCI_CHIP_RADEON_LW:
469 case PCI_CHIP_RADEON_LX:
470 screen->chip_family = CHIP_FAMILY_RV200;
471 screen->chip_flags = RADEON_CHIPSET_TCL;
472 break;
473
474 case PCI_CHIP_R200_BB:
475 case PCI_CHIP_R200_BC:
476 case PCI_CHIP_R200_QH:
477 case PCI_CHIP_R200_QI:
478 case PCI_CHIP_R200_QJ:
479 case PCI_CHIP_R200_QK:
480 case PCI_CHIP_R200_QL:
481 case PCI_CHIP_R200_QM:
482 case PCI_CHIP_R200_QN:
483 case PCI_CHIP_R200_QO:
484 screen->chip_family = CHIP_FAMILY_R200;
485 screen->chip_flags = RADEON_CHIPSET_TCL;
486 break;
487
488 case PCI_CHIP_RV250_Id:
489 case PCI_CHIP_RV250_Ie:
490 case PCI_CHIP_RV250_If:
491 case PCI_CHIP_RV250_Ig:
492 case PCI_CHIP_RV250_Ld:
493 case PCI_CHIP_RV250_Le:
494 case PCI_CHIP_RV250_Lf:
495 case PCI_CHIP_RV250_Lg:
496 screen->chip_family = CHIP_FAMILY_RV250;
497 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
498 break;
499
500 case PCI_CHIP_RV280_5960:
501 case PCI_CHIP_RV280_5961:
502 case PCI_CHIP_RV280_5962:
503 case PCI_CHIP_RV280_5964:
504 case PCI_CHIP_RV280_5965:
505 case PCI_CHIP_RV280_5C61:
506 case PCI_CHIP_RV280_5C63:
507 screen->chip_family = CHIP_FAMILY_RV280;
508 screen->chip_flags = RADEON_CHIPSET_TCL;
509 break;
510
511 case PCI_CHIP_RS300_5834:
512 case PCI_CHIP_RS300_5835:
513 case PCI_CHIP_RS300_5836:
514 case PCI_CHIP_RS300_5837:
515 screen->chip_family = CHIP_FAMILY_RS300;
516 break;
517
518 case PCI_CHIP_R300_AD:
519 case PCI_CHIP_R300_AE:
520 case PCI_CHIP_R300_AF:
521 case PCI_CHIP_R300_AG:
522 case PCI_CHIP_R300_ND:
523 case PCI_CHIP_R300_NE:
524 case PCI_CHIP_R300_NF:
525 case PCI_CHIP_R300_NG:
526 screen->chip_family = CHIP_FAMILY_R300;
527 screen->chip_flags = RADEON_CHIPSET_TCL;
528 break;
529
530 case PCI_CHIP_RV350_AP:
531 case PCI_CHIP_RV350_AQ:
532 case PCI_CHIP_RV350_AR:
533 case PCI_CHIP_RV350_AS:
534 case PCI_CHIP_RV350_AT:
535 case PCI_CHIP_RV350_AV:
536 case PCI_CHIP_RV350_AU:
537 case PCI_CHIP_RV350_NP:
538 case PCI_CHIP_RV350_NQ:
539 case PCI_CHIP_RV350_NR:
540 case PCI_CHIP_RV350_NS:
541 case PCI_CHIP_RV350_NT:
542 case PCI_CHIP_RV350_NV:
543 screen->chip_family = CHIP_FAMILY_RV350;
544 screen->chip_flags = RADEON_CHIPSET_TCL;
545 break;
546
547 case PCI_CHIP_R350_AH:
548 case PCI_CHIP_R350_AI:
549 case PCI_CHIP_R350_AJ:
550 case PCI_CHIP_R350_AK:
551 case PCI_CHIP_R350_NH:
552 case PCI_CHIP_R350_NI:
553 case PCI_CHIP_R360_NJ:
554 case PCI_CHIP_R350_NK:
555 screen->chip_family = CHIP_FAMILY_R350;
556 screen->chip_flags = RADEON_CHIPSET_TCL;
557 break;
558
559 case PCI_CHIP_RV370_5460:
560 case PCI_CHIP_RV370_5464:
561 case PCI_CHIP_RV370_5B60:
562 case PCI_CHIP_RV370_5B62:
563 case PCI_CHIP_RV370_5B64:
564 case PCI_CHIP_RV370_5B65:
565 screen->chip_family = CHIP_FAMILY_RV380;
566 screen->chip_flags = RADEON_CHIPSET_TCL;
567 break;
568
569 case PCI_CHIP_R420_JN:
570 case PCI_CHIP_R420_JH:
571 case PCI_CHIP_R420_JI:
572 case PCI_CHIP_R420_JJ:
573 case PCI_CHIP_R420_JK:
574 case PCI_CHIP_R420_JL:
575 case PCI_CHIP_R420_JM:
576 case PCI_CHIP_R420_JO:
577 case PCI_CHIP_R420_JP:
578 case PCI_CHIP_RV410_5E4B:
579 screen->chip_family = CHIP_FAMILY_R420;
580 screen->chip_flags = RADEON_CHIPSET_TCL;
581 break;
582
583 default:
584 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
585 dri_priv->deviceID);
586 return NULL;
587 }
588
589 if (screen->chip_family <= CHIP_FAMILY_RS200)
590 screen->chip_flags |= RADEON_CLASS_R100;
591 else if (screen->chip_family <= CHIP_FAMILY_RV280)
592 screen->chip_flags |= RADEON_CLASS_R200;
593 else
594 screen->chip_flags |= RADEON_CLASS_R300;
595
596 screen->cpp = dri_priv->bpp / 8;
597 screen->AGPMode = dri_priv->AGPMode;
598
599 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff ) << 16;
600
601 if ( sPriv->drmMinor >= 10 ) {
602 drm_radeon_setparam_t sp;
603
604 sp.param = RADEON_SETPARAM_FB_LOCATION;
605 sp.value = screen->fbLocation;
606
607 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
608 &sp, sizeof( sp ) );
609 }
610
611 screen->frontOffset = dri_priv->frontOffset;
612 screen->frontPitch = dri_priv->frontPitch;
613 screen->backOffset = dri_priv->backOffset;
614 screen->backPitch = dri_priv->backPitch;
615 screen->depthOffset = dri_priv->depthOffset;
616 screen->depthPitch = dri_priv->depthPitch;
617
618 /* Check if ddx has set up a surface reg to cover depth buffer */
619 screen->depthHasSurface = ((sPriv->ddxMajor > 4) &&
620 (screen->chip_flags & RADEON_CHIPSET_TCL));
621
622 if ( dri_priv->textureSize == 0 ) {
623 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
624 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
625 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
626 dri_priv->log2GARTTexGran;
627 } else {
628 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
629 + screen->fbLocation;
630 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
631 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
632 dri_priv->log2TexGran;
633 }
634
635 if ( !screen->gartTextures.map || dri_priv->textureSize == 0
636 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
637 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
638 screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
639 screen->texSize[RADEON_GART_TEX_HEAP] = 0;
640 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
641 } else {
642 screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
643 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
644 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
645 screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
646 dri_priv->log2GARTTexGran;
647 }
648
649 if ( glx_enable_extension != NULL ) {
650 if ( screen->irq != 0 ) {
651 (*glx_enable_extension)( psc, "GLX_SGI_swap_control" );
652 (*glx_enable_extension)( psc, "GLX_SGI_video_sync" );
653 (*glx_enable_extension)( psc, "GLX_MESA_swap_control" );
654 }
655
656 (*glx_enable_extension)( psc, "GLX_MESA_swap_frame_usage" );
657 if (IS_R200_CLASS(screen))
658 (*glx_enable_extension)( psc, "GLX_MESA_allocate_memory" );
659 }
660
661 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
662 if (IS_R200_CLASS(screen)) {
663 sPriv->psc->allocateMemory = (void *) r200AllocateMemoryMESA;
664 sPriv->psc->freeMemory = (void *) r200FreeMemoryMESA;
665 sPriv->psc->memoryOffset = (void *) r200GetMemoryOffsetMESA;
666 }
667 #endif
668
669 screen->driScreen = sPriv;
670 screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
671 return screen;
672 }
673
674 /* Destroy the device specific screen private data struct.
675 */
676 static void
677 radeonDestroyScreen( __DRIscreenPrivate *sPriv )
678 {
679 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
680
681 if (!screen)
682 return;
683
684 if ( screen->gartTextures.map ) {
685 drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
686 }
687 drmUnmapBufs( screen->buffers );
688 drmUnmap( screen->status.map, screen->status.size );
689 drmUnmap( screen->mmio.map, screen->mmio.size );
690
691 /* free all option information */
692 driDestroyOptionInfo (&screen->optionCache);
693
694 FREE( screen );
695 sPriv->private = NULL;
696 }
697
698
699 /* Initialize the driver specific screen private data.
700 */
701 static GLboolean
702 radeonInitDriver( __DRIscreenPrivate *sPriv )
703 {
704 sPriv->private = (void *) radeonCreateScreen( sPriv );
705 if ( !sPriv->private ) {
706 radeonDestroyScreen( sPriv );
707 return GL_FALSE;
708 }
709
710 return GL_TRUE;
711 }
712
713
714 /**
715 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
716 *
717 * \todo This function (and its interface) will need to be updated to support
718 * pbuffers.
719 */
720 static GLboolean
721 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
722 __DRIdrawablePrivate *driDrawPriv,
723 const __GLcontextModes *mesaVis,
724 GLboolean isPixmap )
725 {
726 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
727
728 if (isPixmap) {
729 return GL_FALSE; /* not implemented */
730 }
731 else {
732 const GLboolean swDepth = GL_FALSE;
733 const GLboolean swAlpha = GL_FALSE;
734 const GLboolean swAccum = mesaVis->accumRedBits > 0;
735 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
736 mesaVis->depthBits != 24;
737 struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
738
739 /* front color renderbuffer */
740 {
741 driRenderbuffer *frontRb
742 = driNewRenderbuffer(GL_RGBA,
743 driScrnPriv->pFB + screen->frontOffset,
744 screen->cpp,
745 screen->frontOffset, screen->frontPitch,
746 driDrawPriv);
747 radeonSetSpanFunctions(frontRb, mesaVis);
748 _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
749 }
750
751 /* back color renderbuffer */
752 if (mesaVis->doubleBufferMode) {
753 driRenderbuffer *backRb
754 = driNewRenderbuffer(GL_RGBA,
755 driScrnPriv->pFB + screen->backOffset,
756 screen->cpp,
757 screen->backOffset, screen->backPitch,
758 driDrawPriv);
759 radeonSetSpanFunctions(backRb, mesaVis);
760 _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
761 }
762
763 /* depth renderbuffer */
764 if (mesaVis->depthBits == 16) {
765 driRenderbuffer *depthRb
766 = driNewRenderbuffer(GL_DEPTH_COMPONENT16,
767 driScrnPriv->pFB + screen->depthOffset,
768 screen->cpp,
769 screen->depthOffset, screen->depthPitch,
770 driDrawPriv);
771 radeonSetSpanFunctions(depthRb, mesaVis);
772 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
773 depthRb->depthHasSurface = screen->depthHasSurface;
774 }
775 else if (mesaVis->depthBits == 24) {
776 driRenderbuffer *depthRb
777 = driNewRenderbuffer(GL_DEPTH_COMPONENT24,
778 driScrnPriv->pFB + screen->depthOffset,
779 screen->cpp,
780 screen->depthOffset, screen->depthPitch,
781 driDrawPriv);
782 radeonSetSpanFunctions(depthRb, mesaVis);
783 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
784 depthRb->depthHasSurface = screen->depthHasSurface;
785 }
786
787 /* stencil renderbuffer */
788 if (mesaVis->stencilBits > 0 && !swStencil) {
789 driRenderbuffer *stencilRb
790 = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT,
791 driScrnPriv->pFB + screen->depthOffset,
792 screen->cpp,
793 screen->depthOffset, screen->depthPitch,
794 driDrawPriv);
795 radeonSetSpanFunctions(stencilRb, mesaVis);
796 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
797 stencilRb->depthHasSurface = screen->depthHasSurface;
798 }
799
800 _mesa_add_soft_renderbuffers(fb,
801 GL_FALSE, /* color */
802 swDepth,
803 swStencil,
804 swAccum,
805 swAlpha,
806 GL_FALSE /* aux */);
807 driDrawPriv->driverPrivate = (void *) fb;
808
809 return (driDrawPriv->driverPrivate != NULL);
810 }
811 }
812
813
814 static void
815 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
816 {
817 _mesa_destroy_framebuffer((GLframebuffer *) (driDrawPriv->driverPrivate));
818 }
819
820 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
821 /**
822 * Choose the appropriate CreateContext function based on the chipset.
823 * Eventually, all drivers will go through this process.
824 */
825 static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
826 __DRIcontextPrivate * driContextPriv,
827 void *sharedContextPriv)
828 {
829 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
830 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
831
832 if (IS_R300_CLASS(screen))
833 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
834 return GL_FALSE;
835 }
836
837 /**
838 * Choose the appropriate DestroyContext function based on the chipset.
839 */
840 static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
841 {
842 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
843
844 if (IS_R300_CLASS(radeon->radeonScreen))
845 return r300DestroyContext(driContextPriv);
846 }
847
848
849 #endif
850
851 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
852 static struct __DriverAPIRec radeonAPI = {
853 .InitDriver = radeonInitDriver,
854 .DestroyScreen = radeonDestroyScreen,
855 .CreateContext = radeonCreateContext,
856 .DestroyContext = radeonDestroyContext,
857 .CreateBuffer = radeonCreateBuffer,
858 .DestroyBuffer = radeonDestroyBuffer,
859 .SwapBuffers = radeonSwapBuffers,
860 .MakeCurrent = radeonMakeCurrent,
861 .UnbindContext = radeonUnbindContext,
862 .GetSwapInfo = getSwapInfo,
863 .GetMSC = driGetMSC32,
864 .WaitForMSC = driWaitForMSC32,
865 .WaitForSBC = NULL,
866 .SwapBuffersMSC = NULL
867 };
868 #else
869 static const struct __DriverAPIRec r200API = {
870 .InitDriver = radeonInitDriver,
871 .DestroyScreen = radeonDestroyScreen,
872 .CreateContext = r200CreateContext,
873 .DestroyContext = r200DestroyContext,
874 .CreateBuffer = radeonCreateBuffer,
875 .DestroyBuffer = radeonDestroyBuffer,
876 .SwapBuffers = r200SwapBuffers,
877 .MakeCurrent = r200MakeCurrent,
878 .UnbindContext = r200UnbindContext,
879 .GetSwapInfo = getSwapInfo,
880 .GetMSC = driGetMSC32,
881 .WaitForMSC = driWaitForMSC32,
882 .WaitForSBC = NULL,
883 .SwapBuffersMSC = NULL
884 };
885 #endif
886
887 /**
888 * This is the bootstrap function for the driver. libGL supplies all of the
889 * requisite information about the system, and the driver initializes itself.
890 * This routine also fills in the linked list pointed to by \c driver_modes
891 * with the \c __GLcontextModes that the driver can support for windows or
892 * pbuffers.
893 *
894 * \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on
895 * failure.
896 */
897 PUBLIC void *
898 __driCreateNewScreen_20050727( __DRInativeDisplay *dpy,
899 int scrn, __DRIscreen *psc,
900 const __GLcontextModes * modes,
901 const __DRIversion * ddx_version,
902 const __DRIversion * dri_version,
903 const __DRIversion * drm_version,
904 const __DRIframebuffer * frame_buffer,
905 drmAddress pSAREA, int fd,
906 int internal_api_version,
907 const __DRIinterfaceMethods * interface,
908 __GLcontextModes ** driver_modes )
909 {
910 __DRIscreenPrivate *psp;
911 #if !RADEON_COMMON
912 static const char *driver_name = "Radeon";
913 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
914 static const __DRIversion dri_expected = { 4, 0, 0 };
915 static const __DRIversion drm_expected = { 1, 3, 0 };
916 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
917 static const char *driver_name = "R200";
918 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
919 static const __DRIversion dri_expected = { 4, 0, 0 };
920 static const __DRIversion drm_expected = { 1, 5, 0 };
921 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
922 static const char *driver_name = "R300";
923 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
924 static const __DRIversion dri_expected = { 4, 0, 0 };
925 static const __DRIversion drm_expected = { 1, 22, 0 };
926 #endif
927
928 dri_interface = interface;
929
930 if ( ! driCheckDriDdxDrmVersions3( driver_name,
931 dri_version, & dri_expected,
932 ddx_version, & ddx_expected,
933 drm_version, & drm_expected ) ) {
934 return NULL;
935 }
936 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
937 psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
938 ddx_version, dri_version, drm_version,
939 frame_buffer, pSAREA, fd,
940 internal_api_version, &radeonAPI);
941 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
942 psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
943 ddx_version, dri_version, drm_version,
944 frame_buffer, pSAREA, fd,
945 internal_api_version, &r200API);
946 #endif
947
948 if ( psp != NULL ) {
949 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
950 if (driver_modes) {
951 *driver_modes = radeonFillInModes( dri_priv->bpp,
952 (dri_priv->bpp == 16) ? 16 : 24,
953 (dri_priv->bpp == 16) ? 0 : 8,
954 (dri_priv->backOffset != dri_priv->depthOffset) );
955 }
956
957 /* Calling driInitExtensions here, with a NULL context pointer,
958 * does not actually enable the extensions. It just makes sure
959 * that all the dispatch offsets for all the extensions that
960 * *might* be enables are known. This is needed because the
961 * dispatch offsets need to be known when _mesa_context_create
962 * is called, but we can't enable the extensions until we have a
963 * context pointer.
964 *
965 * Hello chicken. Hello egg. How are you two today?
966 */
967 driInitExtensions( NULL, card_extensions, GL_FALSE );
968 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
969 driInitExtensions( NULL, blend_extensions, GL_FALSE );
970 driInitSingleExtension( NULL, ARB_vp_extension );
971 driInitSingleExtension( NULL, NV_vp_extension );
972 driInitSingleExtension( NULL, ATI_fs_extension );
973 #endif
974 }
975
976 return (void *) psp;
977 }
978
979
980 /**
981 * Get information about previous buffer swaps.
982 */
983 static int
984 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
985 {
986 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
987 radeonContextPtr rmesa;
988 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
989 r200ContextPtr rmesa;
990 #endif
991
992 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
993 || (dPriv->driContextPriv->driverPrivate == NULL)
994 || (sInfo == NULL) ) {
995 return -1;
996 }
997
998 rmesa = dPriv->driContextPriv->driverPrivate;
999 sInfo->swap_count = rmesa->swap_count;
1000 sInfo->swap_ust = rmesa->swap_ust;
1001 sInfo->swap_missed_count = rmesa->swap_missed_count;
1002
1003 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1004 ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
1005 : 0.0;
1006
1007 return 0;
1008 }