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radeon: emit scissor when using cs path
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
36 */
37
38 #include <errno.h>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
44
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #include "radeon_common.h"
50 #include "radeon_span.h"
51 #if !RADEON_COMMON
52 #include "radeon_context.h"
53 #include "radeon_tex.h"
54 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
55 #include "r200_context.h"
56 #include "r200_ioctl.h"
57 #include "r200_tex.h"
58 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
59 #include "r300_context.h"
60 #include "r300_fragprog.h"
61 #include "r300_tex.h"
62 #endif
63
64 #include "utils.h"
65 #include "vblank.h"
66 #include "drirenderbuffer.h"
67
68 #include "radeon_bocs_wrapper.h"
69
70 #include "GL/internal/dri_interface.h"
71
72 /* Radeon configuration
73 */
74 #include "xmlpool.h"
75
76 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
77 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
78 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
79 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
80 DRI_CONF_OPT_END
81
82 #if !RADEON_COMMON /* R100 */
83 PUBLIC const char __driConfigOptions[] =
84 DRI_CONF_BEGIN
85 DRI_CONF_SECTION_PERFORMANCE
86 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
87 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
88 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
89 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
90 DRI_CONF_HYPERZ(false)
91 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
92 DRI_CONF_SECTION_END
93 DRI_CONF_SECTION_QUALITY
94 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
95 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
96 DRI_CONF_NO_NEG_LOD_BIAS(false)
97 DRI_CONF_FORCE_S3TC_ENABLE(false)
98 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
99 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
100 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
101 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
102 DRI_CONF_SECTION_END
103 DRI_CONF_SECTION_DEBUG
104 DRI_CONF_NO_RAST(false)
105 DRI_CONF_SECTION_END
106 DRI_CONF_END;
107 static const GLuint __driNConfigOptions = 15;
108
109 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
110
111 PUBLIC const char __driConfigOptions[] =
112 DRI_CONF_BEGIN
113 DRI_CONF_SECTION_PERFORMANCE
114 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
115 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
116 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
117 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
118 DRI_CONF_HYPERZ(false)
119 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
120 DRI_CONF_SECTION_END
121 DRI_CONF_SECTION_QUALITY
122 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
123 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
124 DRI_CONF_NO_NEG_LOD_BIAS(false)
125 DRI_CONF_FORCE_S3TC_ENABLE(false)
126 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
127 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
128 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
129 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
130 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
131 DRI_CONF_SECTION_END
132 DRI_CONF_SECTION_DEBUG
133 DRI_CONF_NO_RAST(false)
134 DRI_CONF_SECTION_END
135 DRI_CONF_SECTION_SOFTWARE
136 DRI_CONF_NV_VERTEX_PROGRAM(false)
137 DRI_CONF_SECTION_END
138 DRI_CONF_END;
139 static const GLuint __driNConfigOptions = 17;
140
141 extern const struct dri_extension blend_extensions[];
142 extern const struct dri_extension ARB_vp_extension[];
143 extern const struct dri_extension NV_vp_extension[];
144 extern const struct dri_extension ATI_fs_extension[];
145 extern const struct dri_extension point_extensions[];
146
147 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
148
149 /* TODO: integrate these into xmlpool.h! */
150 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
151 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
152 DRI_CONF_DESC(en,"Number of texture image units") \
153 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
154 DRI_CONF_OPT_END
155
156 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
157 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
158 DRI_CONF_DESC(en,"Number of texture coordinate units") \
159 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
160 DRI_CONF_OPT_END
161
162
163
164 #define DRI_CONF_DISABLE_S3TC(def) \
165 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
166 DRI_CONF_DESC(en,"Disable S3TC compression") \
167 DRI_CONF_OPT_END
168
169 #define DRI_CONF_DISABLE_FALLBACK(def) \
170 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
171 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
172 DRI_CONF_OPT_END
173
174 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
175 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
176 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
177 DRI_CONF_OPT_END
178
179 #define DRI_CONF_FP_OPTIMIZATION(def) \
180 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
181 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
182 DRI_CONF_ENUM(0,"Optimize for Speed") \
183 DRI_CONF_ENUM(1,"Optimize for Quality") \
184 DRI_CONF_DESC_END \
185 DRI_CONF_OPT_END
186
187 PUBLIC const char __driConfigOptions[] =
188 DRI_CONF_BEGIN
189 DRI_CONF_SECTION_PERFORMANCE
190 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
191 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
192 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
193 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
194 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
195 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
196 DRI_CONF_DISABLE_FALLBACK(true)
197 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
198 DRI_CONF_SECTION_END
199 DRI_CONF_SECTION_QUALITY
200 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
201 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
202 DRI_CONF_FORCE_S3TC_ENABLE(false)
203 DRI_CONF_DISABLE_S3TC(false)
204 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
205 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
206 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
207 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
208 DRI_CONF_SECTION_END
209 DRI_CONF_SECTION_DEBUG
210 DRI_CONF_NO_RAST(false)
211 DRI_CONF_SECTION_END
212 DRI_CONF_END;
213 static const GLuint __driNConfigOptions = 17;
214
215 extern const struct dri_extension gl_20_extension[];
216
217 #ifndef RADEON_DEBUG
218
219 static const struct dri_debug_control debug_control[] = {
220 {"fall", DEBUG_FALLBACKS},
221 {"tex", DEBUG_TEXTURE},
222 {"ioctl", DEBUG_IOCTL},
223 {"prim", DEBUG_PRIMS},
224 {"vert", DEBUG_VERTS},
225 {"state", DEBUG_STATE},
226 {"code", DEBUG_CODEGEN},
227 {"vfmt", DEBUG_VFMT},
228 {"vtxf", DEBUG_VFMT},
229 {"verb", DEBUG_VERBOSE},
230 {"dri", DEBUG_DRI},
231 {"dma", DEBUG_DMA},
232 {"san", DEBUG_SANITY},
233 {"sync", DEBUG_SYNC},
234 {"pix", DEBUG_PIXEL},
235 {"mem", DEBUG_MEMORY},
236 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
237 {NULL, 0}
238 };
239 #endif /* RADEON_DEBUG */
240
241 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
242
243 extern const struct dri_extension card_extensions[];
244 extern const struct dri_extension mm_extensions[];
245
246 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
247
248 static int
249 radeonGetParam(__DRIscreenPrivate *sPriv, int param, void *value)
250 {
251 int ret;
252 drm_radeon_getparam_t gp;
253 struct drm_radeon_info info;
254
255 if (sPriv->drm_version.major >= 2) {
256 info.value = (uint64_t)value;
257 switch (param) {
258 case RADEON_PARAM_DEVICE_ID:
259 info.request = RADEON_INFO_DEVICE_ID;
260 break;
261 case RADEON_PARAM_NUM_GB_PIPES:
262 info.request = RADEON_INFO_NUM_GB_PIPES;
263 break;
264 default:
265 return -EINVAL;
266 }
267 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info));
268 } else {
269 gp.param = param;
270 gp.value = value;
271
272 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
273 }
274 return ret;
275 }
276
277 static const __DRIconfig **
278 radeonFillInModes( __DRIscreenPrivate *psp,
279 unsigned pixel_bits, unsigned depth_bits,
280 unsigned stencil_bits, GLboolean have_back_buffer )
281 {
282 __DRIconfig **configs;
283 __GLcontextModes *m;
284 unsigned depth_buffer_factor;
285 unsigned back_buffer_factor;
286 int i;
287
288 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
289 * enough to add support. Basically, if a context is created with an
290 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
291 * will never be used.
292 */
293 static const GLenum back_buffer_modes[] = {
294 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
295 };
296
297 uint8_t depth_bits_array[2];
298 uint8_t stencil_bits_array[2];
299 uint8_t msaa_samples_array[1];
300
301 depth_bits_array[0] = depth_bits;
302 depth_bits_array[1] = depth_bits;
303
304 /* Just like with the accumulation buffer, always provide some modes
305 * with a stencil buffer. It will be a sw fallback, but some apps won't
306 * care about that.
307 */
308 stencil_bits_array[0] = 0;
309 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
310
311 msaa_samples_array[0] = 0;
312
313 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
314 back_buffer_factor = (have_back_buffer) ? 2 : 1;
315
316 if (pixel_bits == 16) {
317 __DRIconfig **configs_a8r8g8b8;
318 __DRIconfig **configs_r5g6b5;
319
320 configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5,
321 depth_bits_array, stencil_bits_array,
322 depth_buffer_factor, back_buffer_modes,
323 back_buffer_factor, msaa_samples_array,
324 1);
325 configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
326 depth_bits_array, stencil_bits_array,
327 1, back_buffer_modes, 1,
328 msaa_samples_array, 1);
329 configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8);
330 } else
331 configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
332 depth_bits_array, stencil_bits_array,
333 depth_buffer_factor,
334 back_buffer_modes, back_buffer_factor,
335 msaa_samples_array, 1);
336
337 if (configs == NULL) {
338 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
339 __func__, __LINE__ );
340 return NULL;
341 }
342
343 /* Mark the visual as slow if there are "fake" stencil bits.
344 */
345 for (i = 0; configs[i]; i++) {
346 m = &configs[i]->modes;
347 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
348 m->visualRating = GLX_SLOW_CONFIG;
349 }
350 }
351
352 return (const __DRIconfig **) configs;
353 }
354
355 #if !RADEON_COMMON
356 static const __DRItexOffsetExtension radeonTexOffsetExtension = {
357 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
358 radeonSetTexOffset,
359 };
360
361 static const __DRItexBufferExtension radeonTexBufferExtension = {
362 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
363 radeonSetTexBuffer,
364 radeonSetTexBuffer2,
365 };
366 #endif
367
368 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
369 static const __DRIallocateExtension r200AllocateExtension = {
370 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
371 r200AllocateMemoryMESA,
372 r200FreeMemoryMESA,
373 r200GetMemoryOffsetMESA
374 };
375
376 static const __DRItexOffsetExtension r200texOffsetExtension = {
377 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
378 r200SetTexOffset,
379 };
380
381 static const __DRItexBufferExtension r200TexBufferExtension = {
382 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
383 r200SetTexBuffer,
384 r200SetTexBuffer2,
385 };
386 #endif
387
388 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
389 static const __DRItexOffsetExtension r300texOffsetExtension = {
390 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
391 r300SetTexOffset,
392 };
393
394 static const __DRItexBufferExtension r300TexBufferExtension = {
395 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
396 r300SetTexBuffer,
397 r300SetTexBuffer2,
398 };
399 #endif
400
401 static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
402 {
403 screen->chip_flags = 0;
404 switch ( device_id ) {
405 case PCI_CHIP_RADEON_LY:
406 case PCI_CHIP_RADEON_LZ:
407 case PCI_CHIP_RADEON_QY:
408 case PCI_CHIP_RADEON_QZ:
409 case PCI_CHIP_RN50_515E:
410 case PCI_CHIP_RN50_5969:
411 screen->chip_family = CHIP_FAMILY_RV100;
412 break;
413
414 case PCI_CHIP_RS100_4136:
415 case PCI_CHIP_RS100_4336:
416 screen->chip_family = CHIP_FAMILY_RS100;
417 break;
418
419 case PCI_CHIP_RS200_4137:
420 case PCI_CHIP_RS200_4337:
421 case PCI_CHIP_RS250_4237:
422 case PCI_CHIP_RS250_4437:
423 screen->chip_family = CHIP_FAMILY_RS200;
424 break;
425
426 case PCI_CHIP_RADEON_QD:
427 case PCI_CHIP_RADEON_QE:
428 case PCI_CHIP_RADEON_QF:
429 case PCI_CHIP_RADEON_QG:
430 /* all original radeons (7200) presumably have a stencil op bug */
431 screen->chip_family = CHIP_FAMILY_R100;
432 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
433 break;
434
435 case PCI_CHIP_RV200_QW:
436 case PCI_CHIP_RV200_QX:
437 case PCI_CHIP_RADEON_LW:
438 case PCI_CHIP_RADEON_LX:
439 screen->chip_family = CHIP_FAMILY_RV200;
440 screen->chip_flags = RADEON_CHIPSET_TCL;
441 break;
442
443 case PCI_CHIP_R200_BB:
444 case PCI_CHIP_R200_BC:
445 case PCI_CHIP_R200_QH:
446 case PCI_CHIP_R200_QL:
447 case PCI_CHIP_R200_QM:
448 screen->chip_family = CHIP_FAMILY_R200;
449 screen->chip_flags = RADEON_CHIPSET_TCL;
450 break;
451
452 case PCI_CHIP_RV250_If:
453 case PCI_CHIP_RV250_Ig:
454 case PCI_CHIP_RV250_Ld:
455 case PCI_CHIP_RV250_Lf:
456 case PCI_CHIP_RV250_Lg:
457 screen->chip_family = CHIP_FAMILY_RV250;
458 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
459 break;
460
461 case PCI_CHIP_RV280_5960:
462 case PCI_CHIP_RV280_5961:
463 case PCI_CHIP_RV280_5962:
464 case PCI_CHIP_RV280_5964:
465 case PCI_CHIP_RV280_5965:
466 case PCI_CHIP_RV280_5C61:
467 case PCI_CHIP_RV280_5C63:
468 screen->chip_family = CHIP_FAMILY_RV280;
469 screen->chip_flags = RADEON_CHIPSET_TCL;
470 break;
471
472 case PCI_CHIP_RS300_5834:
473 case PCI_CHIP_RS300_5835:
474 case PCI_CHIP_RS350_7834:
475 case PCI_CHIP_RS350_7835:
476 screen->chip_family = CHIP_FAMILY_RS300;
477 break;
478
479 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
480 case PCI_CHIP_R300_AD:
481 screen->chip_family = CHIP_FAMILY_RV350;
482 screen->chip_flags = RADEON_CHIPSET_TCL;
483 break;
484 case PCI_CHIP_R300_AE:
485 case PCI_CHIP_R300_AF:
486 case PCI_CHIP_R300_AG:
487 case PCI_CHIP_R300_ND:
488 case PCI_CHIP_R300_NE:
489 case PCI_CHIP_R300_NF:
490 case PCI_CHIP_R300_NG:
491 screen->chip_family = CHIP_FAMILY_R300;
492 screen->chip_flags = RADEON_CHIPSET_TCL;
493 break;
494
495 case PCI_CHIP_RV350_AP:
496 case PCI_CHIP_RV350_AQ:
497 case PCI_CHIP_RV350_AR:
498 case PCI_CHIP_RV350_AS:
499 case PCI_CHIP_RV350_AT:
500 case PCI_CHIP_RV350_AV:
501 case PCI_CHIP_RV350_AU:
502 case PCI_CHIP_RV350_NP:
503 case PCI_CHIP_RV350_NQ:
504 case PCI_CHIP_RV350_NR:
505 case PCI_CHIP_RV350_NS:
506 case PCI_CHIP_RV350_NT:
507 case PCI_CHIP_RV350_NV:
508 screen->chip_family = CHIP_FAMILY_RV350;
509 screen->chip_flags = RADEON_CHIPSET_TCL;
510 break;
511
512 case PCI_CHIP_R350_AH:
513 case PCI_CHIP_R350_AI:
514 case PCI_CHIP_R350_AJ:
515 case PCI_CHIP_R350_AK:
516 case PCI_CHIP_R350_NH:
517 case PCI_CHIP_R350_NI:
518 case PCI_CHIP_R360_NJ:
519 case PCI_CHIP_R350_NK:
520 screen->chip_family = CHIP_FAMILY_R350;
521 screen->chip_flags = RADEON_CHIPSET_TCL;
522 break;
523
524 case PCI_CHIP_RV370_5460:
525 case PCI_CHIP_RV370_5462:
526 case PCI_CHIP_RV370_5464:
527 case PCI_CHIP_RV370_5B60:
528 case PCI_CHIP_RV370_5B62:
529 case PCI_CHIP_RV370_5B63:
530 case PCI_CHIP_RV370_5B64:
531 case PCI_CHIP_RV370_5B65:
532 case PCI_CHIP_RV380_3150:
533 case PCI_CHIP_RV380_3152:
534 case PCI_CHIP_RV380_3154:
535 case PCI_CHIP_RV380_3E50:
536 case PCI_CHIP_RV380_3E54:
537 screen->chip_family = CHIP_FAMILY_RV380;
538 screen->chip_flags = RADEON_CHIPSET_TCL;
539 break;
540
541 case PCI_CHIP_R420_JN:
542 case PCI_CHIP_R420_JH:
543 case PCI_CHIP_R420_JI:
544 case PCI_CHIP_R420_JJ:
545 case PCI_CHIP_R420_JK:
546 case PCI_CHIP_R420_JL:
547 case PCI_CHIP_R420_JM:
548 case PCI_CHIP_R420_JO:
549 case PCI_CHIP_R420_JP:
550 case PCI_CHIP_R420_JT:
551 case PCI_CHIP_R481_4B49:
552 case PCI_CHIP_R481_4B4A:
553 case PCI_CHIP_R481_4B4B:
554 case PCI_CHIP_R481_4B4C:
555 case PCI_CHIP_R423_UH:
556 case PCI_CHIP_R423_UI:
557 case PCI_CHIP_R423_UJ:
558 case PCI_CHIP_R423_UK:
559 case PCI_CHIP_R430_554C:
560 case PCI_CHIP_R430_554D:
561 case PCI_CHIP_R430_554E:
562 case PCI_CHIP_R430_554F:
563 case PCI_CHIP_R423_5550:
564 case PCI_CHIP_R423_UQ:
565 case PCI_CHIP_R423_UR:
566 case PCI_CHIP_R423_UT:
567 case PCI_CHIP_R430_5D48:
568 case PCI_CHIP_R430_5D49:
569 case PCI_CHIP_R430_5D4A:
570 case PCI_CHIP_R480_5D4C:
571 case PCI_CHIP_R480_5D4D:
572 case PCI_CHIP_R480_5D4E:
573 case PCI_CHIP_R480_5D4F:
574 case PCI_CHIP_R480_5D50:
575 case PCI_CHIP_R480_5D52:
576 case PCI_CHIP_R423_5D57:
577 screen->chip_family = CHIP_FAMILY_R420;
578 screen->chip_flags = RADEON_CHIPSET_TCL;
579 break;
580
581 case PCI_CHIP_RV410_5E4C:
582 case PCI_CHIP_RV410_5E4F:
583 case PCI_CHIP_RV410_564A:
584 case PCI_CHIP_RV410_564B:
585 case PCI_CHIP_RV410_564F:
586 case PCI_CHIP_RV410_5652:
587 case PCI_CHIP_RV410_5653:
588 case PCI_CHIP_RV410_5657:
589 case PCI_CHIP_RV410_5E48:
590 case PCI_CHIP_RV410_5E4A:
591 case PCI_CHIP_RV410_5E4B:
592 case PCI_CHIP_RV410_5E4D:
593 screen->chip_family = CHIP_FAMILY_RV410;
594 screen->chip_flags = RADEON_CHIPSET_TCL;
595 break;
596
597 case PCI_CHIP_RS480_5954:
598 case PCI_CHIP_RS480_5955:
599 case PCI_CHIP_RS482_5974:
600 case PCI_CHIP_RS482_5975:
601 case PCI_CHIP_RS400_5A41:
602 case PCI_CHIP_RS400_5A42:
603 case PCI_CHIP_RC410_5A61:
604 case PCI_CHIP_RC410_5A62:
605 screen->chip_family = CHIP_FAMILY_RS400;
606 break;
607
608 case PCI_CHIP_RS600_793F:
609 case PCI_CHIP_RS600_7941:
610 case PCI_CHIP_RS600_7942:
611 screen->chip_family = CHIP_FAMILY_RS600;
612 break;
613
614 case PCI_CHIP_RS690_791E:
615 case PCI_CHIP_RS690_791F:
616 screen->chip_family = CHIP_FAMILY_RS690;
617 break;
618 case PCI_CHIP_RS740_796C:
619 case PCI_CHIP_RS740_796D:
620 case PCI_CHIP_RS740_796E:
621 case PCI_CHIP_RS740_796F:
622 screen->chip_family = CHIP_FAMILY_RS740;
623 break;
624
625 case PCI_CHIP_R520_7100:
626 case PCI_CHIP_R520_7101:
627 case PCI_CHIP_R520_7102:
628 case PCI_CHIP_R520_7103:
629 case PCI_CHIP_R520_7104:
630 case PCI_CHIP_R520_7105:
631 case PCI_CHIP_R520_7106:
632 case PCI_CHIP_R520_7108:
633 case PCI_CHIP_R520_7109:
634 case PCI_CHIP_R520_710A:
635 case PCI_CHIP_R520_710B:
636 case PCI_CHIP_R520_710C:
637 case PCI_CHIP_R520_710E:
638 case PCI_CHIP_R520_710F:
639 screen->chip_family = CHIP_FAMILY_R520;
640 screen->chip_flags = RADEON_CHIPSET_TCL;
641 break;
642
643 case PCI_CHIP_RV515_7140:
644 case PCI_CHIP_RV515_7141:
645 case PCI_CHIP_RV515_7142:
646 case PCI_CHIP_RV515_7143:
647 case PCI_CHIP_RV515_7144:
648 case PCI_CHIP_RV515_7145:
649 case PCI_CHIP_RV515_7146:
650 case PCI_CHIP_RV515_7147:
651 case PCI_CHIP_RV515_7149:
652 case PCI_CHIP_RV515_714A:
653 case PCI_CHIP_RV515_714B:
654 case PCI_CHIP_RV515_714C:
655 case PCI_CHIP_RV515_714D:
656 case PCI_CHIP_RV515_714E:
657 case PCI_CHIP_RV515_714F:
658 case PCI_CHIP_RV515_7151:
659 case PCI_CHIP_RV515_7152:
660 case PCI_CHIP_RV515_7153:
661 case PCI_CHIP_RV515_715E:
662 case PCI_CHIP_RV515_715F:
663 case PCI_CHIP_RV515_7180:
664 case PCI_CHIP_RV515_7181:
665 case PCI_CHIP_RV515_7183:
666 case PCI_CHIP_RV515_7186:
667 case PCI_CHIP_RV515_7187:
668 case PCI_CHIP_RV515_7188:
669 case PCI_CHIP_RV515_718A:
670 case PCI_CHIP_RV515_718B:
671 case PCI_CHIP_RV515_718C:
672 case PCI_CHIP_RV515_718D:
673 case PCI_CHIP_RV515_718F:
674 case PCI_CHIP_RV515_7193:
675 case PCI_CHIP_RV515_7196:
676 case PCI_CHIP_RV515_719B:
677 case PCI_CHIP_RV515_719F:
678 case PCI_CHIP_RV515_7200:
679 case PCI_CHIP_RV515_7210:
680 case PCI_CHIP_RV515_7211:
681 screen->chip_family = CHIP_FAMILY_RV515;
682 screen->chip_flags = RADEON_CHIPSET_TCL;
683 break;
684
685 case PCI_CHIP_RV530_71C0:
686 case PCI_CHIP_RV530_71C1:
687 case PCI_CHIP_RV530_71C2:
688 case PCI_CHIP_RV530_71C3:
689 case PCI_CHIP_RV530_71C4:
690 case PCI_CHIP_RV530_71C5:
691 case PCI_CHIP_RV530_71C6:
692 case PCI_CHIP_RV530_71C7:
693 case PCI_CHIP_RV530_71CD:
694 case PCI_CHIP_RV530_71CE:
695 case PCI_CHIP_RV530_71D2:
696 case PCI_CHIP_RV530_71D4:
697 case PCI_CHIP_RV530_71D5:
698 case PCI_CHIP_RV530_71D6:
699 case PCI_CHIP_RV530_71DA:
700 case PCI_CHIP_RV530_71DE:
701 screen->chip_family = CHIP_FAMILY_RV530;
702 screen->chip_flags = RADEON_CHIPSET_TCL;
703 break;
704
705 case PCI_CHIP_R580_7240:
706 case PCI_CHIP_R580_7243:
707 case PCI_CHIP_R580_7244:
708 case PCI_CHIP_R580_7245:
709 case PCI_CHIP_R580_7246:
710 case PCI_CHIP_R580_7247:
711 case PCI_CHIP_R580_7248:
712 case PCI_CHIP_R580_7249:
713 case PCI_CHIP_R580_724A:
714 case PCI_CHIP_R580_724B:
715 case PCI_CHIP_R580_724C:
716 case PCI_CHIP_R580_724D:
717 case PCI_CHIP_R580_724E:
718 case PCI_CHIP_R580_724F:
719 case PCI_CHIP_R580_7284:
720 screen->chip_family = CHIP_FAMILY_R580;
721 screen->chip_flags = RADEON_CHIPSET_TCL;
722 break;
723
724 case PCI_CHIP_RV570_7280:
725 case PCI_CHIP_RV560_7281:
726 case PCI_CHIP_RV560_7283:
727 case PCI_CHIP_RV560_7287:
728 case PCI_CHIP_RV570_7288:
729 case PCI_CHIP_RV570_7289:
730 case PCI_CHIP_RV570_728B:
731 case PCI_CHIP_RV570_728C:
732 case PCI_CHIP_RV560_7290:
733 case PCI_CHIP_RV560_7291:
734 case PCI_CHIP_RV560_7293:
735 case PCI_CHIP_RV560_7297:
736 screen->chip_family = CHIP_FAMILY_RV560;
737 screen->chip_flags = RADEON_CHIPSET_TCL;
738 break;
739
740 default:
741 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
742 device_id);
743 return -1;
744 }
745
746 return 0;
747 }
748
749
750 /* Create the device specific screen private data struct.
751 */
752 static radeonScreenPtr
753 radeonCreateScreen( __DRIscreenPrivate *sPriv )
754 {
755 radeonScreenPtr screen;
756 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
757 unsigned char *RADEONMMIO = NULL;
758 int i;
759 int ret;
760 uint32_t temp = 0;
761
762 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
763 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
764 return GL_FALSE;
765 }
766
767 /* Allocate the private area */
768 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
769 if ( !screen ) {
770 __driUtilMessage("%s: Could not allocate memory for screen structure",
771 __FUNCTION__);
772 return NULL;
773 }
774
775 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
776 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
777 #endif
778
779 /* parse information in __driConfigOptions */
780 driParseOptionInfo (&screen->optionCache,
781 __driConfigOptions, __driNConfigOptions);
782
783 /* This is first since which regions we map depends on whether or
784 * not we are using a PCI card.
785 */
786 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
787 {
788 int ret;
789
790 #ifdef RADEON_PARAM_KERNEL_MM
791 ret = radeonGetParam(sPriv, RADEON_PARAM_KERNEL_MM, &screen->kernel_mm);
792
793 if (ret && ret != -EINVAL) {
794 FREE( screen );
795 fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret);
796 return NULL;
797 }
798
799 if (ret == -EINVAL)
800 screen->kernel_mm = 0;
801 #endif
802
803 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET,
804 &screen->gart_buffer_offset);
805
806 if (ret) {
807 FREE( screen );
808 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
809 return NULL;
810 }
811
812 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE,
813 &screen->gart_base);
814 if (ret) {
815 FREE( screen );
816 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
817 return NULL;
818 }
819
820 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR,
821 &screen->irq);
822 if (ret) {
823 FREE( screen );
824 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
825 return NULL;
826 }
827 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
828 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
829 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
830 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
831 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
832 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
833 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
834 }
835
836 if (!screen->kernel_mm) {
837 screen->mmio.handle = dri_priv->registerHandle;
838 screen->mmio.size = dri_priv->registerSize;
839 if ( drmMap( sPriv->fd,
840 screen->mmio.handle,
841 screen->mmio.size,
842 &screen->mmio.map ) ) {
843 FREE( screen );
844 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
845 return NULL;
846 }
847
848 RADEONMMIO = screen->mmio.map;
849
850 screen->status.handle = dri_priv->statusHandle;
851 screen->status.size = dri_priv->statusSize;
852 if ( drmMap( sPriv->fd,
853 screen->status.handle,
854 screen->status.size,
855 &screen->status.map ) ) {
856 drmUnmap( screen->mmio.map, screen->mmio.size );
857 FREE( screen );
858 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
859 return NULL;
860 }
861 screen->scratch = (__volatile__ uint32_t *)
862 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
863
864 screen->buffers = drmMapBufs( sPriv->fd );
865 if ( !screen->buffers ) {
866 drmUnmap( screen->status.map, screen->status.size );
867 drmUnmap( screen->mmio.map, screen->mmio.size );
868 FREE( screen );
869 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
870 return NULL;
871 }
872
873 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
874 screen->gartTextures.handle = dri_priv->gartTexHandle;
875 screen->gartTextures.size = dri_priv->gartTexMapSize;
876 if ( drmMap( sPriv->fd,
877 screen->gartTextures.handle,
878 screen->gartTextures.size,
879 (drmAddressPtr)&screen->gartTextures.map ) ) {
880 drmUnmapBufs( screen->buffers );
881 drmUnmap( screen->status.map, screen->status.size );
882 drmUnmap( screen->mmio.map, screen->mmio.size );
883 FREE( screen );
884 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
885 return NULL;
886 }
887
888 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
889 }
890 }
891
892
893 ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
894 if (ret == -1)
895 return NULL;
896
897 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
898 sPriv->ddx_version.minor < 2) {
899 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
900 return NULL;
901 }
902
903 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
904 fprintf(stderr, "R500 support requires a newer drm.\n");
905 return NULL;
906 }
907
908 if (getenv("R300_NO_TCL"))
909 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
910
911 if (screen->chip_family <= CHIP_FAMILY_RS200)
912 screen->chip_flags |= RADEON_CLASS_R100;
913 else if (screen->chip_family <= CHIP_FAMILY_RV280)
914 screen->chip_flags |= RADEON_CLASS_R200;
915 else
916 screen->chip_flags |= RADEON_CLASS_R300;
917
918 screen->cpp = dri_priv->bpp / 8;
919 screen->AGPMode = dri_priv->AGPMode;
920
921 ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp);
922 if (ret) {
923 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm)
924 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
925 else {
926 FREE( screen );
927 fprintf(stderr, "Unable to get fb location need newer drm\n");
928 return NULL;
929 }
930 } else {
931 screen->fbLocation = (temp & 0xffff) << 16;
932 }
933
934 if (screen->chip_family >= CHIP_FAMILY_R300) {
935 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
936 if (ret) {
937 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
938 switch (screen->chip_family) {
939 case CHIP_FAMILY_R300:
940 case CHIP_FAMILY_R350:
941 screen->num_gb_pipes = 2;
942 break;
943 case CHIP_FAMILY_R420:
944 case CHIP_FAMILY_R520:
945 case CHIP_FAMILY_R580:
946 case CHIP_FAMILY_RV560:
947 case CHIP_FAMILY_RV570:
948 screen->num_gb_pipes = 4;
949 break;
950 case CHIP_FAMILY_RV350:
951 case CHIP_FAMILY_RV515:
952 case CHIP_FAMILY_RV530:
953 case CHIP_FAMILY_RV410:
954 default:
955 screen->num_gb_pipes = 1;
956 break;
957 }
958 } else {
959 screen->num_gb_pipes = temp;
960 }
961 }
962
963 if ( sPriv->drm_version.minor >= 10 ) {
964 drm_radeon_setparam_t sp;
965
966 sp.param = RADEON_SETPARAM_FB_LOCATION;
967 sp.value = screen->fbLocation;
968
969 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
970 &sp, sizeof( sp ) );
971 }
972
973 screen->frontOffset = dri_priv->frontOffset;
974 screen->frontPitch = dri_priv->frontPitch;
975 screen->backOffset = dri_priv->backOffset;
976 screen->backPitch = dri_priv->backPitch;
977 screen->depthOffset = dri_priv->depthOffset;
978 screen->depthPitch = dri_priv->depthPitch;
979
980 /* Check if ddx has set up a surface reg to cover depth buffer */
981 screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
982 /* these chips don't use tiled z without hyperz. So always pretend
983 we have set up a surface which will cause linear reads/writes */
984 (IS_R100_CLASS(screen) &&
985 !(screen->chip_flags & RADEON_CHIPSET_TCL));
986
987 if ( dri_priv->textureSize == 0 ) {
988 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
989 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
990 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
991 dri_priv->log2GARTTexGran;
992 } else {
993 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
994 + screen->fbLocation;
995 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
996 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
997 dri_priv->log2TexGran;
998 }
999
1000 if ( !screen->gartTextures.map || dri_priv->textureSize == 0
1001 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
1002 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
1003 screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
1004 screen->texSize[RADEON_GART_TEX_HEAP] = 0;
1005 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
1006 } else {
1007 screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
1008 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
1009 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
1010 screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
1011 dri_priv->log2GARTTexGran;
1012 }
1013
1014 i = 0;
1015 screen->extensions[i++] = &driCopySubBufferExtension.base;
1016 screen->extensions[i++] = &driFrameTrackingExtension.base;
1017 screen->extensions[i++] = &driReadDrawableExtension;
1018
1019 if ( screen->irq != 0 ) {
1020 screen->extensions[i++] = &driSwapControlExtension.base;
1021 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1022 }
1023
1024 if (!screen->kernel_mm) {
1025 #if !RADEON_COMMON
1026 screen->extensions[i++] = &radeonTexOffsetExtension.base;
1027 #endif
1028
1029 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1030 if (IS_R200_CLASS(screen))
1031 screen->extensions[i++] = &r200AllocateExtension.base;
1032
1033 screen->extensions[i++] = &r200texOffsetExtension.base;
1034 #endif
1035
1036 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1037 screen->extensions[i++] = &r300texOffsetExtension.base;
1038 #endif
1039 }
1040
1041 screen->extensions[i++] = NULL;
1042 sPriv->extensions = screen->extensions;
1043
1044 screen->driScreen = sPriv;
1045 screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
1046 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
1047 screen->sarea_priv_offset);
1048
1049 if (screen->kernel_mm)
1050 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1051 else
1052 screen->bom = radeon_bo_manager_legacy_ctor(screen);
1053 if (screen->bom == NULL) {
1054 free(screen);
1055 return NULL;
1056 }
1057
1058 return screen;
1059 }
1060
1061 static radeonScreenPtr
1062 radeonCreateScreen2(__DRIscreenPrivate *sPriv)
1063 {
1064 radeonScreenPtr screen;
1065 int i;
1066 int ret;
1067 uint32_t device_id;
1068 uint32_t temp = 0;
1069
1070 /* Allocate the private area */
1071 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1072 if ( !screen ) {
1073 __driUtilMessage("%s: Could not allocate memory for screen structure",
1074 __FUNCTION__);
1075 fprintf(stderr, "leaving here\n");
1076 return NULL;
1077 }
1078
1079 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1080 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
1081 #endif
1082
1083 /* parse information in __driConfigOptions */
1084 driParseOptionInfo (&screen->optionCache,
1085 __driConfigOptions, __driNConfigOptions);
1086
1087 screen->kernel_mm = 1;
1088 screen->chip_flags = 0;
1089
1090 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR, &screen->irq);
1091
1092 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id);
1093 if (ret) {
1094 FREE( screen );
1095 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret);
1096 return NULL;
1097 }
1098
1099 ret = radeon_set_screen_flags(screen, device_id);
1100 if (ret == -1)
1101 return NULL;
1102
1103 if (screen->chip_family >= CHIP_FAMILY_R300) {
1104 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1105 if (ret) {
1106 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1107 switch (screen->chip_family) {
1108 case CHIP_FAMILY_R300:
1109 case CHIP_FAMILY_R350:
1110 screen->num_gb_pipes = 2;
1111 break;
1112 case CHIP_FAMILY_R420:
1113 case CHIP_FAMILY_R520:
1114 case CHIP_FAMILY_R580:
1115 case CHIP_FAMILY_RV560:
1116 case CHIP_FAMILY_RV570:
1117 screen->num_gb_pipes = 4;
1118 break;
1119 case CHIP_FAMILY_RV350:
1120 case CHIP_FAMILY_RV515:
1121 case CHIP_FAMILY_RV530:
1122 case CHIP_FAMILY_RV410:
1123 default:
1124 screen->num_gb_pipes = 1;
1125 break;
1126 }
1127 } else {
1128 screen->num_gb_pipes = temp;
1129 }
1130 }
1131
1132 if (screen->chip_family <= CHIP_FAMILY_RS200)
1133 screen->chip_flags |= RADEON_CLASS_R100;
1134 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1135 screen->chip_flags |= RADEON_CLASS_R200;
1136 else
1137 screen->chip_flags |= RADEON_CLASS_R300;
1138
1139 if (getenv("R300_NO_TCL"))
1140 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1141
1142 i = 0;
1143 screen->extensions[i++] = &driCopySubBufferExtension.base;
1144 screen->extensions[i++] = &driFrameTrackingExtension.base;
1145 screen->extensions[i++] = &driReadDrawableExtension;
1146
1147 if ( screen->irq != 0 ) {
1148 screen->extensions[i++] = &driSwapControlExtension.base;
1149 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1150 }
1151
1152 #if !RADEON_COMMON
1153 screen->extensions[i++] = &radeonTexBufferExtension.base;
1154 #endif
1155
1156 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1157 if (IS_R200_CLASS(screen))
1158 screen->extensions[i++] = &r200AllocateExtension.base;
1159
1160 screen->extensions[i++] = &r200TexBufferExtension.base;
1161 #endif
1162
1163 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1164 screen->extensions[i++] = &r300TexBufferExtension.base;
1165 #endif
1166
1167 screen->extensions[i++] = NULL;
1168 sPriv->extensions = screen->extensions;
1169
1170 screen->driScreen = sPriv;
1171 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1172 if (screen->bom == NULL) {
1173 free(screen);
1174 return NULL;
1175 }
1176 return screen;
1177 }
1178
1179 /* Destroy the device specific screen private data struct.
1180 */
1181 static void
1182 radeonDestroyScreen( __DRIscreenPrivate *sPriv )
1183 {
1184 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1185
1186 if (!screen)
1187 return;
1188
1189 if (screen->kernel_mm) {
1190 #ifdef RADEON_BO_TRACK
1191 radeon_tracker_print(&screen->bom->tracker, stderr);
1192 #endif
1193 radeon_bo_manager_gem_dtor(screen->bom);
1194 } else {
1195 radeon_bo_manager_legacy_dtor(screen->bom);
1196
1197 if ( screen->gartTextures.map ) {
1198 drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
1199 }
1200 drmUnmapBufs( screen->buffers );
1201 drmUnmap( screen->status.map, screen->status.size );
1202 drmUnmap( screen->mmio.map, screen->mmio.size );
1203 }
1204
1205 /* free all option information */
1206 driDestroyOptionInfo (&screen->optionCache);
1207
1208 FREE( screen );
1209 sPriv->private = NULL;
1210 }
1211
1212
1213 /* Initialize the driver specific screen private data.
1214 */
1215 static GLboolean
1216 radeonInitDriver( __DRIscreenPrivate *sPriv )
1217 {
1218 if (sPriv->dri2.enabled) {
1219 sPriv->private = (void *) radeonCreateScreen2( sPriv );
1220 } else {
1221 sPriv->private = (void *) radeonCreateScreen( sPriv );
1222 }
1223 if ( !sPriv->private ) {
1224 radeonDestroyScreen( sPriv );
1225 return GL_FALSE;
1226 }
1227
1228 return GL_TRUE;
1229 }
1230
1231
1232
1233 /**
1234 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1235 *
1236 * \todo This function (and its interface) will need to be updated to support
1237 * pbuffers.
1238 */
1239 static GLboolean
1240 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
1241 __DRIdrawablePrivate *driDrawPriv,
1242 const __GLcontextModes *mesaVis,
1243 GLboolean isPixmap )
1244 {
1245 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1246
1247 const GLboolean swDepth = GL_FALSE;
1248 const GLboolean swAlpha = GL_FALSE;
1249 const GLboolean swAccum = mesaVis->accumRedBits > 0;
1250 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1251 mesaVis->depthBits != 24;
1252 GLenum rgbFormat;
1253 struct radeon_framebuffer *rfb;
1254
1255 if (isPixmap)
1256 return GL_FALSE; /* not implemented */
1257
1258 rfb = CALLOC_STRUCT(radeon_framebuffer);
1259 if (!rfb)
1260 return GL_FALSE;
1261
1262 _mesa_initialize_framebuffer(&rfb->base, mesaVis);
1263
1264 if (mesaVis->redBits == 5)
1265 rgbFormat = GL_RGB5;
1266 else if (mesaVis->alphaBits == 0)
1267 rgbFormat = GL_RGB8;
1268 else
1269 rgbFormat = GL_RGBA8;
1270
1271 /* front color renderbuffer */
1272 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1273 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base);
1274 rfb->color_rb[0]->has_surface = 1;
1275
1276 /* back color renderbuffer */
1277 if (mesaVis->doubleBufferMode) {
1278 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1279 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base);
1280 rfb->color_rb[1]->has_surface = 1;
1281 }
1282
1283 if (mesaVis->depthBits == 24) {
1284 if (mesaVis->stencilBits == 8) {
1285 struct radeon_renderbuffer *depthStencilRb = radeon_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT, driDrawPriv);
1286 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base);
1287 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base);
1288 depthStencilRb->has_surface = screen->depthHasSurface;
1289 } else {
1290 /* depth renderbuffer */
1291 struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT24, driDrawPriv);
1292 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1293 depth->has_surface = screen->depthHasSurface;
1294 }
1295 } else if (mesaVis->depthBits == 16) {
1296 /* just 16-bit depth buffer, no hw stencil */
1297 struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT16, driDrawPriv);
1298 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1299 depth->has_surface = screen->depthHasSurface;
1300 }
1301
1302 _mesa_add_soft_renderbuffers(&rfb->base,
1303 GL_FALSE, /* color */
1304 swDepth,
1305 swStencil,
1306 swAccum,
1307 swAlpha,
1308 GL_FALSE /* aux */);
1309 driDrawPriv->driverPrivate = (void *) rfb;
1310
1311 return (driDrawPriv->driverPrivate != NULL);
1312 }
1313
1314
1315 static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb)
1316 {
1317 struct radeon_renderbuffer *rb;
1318
1319 rb = rfb->color_rb[0];
1320 if (rb && rb->bo) {
1321 radeon_bo_unref(rb->bo);
1322 rb->bo = NULL;
1323 }
1324 rb = rfb->color_rb[1];
1325 if (rb && rb->bo) {
1326 radeon_bo_unref(rb->bo);
1327 rb->bo = NULL;
1328 }
1329 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
1330 if (rb && rb->bo) {
1331 radeon_bo_unref(rb->bo);
1332 rb->bo = NULL;
1333 }
1334 }
1335
1336 void
1337 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
1338 {
1339 struct radeon_framebuffer *rfb;
1340 if (!driDrawPriv)
1341 return;
1342
1343 rfb = (void*)driDrawPriv->driverPrivate;
1344 if (!rfb)
1345 return;
1346 radeon_cleanup_renderbuffers(rfb);
1347 _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL);
1348 }
1349
1350 /**
1351 * Choose the appropriate CreateContext function based on the chipset.
1352 * Eventually, all drivers will go through this process.
1353 */
1354 static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
1355 __DRIcontextPrivate * driContextPriv,
1356 void *sharedContextPriv)
1357 {
1358 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
1359 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
1360 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1361 if (IS_R300_CLASS(screen))
1362 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
1363 #endif
1364
1365 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1366 if (IS_R200_CLASS(screen))
1367 return r200CreateContext(glVisual, driContextPriv, sharedContextPriv);
1368 #endif
1369
1370 #if !RADEON_COMMON
1371 return r100CreateContext(glVisual, driContextPriv, sharedContextPriv);
1372 #endif
1373 return GL_FALSE;
1374 }
1375
1376
1377 /**
1378 * This is the driver specific part of the createNewScreen entry point.
1379 *
1380 * \todo maybe fold this into intelInitDriver
1381 *
1382 * \return the __GLcontextModes supported by this driver
1383 */
1384 static const __DRIconfig **
1385 radeonInitScreen(__DRIscreenPrivate *psp)
1386 {
1387 #if !RADEON_COMMON
1388 static const char *driver_name = "Radeon";
1389 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1390 static const __DRIversion dri_expected = { 4, 0, 0 };
1391 static const __DRIversion drm_expected = { 1, 6, 0 };
1392 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1393 static const char *driver_name = "R200";
1394 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1395 static const __DRIversion dri_expected = { 4, 0, 0 };
1396 static const __DRIversion drm_expected = { 1, 6, 0 };
1397 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1398 static const char *driver_name = "R300";
1399 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1400 static const __DRIversion dri_expected = { 4, 0, 0 };
1401 static const __DRIversion drm_expected = { 1, 24, 0 };
1402 #endif
1403 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1404
1405 if ( ! driCheckDriDdxDrmVersions3( driver_name,
1406 &psp->dri_version, & dri_expected,
1407 &psp->ddx_version, & ddx_expected,
1408 &psp->drm_version, & drm_expected ) ) {
1409 return NULL;
1410 }
1411
1412 /* Calling driInitExtensions here, with a NULL context pointer,
1413 * does not actually enable the extensions. It just makes sure
1414 * that all the dispatch offsets for all the extensions that
1415 * *might* be enables are known. This is needed because the
1416 * dispatch offsets need to be known when _mesa_context_create
1417 * is called, but we can't enable the extensions until we have a
1418 * context pointer.
1419 *
1420 * Hello chicken. Hello egg. How are you two today?
1421 */
1422 driInitExtensions( NULL, card_extensions, GL_FALSE );
1423 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1424 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1425 driInitSingleExtension( NULL, ARB_vp_extension );
1426 driInitSingleExtension( NULL, NV_vp_extension );
1427 driInitSingleExtension( NULL, ATI_fs_extension );
1428 driInitExtensions( NULL, point_extensions, GL_FALSE );
1429 #elif defined(RADEON_COMMON_FOR_R300)
1430 driInitSingleExtension( NULL, gl_20_extension );
1431 #endif
1432
1433 if (!radeonInitDriver(psp))
1434 return NULL;
1435
1436 /* for now fill in all modes */
1437 return radeonFillInModes( psp,
1438 dri_priv->bpp,
1439 (dri_priv->bpp == 16) ? 16 : 24,
1440 (dri_priv->bpp == 16) ? 0 : 8, 1);
1441 }
1442 #define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
1443
1444 /**
1445 * This is the driver specific part of the createNewScreen entry point.
1446 * Called when using DRI2.
1447 *
1448 * \return the __GLcontextModes supported by this driver
1449 */
1450 static const
1451 __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp)
1452 {
1453 GLenum fb_format[3];
1454 GLenum fb_type[3];
1455 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
1456 * support pageflipping at all.
1457 */
1458 static const GLenum back_buffer_modes[] = {
1459 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/
1460 };
1461 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
1462 int color;
1463 __DRIconfig **configs = NULL;
1464
1465 /* Calling driInitExtensions here, with a NULL context pointer,
1466 * does not actually enable the extensions. It just makes sure
1467 * that all the dispatch offsets for all the extensions that
1468 * *might* be enables are known. This is needed because the
1469 * dispatch offsets need to be known when _mesa_context_create
1470 * is called, but we can't enable the extensions until we have a
1471 * context pointer.
1472 *
1473 * Hello chicken. Hello egg. How are you two today?
1474 */
1475 driInitExtensions( NULL, card_extensions, GL_FALSE );
1476 driInitExtensions( NULL, mm_extensions, GL_FALSE );
1477 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1478 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1479 driInitSingleExtension( NULL, ARB_vp_extension );
1480 driInitSingleExtension( NULL, NV_vp_extension );
1481 driInitSingleExtension( NULL, ATI_fs_extension );
1482 driInitExtensions( NULL, point_extensions, GL_FALSE );
1483 #endif
1484
1485 if (!radeonInitDriver(psp)) {
1486 return NULL;
1487 }
1488 depth_bits[0] = 0;
1489 stencil_bits[0] = 0;
1490 depth_bits[1] = 16;
1491 stencil_bits[1] = 0;
1492 depth_bits[2] = 24;
1493 stencil_bits[2] = 0;
1494 depth_bits[3] = 24;
1495 stencil_bits[3] = 8;
1496
1497 msaa_samples_array[0] = 0;
1498
1499 fb_format[0] = GL_RGB;
1500 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5;
1501
1502 fb_format[1] = GL_BGR;
1503 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV;
1504
1505 fb_format[2] = GL_BGRA;
1506 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
1507
1508 for (color = 0; color < ARRAY_SIZE(fb_format); color++) {
1509 __DRIconfig **new_configs;
1510
1511 new_configs = driCreateConfigs(fb_format[color], fb_type[color],
1512 depth_bits,
1513 stencil_bits,
1514 ARRAY_SIZE(depth_bits),
1515 back_buffer_modes,
1516 ARRAY_SIZE(back_buffer_modes),
1517 msaa_samples_array,
1518 ARRAY_SIZE(msaa_samples_array));
1519 if (configs == NULL)
1520 configs = new_configs;
1521 else
1522 configs = driConcatConfigs(configs, new_configs);
1523 }
1524
1525 if (configs == NULL) {
1526 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
1527 __LINE__);
1528 return NULL;
1529 }
1530
1531 return (const __DRIconfig **)configs;
1532 }
1533
1534 /**
1535 * Get information about previous buffer swaps.
1536 */
1537 static int
1538 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1539 {
1540 struct radeon_framebuffer *rfb;
1541
1542 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1543 || (dPriv->driContextPriv->driverPrivate == NULL)
1544 || (sInfo == NULL) ) {
1545 return -1;
1546 }
1547
1548 rfb = dPriv->driverPrivate;
1549 sInfo->swap_count = rfb->swap_count;
1550 sInfo->swap_ust = rfb->swap_ust;
1551 sInfo->swap_missed_count = rfb->swap_missed_count;
1552
1553 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1554 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust )
1555 : 0.0;
1556
1557 return 0;
1558 }
1559
1560 const struct __DriverAPIRec driDriverAPI = {
1561 .InitScreen = radeonInitScreen,
1562 .DestroyScreen = radeonDestroyScreen,
1563 .CreateContext = radeonCreateContext,
1564 .DestroyContext = radeonDestroyContext,
1565 .CreateBuffer = radeonCreateBuffer,
1566 .DestroyBuffer = radeonDestroyBuffer,
1567 .SwapBuffers = radeonSwapBuffers,
1568 .MakeCurrent = radeonMakeCurrent,
1569 .UnbindContext = radeonUnbindContext,
1570 .GetSwapInfo = getSwapInfo,
1571 .GetDrawableMSC = driDrawableGetMSC32,
1572 .WaitForMSC = driWaitForMSC32,
1573 .WaitForSBC = NULL,
1574 .SwapBuffersMSC = NULL,
1575 .CopySubBuffer = radeonCopySubBuffer,
1576 /* DRI2 */
1577 .InitScreen2 = radeonInitScreen2,
1578 };
1579