src/mesa/drivers/dri/radeon/radeon_screen.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file radeon_screen.c
  32  * Screen initialization functions for the Radeon driver.
  33  *
  34  * \author Kevin E. Martin <martin@valinux.com>
  35  * \author  Gareth Hughes <gareth@valinux.com>
  36  */
  37
  38 #include "main/glheader.h"
  39 #include "main/imports.h"
  40 #include "main/mtypes.h"
  41 #include "main/framebuffer.h"
  42 #include "main/renderbuffer.h"
  43
  44 #define STANDALONE_MMIO
  45 #include "radeon_chipset.h"
  46 #include "radeon_macros.h"
  47 #include "radeon_screen.h"
  48 #if !RADEON_COMMON
  49 #include "radeon_context.h"
  50 #include "radeon_span.h"
  51 #include "radeon_tex.h"
  52 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
  53 #include "r200_context.h"
  54 #include "r200_ioctl.h"
  55 #include "r200_span.h"
  56 #include "r200_tex.h"
  57 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
  58 #include "r300_context.h"
  59 #include "r300_fragprog.h"
  60 #include "r300_tex.h"
  61 #include "radeon_span.h"
  62 #endif
  63
  64 #include "utils.h"
  65 #include "vblank.h"
  66 #include "drirenderbuffer.h"
  67
  68 #include "GL/internal/dri_interface.h"
  69
  70 /* Radeon configuration
  71  */
  72 #include "xmlpool.h"
  73
  74 #if !RADEON_COMMON      /* R100 */
  75 PUBLIC const char __driConfigOptions[] =
  76 DRI_CONF_BEGIN
  77     DRI_CONF_SECTION_PERFORMANCE
  78         DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
  79         DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
  80         DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
  81         DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
  82         DRI_CONF_HYPERZ(false)
  83     DRI_CONF_SECTION_END
  84     DRI_CONF_SECTION_QUALITY
  85         DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
  86         DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
  87         DRI_CONF_NO_NEG_LOD_BIAS(false)
  88         DRI_CONF_FORCE_S3TC_ENABLE(false)
  89         DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
  90         DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
  91         DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
  92         DRI_CONF_ALLOW_LARGE_TEXTURES(2)
  93     DRI_CONF_SECTION_END
  94     DRI_CONF_SECTION_DEBUG
  95         DRI_CONF_NO_RAST(false)
  96     DRI_CONF_SECTION_END
  97 DRI_CONF_END;
  98 static const GLuint __driNConfigOptions = 14;
  99
 100 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
 101
 102 PUBLIC const char __driConfigOptions[] =
 103 DRI_CONF_BEGIN
 104     DRI_CONF_SECTION_PERFORMANCE
 105         DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
 106         DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
 107         DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
 108         DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
 109         DRI_CONF_HYPERZ(false)
 110     DRI_CONF_SECTION_END
 111     DRI_CONF_SECTION_QUALITY
 112         DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
 113         DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
 114         DRI_CONF_NO_NEG_LOD_BIAS(false)
 115         DRI_CONF_FORCE_S3TC_ENABLE(false)
 116         DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
 117         DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
 118         DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
 119         DRI_CONF_ALLOW_LARGE_TEXTURES(2)
 120         DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
 121     DRI_CONF_SECTION_END
 122     DRI_CONF_SECTION_DEBUG
 123         DRI_CONF_NO_RAST(false)
 124     DRI_CONF_SECTION_END
 125     DRI_CONF_SECTION_SOFTWARE
 126         DRI_CONF_NV_VERTEX_PROGRAM(false)
 127     DRI_CONF_SECTION_END
 128 DRI_CONF_END;
 129 static const GLuint __driNConfigOptions = 16;
 130
 131 extern const struct dri_extension blend_extensions[];
 132 extern const struct dri_extension ARB_vp_extension[];
 133 extern const struct dri_extension NV_vp_extension[];
 134 extern const struct dri_extension ATI_fs_extension[];
 135 extern const struct dri_extension point_extensions[];
 136
 137 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
 138
 139 /* TODO: integrate these into xmlpool.h! */
 140 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
 141 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
 142         DRI_CONF_DESC(en,"Number of texture image units") \
 143         DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
 144 DRI_CONF_OPT_END
 145
 146 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
 147 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
 148         DRI_CONF_DESC(en,"Number of texture coordinate units") \
 149         DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
 150 DRI_CONF_OPT_END
 151
 152 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
 153 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
 154         DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
 155         DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
 156 DRI_CONF_OPT_END
 157
 158 #define DRI_CONF_DISABLE_S3TC(def) \
 159 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
 160         DRI_CONF_DESC(en,"Disable S3TC compression") \
 161 DRI_CONF_OPT_END
 162
 163 #define DRI_CONF_DISABLE_FALLBACK(def) \
 164 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
 165         DRI_CONF_DESC(en,"Disable Low-impact fallback") \
 166 DRI_CONF_OPT_END
 167
 168 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
 169 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
 170         DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
 171 DRI_CONF_OPT_END
 172
 173 #define DRI_CONF_FP_OPTIMIZATION(def) \
 174 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
 175         DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
 176                 DRI_CONF_ENUM(0,"Optimize for Speed") \
 177                 DRI_CONF_ENUM(1,"Optimize for Quality") \
 178         DRI_CONF_DESC_END \
 179 DRI_CONF_OPT_END
 180
 181 PUBLIC const char __driConfigOptions[] =
 182 DRI_CONF_BEGIN
 183         DRI_CONF_SECTION_PERFORMANCE
 184                 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
 185                 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
 186                 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
 187                 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
 188                 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
 189                 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
 190                 DRI_CONF_DISABLE_FALLBACK(true)
 191                 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
 192         DRI_CONF_SECTION_END
 193         DRI_CONF_SECTION_QUALITY
 194                 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
 195                 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
 196                 DRI_CONF_FORCE_S3TC_ENABLE(false)
 197                 DRI_CONF_DISABLE_S3TC(false)
 198                 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
 199                 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
 200                 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
 201                 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
 202         DRI_CONF_SECTION_END
 203         DRI_CONF_SECTION_DEBUG
 204                 DRI_CONF_NO_RAST(false)
 205         DRI_CONF_SECTION_END
 206 DRI_CONF_END;
 207 static const GLuint __driNConfigOptions = 17;
 208
 209 extern const struct dri_extension gl_20_extension[];
 210
 211 #ifndef RADEON_DEBUG
 212 int RADEON_DEBUG = 0;
 213
 214 static const struct dri_debug_control debug_control[] = {
 215         {"fall", DEBUG_FALLBACKS},
 216         {"tex", DEBUG_TEXTURE},
 217         {"ioctl", DEBUG_IOCTL},
 218         {"prim", DEBUG_PRIMS},
 219         {"vert", DEBUG_VERTS},
 220         {"state", DEBUG_STATE},
 221         {"code", DEBUG_CODEGEN},
 222         {"vfmt", DEBUG_VFMT},
 223         {"vtxf", DEBUG_VFMT},
 224         {"verb", DEBUG_VERBOSE},
 225         {"dri", DEBUG_DRI},
 226         {"dma", DEBUG_DMA},
 227         {"san", DEBUG_SANITY},
 228         {"sync", DEBUG_SYNC},
 229         {"pix", DEBUG_PIXEL},
 230         {"mem", DEBUG_MEMORY},
 231         {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
 232         {NULL, 0}
 233 };
 234 #endif /* RADEON_DEBUG */
 235
 236 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
 237
 238 extern const struct dri_extension card_extensions[];
 239
 240 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
 241
 242 static int
 243 radeonGetParam(int fd, int param, void *value)
 244 {
 245   int ret;
 246   drm_radeon_getparam_t gp;
 247
 248   gp.param = param;
 249   gp.value = value;
 250
 251   ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
 252   return ret;
 253 }
 254
 255 static const __DRIconfig **
 256 radeonFillInModes( __DRIscreenPrivate *psp,
 257                    unsigned pixel_bits, unsigned depth_bits,
 258                    unsigned stencil_bits, GLboolean have_back_buffer )
 259 {
 260     __DRIconfig **configs;
 261     __GLcontextModes *m;
 262     unsigned depth_buffer_factor;
 263     unsigned back_buffer_factor;
 264     GLenum fb_format;
 265     GLenum fb_type;
 266     int i;
 267
 268     /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
 269      * enough to add support.  Basically, if a context is created with an
 270      * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
 271      * will never be used.
 272      */
 273     static const GLenum back_buffer_modes[] = {
 274         GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
 275     };
 276
 277     uint8_t depth_bits_array[2];
 278     uint8_t stencil_bits_array[2];
 279
 280
 281     depth_bits_array[0] = depth_bits;
 282     depth_bits_array[1] = depth_bits;
 283
 284     /* Just like with the accumulation buffer, always provide some modes
 285      * with a stencil buffer.  It will be a sw fallback, but some apps won't
 286      * care about that.
 287      */
 288     stencil_bits_array[0] = 0;
 289     stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
 290
 291     depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
 292     back_buffer_factor  = (have_back_buffer) ? 2 : 1;
 293
 294     if ( pixel_bits == 16 ) {
 295         fb_format = GL_RGB;
 296         fb_type = GL_UNSIGNED_SHORT_5_6_5;
 297     }
 298     else {
 299         fb_format = GL_BGRA;
 300         fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
 301     }
 302
 303     configs = driCreateConfigs(fb_format, fb_type,
 304                                depth_bits_array, stencil_bits_array,
 305                                depth_buffer_factor,
 306                                back_buffer_modes, back_buffer_factor);
 307     if (configs == NULL) {
 308         fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
 309                  __func__, __LINE__ );
 310         return NULL;
 311     }
 312
 313     /* Mark the visual as slow if there are "fake" stencil bits.
 314      */
 315     for (i = 0; configs[i]; i++) {
 316         m = &configs[i]->modes;
 317         if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
 318             m->visualRating = GLX_SLOW_CONFIG;
 319         }
 320     }
 321
 322     return (const __DRIconfig **) configs;
 323 }
 324
 325 #if !RADEON_COMMON
 326 static const __DRItexOffsetExtension radeonTexOffsetExtension = {
 327     { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
 328     radeonSetTexOffset,
 329 };
 330 #endif
 331
 332 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
 333 static const __DRIallocateExtension r200AllocateExtension = {
 334     { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
 335     r200AllocateMemoryMESA,
 336     r200FreeMemoryMESA,
 337     r200GetMemoryOffsetMESA
 338 };
 339
 340 static const __DRItexOffsetExtension r200texOffsetExtension = {
 341     { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
 342    r200SetTexOffset,
 343 };
 344 #endif
 345
 346 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
 347 static const __DRItexOffsetExtension r300texOffsetExtension = {
 348     { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
 349    r300SetTexOffset,
 350 };
 351 #endif
 352
 353 /* Create the device specific screen private data struct.
 354  */
 355 static radeonScreenPtr
 356 radeonCreateScreen( __DRIscreenPrivate *sPriv )
 357 {
 358    radeonScreenPtr screen;
 359    RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
 360    unsigned char *RADEONMMIO;
 361    int i;
 362    int ret;
 363    uint32_t temp;
 364
 365    if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
 366       fprintf(stderr,"\nERROR!  sizeof(RADEONDRIRec) does not match passed size from device driver\n");
 367       return GL_FALSE;
 368    }
 369
 370    /* Allocate the private area */
 371    screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
 372    if ( !screen ) {
 373       __driUtilMessage("%s: Could not allocate memory for screen structure",
 374                        __FUNCTION__);
 375       return NULL;
 376    }
 377
 378 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
 379         RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
 380 #endif
 381
 382    /* parse information in __driConfigOptions */
 383    driParseOptionInfo (&screen->optionCache,
 384                        __driConfigOptions, __driNConfigOptions);
 385
 386    /* This is first since which regions we map depends on whether or
 387     * not we are using a PCI card.
 388     */
 389    screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
 390    {
 391       int ret;
 392       ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET,
 393                             &screen->gart_buffer_offset);
 394
 395       if (ret) {
 396          FREE( screen );
 397          fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
 398          return NULL;
 399       }
 400
 401       ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE,
 402                             &screen->gart_base);
 403       if (ret) {
 404          FREE( screen );
 405          fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
 406          return NULL;
 407       }
 408
 409       ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
 410                             &screen->irq);
 411       if (ret) {
 412          FREE( screen );
 413          fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
 414          return NULL;
 415       }
 416       screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
 417       screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
 418       screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
 419       screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
 420       screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
 421       screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
 422       screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
 423    }
 424
 425    screen->mmio.handle = dri_priv->registerHandle;
 426    screen->mmio.size   = dri_priv->registerSize;
 427    if ( drmMap( sPriv->fd,
 428                 screen->mmio.handle,
 429                 screen->mmio.size,
 430                 &screen->mmio.map ) ) {
 431       FREE( screen );
 432       __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
 433       return NULL;
 434    }
 435
 436    RADEONMMIO = screen->mmio.map;
 437
 438    screen->status.handle = dri_priv->statusHandle;
 439    screen->status.size   = dri_priv->statusSize;
 440    if ( drmMap( sPriv->fd,
 441                 screen->status.handle,
 442                 screen->status.size,
 443                 &screen->status.map ) ) {
 444       drmUnmap( screen->mmio.map, screen->mmio.size );
 445       FREE( screen );
 446       __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
 447       return NULL;
 448    }
 449    screen->scratch = (__volatile__ uint32_t *)
 450       ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
 451
 452    screen->buffers = drmMapBufs( sPriv->fd );
 453    if ( !screen->buffers ) {
 454       drmUnmap( screen->status.map, screen->status.size );
 455       drmUnmap( screen->mmio.map, screen->mmio.size );
 456       FREE( screen );
 457       __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
 458       return NULL;
 459    }
 460
 461    if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
 462       screen->gartTextures.handle = dri_priv->gartTexHandle;
 463       screen->gartTextures.size   = dri_priv->gartTexMapSize;
 464       if ( drmMap( sPriv->fd,
 465                    screen->gartTextures.handle,
 466                    screen->gartTextures.size,
 467                    (drmAddressPtr)&screen->gartTextures.map ) ) {
 468          drmUnmapBufs( screen->buffers );
 469          drmUnmap( screen->status.map, screen->status.size );
 470          drmUnmap( screen->mmio.map, screen->mmio.size );
 471          FREE( screen );
 472          __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
 473          return NULL;
 474       }
 475
 476       screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
 477    }
 478
 479    screen->chip_flags = 0;
 480    /* XXX: add more chipsets */
 481    switch ( dri_priv->deviceID ) {
 482    case PCI_CHIP_RADEON_LY:
 483    case PCI_CHIP_RADEON_LZ:
 484    case PCI_CHIP_RADEON_QY:
 485    case PCI_CHIP_RADEON_QZ:
 486    case PCI_CHIP_RN50_515E:
 487    case PCI_CHIP_RN50_5969:
 488       screen->chip_family = CHIP_FAMILY_RV100;
 489       break;
 490
 491    case PCI_CHIP_RS100_4136:
 492    case PCI_CHIP_RS100_4336:
 493       screen->chip_family = CHIP_FAMILY_RS100;
 494       break;
 495
 496    case PCI_CHIP_RS200_4137:
 497    case PCI_CHIP_RS200_4337:
 498    case PCI_CHIP_RS250_4237:
 499    case PCI_CHIP_RS250_4437:
 500       screen->chip_family = CHIP_FAMILY_RS200;
 501       break;
 502
 503    case PCI_CHIP_RADEON_QD:
 504    case PCI_CHIP_RADEON_QE:
 505    case PCI_CHIP_RADEON_QF:
 506    case PCI_CHIP_RADEON_QG:
 507       /* all original radeons (7200) presumably have a stencil op bug */
 508       screen->chip_family = CHIP_FAMILY_R100;
 509       screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
 510       break;
 511
 512    case PCI_CHIP_RV200_QW:
 513    case PCI_CHIP_RV200_QX:
 514    case PCI_CHIP_RADEON_LW:
 515    case PCI_CHIP_RADEON_LX:
 516       screen->chip_family = CHIP_FAMILY_RV200;
 517       screen->chip_flags = RADEON_CHIPSET_TCL;
 518       break;
 519
 520    case PCI_CHIP_R200_BB:
 521    case PCI_CHIP_R200_BC:
 522    case PCI_CHIP_R200_QH:
 523    case PCI_CHIP_R200_QL:
 524    case PCI_CHIP_R200_QM:
 525       screen->chip_family = CHIP_FAMILY_R200;
 526       screen->chip_flags = RADEON_CHIPSET_TCL;
 527       break;
 528
 529    case PCI_CHIP_RV250_If:
 530    case PCI_CHIP_RV250_Ig:
 531    case PCI_CHIP_RV250_Ld:
 532    case PCI_CHIP_RV250_Lf:
 533    case PCI_CHIP_RV250_Lg:
 534       screen->chip_family = CHIP_FAMILY_RV250;
 535       screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
 536       break;
 537
 538    case PCI_CHIP_RV280_5960:
 539    case PCI_CHIP_RV280_5961:
 540    case PCI_CHIP_RV280_5962:
 541    case PCI_CHIP_RV280_5964:
 542    case PCI_CHIP_RV280_5965:
 543    case PCI_CHIP_RV280_5C61:
 544    case PCI_CHIP_RV280_5C63:
 545       screen->chip_family = CHIP_FAMILY_RV280;
 546       screen->chip_flags = RADEON_CHIPSET_TCL;
 547       break;
 548
 549    case PCI_CHIP_RS300_5834:
 550    case PCI_CHIP_RS300_5835:
 551    case PCI_CHIP_RS350_7834:
 552    case PCI_CHIP_RS350_7835:
 553       screen->chip_family = CHIP_FAMILY_RS300;
 554       break;
 555
 556       /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
 557    case PCI_CHIP_R300_AD:
 558       screen->chip_family = CHIP_FAMILY_RV350;
 559       screen->chip_flags = RADEON_CHIPSET_TCL;
 560       break;
 561    case PCI_CHIP_R300_AE:
 562    case PCI_CHIP_R300_AF:
 563    case PCI_CHIP_R300_AG:
 564    case PCI_CHIP_R300_ND:
 565    case PCI_CHIP_R300_NE:
 566    case PCI_CHIP_R300_NF:
 567    case PCI_CHIP_R300_NG:
 568       screen->chip_family = CHIP_FAMILY_R300;
 569       screen->chip_flags = RADEON_CHIPSET_TCL;
 570       break;
 571
 572    case PCI_CHIP_RV350_AP:
 573    case PCI_CHIP_RV350_AQ:
 574    case PCI_CHIP_RV350_AR:
 575    case PCI_CHIP_RV350_AS:
 576    case PCI_CHIP_RV350_AT:
 577    case PCI_CHIP_RV350_AV:
 578    case PCI_CHIP_RV350_AU:
 579    case PCI_CHIP_RV350_NP:
 580    case PCI_CHIP_RV350_NQ:
 581    case PCI_CHIP_RV350_NR:
 582    case PCI_CHIP_RV350_NS:
 583    case PCI_CHIP_RV350_NT:
 584    case PCI_CHIP_RV350_NV:
 585       screen->chip_family = CHIP_FAMILY_RV350;
 586       screen->chip_flags = RADEON_CHIPSET_TCL;
 587       break;
 588
 589    case PCI_CHIP_R350_AH:
 590    case PCI_CHIP_R350_AI:
 591    case PCI_CHIP_R350_AJ:
 592    case PCI_CHIP_R350_AK:
 593    case PCI_CHIP_R350_NH:
 594    case PCI_CHIP_R350_NI:
 595    case PCI_CHIP_R360_NJ:
 596    case PCI_CHIP_R350_NK:
 597       screen->chip_family = CHIP_FAMILY_R350;
 598       screen->chip_flags = RADEON_CHIPSET_TCL;
 599       break;
 600
 601    case PCI_CHIP_RV370_5460:
 602    case PCI_CHIP_RV370_5462:
 603    case PCI_CHIP_RV370_5464:
 604    case PCI_CHIP_RV370_5B60:
 605    case PCI_CHIP_RV370_5B62:
 606    case PCI_CHIP_RV370_5B63:
 607    case PCI_CHIP_RV370_5B64:
 608    case PCI_CHIP_RV370_5B65:
 609    case PCI_CHIP_RV380_3150:
 610    case PCI_CHIP_RV380_3152:
 611    case PCI_CHIP_RV380_3154:
 612    case PCI_CHIP_RV380_3E50:
 613    case PCI_CHIP_RV380_3E54:
 614       screen->chip_family = CHIP_FAMILY_RV380;
 615       screen->chip_flags = RADEON_CHIPSET_TCL;
 616       break;
 617
 618    case PCI_CHIP_R420_JN:
 619    case PCI_CHIP_R420_JH:
 620    case PCI_CHIP_R420_JI:
 621    case PCI_CHIP_R420_JJ:
 622    case PCI_CHIP_R420_JK:
 623    case PCI_CHIP_R420_JL:
 624    case PCI_CHIP_R420_JM:
 625    case PCI_CHIP_R420_JO:
 626    case PCI_CHIP_R420_JP:
 627    case PCI_CHIP_R420_JT:
 628    case PCI_CHIP_R481_4B49:
 629    case PCI_CHIP_R481_4B4A:
 630    case PCI_CHIP_R481_4B4B:
 631    case PCI_CHIP_R481_4B4C:
 632    case PCI_CHIP_R423_UH:
 633    case PCI_CHIP_R423_UI:
 634    case PCI_CHIP_R423_UJ:
 635    case PCI_CHIP_R423_UK:
 636    case PCI_CHIP_R430_554C:
 637    case PCI_CHIP_R430_554D:
 638    case PCI_CHIP_R430_554E:
 639    case PCI_CHIP_R430_554F:
 640    case PCI_CHIP_R423_5550:
 641    case PCI_CHIP_R423_UQ:
 642    case PCI_CHIP_R423_UR:
 643    case PCI_CHIP_R423_UT:
 644    case PCI_CHIP_R430_5D48:
 645    case PCI_CHIP_R430_5D49:
 646    case PCI_CHIP_R430_5D4A:
 647    case PCI_CHIP_R480_5D4C:
 648    case PCI_CHIP_R480_5D4D:
 649    case PCI_CHIP_R480_5D4E:
 650    case PCI_CHIP_R480_5D4F:
 651    case PCI_CHIP_R480_5D50:
 652    case PCI_CHIP_R480_5D52:
 653    case PCI_CHIP_R423_5D57:
 654       screen->chip_family = CHIP_FAMILY_R420;
 655       screen->chip_flags = RADEON_CHIPSET_TCL;
 656       break;
 657
 658    case PCI_CHIP_RV410_5E4C:
 659    case PCI_CHIP_RV410_5E4F:
 660    case PCI_CHIP_RV410_564A:
 661    case PCI_CHIP_RV410_564B:
 662    case PCI_CHIP_RV410_564F:
 663    case PCI_CHIP_RV410_5652:
 664    case PCI_CHIP_RV410_5653:
 665    case PCI_CHIP_RV410_5657:
 666    case PCI_CHIP_RV410_5E48:
 667    case PCI_CHIP_RV410_5E4A:
 668    case PCI_CHIP_RV410_5E4B:
 669    case PCI_CHIP_RV410_5E4D:
 670       screen->chip_family = CHIP_FAMILY_RV410;
 671       screen->chip_flags = RADEON_CHIPSET_TCL;
 672       break;
 673
 674    case PCI_CHIP_RS480_5954:
 675    case PCI_CHIP_RS480_5955:
 676    case PCI_CHIP_RS482_5974:
 677    case PCI_CHIP_RS482_5975:
 678    case PCI_CHIP_RS400_5A41:
 679    case PCI_CHIP_RS400_5A42:
 680    case PCI_CHIP_RC410_5A61:
 681    case PCI_CHIP_RC410_5A62:
 682       screen->chip_family = CHIP_FAMILY_RS400;
 683       break;
 684
 685    case PCI_CHIP_RS690_791E:
 686    case PCI_CHIP_RS690_791F:
 687       screen->chip_family = CHIP_FAMILY_RS690;
 688       break;
 689    case PCI_CHIP_RS740_796C:
 690    case PCI_CHIP_RS740_796D:
 691    case PCI_CHIP_RS740_796E:
 692    case PCI_CHIP_RS740_796F:
 693       screen->chip_family = CHIP_FAMILY_RS740;
 694       break;
 695
 696    case PCI_CHIP_R520_7100:
 697    case PCI_CHIP_R520_7101:
 698    case PCI_CHIP_R520_7102:
 699    case PCI_CHIP_R520_7103:
 700    case PCI_CHIP_R520_7104:
 701    case PCI_CHIP_R520_7105:
 702    case PCI_CHIP_R520_7106:
 703    case PCI_CHIP_R520_7108:
 704    case PCI_CHIP_R520_7109:
 705    case PCI_CHIP_R520_710A:
 706    case PCI_CHIP_R520_710B:
 707    case PCI_CHIP_R520_710C:
 708    case PCI_CHIP_R520_710E:
 709    case PCI_CHIP_R520_710F:
 710       screen->chip_family = CHIP_FAMILY_R520;
 711       screen->chip_flags = RADEON_CHIPSET_TCL;
 712       break;
 713
 714    case PCI_CHIP_RV515_7140:
 715    case PCI_CHIP_RV515_7141:
 716    case PCI_CHIP_RV515_7142:
 717    case PCI_CHIP_RV515_7143:
 718    case PCI_CHIP_RV515_7144:
 719    case PCI_CHIP_RV515_7145:
 720    case PCI_CHIP_RV515_7146:
 721    case PCI_CHIP_RV515_7147:
 722    case PCI_CHIP_RV515_7149:
 723    case PCI_CHIP_RV515_714A:
 724    case PCI_CHIP_RV515_714B:
 725    case PCI_CHIP_RV515_714C:
 726    case PCI_CHIP_RV515_714D:
 727    case PCI_CHIP_RV515_714E:
 728    case PCI_CHIP_RV515_714F:
 729    case PCI_CHIP_RV515_7151:
 730    case PCI_CHIP_RV515_7152:
 731    case PCI_CHIP_RV515_7153:
 732    case PCI_CHIP_RV515_715E:
 733    case PCI_CHIP_RV515_715F:
 734    case PCI_CHIP_RV515_7180:
 735    case PCI_CHIP_RV515_7181:
 736    case PCI_CHIP_RV515_7183:
 737    case PCI_CHIP_RV515_7186:
 738    case PCI_CHIP_RV515_7187:
 739    case PCI_CHIP_RV515_7188:
 740    case PCI_CHIP_RV515_718A:
 741    case PCI_CHIP_RV515_718B:
 742    case PCI_CHIP_RV515_718C:
 743    case PCI_CHIP_RV515_718D:
 744    case PCI_CHIP_RV515_718F:
 745    case PCI_CHIP_RV515_7193:
 746    case PCI_CHIP_RV515_7196:
 747    case PCI_CHIP_RV515_719B:
 748    case PCI_CHIP_RV515_719F:
 749    case PCI_CHIP_RV515_7200:
 750    case PCI_CHIP_RV515_7210:
 751    case PCI_CHIP_RV515_7211:
 752       screen->chip_family = CHIP_FAMILY_RV515;
 753       screen->chip_flags = RADEON_CHIPSET_TCL;
 754       break;
 755
 756    case PCI_CHIP_RV530_71C0:
 757    case PCI_CHIP_RV530_71C1:
 758    case PCI_CHIP_RV530_71C2:
 759    case PCI_CHIP_RV530_71C3:
 760    case PCI_CHIP_RV530_71C4:
 761    case PCI_CHIP_RV530_71C5:
 762    case PCI_CHIP_RV530_71C6:
 763    case PCI_CHIP_RV530_71C7:
 764    case PCI_CHIP_RV530_71CD:
 765    case PCI_CHIP_RV530_71CE:
 766    case PCI_CHIP_RV530_71D2:
 767    case PCI_CHIP_RV530_71D4:
 768    case PCI_CHIP_RV530_71D5:
 769    case PCI_CHIP_RV530_71D6:
 770    case PCI_CHIP_RV530_71DA:
 771    case PCI_CHIP_RV530_71DE:
 772       screen->chip_family = CHIP_FAMILY_RV530;
 773       screen->chip_flags = RADEON_CHIPSET_TCL;
 774       break;
 775
 776    case PCI_CHIP_R580_7240:
 777    case PCI_CHIP_R580_7243:
 778    case PCI_CHIP_R580_7244:
 779    case PCI_CHIP_R580_7245:
 780    case PCI_CHIP_R580_7246:
 781    case PCI_CHIP_R580_7247:
 782    case PCI_CHIP_R580_7248:
 783    case PCI_CHIP_R580_7249:
 784    case PCI_CHIP_R580_724A:
 785    case PCI_CHIP_R580_724B:
 786    case PCI_CHIP_R580_724C:
 787    case PCI_CHIP_R580_724D:
 788    case PCI_CHIP_R580_724E:
 789    case PCI_CHIP_R580_724F:
 790    case PCI_CHIP_R580_7284:
 791       screen->chip_family = CHIP_FAMILY_R580;
 792       screen->chip_flags = RADEON_CHIPSET_TCL;
 793       break;
 794
 795    case PCI_CHIP_RV570_7280:
 796    case PCI_CHIP_RV560_7281:
 797    case PCI_CHIP_RV560_7283:
 798    case PCI_CHIP_RV560_7287:
 799    case PCI_CHIP_RV570_7288:
 800    case PCI_CHIP_RV570_7289:
 801    case PCI_CHIP_RV570_728B:
 802    case PCI_CHIP_RV570_728C:
 803    case PCI_CHIP_RV560_7290:
 804    case PCI_CHIP_RV560_7291:
 805    case PCI_CHIP_RV560_7293:
 806    case PCI_CHIP_RV560_7297:
 807       screen->chip_family = CHIP_FAMILY_RV560;
 808       screen->chip_flags = RADEON_CHIPSET_TCL;
 809       break;
 810
 811    default:
 812       fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
 813               dri_priv->deviceID);
 814       return NULL;
 815    }
 816    if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
 817        sPriv->ddx_version.minor < 2) {
 818       fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
 819       return NULL;
 820    }
 821
 822    if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
 823       fprintf(stderr, "R500 support requires a newer drm.\n");
 824       return NULL;
 825    }
 826
 827    if (getenv("R300_NO_TCL"))
 828      screen->chip_flags &= ~RADEON_CHIPSET_TCL;
 829
 830    if (screen->chip_family <= CHIP_FAMILY_RS200)
 831       screen->chip_flags |= RADEON_CLASS_R100;
 832    else if (screen->chip_family <= CHIP_FAMILY_RV280)
 833       screen->chip_flags |= RADEON_CLASS_R200;
 834    else
 835       screen->chip_flags |= RADEON_CLASS_R300;
 836
 837    screen->cpp = dri_priv->bpp / 8;
 838    screen->AGPMode = dri_priv->AGPMode;
 839
 840    ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION,
 841                          &temp);
 842    if (ret) {
 843        if (screen->chip_family < CHIP_FAMILY_RS690)
 844            screen->fbLocation      = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
 845        else {
 846            FREE( screen );
 847            fprintf(stderr, "Unable to get fb location need newer drm\n");
 848            return NULL;
 849        }
 850    } else {
 851        screen->fbLocation = (temp & 0xffff) << 16;
 852    }
 853
 854    if (screen->chip_family >= CHIP_FAMILY_RV515) {
 855        ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES,
 856                              &temp);
 857        if (ret) {
 858            fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
 859            switch (screen->chip_family) {
 860            case CHIP_FAMILY_R300:
 861            case CHIP_FAMILY_R350:
 862                screen->num_gb_pipes = 2;
 863                break;
 864            case CHIP_FAMILY_R420:
 865            case CHIP_FAMILY_R520:
 866            case CHIP_FAMILY_R580:
 867            case CHIP_FAMILY_RV560:
 868            case CHIP_FAMILY_RV570:
 869                screen->num_gb_pipes = 4;
 870                break;
 871            case CHIP_FAMILY_RV350:
 872            case CHIP_FAMILY_RV515:
 873            case CHIP_FAMILY_RV530:
 874            case CHIP_FAMILY_RV410:
 875            default:
 876                screen->num_gb_pipes = 1;
 877                break;
 878            }
 879        } else {
 880            screen->num_gb_pipes = temp;
 881        }
 882    }
 883
 884    if ( sPriv->drm_version.minor >= 10 ) {
 885       drm_radeon_setparam_t sp;
 886
 887       sp.param = RADEON_SETPARAM_FB_LOCATION;
 888       sp.value = screen->fbLocation;
 889
 890       drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
 891                        &sp, sizeof( sp ) );
 892    }
 893
 894    screen->frontOffset  = dri_priv->frontOffset;
 895    screen->frontPitch   = dri_priv->frontPitch;
 896    screen->backOffset   = dri_priv->backOffset;
 897    screen->backPitch    = dri_priv->backPitch;
 898    screen->depthOffset  = dri_priv->depthOffset;
 899    screen->depthPitch   = dri_priv->depthPitch;
 900
 901    /* Check if ddx has set up a surface reg to cover depth buffer */
 902    screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
 903       /* these chips don't use tiled z without hyperz. So always pretend
 904          we have set up a surface which will cause linear reads/writes */
 905       (IS_R100_CLASS(screen) &&
 906       !(screen->chip_flags & RADEON_CHIPSET_TCL));
 907
 908    if ( dri_priv->textureSize == 0 ) {
 909       screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
 910       screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
 911       screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
 912          dri_priv->log2GARTTexGran;
 913    } else {
 914       screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
 915                                                + screen->fbLocation;
 916       screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
 917       screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
 918          dri_priv->log2TexGran;
 919    }
 920
 921    if ( !screen->gartTextures.map || dri_priv->textureSize == 0
 922         || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
 923       screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
 924       screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
 925       screen->texSize[RADEON_GART_TEX_HEAP] = 0;
 926       screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
 927    } else {
 928       screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
 929       screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
 930       screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
 931       screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
 932          dri_priv->log2GARTTexGran;
 933    }
 934
 935    i = 0;
 936    screen->extensions[i++] = &driCopySubBufferExtension.base;
 937    screen->extensions[i++] = &driFrameTrackingExtension.base;
 938    screen->extensions[i++] = &driReadDrawableExtension;
 939
 940    if ( screen->irq != 0 ) {
 941        screen->extensions[i++] = &driSwapControlExtension.base;
 942        screen->extensions[i++] = &driMediaStreamCounterExtension.base;
 943    }
 944
 945 #if !RADEON_COMMON
 946    screen->extensions[i++] = &radeonTexOffsetExtension.base;
 947 #endif
 948
 949 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
 950    if (IS_R200_CLASS(screen))
 951        screen->extensions[i++] = &r200AllocateExtension.base;
 952
 953    screen->extensions[i++] = &r200texOffsetExtension.base;
 954 #endif
 955
 956 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
 957    screen->extensions[i++] = &r300texOffsetExtension.base;
 958 #endif
 959
 960    screen->extensions[i++] = NULL;
 961    sPriv->extensions = screen->extensions;
 962
 963    screen->driScreen = sPriv;
 964    screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
 965    return screen;
 966 }
 967
 968 /* Destroy the device specific screen private data struct.
 969  */
 970 static void
 971 radeonDestroyScreen( __DRIscreenPrivate *sPriv )
 972 {
 973    radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
 974
 975    if (!screen)
 976       return;
 977
 978    if ( screen->gartTextures.map ) {
 979       drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
 980    }
 981    drmUnmapBufs( screen->buffers );
 982    drmUnmap( screen->status.map, screen->status.size );
 983    drmUnmap( screen->mmio.map, screen->mmio.size );
 984
 985    /* free all option information */
 986    driDestroyOptionInfo (&screen->optionCache);
 987
 988    FREE( screen );
 989    sPriv->private = NULL;
 990 }
 991
 992
 993 /* Initialize the driver specific screen private data.
 994  */
 995 static GLboolean
 996 radeonInitDriver( __DRIscreenPrivate *sPriv )
 997 {
 998    sPriv->private = (void *) radeonCreateScreen( sPriv );
 999    if ( !sPriv->private ) {
1000       radeonDestroyScreen( sPriv );
1001       return GL_FALSE;
1002    }
1003
1004    return GL_TRUE;
1005 }
1006
1007
1008 /**
1009  * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1010  *
1011  * \todo This function (and its interface) will need to be updated to support
1012  * pbuffers.
1013  */
1014 static GLboolean
1015 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
1016                     __DRIdrawablePrivate *driDrawPriv,
1017                     const __GLcontextModes *mesaVis,
1018                     GLboolean isPixmap )
1019 {
1020    radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1021
1022    if (isPixmap) {
1023       return GL_FALSE; /* not implemented */
1024    }
1025    else {
1026       const GLboolean swDepth = GL_FALSE;
1027       const GLboolean swAlpha = GL_FALSE;
1028       const GLboolean swAccum = mesaVis->accumRedBits > 0;
1029       const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1030          mesaVis->depthBits != 24;
1031       struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
1032
1033       /* front color renderbuffer */
1034       {
1035          driRenderbuffer *frontRb
1036             = driNewRenderbuffer(GL_RGBA,
1037                                  driScrnPriv->pFB + screen->frontOffset,
1038                                  screen->cpp,
1039                                  screen->frontOffset, screen->frontPitch,
1040                                  driDrawPriv);
1041          radeonSetSpanFunctions(frontRb, mesaVis);
1042          _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
1043       }
1044
1045       /* back color renderbuffer */
1046       if (mesaVis->doubleBufferMode) {
1047          driRenderbuffer *backRb
1048             = driNewRenderbuffer(GL_RGBA,
1049                                  driScrnPriv->pFB + screen->backOffset,
1050                                  screen->cpp,
1051                                  screen->backOffset, screen->backPitch,
1052                                  driDrawPriv);
1053          radeonSetSpanFunctions(backRb, mesaVis);
1054          _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
1055       }
1056
1057       /* depth renderbuffer */
1058       if (mesaVis->depthBits == 16) {
1059          driRenderbuffer *depthRb
1060             = driNewRenderbuffer(GL_DEPTH_COMPONENT16,
1061                                  driScrnPriv->pFB + screen->depthOffset,
1062                                  screen->cpp,
1063                                  screen->depthOffset, screen->depthPitch,
1064                                  driDrawPriv);
1065          radeonSetSpanFunctions(depthRb, mesaVis);
1066          _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
1067          depthRb->depthHasSurface = screen->depthHasSurface;
1068       }
1069       else if (mesaVis->depthBits == 24) {
1070          driRenderbuffer *depthRb
1071             = driNewRenderbuffer(GL_DEPTH_COMPONENT24,
1072                                  driScrnPriv->pFB + screen->depthOffset,
1073                                  screen->cpp,
1074                                  screen->depthOffset, screen->depthPitch,
1075                                  driDrawPriv);
1076          radeonSetSpanFunctions(depthRb, mesaVis);
1077          _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
1078          depthRb->depthHasSurface = screen->depthHasSurface;
1079       }
1080
1081       /* stencil renderbuffer */
1082       if (mesaVis->stencilBits > 0 && !swStencil) {
1083          driRenderbuffer *stencilRb
1084             = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT,
1085                                  driScrnPriv->pFB + screen->depthOffset,
1086                                  screen->cpp,
1087                                  screen->depthOffset, screen->depthPitch,
1088                                  driDrawPriv);
1089          radeonSetSpanFunctions(stencilRb, mesaVis);
1090          _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
1091          stencilRb->depthHasSurface = screen->depthHasSurface;
1092       }
1093
1094       _mesa_add_soft_renderbuffers(fb,
1095                                    GL_FALSE, /* color */
1096                                    swDepth,
1097                                    swStencil,
1098                                    swAccum,
1099                                    swAlpha,
1100                                    GL_FALSE /* aux */);
1101       driDrawPriv->driverPrivate = (void *) fb;
1102
1103       return (driDrawPriv->driverPrivate != NULL);
1104    }
1105 }
1106
1107
1108 static void
1109 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
1110 {
1111    _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)));
1112 }
1113
1114 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1115 /**
1116  * Choose the appropriate CreateContext function based on the chipset.
1117  * Eventually, all drivers will go through this process.
1118  */
1119 static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
1120                                      __DRIcontextPrivate * driContextPriv,
1121                                      void *sharedContextPriv)
1122 {
1123         __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
1124         radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
1125
1126         if (IS_R300_CLASS(screen))
1127                 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
1128         return GL_FALSE;
1129 }
1130
1131 /**
1132  * Choose the appropriate DestroyContext function based on the chipset.
1133  */
1134 static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
1135 {
1136         radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
1137
1138         if (IS_R300_CLASS(radeon->radeonScreen))
1139                 return r300DestroyContext(driContextPriv);
1140 }
1141
1142
1143 #endif
1144
1145
1146 /**
1147  * This is the driver specific part of the createNewScreen entry point.
1148  *
1149  * \todo maybe fold this into intelInitDriver
1150  *
1151  * \return the __GLcontextModes supported by this driver
1152  */
1153 static const __DRIconfig **
1154 radeonInitScreen(__DRIscreenPrivate *psp)
1155 {
1156 #if !RADEON_COMMON
1157    static const char *driver_name = "Radeon";
1158    static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1159    static const __DRIversion dri_expected = { 4, 0, 0 };
1160    static const __DRIversion drm_expected = { 1, 6, 0 };
1161 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1162    static const char *driver_name = "R200";
1163    static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1164    static const __DRIversion dri_expected = { 4, 0, 0 };
1165    static const __DRIversion drm_expected = { 1, 6, 0 };
1166 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1167    static const char *driver_name = "R300";
1168    static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1169    static const __DRIversion dri_expected = { 4, 0, 0 };
1170    static const __DRIversion drm_expected = { 1, 24, 0 };
1171 #endif
1172    RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1173
1174    if ( ! driCheckDriDdxDrmVersions3( driver_name,
1175                                       &psp->dri_version, & dri_expected,
1176                                       &psp->ddx_version, & ddx_expected,
1177                                       &psp->drm_version, & drm_expected ) ) {
1178       return NULL;
1179    }
1180
1181    /* Calling driInitExtensions here, with a NULL context pointer,
1182     * does not actually enable the extensions.  It just makes sure
1183     * that all the dispatch offsets for all the extensions that
1184     * *might* be enables are known.  This is needed because the
1185     * dispatch offsets need to be known when _mesa_context_create
1186     * is called, but we can't enable the extensions until we have a
1187     * context pointer.
1188     *
1189     * Hello chicken.  Hello egg.  How are you two today?
1190     */
1191    driInitExtensions( NULL, card_extensions, GL_FALSE );
1192 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1193    driInitExtensions( NULL, blend_extensions, GL_FALSE );
1194    driInitSingleExtension( NULL, ARB_vp_extension );
1195    driInitSingleExtension( NULL, NV_vp_extension );
1196    driInitSingleExtension( NULL, ATI_fs_extension );
1197    driInitExtensions( NULL, point_extensions, GL_FALSE );
1198 #elif defined(RADEON_COMMON_FOR_R300)
1199    driInitSingleExtension( NULL, gl_20_extension );
1200 #endif
1201
1202    if (!radeonInitDriver(psp))
1203        return NULL;
1204
1205    return radeonFillInModes( psp,
1206                              dri_priv->bpp,
1207                              (dri_priv->bpp == 16) ? 16 : 24,
1208                              (dri_priv->bpp == 16) ? 0  : 8,
1209                              (dri_priv->backOffset != dri_priv->depthOffset) );
1210 }
1211
1212
1213 /**
1214  * Get information about previous buffer swaps.
1215  */
1216 static int
1217 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1218 {
1219 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1220    radeonContextPtr  rmesa;
1221 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1222    r200ContextPtr  rmesa;
1223 #endif
1224
1225    if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1226         || (dPriv->driContextPriv->driverPrivate == NULL)
1227         || (sInfo == NULL) ) {
1228       return -1;
1229    }
1230
1231    rmesa = dPriv->driContextPriv->driverPrivate;
1232    sInfo->swap_count = rmesa->swap_count;
1233    sInfo->swap_ust = rmesa->swap_ust;
1234    sInfo->swap_missed_count = rmesa->swap_missed_count;
1235
1236    sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1237        ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
1238        : 0.0;
1239
1240    return 0;
1241 }
1242
1243 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1244 const struct __DriverAPIRec driDriverAPI = {
1245    .InitScreen      = radeonInitScreen,
1246    .DestroyScreen   = radeonDestroyScreen,
1247    .CreateContext   = radeonCreateContext,
1248    .DestroyContext  = radeonDestroyContext,
1249    .CreateBuffer    = radeonCreateBuffer,
1250    .DestroyBuffer   = radeonDestroyBuffer,
1251    .SwapBuffers     = radeonSwapBuffers,
1252    .MakeCurrent     = radeonMakeCurrent,
1253    .UnbindContext   = radeonUnbindContext,
1254    .GetSwapInfo     = getSwapInfo,
1255    .GetDrawableMSC  = driDrawableGetMSC32,
1256    .WaitForMSC      = driWaitForMSC32,
1257    .WaitForSBC      = NULL,
1258    .SwapBuffersMSC  = NULL,
1259    .CopySubBuffer   = radeonCopySubBuffer,
1260 };
1261 #else
1262 const struct __DriverAPIRec driDriverAPI = {
1263    .InitScreen      = radeonInitScreen,
1264    .DestroyScreen   = radeonDestroyScreen,
1265    .CreateContext   = r200CreateContext,
1266    .DestroyContext  = r200DestroyContext,
1267    .CreateBuffer    = radeonCreateBuffer,
1268    .DestroyBuffer   = radeonDestroyBuffer,
1269    .SwapBuffers     = r200SwapBuffers,
1270    .MakeCurrent     = r200MakeCurrent,
1271    .UnbindContext   = r200UnbindContext,
1272    .GetSwapInfo     = getSwapInfo,
1273    .GetDrawableMSC  = driDrawableGetMSC32,
1274    .WaitForMSC      = driWaitForMSC32,
1275    .WaitForSBC      = NULL,
1276    .SwapBuffersMSC  = NULL,
1277    .CopySubBuffer   = r200CopySubBuffer,
1278 };
1279 #endif