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Merge remote branch 'origin/master' into pipe-video
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
36 */
37
38 #include <errno.h>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
44 #include "main/fbobject.h"
45
46 #define STANDALONE_MMIO
47 #include "radeon_chipset.h"
48 #include "radeon_macros.h"
49 #include "radeon_screen.h"
50 #include "radeon_common.h"
51 #include "radeon_common_context.h"
52 #if defined(RADEON_R100)
53 #include "radeon_context.h"
54 #include "radeon_tex.h"
55 #elif defined(RADEON_R200)
56 #include "r200_context.h"
57 #include "r200_tex.h"
58 #elif defined(RADEON_R300)
59 #include "r300_context.h"
60 #include "r300_tex.h"
61 #elif defined(RADEON_R600)
62 #include "r600_context.h"
63 #include "r700_driconf.h" /* +r6/r7 */
64 #include "r600_tex.h" /* +r6/r7 */
65 #endif
66
67 #include "utils.h"
68 #include "vblank.h"
69
70 #include "radeon_bocs_wrapper.h"
71
72 #include "GL/internal/dri_interface.h"
73
74 /* Radeon configuration
75 */
76 #include "xmlpool.h"
77
78 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
79 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
80 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
81 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
82 DRI_CONF_OPT_END
83
84 #if defined(RADEON_R100) /* R100 */
85 PUBLIC const char __driConfigOptions[] =
86 DRI_CONF_BEGIN
87 DRI_CONF_SECTION_PERFORMANCE
88 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
89 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
90 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
91 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
92 DRI_CONF_HYPERZ(false)
93 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
94 DRI_CONF_SECTION_END
95 DRI_CONF_SECTION_QUALITY
96 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
97 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
98 DRI_CONF_NO_NEG_LOD_BIAS(false)
99 DRI_CONF_FORCE_S3TC_ENABLE(false)
100 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
101 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
102 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
103 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
104 DRI_CONF_SECTION_END
105 DRI_CONF_SECTION_DEBUG
106 DRI_CONF_NO_RAST(false)
107 DRI_CONF_SECTION_END
108 DRI_CONF_END;
109 static const GLuint __driNConfigOptions = 15;
110
111 #elif defined(RADEON_R200)
112
113 PUBLIC const char __driConfigOptions[] =
114 DRI_CONF_BEGIN
115 DRI_CONF_SECTION_PERFORMANCE
116 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
117 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
118 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
119 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
120 DRI_CONF_HYPERZ(false)
121 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
122 DRI_CONF_SECTION_END
123 DRI_CONF_SECTION_QUALITY
124 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
125 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
126 DRI_CONF_NO_NEG_LOD_BIAS(false)
127 DRI_CONF_FORCE_S3TC_ENABLE(false)
128 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
129 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
130 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
131 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
132 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
133 DRI_CONF_SECTION_END
134 DRI_CONF_SECTION_DEBUG
135 DRI_CONF_NO_RAST(false)
136 DRI_CONF_SECTION_END
137 DRI_CONF_SECTION_SOFTWARE
138 DRI_CONF_NV_VERTEX_PROGRAM(false)
139 DRI_CONF_SECTION_END
140 DRI_CONF_END;
141 static const GLuint __driNConfigOptions = 17;
142
143 #elif defined(RADEON_R300) || defined(RADEON_R600)
144
145 #define DRI_CONF_FP_OPTIMIZATION_SPEED 0
146 #define DRI_CONF_FP_OPTIMIZATION_QUALITY 1
147
148 /* TODO: integrate these into xmlpool.h! */
149 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
150 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
151 DRI_CONF_DESC(en,"Number of texture image units") \
152 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
153 DRI_CONF_OPT_END
154
155 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
156 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
157 DRI_CONF_DESC(en,"Number of texture coordinate units") \
158 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
159 DRI_CONF_OPT_END
160
161
162
163 #define DRI_CONF_DISABLE_S3TC(def) \
164 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
165 DRI_CONF_DESC(en,"Disable S3TC compression") \
166 DRI_CONF_OPT_END
167
168 #define DRI_CONF_DISABLE_FALLBACK(def) \
169 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
170 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
171 DRI_CONF_OPT_END
172
173 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
174 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
175 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
176 DRI_CONF_OPT_END
177
178 #define DRI_CONF_FP_OPTIMIZATION(def) \
179 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
180 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
181 DRI_CONF_ENUM(0,"Optimize for Speed") \
182 DRI_CONF_ENUM(1,"Optimize for Quality") \
183 DRI_CONF_DESC_END \
184 DRI_CONF_OPT_END
185
186 PUBLIC const char __driConfigOptions[] =
187 DRI_CONF_BEGIN
188 DRI_CONF_SECTION_PERFORMANCE
189 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
190 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
191 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
192 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
193 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
194 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
195 DRI_CONF_DISABLE_FALLBACK(true)
196 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
197 DRI_CONF_SECTION_END
198 DRI_CONF_SECTION_QUALITY
199 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
200 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
201 DRI_CONF_FORCE_S3TC_ENABLE(false)
202 DRI_CONF_DISABLE_S3TC(false)
203 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
204 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
205 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
206 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
207 DRI_CONF_SECTION_END
208 DRI_CONF_SECTION_DEBUG
209 DRI_CONF_NO_RAST(false)
210 DRI_CONF_SECTION_END
211 DRI_CONF_END;
212 static const GLuint __driNConfigOptions = 17;
213
214 #endif
215
216 static int getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo );
217
218 #ifndef RADEON_INFO_TILE_CONFIG
219 #define RADEON_INFO_TILE_CONFIG 0x6
220 #endif
221
222 static int
223 radeonGetParam(__DRIscreen *sPriv, int param, void *value)
224 {
225 int ret;
226 drm_radeon_getparam_t gp = { 0 };
227 struct drm_radeon_info info = { 0 };
228
229 if (sPriv->drm_version.major >= 2) {
230 info.value = (uint64_t)(uintptr_t)value;
231 switch (param) {
232 case RADEON_PARAM_DEVICE_ID:
233 info.request = RADEON_INFO_DEVICE_ID;
234 break;
235 case RADEON_PARAM_NUM_GB_PIPES:
236 info.request = RADEON_INFO_NUM_GB_PIPES;
237 break;
238 case RADEON_PARAM_NUM_Z_PIPES:
239 info.request = RADEON_INFO_NUM_Z_PIPES;
240 break;
241 case RADEON_INFO_TILE_CONFIG:
242 info.request = RADEON_INFO_TILE_CONFIG;
243 break;
244 default:
245 return -EINVAL;
246 }
247 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info));
248 } else {
249 gp.param = param;
250 gp.value = value;
251
252 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
253 }
254 return ret;
255 }
256
257 static const __DRIconfig **
258 radeonFillInModes( __DRIscreen *psp,
259 unsigned pixel_bits, unsigned depth_bits,
260 unsigned stencil_bits, GLboolean have_back_buffer )
261 {
262 __DRIconfig **configs;
263 struct gl_config *m;
264 unsigned depth_buffer_factor;
265 unsigned back_buffer_factor;
266 int i;
267
268 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
269 * enough to add support. Basically, if a context is created with an
270 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
271 * will never be used.
272 */
273 static const GLenum back_buffer_modes[] = {
274 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
275 };
276
277 uint8_t depth_bits_array[2];
278 uint8_t stencil_bits_array[2];
279 uint8_t msaa_samples_array[1];
280
281 depth_bits_array[0] = depth_bits;
282 depth_bits_array[1] = depth_bits;
283
284 /* Just like with the accumulation buffer, always provide some modes
285 * with a stencil buffer. It will be a sw fallback, but some apps won't
286 * care about that.
287 */
288 stencil_bits_array[0] = stencil_bits;
289 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
290
291 msaa_samples_array[0] = 0;
292
293 depth_buffer_factor = (stencil_bits == 0) ? 2 : 1;
294 back_buffer_factor = (have_back_buffer) ? 2 : 1;
295
296 if (pixel_bits == 16) {
297 __DRIconfig **configs_a8r8g8b8;
298 __DRIconfig **configs_r5g6b5;
299
300 configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5,
301 depth_bits_array, stencil_bits_array,
302 depth_buffer_factor, back_buffer_modes,
303 back_buffer_factor, msaa_samples_array,
304 1, GL_TRUE);
305 configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
306 depth_bits_array, stencil_bits_array,
307 1, back_buffer_modes, 1,
308 msaa_samples_array, 1, GL_TRUE);
309 configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8);
310 } else
311 configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
312 depth_bits_array, stencil_bits_array,
313 depth_buffer_factor,
314 back_buffer_modes, back_buffer_factor,
315 msaa_samples_array, 1, GL_TRUE);
316
317 if (configs == NULL) {
318 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
319 __func__, __LINE__ );
320 return NULL;
321 }
322
323 /* Mark the visual as slow if there are "fake" stencil bits.
324 */
325 for (i = 0; configs[i]; i++) {
326 m = &configs[i]->modes;
327 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
328 m->visualRating = GLX_SLOW_CONFIG;
329 }
330 }
331
332 return (const __DRIconfig **) configs;
333 }
334
335 #if defined(RADEON_R100)
336 static const __DRItexOffsetExtension radeonTexOffsetExtension = {
337 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
338 radeonSetTexOffset,
339 };
340
341 static const __DRItexBufferExtension radeonTexBufferExtension = {
342 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
343 radeonSetTexBuffer,
344 radeonSetTexBuffer2,
345 };
346 #endif
347
348 #if defined(RADEON_R200)
349
350 static const __DRItexOffsetExtension r200texOffsetExtension = {
351 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
352 r200SetTexOffset,
353 };
354
355 static const __DRItexBufferExtension r200TexBufferExtension = {
356 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
357 r200SetTexBuffer,
358 r200SetTexBuffer2,
359 };
360 #endif
361
362 #if defined(RADEON_R300)
363 static const __DRItexOffsetExtension r300texOffsetExtension = {
364 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
365 r300SetTexOffset,
366 };
367
368 static const __DRItexBufferExtension r300TexBufferExtension = {
369 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
370 r300SetTexBuffer,
371 r300SetTexBuffer2,
372 };
373 #endif
374
375 #if defined(RADEON_R600)
376 static const __DRItexOffsetExtension r600texOffsetExtension = {
377 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
378 r600SetTexOffset, /* +r6/r7 */
379 };
380
381 static const __DRItexBufferExtension r600TexBufferExtension = {
382 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
383 r600SetTexBuffer, /* +r6/r7 */
384 r600SetTexBuffer2, /* +r6/r7 */
385 };
386 #endif
387
388 static void
389 radeonDRI2Flush(__DRIdrawable *drawable)
390 {
391 radeonContextPtr rmesa;
392
393 rmesa = (radeonContextPtr) drawable->driContextPriv->driverPrivate;
394 radeonFlush(rmesa->glCtx);
395 }
396
397 static const struct __DRI2flushExtensionRec radeonFlushExtension = {
398 { __DRI2_FLUSH, __DRI2_FLUSH_VERSION },
399 radeonDRI2Flush,
400 dri2InvalidateDrawable,
401 };
402
403 static __DRIimage *
404 radeon_create_image_from_name(__DRIcontext *context,
405 int width, int height, int format,
406 int name, int pitch, void *loaderPrivate)
407 {
408 __DRIimage *image;
409 radeonContextPtr radeon = context->driverPrivate;
410
411 if (name == 0)
412 return NULL;
413
414 image = CALLOC(sizeof *image);
415 if (image == NULL)
416 return NULL;
417
418 switch (format) {
419 case __DRI_IMAGE_FORMAT_RGB565:
420 image->format = MESA_FORMAT_RGB565;
421 image->internal_format = GL_RGB;
422 image->data_type = GL_UNSIGNED_BYTE;
423 break;
424 case __DRI_IMAGE_FORMAT_XRGB8888:
425 image->format = MESA_FORMAT_XRGB8888;
426 image->internal_format = GL_RGB;
427 image->data_type = GL_UNSIGNED_BYTE;
428 break;
429 case __DRI_IMAGE_FORMAT_ARGB8888:
430 image->format = MESA_FORMAT_ARGB8888;
431 image->internal_format = GL_RGBA;
432 image->data_type = GL_UNSIGNED_BYTE;
433 break;
434 default:
435 free(image);
436 return NULL;
437 }
438
439 image->data = loaderPrivate;
440 image->cpp = _mesa_get_format_bytes(image->format);
441 image->width = width;
442 image->pitch = pitch;
443 image->height = height;
444
445 image->bo = radeon_bo_open(radeon->radeonScreen->bom,
446 (uint32_t)name,
447 image->pitch * image->height * image->cpp,
448 0,
449 RADEON_GEM_DOMAIN_VRAM,
450 0);
451
452 if (image->bo == NULL) {
453 FREE(image);
454 return NULL;
455 }
456
457 return image;
458 }
459
460 static __DRIimage *
461 radeon_create_image_from_renderbuffer(__DRIcontext *context,
462 int renderbuffer, void *loaderPrivate)
463 {
464 __DRIimage *image;
465 radeonContextPtr radeon = context->driverPrivate;
466 struct gl_renderbuffer *rb;
467 struct radeon_renderbuffer *rrb;
468
469 rb = _mesa_lookup_renderbuffer(radeon->glCtx, renderbuffer);
470 if (!rb) {
471 _mesa_error(radeon->glCtx,
472 GL_INVALID_OPERATION, "glRenderbufferExternalMESA");
473 return NULL;
474 }
475
476 rrb = radeon_renderbuffer(rb);
477 image = CALLOC(sizeof *image);
478 if (image == NULL)
479 return NULL;
480
481 image->internal_format = rb->InternalFormat;
482 image->format = rb->Format;
483 image->cpp = rrb->cpp;
484 image->data_type = rb->DataType;
485 image->data = loaderPrivate;
486 radeon_bo_ref(rrb->bo);
487 image->bo = rrb->bo;
488
489 image->width = rb->Width;
490 image->height = rb->Height;
491 image->pitch = rrb->pitch / image->cpp;
492
493 return image;
494 }
495
496 static void
497 radeon_destroy_image(__DRIimage *image)
498 {
499 radeon_bo_unref(image->bo);
500 FREE(image);
501 }
502
503 static __DRIimage *
504 radeon_create_image(__DRIscreen *screen,
505 int width, int height, int format,
506 unsigned int use,
507 void *loaderPrivate)
508 {
509 __DRIimage *image;
510 radeonScreenPtr radeonScreen = screen->private;
511
512 image = CALLOC(sizeof *image);
513 if (image == NULL)
514 return NULL;
515
516 switch (format) {
517 case __DRI_IMAGE_FORMAT_RGB565:
518 image->format = MESA_FORMAT_RGB565;
519 image->internal_format = GL_RGB;
520 image->data_type = GL_UNSIGNED_BYTE;
521 break;
522 case __DRI_IMAGE_FORMAT_XRGB8888:
523 image->format = MESA_FORMAT_XRGB8888;
524 image->internal_format = GL_RGB;
525 image->data_type = GL_UNSIGNED_BYTE;
526 break;
527 case __DRI_IMAGE_FORMAT_ARGB8888:
528 image->format = MESA_FORMAT_ARGB8888;
529 image->internal_format = GL_RGBA;
530 image->data_type = GL_UNSIGNED_BYTE;
531 break;
532 default:
533 free(image);
534 return NULL;
535 }
536
537 image->data = loaderPrivate;
538 image->cpp = _mesa_get_format_bytes(image->format);
539 image->width = width;
540 image->height = height;
541 image->pitch = ((image->cpp * image->width + 255) & ~255) / image->cpp;
542
543 image->bo = radeon_bo_open(radeonScreen->bom,
544 0,
545 image->pitch * image->height * image->cpp,
546 0,
547 RADEON_GEM_DOMAIN_VRAM,
548 0);
549
550 if (image->bo == NULL) {
551 FREE(image);
552 return NULL;
553 }
554
555 return image;
556 }
557
558 static GLboolean
559 radeon_query_image(__DRIimage *image, int attrib, int *value)
560 {
561 switch (attrib) {
562 case __DRI_IMAGE_ATTRIB_STRIDE:
563 *value = image->pitch * image->cpp;
564 return GL_TRUE;
565 case __DRI_IMAGE_ATTRIB_HANDLE:
566 *value = image->bo->handle;
567 return GL_TRUE;
568 case __DRI_IMAGE_ATTRIB_NAME:
569 radeon_gem_get_kernel_name(image->bo, (uint32_t *) value);
570 return GL_TRUE;
571 default:
572 return GL_FALSE;
573 }
574 }
575
576 static struct __DRIimageExtensionRec radeonImageExtension = {
577 { __DRI_IMAGE, __DRI_IMAGE_VERSION },
578 radeon_create_image_from_name,
579 radeon_create_image_from_renderbuffer,
580 radeon_destroy_image,
581 radeon_create_image,
582 radeon_query_image
583 };
584
585 static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
586 {
587 screen->device_id = device_id;
588 screen->chip_flags = 0;
589 switch ( device_id ) {
590 case PCI_CHIP_RN50_515E:
591 case PCI_CHIP_RN50_5969:
592 return -1;
593
594 case PCI_CHIP_RADEON_LY:
595 case PCI_CHIP_RADEON_LZ:
596 case PCI_CHIP_RADEON_QY:
597 case PCI_CHIP_RADEON_QZ:
598 screen->chip_family = CHIP_FAMILY_RV100;
599 break;
600
601 case PCI_CHIP_RS100_4136:
602 case PCI_CHIP_RS100_4336:
603 screen->chip_family = CHIP_FAMILY_RS100;
604 break;
605
606 case PCI_CHIP_RS200_4137:
607 case PCI_CHIP_RS200_4337:
608 case PCI_CHIP_RS250_4237:
609 case PCI_CHIP_RS250_4437:
610 screen->chip_family = CHIP_FAMILY_RS200;
611 break;
612
613 case PCI_CHIP_RADEON_QD:
614 case PCI_CHIP_RADEON_QE:
615 case PCI_CHIP_RADEON_QF:
616 case PCI_CHIP_RADEON_QG:
617 /* all original radeons (7200) presumably have a stencil op bug */
618 screen->chip_family = CHIP_FAMILY_R100;
619 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
620 break;
621
622 case PCI_CHIP_RV200_QW:
623 case PCI_CHIP_RV200_QX:
624 case PCI_CHIP_RADEON_LW:
625 case PCI_CHIP_RADEON_LX:
626 screen->chip_family = CHIP_FAMILY_RV200;
627 screen->chip_flags = RADEON_CHIPSET_TCL;
628 break;
629
630 case PCI_CHIP_R200_BB:
631 case PCI_CHIP_R200_BC:
632 case PCI_CHIP_R200_QH:
633 case PCI_CHIP_R200_QL:
634 case PCI_CHIP_R200_QM:
635 screen->chip_family = CHIP_FAMILY_R200;
636 screen->chip_flags = RADEON_CHIPSET_TCL;
637 break;
638
639 case PCI_CHIP_RV250_If:
640 case PCI_CHIP_RV250_Ig:
641 case PCI_CHIP_RV250_Ld:
642 case PCI_CHIP_RV250_Lf:
643 case PCI_CHIP_RV250_Lg:
644 screen->chip_family = CHIP_FAMILY_RV250;
645 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
646 break;
647
648 case PCI_CHIP_RV280_5960:
649 case PCI_CHIP_RV280_5961:
650 case PCI_CHIP_RV280_5962:
651 case PCI_CHIP_RV280_5964:
652 case PCI_CHIP_RV280_5965:
653 case PCI_CHIP_RV280_5C61:
654 case PCI_CHIP_RV280_5C63:
655 screen->chip_family = CHIP_FAMILY_RV280;
656 screen->chip_flags = RADEON_CHIPSET_TCL;
657 break;
658
659 case PCI_CHIP_RS300_5834:
660 case PCI_CHIP_RS300_5835:
661 case PCI_CHIP_RS350_7834:
662 case PCI_CHIP_RS350_7835:
663 screen->chip_family = CHIP_FAMILY_RS300;
664 break;
665
666 case PCI_CHIP_R300_AD:
667 case PCI_CHIP_R300_AE:
668 case PCI_CHIP_R300_AF:
669 case PCI_CHIP_R300_AG:
670 case PCI_CHIP_R300_ND:
671 case PCI_CHIP_R300_NE:
672 case PCI_CHIP_R300_NF:
673 case PCI_CHIP_R300_NG:
674 screen->chip_family = CHIP_FAMILY_R300;
675 screen->chip_flags = RADEON_CHIPSET_TCL;
676 break;
677
678 case PCI_CHIP_RV350_AP:
679 case PCI_CHIP_RV350_AQ:
680 case PCI_CHIP_RV350_AR:
681 case PCI_CHIP_RV350_AS:
682 case PCI_CHIP_RV350_AT:
683 case PCI_CHIP_RV350_AV:
684 case PCI_CHIP_RV350_AU:
685 case PCI_CHIP_RV350_NP:
686 case PCI_CHIP_RV350_NQ:
687 case PCI_CHIP_RV350_NR:
688 case PCI_CHIP_RV350_NS:
689 case PCI_CHIP_RV350_NT:
690 case PCI_CHIP_RV350_NV:
691 screen->chip_family = CHIP_FAMILY_RV350;
692 screen->chip_flags = RADEON_CHIPSET_TCL;
693 break;
694
695 case PCI_CHIP_R350_AH:
696 case PCI_CHIP_R350_AI:
697 case PCI_CHIP_R350_AJ:
698 case PCI_CHIP_R350_AK:
699 case PCI_CHIP_R350_NH:
700 case PCI_CHIP_R350_NI:
701 case PCI_CHIP_R360_NJ:
702 case PCI_CHIP_R350_NK:
703 screen->chip_family = CHIP_FAMILY_R350;
704 screen->chip_flags = RADEON_CHIPSET_TCL;
705 break;
706
707 case PCI_CHIP_RV370_5460:
708 case PCI_CHIP_RV370_5462:
709 case PCI_CHIP_RV370_5464:
710 case PCI_CHIP_RV370_5B60:
711 case PCI_CHIP_RV370_5B62:
712 case PCI_CHIP_RV370_5B63:
713 case PCI_CHIP_RV370_5B64:
714 case PCI_CHIP_RV370_5B65:
715 case PCI_CHIP_RV380_3150:
716 case PCI_CHIP_RV380_3152:
717 case PCI_CHIP_RV380_3154:
718 case PCI_CHIP_RV380_3155:
719 case PCI_CHIP_RV380_3E50:
720 case PCI_CHIP_RV380_3E54:
721 screen->chip_family = CHIP_FAMILY_RV380;
722 screen->chip_flags = RADEON_CHIPSET_TCL;
723 break;
724
725 case PCI_CHIP_R420_JN:
726 case PCI_CHIP_R420_JH:
727 case PCI_CHIP_R420_JI:
728 case PCI_CHIP_R420_JJ:
729 case PCI_CHIP_R420_JK:
730 case PCI_CHIP_R420_JL:
731 case PCI_CHIP_R420_JM:
732 case PCI_CHIP_R420_JO:
733 case PCI_CHIP_R420_JP:
734 case PCI_CHIP_R420_JT:
735 case PCI_CHIP_R481_4B49:
736 case PCI_CHIP_R481_4B4A:
737 case PCI_CHIP_R481_4B4B:
738 case PCI_CHIP_R481_4B4C:
739 case PCI_CHIP_R423_UH:
740 case PCI_CHIP_R423_UI:
741 case PCI_CHIP_R423_UJ:
742 case PCI_CHIP_R423_UK:
743 case PCI_CHIP_R430_554C:
744 case PCI_CHIP_R430_554D:
745 case PCI_CHIP_R430_554E:
746 case PCI_CHIP_R430_554F:
747 case PCI_CHIP_R423_5550:
748 case PCI_CHIP_R423_UQ:
749 case PCI_CHIP_R423_UR:
750 case PCI_CHIP_R423_UT:
751 case PCI_CHIP_R430_5D48:
752 case PCI_CHIP_R430_5D49:
753 case PCI_CHIP_R430_5D4A:
754 case PCI_CHIP_R480_5D4C:
755 case PCI_CHIP_R480_5D4D:
756 case PCI_CHIP_R480_5D4E:
757 case PCI_CHIP_R480_5D4F:
758 case PCI_CHIP_R480_5D50:
759 case PCI_CHIP_R480_5D52:
760 case PCI_CHIP_R423_5D57:
761 screen->chip_family = CHIP_FAMILY_R420;
762 screen->chip_flags = RADEON_CHIPSET_TCL;
763 break;
764
765 case PCI_CHIP_RV410_5E4C:
766 case PCI_CHIP_RV410_5E4F:
767 case PCI_CHIP_RV410_564A:
768 case PCI_CHIP_RV410_564B:
769 case PCI_CHIP_RV410_564F:
770 case PCI_CHIP_RV410_5652:
771 case PCI_CHIP_RV410_5653:
772 case PCI_CHIP_RV410_5657:
773 case PCI_CHIP_RV410_5E48:
774 case PCI_CHIP_RV410_5E4A:
775 case PCI_CHIP_RV410_5E4B:
776 case PCI_CHIP_RV410_5E4D:
777 screen->chip_family = CHIP_FAMILY_RV410;
778 screen->chip_flags = RADEON_CHIPSET_TCL;
779 break;
780
781 case PCI_CHIP_RS480_5954:
782 case PCI_CHIP_RS480_5955:
783 case PCI_CHIP_RS482_5974:
784 case PCI_CHIP_RS482_5975:
785 case PCI_CHIP_RS400_5A41:
786 case PCI_CHIP_RS400_5A42:
787 case PCI_CHIP_RC410_5A61:
788 case PCI_CHIP_RC410_5A62:
789 screen->chip_family = CHIP_FAMILY_RS400;
790 break;
791
792 case PCI_CHIP_RS600_793F:
793 case PCI_CHIP_RS600_7941:
794 case PCI_CHIP_RS600_7942:
795 screen->chip_family = CHIP_FAMILY_RS600;
796 break;
797
798 case PCI_CHIP_RS690_791E:
799 case PCI_CHIP_RS690_791F:
800 screen->chip_family = CHIP_FAMILY_RS690;
801 break;
802 case PCI_CHIP_RS740_796C:
803 case PCI_CHIP_RS740_796D:
804 case PCI_CHIP_RS740_796E:
805 case PCI_CHIP_RS740_796F:
806 screen->chip_family = CHIP_FAMILY_RS740;
807 break;
808
809 case PCI_CHIP_R520_7100:
810 case PCI_CHIP_R520_7101:
811 case PCI_CHIP_R520_7102:
812 case PCI_CHIP_R520_7103:
813 case PCI_CHIP_R520_7104:
814 case PCI_CHIP_R520_7105:
815 case PCI_CHIP_R520_7106:
816 case PCI_CHIP_R520_7108:
817 case PCI_CHIP_R520_7109:
818 case PCI_CHIP_R520_710A:
819 case PCI_CHIP_R520_710B:
820 case PCI_CHIP_R520_710C:
821 case PCI_CHIP_R520_710E:
822 case PCI_CHIP_R520_710F:
823 screen->chip_family = CHIP_FAMILY_R520;
824 screen->chip_flags = RADEON_CHIPSET_TCL;
825 break;
826
827 case PCI_CHIP_RV515_7140:
828 case PCI_CHIP_RV515_7141:
829 case PCI_CHIP_RV515_7142:
830 case PCI_CHIP_RV515_7143:
831 case PCI_CHIP_RV515_7144:
832 case PCI_CHIP_RV515_7145:
833 case PCI_CHIP_RV515_7146:
834 case PCI_CHIP_RV515_7147:
835 case PCI_CHIP_RV515_7149:
836 case PCI_CHIP_RV515_714A:
837 case PCI_CHIP_RV515_714B:
838 case PCI_CHIP_RV515_714C:
839 case PCI_CHIP_RV515_714D:
840 case PCI_CHIP_RV515_714E:
841 case PCI_CHIP_RV515_714F:
842 case PCI_CHIP_RV515_7151:
843 case PCI_CHIP_RV515_7152:
844 case PCI_CHIP_RV515_7153:
845 case PCI_CHIP_RV515_715E:
846 case PCI_CHIP_RV515_715F:
847 case PCI_CHIP_RV515_7180:
848 case PCI_CHIP_RV515_7181:
849 case PCI_CHIP_RV515_7183:
850 case PCI_CHIP_RV515_7186:
851 case PCI_CHIP_RV515_7187:
852 case PCI_CHIP_RV515_7188:
853 case PCI_CHIP_RV515_718A:
854 case PCI_CHIP_RV515_718B:
855 case PCI_CHIP_RV515_718C:
856 case PCI_CHIP_RV515_718D:
857 case PCI_CHIP_RV515_718F:
858 case PCI_CHIP_RV515_7193:
859 case PCI_CHIP_RV515_7196:
860 case PCI_CHIP_RV515_719B:
861 case PCI_CHIP_RV515_719F:
862 case PCI_CHIP_RV515_7200:
863 case PCI_CHIP_RV515_7210:
864 case PCI_CHIP_RV515_7211:
865 screen->chip_family = CHIP_FAMILY_RV515;
866 screen->chip_flags = RADEON_CHIPSET_TCL;
867 break;
868
869 case PCI_CHIP_RV530_71C0:
870 case PCI_CHIP_RV530_71C1:
871 case PCI_CHIP_RV530_71C2:
872 case PCI_CHIP_RV530_71C3:
873 case PCI_CHIP_RV530_71C4:
874 case PCI_CHIP_RV530_71C5:
875 case PCI_CHIP_RV530_71C6:
876 case PCI_CHIP_RV530_71C7:
877 case PCI_CHIP_RV530_71CD:
878 case PCI_CHIP_RV530_71CE:
879 case PCI_CHIP_RV530_71D2:
880 case PCI_CHIP_RV530_71D4:
881 case PCI_CHIP_RV530_71D5:
882 case PCI_CHIP_RV530_71D6:
883 case PCI_CHIP_RV530_71DA:
884 case PCI_CHIP_RV530_71DE:
885 screen->chip_family = CHIP_FAMILY_RV530;
886 screen->chip_flags = RADEON_CHIPSET_TCL;
887 break;
888
889 case PCI_CHIP_R580_7240:
890 case PCI_CHIP_R580_7243:
891 case PCI_CHIP_R580_7244:
892 case PCI_CHIP_R580_7245:
893 case PCI_CHIP_R580_7246:
894 case PCI_CHIP_R580_7247:
895 case PCI_CHIP_R580_7248:
896 case PCI_CHIP_R580_7249:
897 case PCI_CHIP_R580_724A:
898 case PCI_CHIP_R580_724B:
899 case PCI_CHIP_R580_724C:
900 case PCI_CHIP_R580_724D:
901 case PCI_CHIP_R580_724E:
902 case PCI_CHIP_R580_724F:
903 case PCI_CHIP_R580_7284:
904 screen->chip_family = CHIP_FAMILY_R580;
905 screen->chip_flags = RADEON_CHIPSET_TCL;
906 break;
907
908 case PCI_CHIP_RV570_7280:
909 case PCI_CHIP_RV560_7281:
910 case PCI_CHIP_RV560_7283:
911 case PCI_CHIP_RV560_7287:
912 case PCI_CHIP_RV570_7288:
913 case PCI_CHIP_RV570_7289:
914 case PCI_CHIP_RV570_728B:
915 case PCI_CHIP_RV570_728C:
916 case PCI_CHIP_RV560_7290:
917 case PCI_CHIP_RV560_7291:
918 case PCI_CHIP_RV560_7293:
919 case PCI_CHIP_RV560_7297:
920 screen->chip_family = CHIP_FAMILY_RV560;
921 screen->chip_flags = RADEON_CHIPSET_TCL;
922 break;
923
924 case PCI_CHIP_R600_9400:
925 case PCI_CHIP_R600_9401:
926 case PCI_CHIP_R600_9402:
927 case PCI_CHIP_R600_9403:
928 case PCI_CHIP_R600_9405:
929 case PCI_CHIP_R600_940A:
930 case PCI_CHIP_R600_940B:
931 case PCI_CHIP_R600_940F:
932 screen->chip_family = CHIP_FAMILY_R600;
933 screen->chip_flags = RADEON_CHIPSET_TCL;
934 break;
935
936 case PCI_CHIP_RV610_94C0:
937 case PCI_CHIP_RV610_94C1:
938 case PCI_CHIP_RV610_94C3:
939 case PCI_CHIP_RV610_94C4:
940 case PCI_CHIP_RV610_94C5:
941 case PCI_CHIP_RV610_94C6:
942 case PCI_CHIP_RV610_94C7:
943 case PCI_CHIP_RV610_94C8:
944 case PCI_CHIP_RV610_94C9:
945 case PCI_CHIP_RV610_94CB:
946 case PCI_CHIP_RV610_94CC:
947 case PCI_CHIP_RV610_94CD:
948 screen->chip_family = CHIP_FAMILY_RV610;
949 screen->chip_flags = RADEON_CHIPSET_TCL;
950 break;
951
952 case PCI_CHIP_RV630_9580:
953 case PCI_CHIP_RV630_9581:
954 case PCI_CHIP_RV630_9583:
955 case PCI_CHIP_RV630_9586:
956 case PCI_CHIP_RV630_9587:
957 case PCI_CHIP_RV630_9588:
958 case PCI_CHIP_RV630_9589:
959 case PCI_CHIP_RV630_958A:
960 case PCI_CHIP_RV630_958B:
961 case PCI_CHIP_RV630_958C:
962 case PCI_CHIP_RV630_958D:
963 case PCI_CHIP_RV630_958E:
964 case PCI_CHIP_RV630_958F:
965 screen->chip_family = CHIP_FAMILY_RV630;
966 screen->chip_flags = RADEON_CHIPSET_TCL;
967 break;
968
969 case PCI_CHIP_RV670_9500:
970 case PCI_CHIP_RV670_9501:
971 case PCI_CHIP_RV670_9504:
972 case PCI_CHIP_RV670_9505:
973 case PCI_CHIP_RV670_9506:
974 case PCI_CHIP_RV670_9507:
975 case PCI_CHIP_RV670_9508:
976 case PCI_CHIP_RV670_9509:
977 case PCI_CHIP_RV670_950F:
978 case PCI_CHIP_RV670_9511:
979 case PCI_CHIP_RV670_9515:
980 case PCI_CHIP_RV670_9517:
981 case PCI_CHIP_RV670_9519:
982 screen->chip_family = CHIP_FAMILY_RV670;
983 screen->chip_flags = RADEON_CHIPSET_TCL;
984 break;
985
986 case PCI_CHIP_RV620_95C0:
987 case PCI_CHIP_RV620_95C2:
988 case PCI_CHIP_RV620_95C4:
989 case PCI_CHIP_RV620_95C5:
990 case PCI_CHIP_RV620_95C6:
991 case PCI_CHIP_RV620_95C7:
992 case PCI_CHIP_RV620_95C9:
993 case PCI_CHIP_RV620_95CC:
994 case PCI_CHIP_RV620_95CD:
995 case PCI_CHIP_RV620_95CE:
996 case PCI_CHIP_RV620_95CF:
997 screen->chip_family = CHIP_FAMILY_RV620;
998 screen->chip_flags = RADEON_CHIPSET_TCL;
999 break;
1000
1001 case PCI_CHIP_RV635_9590:
1002 case PCI_CHIP_RV635_9591:
1003 case PCI_CHIP_RV635_9593:
1004 case PCI_CHIP_RV635_9595:
1005 case PCI_CHIP_RV635_9596:
1006 case PCI_CHIP_RV635_9597:
1007 case PCI_CHIP_RV635_9598:
1008 case PCI_CHIP_RV635_9599:
1009 case PCI_CHIP_RV635_959B:
1010 screen->chip_family = CHIP_FAMILY_RV635;
1011 screen->chip_flags = RADEON_CHIPSET_TCL;
1012 break;
1013
1014 case PCI_CHIP_RS780_9610:
1015 case PCI_CHIP_RS780_9611:
1016 case PCI_CHIP_RS780_9612:
1017 case PCI_CHIP_RS780_9613:
1018 case PCI_CHIP_RS780_9614:
1019 case PCI_CHIP_RS780_9615:
1020 case PCI_CHIP_RS780_9616:
1021 screen->chip_family = CHIP_FAMILY_RS780;
1022 screen->chip_flags = RADEON_CHIPSET_TCL;
1023 break;
1024 case PCI_CHIP_RS880_9710:
1025 case PCI_CHIP_RS880_9711:
1026 case PCI_CHIP_RS880_9712:
1027 case PCI_CHIP_RS880_9713:
1028 case PCI_CHIP_RS880_9714:
1029 case PCI_CHIP_RS880_9715:
1030 screen->chip_family = CHIP_FAMILY_RS880;
1031 screen->chip_flags = RADEON_CHIPSET_TCL;
1032 break;
1033
1034 case PCI_CHIP_RV770_9440:
1035 case PCI_CHIP_RV770_9441:
1036 case PCI_CHIP_RV770_9442:
1037 case PCI_CHIP_RV770_9443:
1038 case PCI_CHIP_RV770_9444:
1039 case PCI_CHIP_RV770_9446:
1040 case PCI_CHIP_RV770_944A:
1041 case PCI_CHIP_RV770_944B:
1042 case PCI_CHIP_RV770_944C:
1043 case PCI_CHIP_RV770_944E:
1044 case PCI_CHIP_RV770_9450:
1045 case PCI_CHIP_RV770_9452:
1046 case PCI_CHIP_RV770_9456:
1047 case PCI_CHIP_RV770_945A:
1048 case PCI_CHIP_RV770_945B:
1049 case PCI_CHIP_RV770_945E:
1050 case PCI_CHIP_RV790_9460:
1051 case PCI_CHIP_RV790_9462:
1052 case PCI_CHIP_RV770_946A:
1053 case PCI_CHIP_RV770_946B:
1054 case PCI_CHIP_RV770_947A:
1055 case PCI_CHIP_RV770_947B:
1056 screen->chip_family = CHIP_FAMILY_RV770;
1057 screen->chip_flags = RADEON_CHIPSET_TCL;
1058 break;
1059
1060 case PCI_CHIP_RV730_9480:
1061 case PCI_CHIP_RV730_9487:
1062 case PCI_CHIP_RV730_9488:
1063 case PCI_CHIP_RV730_9489:
1064 case PCI_CHIP_RV730_948A:
1065 case PCI_CHIP_RV730_948F:
1066 case PCI_CHIP_RV730_9490:
1067 case PCI_CHIP_RV730_9491:
1068 case PCI_CHIP_RV730_9495:
1069 case PCI_CHIP_RV730_9498:
1070 case PCI_CHIP_RV730_949C:
1071 case PCI_CHIP_RV730_949E:
1072 case PCI_CHIP_RV730_949F:
1073 screen->chip_family = CHIP_FAMILY_RV730;
1074 screen->chip_flags = RADEON_CHIPSET_TCL;
1075 break;
1076
1077 case PCI_CHIP_RV710_9540:
1078 case PCI_CHIP_RV710_9541:
1079 case PCI_CHIP_RV710_9542:
1080 case PCI_CHIP_RV710_954E:
1081 case PCI_CHIP_RV710_954F:
1082 case PCI_CHIP_RV710_9552:
1083 case PCI_CHIP_RV710_9553:
1084 case PCI_CHIP_RV710_9555:
1085 case PCI_CHIP_RV710_9557:
1086 case PCI_CHIP_RV710_955F:
1087 screen->chip_family = CHIP_FAMILY_RV710;
1088 screen->chip_flags = RADEON_CHIPSET_TCL;
1089 break;
1090
1091 case PCI_CHIP_RV740_94A0:
1092 case PCI_CHIP_RV740_94A1:
1093 case PCI_CHIP_RV740_94A3:
1094 case PCI_CHIP_RV740_94B1:
1095 case PCI_CHIP_RV740_94B3:
1096 case PCI_CHIP_RV740_94B4:
1097 case PCI_CHIP_RV740_94B5:
1098 case PCI_CHIP_RV740_94B9:
1099 screen->chip_family = CHIP_FAMILY_RV740;
1100 screen->chip_flags = RADEON_CHIPSET_TCL;
1101 break;
1102
1103 case PCI_CHIP_CEDAR_68E0:
1104 case PCI_CHIP_CEDAR_68E1:
1105 case PCI_CHIP_CEDAR_68E4:
1106 case PCI_CHIP_CEDAR_68E5:
1107 case PCI_CHIP_CEDAR_68E8:
1108 case PCI_CHIP_CEDAR_68E9:
1109 case PCI_CHIP_CEDAR_68F1:
1110 case PCI_CHIP_CEDAR_68F8:
1111 case PCI_CHIP_CEDAR_68F9:
1112 case PCI_CHIP_CEDAR_68FE:
1113 screen->chip_family = CHIP_FAMILY_CEDAR;
1114 screen->chip_flags = RADEON_CHIPSET_TCL;
1115 break;
1116
1117 case PCI_CHIP_REDWOOD_68C0:
1118 case PCI_CHIP_REDWOOD_68C1:
1119 case PCI_CHIP_REDWOOD_68C8:
1120 case PCI_CHIP_REDWOOD_68C9:
1121 case PCI_CHIP_REDWOOD_68D8:
1122 case PCI_CHIP_REDWOOD_68D9:
1123 case PCI_CHIP_REDWOOD_68DA:
1124 case PCI_CHIP_REDWOOD_68DE:
1125 screen->chip_family = CHIP_FAMILY_REDWOOD;
1126 screen->chip_flags = RADEON_CHIPSET_TCL;
1127 break;
1128
1129 case PCI_CHIP_JUNIPER_68A0:
1130 case PCI_CHIP_JUNIPER_68A1:
1131 case PCI_CHIP_JUNIPER_68A8:
1132 case PCI_CHIP_JUNIPER_68A9:
1133 case PCI_CHIP_JUNIPER_68B0:
1134 case PCI_CHIP_JUNIPER_68B8:
1135 case PCI_CHIP_JUNIPER_68B9:
1136 case PCI_CHIP_JUNIPER_68BE:
1137 screen->chip_family = CHIP_FAMILY_JUNIPER;
1138 screen->chip_flags = RADEON_CHIPSET_TCL;
1139 break;
1140
1141 case PCI_CHIP_CYPRESS_6880:
1142 case PCI_CHIP_CYPRESS_6888:
1143 case PCI_CHIP_CYPRESS_6889:
1144 case PCI_CHIP_CYPRESS_688A:
1145 case PCI_CHIP_CYPRESS_6898:
1146 case PCI_CHIP_CYPRESS_6899:
1147 case PCI_CHIP_CYPRESS_689E:
1148 screen->chip_family = CHIP_FAMILY_CYPRESS;
1149 screen->chip_flags = RADEON_CHIPSET_TCL;
1150 break;
1151
1152 case PCI_CHIP_HEMLOCK_689C:
1153 case PCI_CHIP_HEMLOCK_689D:
1154 screen->chip_family = CHIP_FAMILY_HEMLOCK;
1155 screen->chip_flags = RADEON_CHIPSET_TCL;
1156 break;
1157
1158 default:
1159 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
1160 device_id);
1161 return -1;
1162 }
1163
1164 return 0;
1165 }
1166
1167
1168 /* Create the device specific screen private data struct.
1169 */
1170 static radeonScreenPtr
1171 radeonCreateScreen( __DRIscreen *sPriv )
1172 {
1173 radeonScreenPtr screen;
1174 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
1175 unsigned char *RADEONMMIO = NULL;
1176 int i;
1177 int ret;
1178 uint32_t temp = 0;
1179
1180 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
1181 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
1182 return GL_FALSE;
1183 }
1184
1185 /* Allocate the private area */
1186 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1187 if ( !screen ) {
1188 __driUtilMessage("%s: Could not allocate memory for screen structure",
1189 __FUNCTION__);
1190 return NULL;
1191 }
1192
1193 radeon_init_debug();
1194
1195 /* parse information in __driConfigOptions */
1196 driParseOptionInfo (&screen->optionCache,
1197 __driConfigOptions, __driNConfigOptions);
1198
1199 /* This is first since which regions we map depends on whether or
1200 * not we are using a PCI card.
1201 */
1202 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
1203 {
1204 int ret;
1205
1206 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET,
1207 &screen->gart_buffer_offset);
1208
1209 if (ret) {
1210 FREE( screen );
1211 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
1212 return NULL;
1213 }
1214
1215 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE,
1216 &screen->gart_base);
1217 if (ret) {
1218 FREE( screen );
1219 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
1220 return NULL;
1221 }
1222
1223 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR,
1224 &screen->irq);
1225 if (ret) {
1226 FREE( screen );
1227 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
1228 return NULL;
1229 }
1230 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
1231 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
1232 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
1233 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
1234 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
1235 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
1236 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
1237 screen->drmSupportsOcclusionQueries = (sPriv->drm_version.minor >= 30);
1238 }
1239
1240 ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
1241 if (ret == -1)
1242 return NULL;
1243
1244 screen->mmio.handle = dri_priv->registerHandle;
1245 screen->mmio.size = dri_priv->registerSize;
1246 if ( drmMap( sPriv->fd,
1247 screen->mmio.handle,
1248 screen->mmio.size,
1249 &screen->mmio.map ) ) {
1250 FREE( screen );
1251 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
1252 return NULL;
1253 }
1254
1255 RADEONMMIO = screen->mmio.map;
1256
1257 screen->status.handle = dri_priv->statusHandle;
1258 screen->status.size = dri_priv->statusSize;
1259 if ( drmMap( sPriv->fd,
1260 screen->status.handle,
1261 screen->status.size,
1262 &screen->status.map ) ) {
1263 drmUnmap( screen->mmio.map, screen->mmio.size );
1264 FREE( screen );
1265 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
1266 return NULL;
1267 }
1268 if (screen->chip_family < CHIP_FAMILY_R600)
1269 screen->scratch = (__volatile__ uint32_t *)
1270 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
1271 else
1272 screen->scratch = (__volatile__ uint32_t *)
1273 ((GLubyte *)screen->status.map + R600_SCRATCH_REG_OFFSET);
1274
1275 screen->buffers = drmMapBufs( sPriv->fd );
1276 if ( !screen->buffers ) {
1277 drmUnmap( screen->status.map, screen->status.size );
1278 drmUnmap( screen->mmio.map, screen->mmio.size );
1279 FREE( screen );
1280 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
1281 return NULL;
1282 }
1283
1284 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
1285 screen->gartTextures.handle = dri_priv->gartTexHandle;
1286 screen->gartTextures.size = dri_priv->gartTexMapSize;
1287 if ( drmMap( sPriv->fd,
1288 screen->gartTextures.handle,
1289 screen->gartTextures.size,
1290 (drmAddressPtr)&screen->gartTextures.map ) ) {
1291 drmUnmapBufs( screen->buffers );
1292 drmUnmap( screen->status.map, screen->status.size );
1293 drmUnmap( screen->mmio.map, screen->mmio.size );
1294 FREE( screen );
1295 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
1296 return NULL;
1297 }
1298
1299 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
1300 }
1301
1302 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
1303 sPriv->ddx_version.minor < 2) {
1304 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
1305 return NULL;
1306 }
1307
1308 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
1309 fprintf(stderr, "R500 support requires a newer drm.\n");
1310 return NULL;
1311 }
1312
1313 if (getenv("R300_NO_TCL"))
1314 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1315
1316 if (screen->chip_family <= CHIP_FAMILY_RS200)
1317 screen->chip_flags |= RADEON_CLASS_R100;
1318 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1319 screen->chip_flags |= RADEON_CLASS_R200;
1320 else if (screen->chip_family <= CHIP_FAMILY_RV570)
1321 screen->chip_flags |= RADEON_CLASS_R300;
1322 else
1323 screen->chip_flags |= RADEON_CLASS_R600;
1324
1325 /* set group bytes for r6xx+ */
1326 screen->group_bytes = 256;
1327 screen->cpp = dri_priv->bpp / 8;
1328 screen->AGPMode = dri_priv->AGPMode;
1329
1330 ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp);
1331
1332 /* +r6/r7 */
1333 if(screen->chip_family >= CHIP_FAMILY_R600)
1334 {
1335 if (ret)
1336 {
1337 FREE( screen );
1338 fprintf(stderr, "Unable to get fb location need newer drm\n");
1339 return NULL;
1340 }
1341 else
1342 {
1343 screen->fbLocation = (temp & 0xffff) << 24;
1344 }
1345 }
1346 else
1347 {
1348 if (ret)
1349 {
1350 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm)
1351 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
1352 else
1353 {
1354 FREE( screen );
1355 fprintf(stderr, "Unable to get fb location need newer drm\n");
1356 return NULL;
1357 }
1358 }
1359 else
1360 {
1361 screen->fbLocation = (temp & 0xffff) << 16;
1362 }
1363 }
1364
1365 if (IS_R300_CLASS(screen)) {
1366 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1367 if (ret) {
1368 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1369 switch (screen->chip_family) {
1370 case CHIP_FAMILY_R300:
1371 case CHIP_FAMILY_R350:
1372 screen->num_gb_pipes = 2;
1373 break;
1374 case CHIP_FAMILY_R420:
1375 case CHIP_FAMILY_R520:
1376 case CHIP_FAMILY_R580:
1377 case CHIP_FAMILY_RV560:
1378 case CHIP_FAMILY_RV570:
1379 screen->num_gb_pipes = 4;
1380 break;
1381 case CHIP_FAMILY_RV350:
1382 case CHIP_FAMILY_RV515:
1383 case CHIP_FAMILY_RV530:
1384 case CHIP_FAMILY_RV410:
1385 default:
1386 screen->num_gb_pipes = 1;
1387 break;
1388 }
1389 } else {
1390 screen->num_gb_pipes = temp;
1391 }
1392
1393 /* pipe overrides */
1394 switch (dri_priv->deviceID) {
1395 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1396 case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */
1397 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
1398 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
1399 screen->num_gb_pipes = 1;
1400 break;
1401 default:
1402 break;
1403 }
1404
1405 if ( sPriv->drm_version.minor >= 31 ) {
1406 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp);
1407 if (ret)
1408 screen->num_z_pipes = 2;
1409 else
1410 screen->num_z_pipes = temp;
1411 } else
1412 screen->num_z_pipes = 2;
1413 }
1414
1415 if ( sPriv->drm_version.minor >= 10 ) {
1416 drm_radeon_setparam_t sp;
1417
1418 sp.param = RADEON_SETPARAM_FB_LOCATION;
1419 sp.value = screen->fbLocation;
1420
1421 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
1422 &sp, sizeof( sp ) );
1423 }
1424
1425 screen->frontOffset = dri_priv->frontOffset;
1426 screen->frontPitch = dri_priv->frontPitch;
1427 screen->backOffset = dri_priv->backOffset;
1428 screen->backPitch = dri_priv->backPitch;
1429 screen->depthOffset = dri_priv->depthOffset;
1430 screen->depthPitch = dri_priv->depthPitch;
1431
1432 /* Check if ddx has set up a surface reg to cover depth buffer */
1433 screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
1434 /* these chips don't use tiled z without hyperz. So always pretend
1435 we have set up a surface which will cause linear reads/writes */
1436 (IS_R100_CLASS(screen) &&
1437 !(screen->chip_flags & RADEON_CHIPSET_TCL));
1438
1439 if ( dri_priv->textureSize == 0 ) {
1440 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
1441 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
1442 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
1443 dri_priv->log2GARTTexGran;
1444 } else {
1445 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
1446 + screen->fbLocation;
1447 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
1448 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
1449 dri_priv->log2TexGran;
1450 }
1451
1452 if ( !screen->gartTextures.map || dri_priv->textureSize == 0
1453 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
1454 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
1455 screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
1456 screen->texSize[RADEON_GART_TEX_HEAP] = 0;
1457 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
1458 } else {
1459 screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
1460 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
1461 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
1462 screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
1463 dri_priv->log2GARTTexGran;
1464 }
1465
1466 i = 0;
1467 screen->extensions[i++] = &driCopySubBufferExtension.base;
1468 screen->extensions[i++] = &driReadDrawableExtension;
1469
1470 if ( screen->irq != 0 ) {
1471 screen->extensions[i++] = &driSwapControlExtension.base;
1472 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1473 }
1474
1475 #if defined(RADEON_R100)
1476 screen->extensions[i++] = &radeonTexOffsetExtension.base;
1477 #endif
1478
1479 #if defined(RADEON_R200)
1480 screen->extensions[i++] = &r200texOffsetExtension.base;
1481 #endif
1482
1483 #if defined(RADEON_R300)
1484 screen->extensions[i++] = &r300texOffsetExtension.base;
1485 #endif
1486
1487 #if defined(RADEON_R600)
1488 screen->extensions[i++] = &r600texOffsetExtension.base;
1489 #endif
1490
1491 screen->extensions[i++] = &dri2ConfigQueryExtension.base;
1492
1493 screen->extensions[i++] = NULL;
1494 sPriv->extensions = screen->extensions;
1495
1496 screen->driScreen = sPriv;
1497 screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
1498 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
1499 screen->sarea_priv_offset);
1500
1501 screen->bom = radeon_bo_manager_legacy_ctor(screen);
1502 if (screen->bom == NULL) {
1503 free(screen);
1504 return NULL;
1505 }
1506
1507 return screen;
1508 }
1509
1510 static radeonScreenPtr
1511 radeonCreateScreen2(__DRIscreen *sPriv)
1512 {
1513 radeonScreenPtr screen;
1514 int i;
1515 int ret;
1516 uint32_t device_id = 0;
1517 uint32_t temp = 0;
1518
1519 /* Allocate the private area */
1520 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1521 if ( !screen ) {
1522 __driUtilMessage("%s: Could not allocate memory for screen structure",
1523 __FUNCTION__);
1524 fprintf(stderr, "leaving here\n");
1525 return NULL;
1526 }
1527
1528 radeon_init_debug();
1529
1530 /* parse information in __driConfigOptions */
1531 driParseOptionInfo (&screen->optionCache,
1532 __driConfigOptions, __driNConfigOptions);
1533
1534 screen->kernel_mm = 1;
1535 screen->chip_flags = 0;
1536
1537 /* if we have kms we can support all of these */
1538 screen->drmSupportsCubeMapsR200 = 1;
1539 screen->drmSupportsBlendColor = 1;
1540 screen->drmSupportsTriPerf = 1;
1541 screen->drmSupportsFragShader = 1;
1542 screen->drmSupportsPointSprites = 1;
1543 screen->drmSupportsCubeMapsR100 = 1;
1544 screen->drmSupportsVertexProgram = 1;
1545 screen->drmSupportsOcclusionQueries = 1;
1546 screen->irq = 1;
1547
1548 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id);
1549 if (ret) {
1550 FREE( screen );
1551 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret);
1552 return NULL;
1553 }
1554
1555 ret = radeon_set_screen_flags(screen, device_id);
1556 if (ret == -1)
1557 return NULL;
1558
1559 if (getenv("R300_NO_TCL"))
1560 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1561
1562 if (screen->chip_family <= CHIP_FAMILY_RS200)
1563 screen->chip_flags |= RADEON_CLASS_R100;
1564 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1565 screen->chip_flags |= RADEON_CLASS_R200;
1566 else if (screen->chip_family <= CHIP_FAMILY_RV570)
1567 screen->chip_flags |= RADEON_CLASS_R300;
1568 else
1569 screen->chip_flags |= RADEON_CLASS_R600;
1570
1571 /* r6xx+ tiling, default to 256 group bytes */
1572 screen->group_bytes = 256;
1573 if (IS_R600_CLASS(screen) && (sPriv->drm_version.minor >= 6)) {
1574 ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
1575 if (ret)
1576 fprintf(stderr, "failed to get tiling info\n");
1577 else {
1578 screen->tile_config = temp;
1579 screen->r7xx_bank_op = 0;
1580 switch((screen->tile_config & 0xe) >> 1) {
1581 case 0:
1582 screen->num_channels = 1;
1583 break;
1584 case 1:
1585 screen->num_channels = 2;
1586 break;
1587 case 2:
1588 screen->num_channels = 4;
1589 break;
1590 case 3:
1591 screen->num_channels = 8;
1592 break;
1593 default:
1594 fprintf(stderr, "bad channels\n");
1595 break;
1596 }
1597 switch((screen->tile_config & 0x30) >> 4) {
1598 case 0:
1599 screen->num_banks = 4;
1600 break;
1601 case 1:
1602 screen->num_banks = 8;
1603 break;
1604 default:
1605 fprintf(stderr, "bad banks\n");
1606 break;
1607 }
1608 switch((screen->tile_config & 0xc0) >> 6) {
1609 case 0:
1610 screen->group_bytes = 256;
1611 break;
1612 case 1:
1613 screen->group_bytes = 512;
1614 break;
1615 default:
1616 fprintf(stderr, "bad group_bytes\n");
1617 break;
1618 }
1619 }
1620 }
1621
1622 if (IS_R300_CLASS(screen)) {
1623 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1624 if (ret) {
1625 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1626 switch (screen->chip_family) {
1627 case CHIP_FAMILY_R300:
1628 case CHIP_FAMILY_R350:
1629 screen->num_gb_pipes = 2;
1630 break;
1631 case CHIP_FAMILY_R420:
1632 case CHIP_FAMILY_R520:
1633 case CHIP_FAMILY_R580:
1634 case CHIP_FAMILY_RV560:
1635 case CHIP_FAMILY_RV570:
1636 screen->num_gb_pipes = 4;
1637 break;
1638 case CHIP_FAMILY_RV350:
1639 case CHIP_FAMILY_RV515:
1640 case CHIP_FAMILY_RV530:
1641 case CHIP_FAMILY_RV410:
1642 default:
1643 screen->num_gb_pipes = 1;
1644 break;
1645 }
1646 } else {
1647 screen->num_gb_pipes = temp;
1648 }
1649
1650 /* pipe overrides */
1651 switch (device_id) {
1652 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1653 case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */
1654 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
1655 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
1656 screen->num_gb_pipes = 1;
1657 break;
1658 default:
1659 break;
1660 }
1661
1662 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp);
1663 if (ret)
1664 screen->num_z_pipes = 2;
1665 else
1666 screen->num_z_pipes = temp;
1667
1668 }
1669
1670 i = 0;
1671 screen->extensions[i++] = &driCopySubBufferExtension.base;
1672 screen->extensions[i++] = &driReadDrawableExtension;
1673 screen->extensions[i++] = &dri2ConfigQueryExtension.base;
1674
1675 if ( screen->irq != 0 ) {
1676 screen->extensions[i++] = &driSwapControlExtension.base;
1677 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1678 }
1679
1680 #if defined(RADEON_R100)
1681 screen->extensions[i++] = &radeonTexBufferExtension.base;
1682 #endif
1683
1684 #if defined(RADEON_R200)
1685 screen->extensions[i++] = &r200TexBufferExtension.base;
1686 #endif
1687
1688 #if defined(RADEON_R300)
1689 screen->extensions[i++] = &r300TexBufferExtension.base;
1690 #endif
1691
1692 #if defined(RADEON_R600)
1693 screen->extensions[i++] = &r600TexBufferExtension.base;
1694 #endif
1695
1696 screen->extensions[i++] = &radeonFlushExtension.base;
1697 screen->extensions[i++] = &radeonImageExtension.base;
1698
1699 screen->extensions[i++] = NULL;
1700 sPriv->extensions = screen->extensions;
1701
1702 screen->driScreen = sPriv;
1703 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1704 if (screen->bom == NULL) {
1705 free(screen);
1706 return NULL;
1707 }
1708 return screen;
1709 }
1710
1711 /* Destroy the device specific screen private data struct.
1712 */
1713 static void
1714 radeonDestroyScreen( __DRIscreen *sPriv )
1715 {
1716 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1717
1718 if (!screen)
1719 return;
1720
1721 if (screen->kernel_mm) {
1722 #ifdef RADEON_BO_TRACK
1723 radeon_tracker_print(&screen->bom->tracker, stderr);
1724 #endif
1725 radeon_bo_manager_gem_dtor(screen->bom);
1726 } else {
1727 radeon_bo_manager_legacy_dtor(screen->bom);
1728
1729 if ( screen->gartTextures.map ) {
1730 drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
1731 }
1732 drmUnmapBufs( screen->buffers );
1733 drmUnmap( screen->status.map, screen->status.size );
1734 drmUnmap( screen->mmio.map, screen->mmio.size );
1735 }
1736
1737 /* free all option information */
1738 driDestroyOptionInfo (&screen->optionCache);
1739
1740 FREE( screen );
1741 sPriv->private = NULL;
1742 }
1743
1744
1745 /* Initialize the driver specific screen private data.
1746 */
1747 static GLboolean
1748 radeonInitDriver( __DRIscreen *sPriv )
1749 {
1750 if (sPriv->dri2.enabled) {
1751 sPriv->private = (void *) radeonCreateScreen2( sPriv );
1752 } else {
1753 sPriv->private = (void *) radeonCreateScreen( sPriv );
1754 }
1755 if ( !sPriv->private ) {
1756 radeonDestroyScreen( sPriv );
1757 return GL_FALSE;
1758 }
1759
1760 return GL_TRUE;
1761 }
1762
1763
1764
1765 /**
1766 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1767 *
1768 * \todo This function (and its interface) will need to be updated to support
1769 * pbuffers.
1770 */
1771 static GLboolean
1772 radeonCreateBuffer( __DRIscreen *driScrnPriv,
1773 __DRIdrawable *driDrawPriv,
1774 const struct gl_config *mesaVis,
1775 GLboolean isPixmap )
1776 {
1777 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1778
1779 const GLboolean swDepth = GL_FALSE;
1780 const GLboolean swAlpha = GL_FALSE;
1781 const GLboolean swAccum = mesaVis->accumRedBits > 0;
1782 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1783 mesaVis->depthBits != 24;
1784 gl_format rgbFormat;
1785 struct radeon_framebuffer *rfb;
1786
1787 if (isPixmap)
1788 return GL_FALSE; /* not implemented */
1789
1790 rfb = CALLOC_STRUCT(radeon_framebuffer);
1791 if (!rfb)
1792 return GL_FALSE;
1793
1794 _mesa_initialize_window_framebuffer(&rfb->base, mesaVis);
1795
1796 if (mesaVis->redBits == 5)
1797 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_RGB565 : MESA_FORMAT_RGB565_REV;
1798 else if (mesaVis->alphaBits == 0)
1799 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_XRGB8888 : MESA_FORMAT_XRGB8888_REV;
1800 else
1801 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB8888_REV;
1802
1803 /* front color renderbuffer */
1804 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1805 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base);
1806 rfb->color_rb[0]->has_surface = 1;
1807
1808 /* back color renderbuffer */
1809 if (mesaVis->doubleBufferMode) {
1810 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1811 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base);
1812 rfb->color_rb[1]->has_surface = 1;
1813 }
1814
1815 if (mesaVis->depthBits == 24) {
1816 if (mesaVis->stencilBits == 8) {
1817 struct radeon_renderbuffer *depthStencilRb =
1818 radeon_create_renderbuffer(MESA_FORMAT_S8_Z24, driDrawPriv);
1819 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base);
1820 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base);
1821 depthStencilRb->has_surface = screen->depthHasSurface;
1822 } else {
1823 /* depth renderbuffer */
1824 struct radeon_renderbuffer *depth =
1825 radeon_create_renderbuffer(MESA_FORMAT_X8_Z24, driDrawPriv);
1826 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1827 depth->has_surface = screen->depthHasSurface;
1828 }
1829 } else if (mesaVis->depthBits == 16) {
1830 /* just 16-bit depth buffer, no hw stencil */
1831 struct radeon_renderbuffer *depth =
1832 radeon_create_renderbuffer(MESA_FORMAT_Z16, driDrawPriv);
1833 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1834 depth->has_surface = screen->depthHasSurface;
1835 }
1836
1837 _mesa_add_soft_renderbuffers(&rfb->base,
1838 GL_FALSE, /* color */
1839 swDepth,
1840 swStencil,
1841 swAccum,
1842 swAlpha,
1843 GL_FALSE /* aux */);
1844 driDrawPriv->driverPrivate = (void *) rfb;
1845
1846 return (driDrawPriv->driverPrivate != NULL);
1847 }
1848
1849
1850 static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb)
1851 {
1852 struct radeon_renderbuffer *rb;
1853
1854 rb = rfb->color_rb[0];
1855 if (rb && rb->bo) {
1856 radeon_bo_unref(rb->bo);
1857 rb->bo = NULL;
1858 }
1859 rb = rfb->color_rb[1];
1860 if (rb && rb->bo) {
1861 radeon_bo_unref(rb->bo);
1862 rb->bo = NULL;
1863 }
1864 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
1865 if (rb && rb->bo) {
1866 radeon_bo_unref(rb->bo);
1867 rb->bo = NULL;
1868 }
1869 }
1870
1871 void
1872 radeonDestroyBuffer(__DRIdrawable *driDrawPriv)
1873 {
1874 struct radeon_framebuffer *rfb;
1875 if (!driDrawPriv)
1876 return;
1877
1878 rfb = (void*)driDrawPriv->driverPrivate;
1879 if (!rfb)
1880 return;
1881 radeon_cleanup_renderbuffers(rfb);
1882 _mesa_reference_framebuffer((struct gl_framebuffer **)(&(driDrawPriv->driverPrivate)), NULL);
1883 }
1884
1885
1886 /**
1887 * This is the driver specific part of the createNewScreen entry point.
1888 *
1889 * \todo maybe fold this into intelInitDriver
1890 *
1891 * \return the struct gl_config supported by this driver
1892 */
1893 static const __DRIconfig **
1894 radeonInitScreen(__DRIscreen *psp)
1895 {
1896 #if defined(RADEON_R100)
1897 static const char *driver_name = "Radeon";
1898 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1899 static const __DRIversion dri_expected = { 4, 0, 0 };
1900 static const __DRIversion drm_expected = { 1, 6, 0 };
1901 #elif defined(RADEON_R200)
1902 static const char *driver_name = "R200";
1903 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1904 static const __DRIversion dri_expected = { 4, 0, 0 };
1905 static const __DRIversion drm_expected = { 1, 6, 0 };
1906 #elif defined(RADEON_R300)
1907 static const char *driver_name = "R300";
1908 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1909 static const __DRIversion dri_expected = { 4, 0, 0 };
1910 static const __DRIversion drm_expected = { 1, 24, 0 };
1911 #elif defined(RADEON_R600)
1912 static const char *driver_name = "R600";
1913 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1914 static const __DRIversion dri_expected = { 4, 0, 0 };
1915 static const __DRIversion drm_expected = { 1, 24, 0 };
1916 #endif
1917 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1918
1919 if ( ! driCheckDriDdxDrmVersions3( driver_name,
1920 &psp->dri_version, & dri_expected,
1921 &psp->ddx_version, & ddx_expected,
1922 &psp->drm_version, & drm_expected ) ) {
1923 return NULL;
1924 }
1925
1926 if (!radeonInitDriver(psp))
1927 return NULL;
1928
1929 /* for now fill in all modes */
1930 return radeonFillInModes( psp,
1931 dri_priv->bpp,
1932 (dri_priv->bpp == 16) ? 16 : 24,
1933 (dri_priv->bpp == 16) ? 0 : 8, 1);
1934 }
1935 #define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
1936
1937 /**
1938 * This is the driver specific part of the createNewScreen entry point.
1939 * Called when using DRI2.
1940 *
1941 * \return the struct gl_config supported by this driver
1942 */
1943 static const
1944 __DRIconfig **radeonInitScreen2(__DRIscreen *psp)
1945 {
1946 GLenum fb_format[3];
1947 GLenum fb_type[3];
1948 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
1949 * support pageflipping at all.
1950 */
1951 static const GLenum back_buffer_modes[] = {
1952 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/
1953 };
1954 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
1955 int color;
1956 __DRIconfig **configs = NULL;
1957
1958 if (!radeonInitDriver(psp)) {
1959 return NULL;
1960 }
1961 depth_bits[0] = 0;
1962 stencil_bits[0] = 0;
1963 depth_bits[1] = 16;
1964 stencil_bits[1] = 0;
1965 depth_bits[2] = 24;
1966 stencil_bits[2] = 0;
1967 depth_bits[3] = 24;
1968 stencil_bits[3] = 8;
1969
1970 msaa_samples_array[0] = 0;
1971
1972 fb_format[0] = GL_RGB;
1973 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5;
1974
1975 fb_format[1] = GL_BGR;
1976 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV;
1977
1978 fb_format[2] = GL_BGRA;
1979 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
1980
1981 for (color = 0; color < ARRAY_SIZE(fb_format); color++) {
1982 __DRIconfig **new_configs;
1983
1984 new_configs = driCreateConfigs(fb_format[color], fb_type[color],
1985 depth_bits,
1986 stencil_bits,
1987 ARRAY_SIZE(depth_bits),
1988 back_buffer_modes,
1989 ARRAY_SIZE(back_buffer_modes),
1990 msaa_samples_array,
1991 ARRAY_SIZE(msaa_samples_array),
1992 GL_TRUE);
1993 if (configs == NULL)
1994 configs = new_configs;
1995 else
1996 configs = driConcatConfigs(configs, new_configs);
1997 }
1998
1999 if (configs == NULL) {
2000 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
2001 __LINE__);
2002 return NULL;
2003 }
2004
2005 return (const __DRIconfig **)configs;
2006 }
2007
2008 /**
2009 * Get information about previous buffer swaps.
2010 */
2011 static int
2012 getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo )
2013 {
2014 struct radeon_framebuffer *rfb;
2015
2016 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
2017 || (dPriv->driContextPriv->driverPrivate == NULL)
2018 || (sInfo == NULL) ) {
2019 return -1;
2020 }
2021
2022 rfb = dPriv->driverPrivate;
2023 sInfo->swap_count = rfb->swap_count;
2024 sInfo->swap_ust = rfb->swap_ust;
2025 sInfo->swap_missed_count = rfb->swap_missed_count;
2026
2027 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
2028 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust )
2029 : 0.0;
2030
2031 return 0;
2032 }
2033
2034 const struct __DriverAPIRec driDriverAPI = {
2035 .InitScreen = radeonInitScreen,
2036 .DestroyScreen = radeonDestroyScreen,
2037 #if defined(RADEON_R200)
2038 .CreateContext = r200CreateContext,
2039 .DestroyContext = r200DestroyContext,
2040 #elif defined(RADEON_R600)
2041 .CreateContext = r600CreateContext,
2042 .DestroyContext = radeonDestroyContext,
2043 #elif defined(RADEON_R300)
2044 .CreateContext = r300CreateContext,
2045 .DestroyContext = radeonDestroyContext,
2046 #else
2047 .CreateContext = r100CreateContext,
2048 .DestroyContext = radeonDestroyContext,
2049 #endif
2050 .CreateBuffer = radeonCreateBuffer,
2051 .DestroyBuffer = radeonDestroyBuffer,
2052 .SwapBuffers = radeonSwapBuffers,
2053 .MakeCurrent = radeonMakeCurrent,
2054 .UnbindContext = radeonUnbindContext,
2055 .GetSwapInfo = getSwapInfo,
2056 .GetDrawableMSC = driDrawableGetMSC32,
2057 .WaitForMSC = driWaitForMSC32,
2058 .WaitForSBC = NULL,
2059 .SwapBuffersMSC = NULL,
2060 .CopySubBuffer = radeonCopySubBuffer,
2061 /* DRI2 */
2062 .InitScreen2 = radeonInitScreen2,
2063 };
2064
2065 /* This is the table of extensions that the loader will dlsym() for. */
2066 PUBLIC const __DRIextension *__driDriverExtensions[] = {
2067 &driCoreExtension.base,
2068 &driLegacyExtension.base,
2069 &driDRI2Extension.base,
2070 NULL
2071 };