1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
32 * \file radeon_screen.c
33 * Screen initialization functions for the Radeon driver.
35 * \author Kevin E. Martin <martin@valinux.com>
36 * \author Gareth Hughes <gareth@valinux.com>
42 #include "framebuffer.h"
43 #include "renderbuffer.h"
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
50 #include "radeon_context.h"
51 #include "radeon_span.h"
52 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
53 #include "r200_context.h"
54 #include "r200_ioctl.h"
55 #include "r200_span.h"
57 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
58 #include "r300_context.h"
59 #include "r300_fragprog.h"
61 #include "radeon_span.h"
67 #include "drirenderbuffer.h"
69 #include "GL/internal/dri_interface.h"
71 /* Radeon configuration
75 #if !RADEON_COMMON /* R100 */
76 PUBLIC
const char __driConfigOptions
[] =
78 DRI_CONF_SECTION_PERFORMANCE
79 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
80 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
81 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
82 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
83 DRI_CONF_HYPERZ(false)
85 DRI_CONF_SECTION_QUALITY
86 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
87 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
88 DRI_CONF_NO_NEG_LOD_BIAS(false)
89 DRI_CONF_FORCE_S3TC_ENABLE(false)
90 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
91 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
92 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
93 DRI_CONF_ALLOW_LARGE_TEXTURES(1)
95 DRI_CONF_SECTION_DEBUG
96 DRI_CONF_NO_RAST(false)
99 static const GLuint __driNConfigOptions
= 14;
101 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
103 PUBLIC
const char __driConfigOptions
[] =
105 DRI_CONF_SECTION_PERFORMANCE
106 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
107 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
108 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
109 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
110 DRI_CONF_HYPERZ(false)
112 DRI_CONF_SECTION_QUALITY
113 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
114 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
115 DRI_CONF_NO_NEG_LOD_BIAS(false)
116 DRI_CONF_FORCE_S3TC_ENABLE(false)
117 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
118 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
119 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
120 DRI_CONF_ALLOW_LARGE_TEXTURES(1)
121 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
123 DRI_CONF_SECTION_DEBUG
124 DRI_CONF_NO_RAST(false)
126 DRI_CONF_SECTION_SOFTWARE
127 DRI_CONF_NV_VERTEX_PROGRAM(false)
130 static const GLuint __driNConfigOptions
= 16;
132 extern const struct dri_extension blend_extensions
[];
133 extern const struct dri_extension ARB_vp_extension
[];
134 extern const struct dri_extension NV_vp_extension
[];
135 extern const struct dri_extension ATI_fs_extension
[];
136 extern const struct dri_extension point_extensions
[];
138 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
140 /* TODO: integrate these into xmlpool.h! */
141 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
142 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
143 DRI_CONF_DESC(en,"Number of texture image units") \
144 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
147 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
148 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
149 DRI_CONF_DESC(en,"Number of texture coordinate units") \
150 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
153 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
154 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
155 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
156 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
159 #define DRI_CONF_DISABLE_S3TC(def) \
160 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
161 DRI_CONF_DESC(en,"Disable S3TC compression") \
164 #define DRI_CONF_DISABLE_FALLBACK(def) \
165 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
166 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
169 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
170 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
171 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
174 #define DRI_CONF_FP_OPTIMIZATION(def) \
175 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
176 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
177 DRI_CONF_ENUM(0,"Optimize for Speed") \
178 DRI_CONF_ENUM(1,"Optimize for Quality") \
182 PUBLIC
const char __driConfigOptions
[] =
184 DRI_CONF_SECTION_PERFORMANCE
185 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
186 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
187 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
188 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
189 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
190 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
191 DRI_CONF_DISABLE_FALLBACK(false)
192 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
194 DRI_CONF_SECTION_QUALITY
195 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
196 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
197 DRI_CONF_NO_NEG_LOD_BIAS(false)
198 DRI_CONF_FORCE_S3TC_ENABLE(false)
199 DRI_CONF_DISABLE_S3TC(false)
200 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
201 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
202 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
203 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED
)
205 DRI_CONF_SECTION_DEBUG
206 DRI_CONF_NO_RAST(false)
209 static const GLuint __driNConfigOptions
= 18;
212 int RADEON_DEBUG
= 0;
214 static const struct dri_debug_control debug_control
[] = {
215 {"fall", DEBUG_FALLBACKS
},
216 {"tex", DEBUG_TEXTURE
},
217 {"ioctl", DEBUG_IOCTL
},
218 {"prim", DEBUG_PRIMS
},
219 {"vert", DEBUG_VERTS
},
220 {"state", DEBUG_STATE
},
221 {"code", DEBUG_CODEGEN
},
222 {"vfmt", DEBUG_VFMT
},
223 {"vtxf", DEBUG_VFMT
},
224 {"verb", DEBUG_VERBOSE
},
227 {"san", DEBUG_SANITY
},
228 {"sync", DEBUG_SYNC
},
229 {"pix", DEBUG_PIXEL
},
230 {"mem", DEBUG_MEMORY
},
231 {"allmsg", ~DEBUG_SYNC
}, /* avoid the term "sync" because the parser uses strstr */
234 #endif /* RADEON_DEBUG */
236 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
238 extern const struct dri_extension card_extensions
[];
240 static int getSwapInfo( __DRIdrawablePrivate
*dPriv
, __DRIswapInfo
* sInfo
);
243 radeonGetParam(int fd
, int param
, void *value
)
246 drm_radeon_getparam_t gp
;
251 ret
= drmCommandWriteRead( fd
, DRM_RADEON_GETPARAM
, &gp
, sizeof(gp
));
255 static __GLcontextModes
*
256 radeonFillInModes( unsigned pixel_bits
, unsigned depth_bits
,
257 unsigned stencil_bits
, GLboolean have_back_buffer
)
259 __GLcontextModes
* modes
;
260 __GLcontextModes
* m
;
262 unsigned depth_buffer_factor
;
263 unsigned back_buffer_factor
;
267 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
268 * enough to add support. Basically, if a context is created with an
269 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
270 * will never be used.
272 static const GLenum back_buffer_modes
[] = {
273 GLX_NONE
, GLX_SWAP_UNDEFINED_OML
/*, GLX_SWAP_COPY_OML */
276 u_int8_t depth_bits_array
[2];
277 u_int8_t stencil_bits_array
[2];
280 depth_bits_array
[0] = depth_bits
;
281 depth_bits_array
[1] = depth_bits
;
283 /* Just like with the accumulation buffer, always provide some modes
284 * with a stencil buffer. It will be a sw fallback, but some apps won't
287 stencil_bits_array
[0] = 0;
288 stencil_bits_array
[1] = (stencil_bits
== 0) ? 8 : stencil_bits
;
290 depth_buffer_factor
= ((depth_bits
!= 0) || (stencil_bits
!= 0)) ? 2 : 1;
291 back_buffer_factor
= (have_back_buffer
) ? 2 : 1;
293 num_modes
= depth_buffer_factor
* back_buffer_factor
* 4;
295 if ( pixel_bits
== 16 ) {
297 fb_type
= GL_UNSIGNED_SHORT_5_6_5
;
301 fb_type
= GL_UNSIGNED_INT_8_8_8_8_REV
;
304 modes
= (*dri_interface
->createContextModes
)( num_modes
, sizeof( __GLcontextModes
) );
306 if ( ! driFillInModes( & m
, fb_format
, fb_type
,
307 depth_bits_array
, stencil_bits_array
, depth_buffer_factor
,
308 back_buffer_modes
, back_buffer_factor
,
310 fprintf( stderr
, "[%s:%u] Error creating FBConfig!\n",
311 __func__
, __LINE__
);
315 if ( ! driFillInModes( & m
, fb_format
, fb_type
,
316 depth_bits_array
, stencil_bits_array
, depth_buffer_factor
,
317 back_buffer_modes
, back_buffer_factor
,
318 GLX_DIRECT_COLOR
) ) {
319 fprintf( stderr
, "[%s:%u] Error creating FBConfig!\n",
320 __func__
, __LINE__
);
324 /* Mark the visual as slow if there are "fake" stencil bits.
326 for ( m
= modes
; m
!= NULL
; m
= m
->next
) {
327 if ( (m
->stencilBits
!= 0) && (m
->stencilBits
!= stencil_bits
) ) {
328 m
->visualRating
= GLX_SLOW_CONFIG
;
335 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
336 static const __DRIallocateExtension r200AllocateExtension
= {
337 { __DRI_ALLOCATE
, __DRI_ALLOCATE_VERSION
},
338 r200AllocateMemoryMESA
,
340 r200GetMemoryOffsetMESA
343 static const __DRItexOffsetExtension r200texOffsetExtension
= {
344 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
349 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
350 static const __DRItexOffsetExtension r300texOffsetExtension
= {
351 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
356 /* Create the device specific screen private data struct.
358 static radeonScreenPtr
359 radeonCreateScreen( __DRIscreenPrivate
*sPriv
)
361 radeonScreenPtr screen
;
362 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
)sPriv
->pDevPriv
;
363 unsigned char *RADEONMMIO
;
366 if (sPriv
->devPrivSize
!= sizeof(RADEONDRIRec
)) {
367 fprintf(stderr
,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
371 /* Allocate the private area */
372 screen
= (radeonScreenPtr
) CALLOC( sizeof(*screen
) );
374 __driUtilMessage("%s: Could not allocate memory for screen structure",
379 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
380 RADEON_DEBUG
= driParseDebugString(getenv("RADEON_DEBUG"), debug_control
);
383 /* parse information in __driConfigOptions */
384 driParseOptionInfo (&screen
->optionCache
,
385 __driConfigOptions
, __driNConfigOptions
);
387 /* This is first since which regions we map depends on whether or
388 * not we are using a PCI card.
390 screen
->card_type
= (dri_priv
->IsPCI
? RADEON_CARD_PCI
: RADEON_CARD_AGP
);
393 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_GART_BUFFER_OFFSET
,
394 &screen
->gart_buffer_offset
);
398 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret
);
402 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_GART_BASE
,
406 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret
);
410 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_IRQ_NR
,
414 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret
);
417 screen
->drmSupportsCubeMapsR200
= (sPriv
->drm_version
.minor
>= 7);
418 screen
->drmSupportsBlendColor
= (sPriv
->drm_version
.minor
>= 11);
419 screen
->drmSupportsTriPerf
= (sPriv
->drm_version
.minor
>= 16);
420 screen
->drmSupportsFragShader
= (sPriv
->drm_version
.minor
>= 18);
421 screen
->drmSupportsPointSprites
= (sPriv
->drm_version
.minor
>= 13);
422 screen
->drmSupportsCubeMapsR100
= (sPriv
->drm_version
.minor
>= 15);
423 screen
->drmSupportsVertexProgram
= (sPriv
->drm_version
.minor
>= 25);
426 screen
->mmio
.handle
= dri_priv
->registerHandle
;
427 screen
->mmio
.size
= dri_priv
->registerSize
;
428 if ( drmMap( sPriv
->fd
,
431 &screen
->mmio
.map
) ) {
433 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__
);
437 RADEONMMIO
= screen
->mmio
.map
;
439 screen
->status
.handle
= dri_priv
->statusHandle
;
440 screen
->status
.size
= dri_priv
->statusSize
;
441 if ( drmMap( sPriv
->fd
,
442 screen
->status
.handle
,
444 &screen
->status
.map
) ) {
445 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
447 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__
);
450 screen
->scratch
= (__volatile__ u_int32_t
*)
451 ((GLubyte
*)screen
->status
.map
+ RADEON_SCRATCH_REG_OFFSET
);
453 screen
->buffers
= drmMapBufs( sPriv
->fd
);
454 if ( !screen
->buffers
) {
455 drmUnmap( screen
->status
.map
, screen
->status
.size
);
456 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
458 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__
);
462 if ( dri_priv
->gartTexHandle
&& dri_priv
->gartTexMapSize
) {
463 screen
->gartTextures
.handle
= dri_priv
->gartTexHandle
;
464 screen
->gartTextures
.size
= dri_priv
->gartTexMapSize
;
465 if ( drmMap( sPriv
->fd
,
466 screen
->gartTextures
.handle
,
467 screen
->gartTextures
.size
,
468 (drmAddressPtr
)&screen
->gartTextures
.map
) ) {
469 drmUnmapBufs( screen
->buffers
);
470 drmUnmap( screen
->status
.map
, screen
->status
.size
);
471 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
473 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__
);
477 screen
->gart_texture_offset
= dri_priv
->gartTexOffset
+ screen
->gart_base
;
480 screen
->chip_flags
= 0;
481 /* XXX: add more chipsets */
482 switch ( dri_priv
->deviceID
) {
483 case PCI_CHIP_RADEON_LY
:
484 case PCI_CHIP_RADEON_LZ
:
485 case PCI_CHIP_RADEON_QY
:
486 case PCI_CHIP_RADEON_QZ
:
487 case PCI_CHIP_RN50_515E
:
488 case PCI_CHIP_RN50_5969
:
489 screen
->chip_family
= CHIP_FAMILY_RV100
;
492 case PCI_CHIP_RS100_4136
:
493 case PCI_CHIP_RS100_4336
:
494 screen
->chip_family
= CHIP_FAMILY_RS100
;
497 case PCI_CHIP_RS200_4137
:
498 case PCI_CHIP_RS200_4337
:
499 case PCI_CHIP_RS250_4237
:
500 case PCI_CHIP_RS250_4437
:
501 screen
->chip_family
= CHIP_FAMILY_RS200
;
504 case PCI_CHIP_RADEON_QD
:
505 case PCI_CHIP_RADEON_QE
:
506 case PCI_CHIP_RADEON_QF
:
507 case PCI_CHIP_RADEON_QG
:
508 /* all original radeons (7200) presumably have a stencil op bug */
509 screen
->chip_family
= CHIP_FAMILY_R100
;
510 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_BROKEN_STENCIL
;
513 case PCI_CHIP_RV200_QW
:
514 case PCI_CHIP_RV200_QX
:
515 case PCI_CHIP_RADEON_LW
:
516 case PCI_CHIP_RADEON_LX
:
517 screen
->chip_family
= CHIP_FAMILY_RV200
;
518 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
521 case PCI_CHIP_R200_BB
:
522 case PCI_CHIP_R200_BC
:
523 case PCI_CHIP_R200_QH
:
524 case PCI_CHIP_R200_QL
:
525 case PCI_CHIP_R200_QM
:
526 screen
->chip_family
= CHIP_FAMILY_R200
;
527 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
530 case PCI_CHIP_RV250_If
:
531 case PCI_CHIP_RV250_Ig
:
532 case PCI_CHIP_RV250_Ld
:
533 case PCI_CHIP_RV250_Lf
:
534 case PCI_CHIP_RV250_Lg
:
535 screen
->chip_family
= CHIP_FAMILY_RV250
;
536 screen
->chip_flags
= R200_CHIPSET_YCBCR_BROKEN
| RADEON_CHIPSET_TCL
;
539 case PCI_CHIP_RV280_5960
:
540 case PCI_CHIP_RV280_5961
:
541 case PCI_CHIP_RV280_5962
:
542 case PCI_CHIP_RV280_5964
:
543 case PCI_CHIP_RV280_5965
:
544 case PCI_CHIP_RV280_5C61
:
545 case PCI_CHIP_RV280_5C63
:
546 screen
->chip_family
= CHIP_FAMILY_RV280
;
547 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
550 case PCI_CHIP_RS300_5834
:
551 case PCI_CHIP_RS300_5835
:
552 case PCI_CHIP_RS350_7834
:
553 case PCI_CHIP_RS350_7835
:
554 screen
->chip_family
= CHIP_FAMILY_RS300
;
557 case PCI_CHIP_R300_AD
:
558 case PCI_CHIP_R300_AE
:
559 case PCI_CHIP_R300_AF
:
560 case PCI_CHIP_R300_AG
:
561 case PCI_CHIP_R300_ND
:
562 case PCI_CHIP_R300_NE
:
563 case PCI_CHIP_R300_NF
:
564 case PCI_CHIP_R300_NG
:
565 screen
->chip_family
= CHIP_FAMILY_R300
;
566 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
569 case PCI_CHIP_RV350_AP
:
570 case PCI_CHIP_RV350_AQ
:
571 case PCI_CHIP_RV350_AR
:
572 case PCI_CHIP_RV350_AS
:
573 case PCI_CHIP_RV350_AT
:
574 case PCI_CHIP_RV350_AV
:
575 case PCI_CHIP_RV350_AU
:
576 case PCI_CHIP_RV350_NP
:
577 case PCI_CHIP_RV350_NQ
:
578 case PCI_CHIP_RV350_NR
:
579 case PCI_CHIP_RV350_NS
:
580 case PCI_CHIP_RV350_NT
:
581 case PCI_CHIP_RV350_NV
:
582 screen
->chip_family
= CHIP_FAMILY_RV350
;
583 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
586 case PCI_CHIP_R350_AH
:
587 case PCI_CHIP_R350_AI
:
588 case PCI_CHIP_R350_AJ
:
589 case PCI_CHIP_R350_AK
:
590 case PCI_CHIP_R350_NH
:
591 case PCI_CHIP_R350_NI
:
592 case PCI_CHIP_R360_NJ
:
593 case PCI_CHIP_R350_NK
:
594 screen
->chip_family
= CHIP_FAMILY_R350
;
595 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
598 case PCI_CHIP_RV370_5460
:
599 case PCI_CHIP_RV370_5462
:
600 case PCI_CHIP_RV370_5464
:
601 case PCI_CHIP_RV370_5B60
:
602 case PCI_CHIP_RV370_5B62
:
603 case PCI_CHIP_RV370_5B63
:
604 case PCI_CHIP_RV370_5B64
:
605 case PCI_CHIP_RV370_5B65
:
606 case PCI_CHIP_RV380_3150
:
607 case PCI_CHIP_RV380_3152
:
608 case PCI_CHIP_RV380_3154
:
609 case PCI_CHIP_RV380_3E50
:
610 case PCI_CHIP_RV380_3E54
:
611 screen
->chip_family
= CHIP_FAMILY_RV380
;
612 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
615 case PCI_CHIP_R420_JN
:
616 case PCI_CHIP_R420_JH
:
617 case PCI_CHIP_R420_JI
:
618 case PCI_CHIP_R420_JJ
:
619 case PCI_CHIP_R420_JK
:
620 case PCI_CHIP_R420_JL
:
621 case PCI_CHIP_R420_JM
:
622 case PCI_CHIP_R420_JO
:
623 case PCI_CHIP_R420_JP
:
624 case PCI_CHIP_R420_JT
:
625 case PCI_CHIP_R481_4B49
:
626 case PCI_CHIP_R481_4B4A
:
627 case PCI_CHIP_R481_4B4B
:
628 case PCI_CHIP_R481_4B4C
:
629 case PCI_CHIP_R423_UH
:
630 case PCI_CHIP_R423_UI
:
631 case PCI_CHIP_R423_UJ
:
632 case PCI_CHIP_R423_UK
:
633 case PCI_CHIP_R430_554C
:
634 case PCI_CHIP_R430_554D
:
635 case PCI_CHIP_R430_554E
:
636 case PCI_CHIP_R430_554F
:
637 case PCI_CHIP_R423_5550
:
638 case PCI_CHIP_R423_UQ
:
639 case PCI_CHIP_R423_UR
:
640 case PCI_CHIP_R423_UT
:
641 case PCI_CHIP_R430_5D48
:
642 case PCI_CHIP_R430_5D49
:
643 case PCI_CHIP_R430_5D4A
:
644 case PCI_CHIP_R480_5D4C
:
645 case PCI_CHIP_R480_5D4D
:
646 case PCI_CHIP_R480_5D4E
:
647 case PCI_CHIP_R480_5D4F
:
648 case PCI_CHIP_R480_5D50
:
649 case PCI_CHIP_R480_5D52
:
650 case PCI_CHIP_R423_5D57
:
651 screen
->chip_family
= CHIP_FAMILY_R420
;
652 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
655 /* RV410 SE chips have half the pipes of regular RV410 */
656 case PCI_CHIP_RV410_5E4C
:
657 case PCI_CHIP_RV410_5E4F
:
658 screen
->chip_family
= CHIP_FAMILY_RV380
;
659 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
662 case PCI_CHIP_RV410_564A
:
663 case PCI_CHIP_RV410_564B
:
664 case PCI_CHIP_RV410_564F
:
665 case PCI_CHIP_RV410_5652
:
666 case PCI_CHIP_RV410_5653
:
667 case PCI_CHIP_RV410_5E48
:
668 case PCI_CHIP_RV410_5E4A
:
669 case PCI_CHIP_RV410_5E4B
:
670 case PCI_CHIP_RV410_5E4D
:
671 screen
->chip_family
= CHIP_FAMILY_RV410
;
672 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
675 case PCI_CHIP_RS480_5954
:
676 case PCI_CHIP_RS480_5955
:
677 case PCI_CHIP_RS482_5974
:
678 case PCI_CHIP_RS482_5975
:
679 case PCI_CHIP_RS400_5A41
:
680 case PCI_CHIP_RS400_5A42
:
681 case PCI_CHIP_RC410_5A61
:
682 case PCI_CHIP_RC410_5A62
:
683 screen
->chip_family
= CHIP_FAMILY_RS400
;
684 fprintf(stderr
, "Warning, xpress200 detected.\n");
688 fprintf(stderr
, "unknown chip id 0x%x, can't guess.\n",
692 if ((screen
->chip_family
== CHIP_FAMILY_R350
|| screen
->chip_family
== CHIP_FAMILY_R300
) &&
693 sPriv
->ddx_version
.minor
< 2) {
694 fprintf(stderr
, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
698 if (screen
->chip_family
<= CHIP_FAMILY_RS200
)
699 screen
->chip_flags
|= RADEON_CLASS_R100
;
700 else if (screen
->chip_family
<= CHIP_FAMILY_RV280
)
701 screen
->chip_flags
|= RADEON_CLASS_R200
;
703 screen
->chip_flags
|= RADEON_CLASS_R300
;
705 screen
->cpp
= dri_priv
->bpp
/ 8;
706 screen
->AGPMode
= dri_priv
->AGPMode
;
708 screen
->fbLocation
= ( INREG( RADEON_MC_FB_LOCATION
) & 0xffff ) << 16;
710 if ( sPriv
->drm_version
.minor
>= 10 ) {
711 drm_radeon_setparam_t sp
;
713 sp
.param
= RADEON_SETPARAM_FB_LOCATION
;
714 sp
.value
= screen
->fbLocation
;
716 drmCommandWrite( sPriv
->fd
, DRM_RADEON_SETPARAM
,
720 screen
->frontOffset
= dri_priv
->frontOffset
;
721 screen
->frontPitch
= dri_priv
->frontPitch
;
722 screen
->backOffset
= dri_priv
->backOffset
;
723 screen
->backPitch
= dri_priv
->backPitch
;
724 screen
->depthOffset
= dri_priv
->depthOffset
;
725 screen
->depthPitch
= dri_priv
->depthPitch
;
727 /* Check if ddx has set up a surface reg to cover depth buffer */
728 screen
->depthHasSurface
= (sPriv
->ddx_version
.major
> 4) ||
729 /* these chips don't use tiled z without hyperz. So always pretend
730 we have set up a surface which will cause linear reads/writes */
731 ((screen
->chip_family
& RADEON_CLASS_R100
) &&
732 !(screen
->chip_flags
& RADEON_CHIPSET_TCL
));
734 if ( dri_priv
->textureSize
== 0 ) {
735 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = screen
->gart_texture_offset
;
736 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
737 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
738 dri_priv
->log2GARTTexGran
;
740 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureOffset
741 + screen
->fbLocation
;
742 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureSize
;
743 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
744 dri_priv
->log2TexGran
;
747 if ( !screen
->gartTextures
.map
|| dri_priv
->textureSize
== 0
748 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
749 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
- 1;
750 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = 0;
751 screen
->texSize
[RADEON_GART_TEX_HEAP
] = 0;
752 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] = 0;
754 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
;
755 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = screen
->gart_texture_offset
;
756 screen
->texSize
[RADEON_GART_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
757 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] =
758 dri_priv
->log2GARTTexGran
;
762 screen
->extensions
[i
++] = &driCopySubBufferExtension
.base
;
763 screen
->extensions
[i
++] = &driFrameTrackingExtension
.base
;
764 screen
->extensions
[i
++] = &driReadDrawableExtension
;
766 if ( screen
->irq
!= 0 ) {
767 screen
->extensions
[i
++] = &driSwapControlExtension
.base
;
768 screen
->extensions
[i
++] = &driMediaStreamCounterExtension
.base
;
771 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
772 if (IS_R200_CLASS(screen
))
773 screen
->extensions
[i
++] = &r200AllocateExtension
.base
;
775 screen
->extensions
[i
++] = &r200texOffsetExtension
.base
;
778 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
779 screen
->extensions
[i
++] = &r300texOffsetExtension
.base
;
782 screen
->extensions
[i
++] = NULL
;
783 sPriv
->extensions
= screen
->extensions
;
785 screen
->driScreen
= sPriv
;
786 screen
->sarea_priv_offset
= dri_priv
->sarea_priv_offset
;
790 /* Destroy the device specific screen private data struct.
793 radeonDestroyScreen( __DRIscreenPrivate
*sPriv
)
795 radeonScreenPtr screen
= (radeonScreenPtr
)sPriv
->private;
800 if ( screen
->gartTextures
.map
) {
801 drmUnmap( screen
->gartTextures
.map
, screen
->gartTextures
.size
);
803 drmUnmapBufs( screen
->buffers
);
804 drmUnmap( screen
->status
.map
, screen
->status
.size
);
805 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
807 /* free all option information */
808 driDestroyOptionInfo (&screen
->optionCache
);
811 sPriv
->private = NULL
;
815 /* Initialize the driver specific screen private data.
818 radeonInitDriver( __DRIscreenPrivate
*sPriv
)
820 sPriv
->private = (void *) radeonCreateScreen( sPriv
);
821 if ( !sPriv
->private ) {
822 radeonDestroyScreen( sPriv
);
831 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
833 * \todo This function (and its interface) will need to be updated to support
837 radeonCreateBuffer( __DRIscreenPrivate
*driScrnPriv
,
838 __DRIdrawablePrivate
*driDrawPriv
,
839 const __GLcontextModes
*mesaVis
,
842 radeonScreenPtr screen
= (radeonScreenPtr
) driScrnPriv
->private;
845 return GL_FALSE
; /* not implemented */
848 const GLboolean swDepth
= GL_FALSE
;
849 const GLboolean swAlpha
= GL_FALSE
;
850 const GLboolean swAccum
= mesaVis
->accumRedBits
> 0;
851 const GLboolean swStencil
= mesaVis
->stencilBits
> 0 &&
852 mesaVis
->depthBits
!= 24;
853 struct gl_framebuffer
*fb
= _mesa_create_framebuffer(mesaVis
);
855 /* front color renderbuffer */
857 driRenderbuffer
*frontRb
858 = driNewRenderbuffer(GL_RGBA
,
859 driScrnPriv
->pFB
+ screen
->frontOffset
,
861 screen
->frontOffset
, screen
->frontPitch
,
863 radeonSetSpanFunctions(frontRb
, mesaVis
);
864 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &frontRb
->Base
);
867 /* back color renderbuffer */
868 if (mesaVis
->doubleBufferMode
) {
869 driRenderbuffer
*backRb
870 = driNewRenderbuffer(GL_RGBA
,
871 driScrnPriv
->pFB
+ screen
->backOffset
,
873 screen
->backOffset
, screen
->backPitch
,
875 radeonSetSpanFunctions(backRb
, mesaVis
);
876 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &backRb
->Base
);
879 /* depth renderbuffer */
880 if (mesaVis
->depthBits
== 16) {
881 driRenderbuffer
*depthRb
882 = driNewRenderbuffer(GL_DEPTH_COMPONENT16
,
883 driScrnPriv
->pFB
+ screen
->depthOffset
,
885 screen
->depthOffset
, screen
->depthPitch
,
887 radeonSetSpanFunctions(depthRb
, mesaVis
);
888 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &depthRb
->Base
);
889 depthRb
->depthHasSurface
= screen
->depthHasSurface
;
891 else if (mesaVis
->depthBits
== 24) {
892 driRenderbuffer
*depthRb
893 = driNewRenderbuffer(GL_DEPTH_COMPONENT24
,
894 driScrnPriv
->pFB
+ screen
->depthOffset
,
896 screen
->depthOffset
, screen
->depthPitch
,
898 radeonSetSpanFunctions(depthRb
, mesaVis
);
899 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &depthRb
->Base
);
900 depthRb
->depthHasSurface
= screen
->depthHasSurface
;
903 /* stencil renderbuffer */
904 if (mesaVis
->stencilBits
> 0 && !swStencil
) {
905 driRenderbuffer
*stencilRb
906 = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT
,
907 driScrnPriv
->pFB
+ screen
->depthOffset
,
909 screen
->depthOffset
, screen
->depthPitch
,
911 radeonSetSpanFunctions(stencilRb
, mesaVis
);
912 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &stencilRb
->Base
);
913 stencilRb
->depthHasSurface
= screen
->depthHasSurface
;
916 _mesa_add_soft_renderbuffers(fb
,
917 GL_FALSE
, /* color */
923 driDrawPriv
->driverPrivate
= (void *) fb
;
925 return (driDrawPriv
->driverPrivate
!= NULL
);
931 radeonDestroyBuffer(__DRIdrawablePrivate
*driDrawPriv
)
933 _mesa_unreference_framebuffer((GLframebuffer
**)(&(driDrawPriv
->driverPrivate
)));
936 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
938 * Choose the appropriate CreateContext function based on the chipset.
939 * Eventually, all drivers will go through this process.
941 static GLboolean
radeonCreateContext(const __GLcontextModes
* glVisual
,
942 __DRIcontextPrivate
* driContextPriv
,
943 void *sharedContextPriv
)
945 __DRIscreenPrivate
*sPriv
= driContextPriv
->driScreenPriv
;
946 radeonScreenPtr screen
= (radeonScreenPtr
) (sPriv
->private);
948 if (IS_R300_CLASS(screen
))
949 return r300CreateContext(glVisual
, driContextPriv
, sharedContextPriv
);
954 * Choose the appropriate DestroyContext function based on the chipset.
956 static void radeonDestroyContext(__DRIcontextPrivate
* driContextPriv
)
958 radeonContextPtr radeon
= (radeonContextPtr
) driContextPriv
->driverPrivate
;
960 if (IS_R300_CLASS(radeon
->radeonScreen
))
961 return r300DestroyContext(driContextPriv
);
967 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
968 static struct __DriverAPIRec radeonAPI
= {
969 .DestroyScreen
= radeonDestroyScreen
,
970 .CreateContext
= radeonCreateContext
,
971 .DestroyContext
= radeonDestroyContext
,
972 .CreateBuffer
= radeonCreateBuffer
,
973 .DestroyBuffer
= radeonDestroyBuffer
,
974 .SwapBuffers
= radeonSwapBuffers
,
975 .MakeCurrent
= radeonMakeCurrent
,
976 .UnbindContext
= radeonUnbindContext
,
977 .GetSwapInfo
= getSwapInfo
,
978 .GetMSC
= driGetMSC32
,
979 .GetDrawableMSC
= driDrawableGetMSC32
,
980 .WaitForMSC
= driWaitForMSC32
,
982 .SwapBuffersMSC
= NULL
,
983 .CopySubBuffer
= radeonCopySubBuffer
,
986 static const struct __DriverAPIRec r200API
= {
987 .DestroyScreen
= radeonDestroyScreen
,
988 .CreateContext
= r200CreateContext
,
989 .DestroyContext
= r200DestroyContext
,
990 .CreateBuffer
= radeonCreateBuffer
,
991 .DestroyBuffer
= radeonDestroyBuffer
,
992 .SwapBuffers
= r200SwapBuffers
,
993 .MakeCurrent
= r200MakeCurrent
,
994 .UnbindContext
= r200UnbindContext
,
995 .GetSwapInfo
= getSwapInfo
,
996 .GetMSC
= driGetMSC32
,
997 .GetDrawableMSC
= driDrawableGetMSC32
,
998 .WaitForMSC
= driWaitForMSC32
,
1000 .SwapBuffersMSC
= NULL
,
1001 .CopySubBuffer
= r200CopySubBuffer
,
1007 * This is the driver specific part of the createNewScreen entry point.
1009 * \todo maybe fold this into intelInitDriver
1011 * \return the __GLcontextModes supported by this driver
1013 __GLcontextModes
*__driDriverInitScreen(__DRIscreenPrivate
*psp
)
1016 static const char *driver_name
= "Radeon";
1017 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1018 static const __DRIversion dri_expected
= { 4, 0, 0 };
1019 static const __DRIversion drm_expected
= { 1, 6, 0 };
1020 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1021 static const char *driver_name
= "R200";
1022 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1023 static const __DRIversion dri_expected
= { 4, 0, 0 };
1024 static const __DRIversion drm_expected
= { 1, 6, 0 };
1025 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1026 static const char *driver_name
= "R300";
1027 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1028 static const __DRIversion dri_expected
= { 4, 0, 0 };
1029 static const __DRIversion drm_expected
= { 1, 24, 0 };
1031 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
) psp
->pDevPriv
;
1033 if ( ! driCheckDriDdxDrmVersions3( driver_name
,
1034 &psp
->dri_version
, & dri_expected
,
1035 &psp
->ddx_version
, & ddx_expected
,
1036 &psp
->drm_version
, & drm_expected
) ) {
1039 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1040 psp
->DriverAPI
= radeonAPI
;
1041 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1042 psp
->DriverAPI
= r200API
;
1045 /* Calling driInitExtensions here, with a NULL context pointer,
1046 * does not actually enable the extensions. It just makes sure
1047 * that all the dispatch offsets for all the extensions that
1048 * *might* be enables are known. This is needed because the
1049 * dispatch offsets need to be known when _mesa_context_create
1050 * is called, but we can't enable the extensions until we have a
1053 * Hello chicken. Hello egg. How are you two today?
1055 driInitExtensions( NULL
, card_extensions
, GL_FALSE
);
1056 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1057 driInitExtensions( NULL
, blend_extensions
, GL_FALSE
);
1058 driInitSingleExtension( NULL
, ARB_vp_extension
);
1059 driInitSingleExtension( NULL
, NV_vp_extension
);
1060 driInitSingleExtension( NULL
, ATI_fs_extension
);
1061 driInitExtensions( NULL
, point_extensions
, GL_FALSE
);
1064 if (!radeonInitDriver(psp
))
1067 return radeonFillInModes( dri_priv
->bpp
,
1068 (dri_priv
->bpp
== 16) ? 16 : 24,
1069 (dri_priv
->bpp
== 16) ? 0 : 8,
1070 (dri_priv
->backOffset
!= dri_priv
->depthOffset
) );
1075 * Get information about previous buffer swaps.
1078 getSwapInfo( __DRIdrawablePrivate
*dPriv
, __DRIswapInfo
* sInfo
)
1080 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1081 radeonContextPtr rmesa
;
1082 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1083 r200ContextPtr rmesa
;
1086 if ( (dPriv
== NULL
) || (dPriv
->driContextPriv
== NULL
)
1087 || (dPriv
->driContextPriv
->driverPrivate
== NULL
)
1088 || (sInfo
== NULL
) ) {
1092 rmesa
= dPriv
->driContextPriv
->driverPrivate
;
1093 sInfo
->swap_count
= rmesa
->swap_count
;
1094 sInfo
->swap_ust
= rmesa
->swap_ust
;
1095 sInfo
->swap_missed_count
= rmesa
->swap_missed_count
;
1097 sInfo
->swap_missed_usage
= (sInfo
->swap_missed_count
!= 0)
1098 ? driCalculateSwapUsage( dPriv
, 0, rmesa
->swap_missed_ust
)