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Merge branch 'r300-vertprog-branch' of ssh://people.freedesktop.org/~z3ro/mesa
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c
1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
2 /**************************************************************************
3
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
6
7 All Rights Reserved.
8
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
16
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
20
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28
29 **************************************************************************/
30
31 /**
32 * \file radeon_screen.c
33 * Screen initialization functions for the Radeon driver.
34 *
35 * \author Kevin E. Martin <martin@valinux.com>
36 * \author Gareth Hughes <gareth@valinux.com>
37 */
38
39 #include "glheader.h"
40 #include "imports.h"
41 #include "mtypes.h"
42 #include "framebuffer.h"
43 #include "renderbuffer.h"
44
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #if !RADEON_COMMON
50 #include "radeon_context.h"
51 #include "radeon_span.h"
52 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
53 #include "r200_context.h"
54 #include "r200_ioctl.h"
55 #include "r200_span.h"
56 #include "r200_tex.h"
57 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
58 #include "r300_context.h"
59 #include "r300_fragprog.h"
60 #include "r300_tex.h"
61 #include "radeon_span.h"
62 #endif
63
64 #include "utils.h"
65 #include "context.h"
66 #include "vblank.h"
67 #include "drirenderbuffer.h"
68
69 #include "GL/internal/dri_interface.h"
70
71 /* Radeon configuration
72 */
73 #include "xmlpool.h"
74
75 #if !RADEON_COMMON /* R100 */
76 PUBLIC const char __driConfigOptions[] =
77 DRI_CONF_BEGIN
78 DRI_CONF_SECTION_PERFORMANCE
79 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
80 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
81 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
82 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
83 DRI_CONF_HYPERZ(false)
84 DRI_CONF_SECTION_END
85 DRI_CONF_SECTION_QUALITY
86 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
87 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
88 DRI_CONF_NO_NEG_LOD_BIAS(false)
89 DRI_CONF_FORCE_S3TC_ENABLE(false)
90 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
91 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
92 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
93 DRI_CONF_ALLOW_LARGE_TEXTURES(1)
94 DRI_CONF_SECTION_END
95 DRI_CONF_SECTION_DEBUG
96 DRI_CONF_NO_RAST(false)
97 DRI_CONF_SECTION_END
98 DRI_CONF_END;
99 static const GLuint __driNConfigOptions = 14;
100
101 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
102
103 PUBLIC const char __driConfigOptions[] =
104 DRI_CONF_BEGIN
105 DRI_CONF_SECTION_PERFORMANCE
106 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
107 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
108 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
109 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
110 DRI_CONF_HYPERZ(false)
111 DRI_CONF_SECTION_END
112 DRI_CONF_SECTION_QUALITY
113 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
114 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
115 DRI_CONF_NO_NEG_LOD_BIAS(false)
116 DRI_CONF_FORCE_S3TC_ENABLE(false)
117 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
118 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
119 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
120 DRI_CONF_ALLOW_LARGE_TEXTURES(1)
121 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
122 DRI_CONF_SECTION_END
123 DRI_CONF_SECTION_DEBUG
124 DRI_CONF_NO_RAST(false)
125 DRI_CONF_SECTION_END
126 DRI_CONF_SECTION_SOFTWARE
127 DRI_CONF_NV_VERTEX_PROGRAM(false)
128 DRI_CONF_SECTION_END
129 DRI_CONF_END;
130 static const GLuint __driNConfigOptions = 16;
131
132 extern const struct dri_extension blend_extensions[];
133 extern const struct dri_extension ARB_vp_extension[];
134 extern const struct dri_extension NV_vp_extension[];
135 extern const struct dri_extension ATI_fs_extension[];
136 extern const struct dri_extension point_extensions[];
137
138 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
139
140 /* TODO: integrate these into xmlpool.h! */
141 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
142 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
143 DRI_CONF_DESC(en,"Number of texture image units") \
144 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
145 DRI_CONF_OPT_END
146
147 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
148 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
149 DRI_CONF_DESC(en,"Number of texture coordinate units") \
150 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
151 DRI_CONF_OPT_END
152
153 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
154 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
155 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
156 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
157 DRI_CONF_OPT_END
158
159 #define DRI_CONF_DISABLE_S3TC(def) \
160 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
161 DRI_CONF_DESC(en,"Disable S3TC compression") \
162 DRI_CONF_OPT_END
163
164 #define DRI_CONF_DISABLE_FALLBACK(def) \
165 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
166 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
167 DRI_CONF_OPT_END
168
169 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
170 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
171 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
172 DRI_CONF_OPT_END
173
174 #define DRI_CONF_FP_OPTIMIZATION(def) \
175 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
176 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
177 DRI_CONF_ENUM(0,"Optimize for Speed") \
178 DRI_CONF_ENUM(1,"Optimize for Quality") \
179 DRI_CONF_DESC_END \
180 DRI_CONF_OPT_END
181
182 PUBLIC const char __driConfigOptions[] =
183 DRI_CONF_BEGIN
184 DRI_CONF_SECTION_PERFORMANCE
185 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
186 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
187 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
188 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
189 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
190 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
191 DRI_CONF_DISABLE_FALLBACK(false)
192 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
193 DRI_CONF_SECTION_END
194 DRI_CONF_SECTION_QUALITY
195 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
196 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
197 DRI_CONF_NO_NEG_LOD_BIAS(false)
198 DRI_CONF_FORCE_S3TC_ENABLE(false)
199 DRI_CONF_DISABLE_S3TC(false)
200 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
201 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
202 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
203 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
204 DRI_CONF_SECTION_END
205 DRI_CONF_SECTION_DEBUG
206 DRI_CONF_NO_RAST(false)
207 DRI_CONF_SECTION_END
208 DRI_CONF_END;
209 static const GLuint __driNConfigOptions = 18;
210
211 #ifndef RADEON_DEBUG
212 int RADEON_DEBUG = 0;
213
214 static const struct dri_debug_control debug_control[] = {
215 {"fall", DEBUG_FALLBACKS},
216 {"tex", DEBUG_TEXTURE},
217 {"ioctl", DEBUG_IOCTL},
218 {"prim", DEBUG_PRIMS},
219 {"vert", DEBUG_VERTS},
220 {"state", DEBUG_STATE},
221 {"code", DEBUG_CODEGEN},
222 {"vfmt", DEBUG_VFMT},
223 {"vtxf", DEBUG_VFMT},
224 {"verb", DEBUG_VERBOSE},
225 {"dri", DEBUG_DRI},
226 {"dma", DEBUG_DMA},
227 {"san", DEBUG_SANITY},
228 {"sync", DEBUG_SYNC},
229 {"pix", DEBUG_PIXEL},
230 {"mem", DEBUG_MEMORY},
231 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
232 {NULL, 0}
233 };
234 #endif /* RADEON_DEBUG */
235
236 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
237
238 extern const struct dri_extension card_extensions[];
239
240 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
241
242 static int
243 radeonGetParam(int fd, int param, void *value)
244 {
245 int ret;
246 drm_radeon_getparam_t gp;
247
248 gp.param = param;
249 gp.value = value;
250
251 ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
252 return ret;
253 }
254
255 static __GLcontextModes *
256 radeonFillInModes( __DRIscreenPrivate *psp,
257 unsigned pixel_bits, unsigned depth_bits,
258 unsigned stencil_bits, GLboolean have_back_buffer )
259 {
260 __GLcontextModes * modes;
261 __GLcontextModes * m;
262 unsigned num_modes;
263 unsigned depth_buffer_factor;
264 unsigned back_buffer_factor;
265 GLenum fb_format;
266 GLenum fb_type;
267
268 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
269 * enough to add support. Basically, if a context is created with an
270 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
271 * will never be used.
272 */
273 static const GLenum back_buffer_modes[] = {
274 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
275 };
276
277 u_int8_t depth_bits_array[2];
278 u_int8_t stencil_bits_array[2];
279
280
281 depth_bits_array[0] = depth_bits;
282 depth_bits_array[1] = depth_bits;
283
284 /* Just like with the accumulation buffer, always provide some modes
285 * with a stencil buffer. It will be a sw fallback, but some apps won't
286 * care about that.
287 */
288 stencil_bits_array[0] = 0;
289 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
290
291 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
292 back_buffer_factor = (have_back_buffer) ? 2 : 1;
293
294 num_modes = depth_buffer_factor * back_buffer_factor * 4;
295
296 if ( pixel_bits == 16 ) {
297 fb_format = GL_RGB;
298 fb_type = GL_UNSIGNED_SHORT_5_6_5;
299 }
300 else {
301 fb_format = GL_BGRA;
302 fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
303 }
304
305 modes = (*psp->contextModes->createContextModes)( num_modes, sizeof( __GLcontextModes ) );
306 m = modes;
307 if ( ! driFillInModes( & m, fb_format, fb_type,
308 depth_bits_array, stencil_bits_array, depth_buffer_factor,
309 back_buffer_modes, back_buffer_factor,
310 GLX_TRUE_COLOR ) ) {
311 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
312 __func__, __LINE__ );
313 return NULL;
314 }
315
316 if ( ! driFillInModes( & m, fb_format, fb_type,
317 depth_bits_array, stencil_bits_array, depth_buffer_factor,
318 back_buffer_modes, back_buffer_factor,
319 GLX_DIRECT_COLOR ) ) {
320 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
321 __func__, __LINE__ );
322 return NULL;
323 }
324
325 /* Mark the visual as slow if there are "fake" stencil bits.
326 */
327 for ( m = modes ; m != NULL ; m = m->next ) {
328 if ( (m->stencilBits != 0) && (m->stencilBits != stencil_bits) ) {
329 m->visualRating = GLX_SLOW_CONFIG;
330 }
331 }
332
333 return modes;
334 }
335
336 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
337 static const __DRIallocateExtension r200AllocateExtension = {
338 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
339 r200AllocateMemoryMESA,
340 r200FreeMemoryMESA,
341 r200GetMemoryOffsetMESA
342 };
343
344 static const __DRItexOffsetExtension r200texOffsetExtension = {
345 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
346 r200SetTexOffset,
347 };
348 #endif
349
350 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
351 static const __DRItexOffsetExtension r300texOffsetExtension = {
352 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
353 r300SetTexOffset,
354 };
355 #endif
356
357 /* Create the device specific screen private data struct.
358 */
359 static radeonScreenPtr
360 radeonCreateScreen( __DRIscreenPrivate *sPriv )
361 {
362 radeonScreenPtr screen;
363 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
364 unsigned char *RADEONMMIO;
365 int i;
366 int ret;
367 uint32_t temp;
368
369 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
370 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
371 return GL_FALSE;
372 }
373
374 /* Allocate the private area */
375 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
376 if ( !screen ) {
377 __driUtilMessage("%s: Could not allocate memory for screen structure",
378 __FUNCTION__);
379 return NULL;
380 }
381
382 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
383 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
384 #endif
385
386 /* parse information in __driConfigOptions */
387 driParseOptionInfo (&screen->optionCache,
388 __driConfigOptions, __driNConfigOptions);
389
390 /* This is first since which regions we map depends on whether or
391 * not we are using a PCI card.
392 */
393 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
394 {
395 int ret;
396 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET,
397 &screen->gart_buffer_offset);
398
399 if (ret) {
400 FREE( screen );
401 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
402 return NULL;
403 }
404
405 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE,
406 &screen->gart_base);
407 if (ret) {
408 FREE( screen );
409 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
410 return NULL;
411 }
412
413 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
414 &screen->irq);
415 if (ret) {
416 FREE( screen );
417 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
418 return NULL;
419 }
420 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
421 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
422 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
423 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
424 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
425 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
426 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
427 }
428
429 screen->mmio.handle = dri_priv->registerHandle;
430 screen->mmio.size = dri_priv->registerSize;
431 if ( drmMap( sPriv->fd,
432 screen->mmio.handle,
433 screen->mmio.size,
434 &screen->mmio.map ) ) {
435 FREE( screen );
436 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
437 return NULL;
438 }
439
440 RADEONMMIO = screen->mmio.map;
441
442 screen->status.handle = dri_priv->statusHandle;
443 screen->status.size = dri_priv->statusSize;
444 if ( drmMap( sPriv->fd,
445 screen->status.handle,
446 screen->status.size,
447 &screen->status.map ) ) {
448 drmUnmap( screen->mmio.map, screen->mmio.size );
449 FREE( screen );
450 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
451 return NULL;
452 }
453 screen->scratch = (__volatile__ u_int32_t *)
454 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
455
456 screen->buffers = drmMapBufs( sPriv->fd );
457 if ( !screen->buffers ) {
458 drmUnmap( screen->status.map, screen->status.size );
459 drmUnmap( screen->mmio.map, screen->mmio.size );
460 FREE( screen );
461 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
462 return NULL;
463 }
464
465 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
466 screen->gartTextures.handle = dri_priv->gartTexHandle;
467 screen->gartTextures.size = dri_priv->gartTexMapSize;
468 if ( drmMap( sPriv->fd,
469 screen->gartTextures.handle,
470 screen->gartTextures.size,
471 (drmAddressPtr)&screen->gartTextures.map ) ) {
472 drmUnmapBufs( screen->buffers );
473 drmUnmap( screen->status.map, screen->status.size );
474 drmUnmap( screen->mmio.map, screen->mmio.size );
475 FREE( screen );
476 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
477 return NULL;
478 }
479
480 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
481 }
482
483 screen->chip_flags = 0;
484 /* XXX: add more chipsets */
485 switch ( dri_priv->deviceID ) {
486 case PCI_CHIP_RADEON_LY:
487 case PCI_CHIP_RADEON_LZ:
488 case PCI_CHIP_RADEON_QY:
489 case PCI_CHIP_RADEON_QZ:
490 case PCI_CHIP_RN50_515E:
491 case PCI_CHIP_RN50_5969:
492 screen->chip_family = CHIP_FAMILY_RV100;
493 break;
494
495 case PCI_CHIP_RS100_4136:
496 case PCI_CHIP_RS100_4336:
497 screen->chip_family = CHIP_FAMILY_RS100;
498 break;
499
500 case PCI_CHIP_RS200_4137:
501 case PCI_CHIP_RS200_4337:
502 case PCI_CHIP_RS250_4237:
503 case PCI_CHIP_RS250_4437:
504 screen->chip_family = CHIP_FAMILY_RS200;
505 break;
506
507 case PCI_CHIP_RADEON_QD:
508 case PCI_CHIP_RADEON_QE:
509 case PCI_CHIP_RADEON_QF:
510 case PCI_CHIP_RADEON_QG:
511 /* all original radeons (7200) presumably have a stencil op bug */
512 screen->chip_family = CHIP_FAMILY_R100;
513 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
514 break;
515
516 case PCI_CHIP_RV200_QW:
517 case PCI_CHIP_RV200_QX:
518 case PCI_CHIP_RADEON_LW:
519 case PCI_CHIP_RADEON_LX:
520 screen->chip_family = CHIP_FAMILY_RV200;
521 screen->chip_flags = RADEON_CHIPSET_TCL;
522 break;
523
524 case PCI_CHIP_R200_BB:
525 case PCI_CHIP_R200_BC:
526 case PCI_CHIP_R200_QH:
527 case PCI_CHIP_R200_QL:
528 case PCI_CHIP_R200_QM:
529 screen->chip_family = CHIP_FAMILY_R200;
530 screen->chip_flags = RADEON_CHIPSET_TCL;
531 break;
532
533 case PCI_CHIP_RV250_If:
534 case PCI_CHIP_RV250_Ig:
535 case PCI_CHIP_RV250_Ld:
536 case PCI_CHIP_RV250_Lf:
537 case PCI_CHIP_RV250_Lg:
538 screen->chip_family = CHIP_FAMILY_RV250;
539 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
540 break;
541
542 case PCI_CHIP_RV280_5960:
543 case PCI_CHIP_RV280_5961:
544 case PCI_CHIP_RV280_5962:
545 case PCI_CHIP_RV280_5964:
546 case PCI_CHIP_RV280_5965:
547 case PCI_CHIP_RV280_5C61:
548 case PCI_CHIP_RV280_5C63:
549 screen->chip_family = CHIP_FAMILY_RV280;
550 screen->chip_flags = RADEON_CHIPSET_TCL;
551 break;
552
553 case PCI_CHIP_RS300_5834:
554 case PCI_CHIP_RS300_5835:
555 case PCI_CHIP_RS350_7834:
556 case PCI_CHIP_RS350_7835:
557 screen->chip_family = CHIP_FAMILY_RS300;
558 break;
559
560 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
561 case PCI_CHIP_R300_AD:
562 screen->chip_family = CHIP_FAMILY_RV350;
563 screen->chip_flags = RADEON_CHIPSET_TCL;
564 break;
565 case PCI_CHIP_R300_AE:
566 case PCI_CHIP_R300_AF:
567 case PCI_CHIP_R300_AG:
568 case PCI_CHIP_R300_ND:
569 case PCI_CHIP_R300_NE:
570 case PCI_CHIP_R300_NF:
571 case PCI_CHIP_R300_NG:
572 screen->chip_family = CHIP_FAMILY_R300;
573 screen->chip_flags = RADEON_CHIPSET_TCL;
574 break;
575
576 case PCI_CHIP_RV350_AP:
577 case PCI_CHIP_RV350_AQ:
578 case PCI_CHIP_RV350_AR:
579 case PCI_CHIP_RV350_AS:
580 case PCI_CHIP_RV350_AT:
581 case PCI_CHIP_RV350_AV:
582 case PCI_CHIP_RV350_AU:
583 case PCI_CHIP_RV350_NP:
584 case PCI_CHIP_RV350_NQ:
585 case PCI_CHIP_RV350_NR:
586 case PCI_CHIP_RV350_NS:
587 case PCI_CHIP_RV350_NT:
588 case PCI_CHIP_RV350_NV:
589 screen->chip_family = CHIP_FAMILY_RV350;
590 screen->chip_flags = RADEON_CHIPSET_TCL;
591 break;
592
593 case PCI_CHIP_R350_AH:
594 case PCI_CHIP_R350_AI:
595 case PCI_CHIP_R350_AJ:
596 case PCI_CHIP_R350_AK:
597 case PCI_CHIP_R350_NH:
598 case PCI_CHIP_R350_NI:
599 case PCI_CHIP_R360_NJ:
600 case PCI_CHIP_R350_NK:
601 screen->chip_family = CHIP_FAMILY_R350;
602 screen->chip_flags = RADEON_CHIPSET_TCL;
603 break;
604
605 case PCI_CHIP_RV370_5460:
606 case PCI_CHIP_RV370_5462:
607 case PCI_CHIP_RV370_5464:
608 case PCI_CHIP_RV370_5B60:
609 case PCI_CHIP_RV370_5B62:
610 case PCI_CHIP_RV370_5B63:
611 case PCI_CHIP_RV370_5B64:
612 case PCI_CHIP_RV370_5B65:
613 case PCI_CHIP_RV370_5657:
614 case PCI_CHIP_RV380_3150:
615 case PCI_CHIP_RV380_3152:
616 case PCI_CHIP_RV380_3154:
617 case PCI_CHIP_RV380_3E50:
618 case PCI_CHIP_RV380_3E54:
619 screen->chip_family = CHIP_FAMILY_RV380;
620 screen->chip_flags = RADEON_CHIPSET_TCL;
621 break;
622
623 case PCI_CHIP_R420_JN:
624 case PCI_CHIP_R420_JH:
625 case PCI_CHIP_R420_JI:
626 case PCI_CHIP_R420_JJ:
627 case PCI_CHIP_R420_JK:
628 case PCI_CHIP_R420_JL:
629 case PCI_CHIP_R420_JM:
630 case PCI_CHIP_R420_JO:
631 case PCI_CHIP_R420_JP:
632 case PCI_CHIP_R420_JT:
633 case PCI_CHIP_R481_4B49:
634 case PCI_CHIP_R481_4B4A:
635 case PCI_CHIP_R481_4B4B:
636 case PCI_CHIP_R481_4B4C:
637 case PCI_CHIP_R423_UH:
638 case PCI_CHIP_R423_UI:
639 case PCI_CHIP_R423_UJ:
640 case PCI_CHIP_R423_UK:
641 case PCI_CHIP_R430_554C:
642 case PCI_CHIP_R430_554D:
643 case PCI_CHIP_R430_554E:
644 case PCI_CHIP_R430_554F:
645 case PCI_CHIP_R423_5550:
646 case PCI_CHIP_R423_UQ:
647 case PCI_CHIP_R423_UR:
648 case PCI_CHIP_R423_UT:
649 case PCI_CHIP_R430_5D48:
650 case PCI_CHIP_R430_5D49:
651 case PCI_CHIP_R430_5D4A:
652 case PCI_CHIP_R480_5D4C:
653 case PCI_CHIP_R480_5D4D:
654 case PCI_CHIP_R480_5D4E:
655 case PCI_CHIP_R480_5D4F:
656 case PCI_CHIP_R480_5D50:
657 case PCI_CHIP_R480_5D52:
658 case PCI_CHIP_R423_5D57:
659 screen->chip_family = CHIP_FAMILY_R420;
660 screen->chip_flags = RADEON_CHIPSET_TCL;
661 break;
662
663 /* RV410 SE chips have half the pipes of regular RV410 */
664 case PCI_CHIP_RV410_5E4C:
665 case PCI_CHIP_RV410_5E4F:
666 screen->chip_family = CHIP_FAMILY_RV380;
667 screen->chip_flags = RADEON_CHIPSET_TCL;
668 break;
669
670 case PCI_CHIP_RV410_564A:
671 case PCI_CHIP_RV410_564B:
672 case PCI_CHIP_RV410_564F:
673 case PCI_CHIP_RV410_5652:
674 case PCI_CHIP_RV410_5653:
675 case PCI_CHIP_RV410_5E48:
676 case PCI_CHIP_RV410_5E4A:
677 case PCI_CHIP_RV410_5E4B:
678 case PCI_CHIP_RV410_5E4D:
679 screen->chip_family = CHIP_FAMILY_RV410;
680 screen->chip_flags = RADEON_CHIPSET_TCL;
681 break;
682
683 case PCI_CHIP_RS480_5954:
684 case PCI_CHIP_RS480_5955:
685 case PCI_CHIP_RS482_5974:
686 case PCI_CHIP_RS482_5975:
687 case PCI_CHIP_RS400_5A41:
688 case PCI_CHIP_RS400_5A42:
689 case PCI_CHIP_RC410_5A61:
690 case PCI_CHIP_RC410_5A62:
691 screen->chip_family = CHIP_FAMILY_RS400;
692 fprintf(stderr, "Warning, xpress200 detected.\n");
693 break;
694
695 case PCI_CHIP_RS690_791E:
696 screen->chip_family = CHIP_FAMILY_RS690;
697 fprintf(stderr, "Warning, RS690 detected, 3D support is incomplete.\n");
698 break;
699
700 default:
701 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
702 dri_priv->deviceID);
703 return NULL;
704 }
705 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
706 sPriv->ddx_version.minor < 2) {
707 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
708 return NULL;
709 }
710
711 if (screen->chip_family <= CHIP_FAMILY_RS200)
712 screen->chip_flags |= RADEON_CLASS_R100;
713 else if (screen->chip_family <= CHIP_FAMILY_RV280)
714 screen->chip_flags |= RADEON_CLASS_R200;
715 else
716 screen->chip_flags |= RADEON_CLASS_R300;
717
718 screen->cpp = dri_priv->bpp / 8;
719 screen->AGPMode = dri_priv->AGPMode;
720
721 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION,
722 &temp);
723 if (ret) {
724 if (screen->chip_family < CHIP_FAMILY_RS690)
725 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
726 else {
727 FREE( screen );
728 fprintf(stderr, "Unable to get fb location need newer drm\n");
729 return NULL;
730 }
731 } else {
732 screen->fbLocation = (temp & 0xffff) << 16;
733 }
734
735 if ( sPriv->drm_version.minor >= 10 ) {
736 drm_radeon_setparam_t sp;
737
738 sp.param = RADEON_SETPARAM_FB_LOCATION;
739 sp.value = screen->fbLocation;
740
741 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
742 &sp, sizeof( sp ) );
743 }
744
745 screen->frontOffset = dri_priv->frontOffset;
746 screen->frontPitch = dri_priv->frontPitch;
747 screen->backOffset = dri_priv->backOffset;
748 screen->backPitch = dri_priv->backPitch;
749 screen->depthOffset = dri_priv->depthOffset;
750 screen->depthPitch = dri_priv->depthPitch;
751
752 /* Check if ddx has set up a surface reg to cover depth buffer */
753 screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
754 /* these chips don't use tiled z without hyperz. So always pretend
755 we have set up a surface which will cause linear reads/writes */
756 ((screen->chip_family & RADEON_CLASS_R100) &&
757 !(screen->chip_flags & RADEON_CHIPSET_TCL));
758
759 if ( dri_priv->textureSize == 0 ) {
760 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
761 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
762 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
763 dri_priv->log2GARTTexGran;
764 } else {
765 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
766 + screen->fbLocation;
767 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
768 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
769 dri_priv->log2TexGran;
770 }
771
772 if ( !screen->gartTextures.map || dri_priv->textureSize == 0
773 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
774 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
775 screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
776 screen->texSize[RADEON_GART_TEX_HEAP] = 0;
777 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
778 } else {
779 screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
780 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
781 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
782 screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
783 dri_priv->log2GARTTexGran;
784 }
785
786 i = 0;
787 screen->extensions[i++] = &driCopySubBufferExtension.base;
788 screen->extensions[i++] = &driFrameTrackingExtension.base;
789 screen->extensions[i++] = &driReadDrawableExtension;
790
791 if ( screen->irq != 0 ) {
792 screen->extensions[i++] = &driSwapControlExtension.base;
793 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
794 }
795
796 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
797 if (IS_R200_CLASS(screen))
798 screen->extensions[i++] = &r200AllocateExtension.base;
799
800 screen->extensions[i++] = &r200texOffsetExtension.base;
801 #endif
802
803 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
804 screen->extensions[i++] = &r300texOffsetExtension.base;
805 #endif
806
807 screen->extensions[i++] = NULL;
808 sPriv->extensions = screen->extensions;
809
810 screen->driScreen = sPriv;
811 screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
812 return screen;
813 }
814
815 /* Destroy the device specific screen private data struct.
816 */
817 static void
818 radeonDestroyScreen( __DRIscreenPrivate *sPriv )
819 {
820 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
821
822 if (!screen)
823 return;
824
825 if ( screen->gartTextures.map ) {
826 drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
827 }
828 drmUnmapBufs( screen->buffers );
829 drmUnmap( screen->status.map, screen->status.size );
830 drmUnmap( screen->mmio.map, screen->mmio.size );
831
832 /* free all option information */
833 driDestroyOptionInfo (&screen->optionCache);
834
835 FREE( screen );
836 sPriv->private = NULL;
837 }
838
839
840 /* Initialize the driver specific screen private data.
841 */
842 static GLboolean
843 radeonInitDriver( __DRIscreenPrivate *sPriv )
844 {
845 sPriv->private = (void *) radeonCreateScreen( sPriv );
846 if ( !sPriv->private ) {
847 radeonDestroyScreen( sPriv );
848 return GL_FALSE;
849 }
850
851 return GL_TRUE;
852 }
853
854
855 /**
856 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
857 *
858 * \todo This function (and its interface) will need to be updated to support
859 * pbuffers.
860 */
861 static GLboolean
862 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
863 __DRIdrawablePrivate *driDrawPriv,
864 const __GLcontextModes *mesaVis,
865 GLboolean isPixmap )
866 {
867 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
868
869 if (isPixmap) {
870 return GL_FALSE; /* not implemented */
871 }
872 else {
873 const GLboolean swDepth = GL_FALSE;
874 const GLboolean swAlpha = GL_FALSE;
875 const GLboolean swAccum = mesaVis->accumRedBits > 0;
876 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
877 mesaVis->depthBits != 24;
878 struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
879
880 /* front color renderbuffer */
881 {
882 driRenderbuffer *frontRb
883 = driNewRenderbuffer(GL_RGBA,
884 driScrnPriv->pFB + screen->frontOffset,
885 screen->cpp,
886 screen->frontOffset, screen->frontPitch,
887 driDrawPriv);
888 radeonSetSpanFunctions(frontRb, mesaVis);
889 _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
890 }
891
892 /* back color renderbuffer */
893 if (mesaVis->doubleBufferMode) {
894 driRenderbuffer *backRb
895 = driNewRenderbuffer(GL_RGBA,
896 driScrnPriv->pFB + screen->backOffset,
897 screen->cpp,
898 screen->backOffset, screen->backPitch,
899 driDrawPriv);
900 radeonSetSpanFunctions(backRb, mesaVis);
901 _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
902 }
903
904 /* depth renderbuffer */
905 if (mesaVis->depthBits == 16) {
906 driRenderbuffer *depthRb
907 = driNewRenderbuffer(GL_DEPTH_COMPONENT16,
908 driScrnPriv->pFB + screen->depthOffset,
909 screen->cpp,
910 screen->depthOffset, screen->depthPitch,
911 driDrawPriv);
912 radeonSetSpanFunctions(depthRb, mesaVis);
913 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
914 depthRb->depthHasSurface = screen->depthHasSurface;
915 }
916 else if (mesaVis->depthBits == 24) {
917 driRenderbuffer *depthRb
918 = driNewRenderbuffer(GL_DEPTH_COMPONENT24,
919 driScrnPriv->pFB + screen->depthOffset,
920 screen->cpp,
921 screen->depthOffset, screen->depthPitch,
922 driDrawPriv);
923 radeonSetSpanFunctions(depthRb, mesaVis);
924 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
925 depthRb->depthHasSurface = screen->depthHasSurface;
926 }
927
928 /* stencil renderbuffer */
929 if (mesaVis->stencilBits > 0 && !swStencil) {
930 driRenderbuffer *stencilRb
931 = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT,
932 driScrnPriv->pFB + screen->depthOffset,
933 screen->cpp,
934 screen->depthOffset, screen->depthPitch,
935 driDrawPriv);
936 radeonSetSpanFunctions(stencilRb, mesaVis);
937 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
938 stencilRb->depthHasSurface = screen->depthHasSurface;
939 }
940
941 _mesa_add_soft_renderbuffers(fb,
942 GL_FALSE, /* color */
943 swDepth,
944 swStencil,
945 swAccum,
946 swAlpha,
947 GL_FALSE /* aux */);
948 driDrawPriv->driverPrivate = (void *) fb;
949
950 return (driDrawPriv->driverPrivate != NULL);
951 }
952 }
953
954
955 static void
956 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
957 {
958 _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)));
959 }
960
961 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
962 /**
963 * Choose the appropriate CreateContext function based on the chipset.
964 * Eventually, all drivers will go through this process.
965 */
966 static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
967 __DRIcontextPrivate * driContextPriv,
968 void *sharedContextPriv)
969 {
970 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
971 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
972
973 if (IS_R300_CLASS(screen))
974 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
975 return GL_FALSE;
976 }
977
978 /**
979 * Choose the appropriate DestroyContext function based on the chipset.
980 */
981 static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
982 {
983 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
984
985 if (IS_R300_CLASS(radeon->radeonScreen))
986 return r300DestroyContext(driContextPriv);
987 }
988
989
990 #endif
991
992 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
993 static struct __DriverAPIRec radeonAPI = {
994 .DestroyScreen = radeonDestroyScreen,
995 .CreateContext = radeonCreateContext,
996 .DestroyContext = radeonDestroyContext,
997 .CreateBuffer = radeonCreateBuffer,
998 .DestroyBuffer = radeonDestroyBuffer,
999 .SwapBuffers = radeonSwapBuffers,
1000 .MakeCurrent = radeonMakeCurrent,
1001 .UnbindContext = radeonUnbindContext,
1002 .GetSwapInfo = getSwapInfo,
1003 .GetDrawableMSC = driDrawableGetMSC32,
1004 .WaitForMSC = driWaitForMSC32,
1005 .WaitForSBC = NULL,
1006 .SwapBuffersMSC = NULL,
1007 .CopySubBuffer = radeonCopySubBuffer,
1008 };
1009 #else
1010 static const struct __DriverAPIRec r200API = {
1011 .DestroyScreen = radeonDestroyScreen,
1012 .CreateContext = r200CreateContext,
1013 .DestroyContext = r200DestroyContext,
1014 .CreateBuffer = radeonCreateBuffer,
1015 .DestroyBuffer = radeonDestroyBuffer,
1016 .SwapBuffers = r200SwapBuffers,
1017 .MakeCurrent = r200MakeCurrent,
1018 .UnbindContext = r200UnbindContext,
1019 .GetSwapInfo = getSwapInfo,
1020 .GetDrawableMSC = driDrawableGetMSC32,
1021 .WaitForMSC = driWaitForMSC32,
1022 .WaitForSBC = NULL,
1023 .SwapBuffersMSC = NULL,
1024 .CopySubBuffer = r200CopySubBuffer,
1025 };
1026 #endif
1027
1028
1029 /**
1030 * This is the driver specific part of the createNewScreen entry point.
1031 *
1032 * \todo maybe fold this into intelInitDriver
1033 *
1034 * \return the __GLcontextModes supported by this driver
1035 */
1036 __GLcontextModes *__driDriverInitScreen(__DRIscreenPrivate *psp)
1037 {
1038 #if !RADEON_COMMON
1039 static const char *driver_name = "Radeon";
1040 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1041 static const __DRIversion dri_expected = { 4, 0, 0 };
1042 static const __DRIversion drm_expected = { 1, 6, 0 };
1043 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1044 static const char *driver_name = "R200";
1045 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1046 static const __DRIversion dri_expected = { 4, 0, 0 };
1047 static const __DRIversion drm_expected = { 1, 6, 0 };
1048 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1049 static const char *driver_name = "R300";
1050 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1051 static const __DRIversion dri_expected = { 4, 0, 0 };
1052 static const __DRIversion drm_expected = { 1, 24, 0 };
1053 #endif
1054 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1055
1056 if ( ! driCheckDriDdxDrmVersions3( driver_name,
1057 &psp->dri_version, & dri_expected,
1058 &psp->ddx_version, & ddx_expected,
1059 &psp->drm_version, & drm_expected ) ) {
1060 return NULL;
1061 }
1062 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1063 psp->DriverAPI = radeonAPI;
1064 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1065 psp->DriverAPI = r200API;
1066 #endif
1067
1068 /* Calling driInitExtensions here, with a NULL context pointer,
1069 * does not actually enable the extensions. It just makes sure
1070 * that all the dispatch offsets for all the extensions that
1071 * *might* be enables are known. This is needed because the
1072 * dispatch offsets need to be known when _mesa_context_create
1073 * is called, but we can't enable the extensions until we have a
1074 * context pointer.
1075 *
1076 * Hello chicken. Hello egg. How are you two today?
1077 */
1078 driInitExtensions( NULL, card_extensions, GL_FALSE );
1079 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1080 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1081 driInitSingleExtension( NULL, ARB_vp_extension );
1082 driInitSingleExtension( NULL, NV_vp_extension );
1083 driInitSingleExtension( NULL, ATI_fs_extension );
1084 driInitExtensions( NULL, point_extensions, GL_FALSE );
1085 #endif
1086
1087 if (!radeonInitDriver(psp))
1088 return NULL;
1089
1090 return radeonFillInModes( psp,
1091 dri_priv->bpp,
1092 (dri_priv->bpp == 16) ? 16 : 24,
1093 (dri_priv->bpp == 16) ? 0 : 8,
1094 (dri_priv->backOffset != dri_priv->depthOffset) );
1095 }
1096
1097
1098 /**
1099 * Get information about previous buffer swaps.
1100 */
1101 static int
1102 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1103 {
1104 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1105 radeonContextPtr rmesa;
1106 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1107 r200ContextPtr rmesa;
1108 #endif
1109
1110 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1111 || (dPriv->driContextPriv->driverPrivate == NULL)
1112 || (sInfo == NULL) ) {
1113 return -1;
1114 }
1115
1116 rmesa = dPriv->driContextPriv->driverPrivate;
1117 sInfo->swap_count = rmesa->swap_count;
1118 sInfo->swap_ust = rmesa->swap_ust;
1119 sInfo->swap_missed_count = rmesa->swap_missed_count;
1120
1121 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1122 ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
1123 : 0.0;
1124
1125 return 0;
1126 }