src/mesa/drivers/dri/radeon/radeon_screen.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file radeon_screen.c
  32  * Screen initialization functions for the Radeon driver.
  33  *
  34  * \author Kevin E. Martin <martin@valinux.com>
  35  * \author  Gareth Hughes <gareth@valinux.com>
  36  */
  37
  38 #include "glheader.h"
  39 #include "imports.h"
  40 #include "mtypes.h"
  41 #include "framebuffer.h"
  42 #include "renderbuffer.h"
  43
  44 #define STANDALONE_MMIO
  45 #include "radeon_chipset.h"
  46 #include "radeon_macros.h"
  47 #include "radeon_screen.h"
  48 #if !RADEON_COMMON
  49 #include "radeon_context.h"
  50 #include "radeon_span.h"
  51 #include "radeon_tex.h"
  52 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
  53 #include "r200_context.h"
  54 #include "r200_ioctl.h"
  55 #include "r200_span.h"
  56 #include "r200_tex.h"
  57 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
  58 #include "r300_context.h"
  59 #include "r300_fragprog.h"
  60 #include "r300_tex.h"
  61 #include "radeon_span.h"
  62 #endif
  63
  64 #include "utils.h"
  65 #include "context.h"
  66 #include "vblank.h"
  67 #include "drirenderbuffer.h"
  68
  69 #include "GL/internal/dri_interface.h"
  70
  71 /* Radeon configuration
  72  */
  73 #include "xmlpool.h"
  74
  75 #if !RADEON_COMMON      /* R100 */
  76 PUBLIC const char __driConfigOptions[] =
  77 DRI_CONF_BEGIN
  78     DRI_CONF_SECTION_PERFORMANCE
  79         DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
  80         DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
  81         DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
  82         DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
  83         DRI_CONF_HYPERZ(false)
  84     DRI_CONF_SECTION_END
  85     DRI_CONF_SECTION_QUALITY
  86         DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
  87         DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
  88         DRI_CONF_NO_NEG_LOD_BIAS(false)
  89         DRI_CONF_FORCE_S3TC_ENABLE(false)
  90         DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
  91         DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
  92         DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
  93         DRI_CONF_ALLOW_LARGE_TEXTURES(2)
  94     DRI_CONF_SECTION_END
  95     DRI_CONF_SECTION_DEBUG
  96         DRI_CONF_NO_RAST(false)
  97     DRI_CONF_SECTION_END
  98 DRI_CONF_END;
  99 static const GLuint __driNConfigOptions = 14;
 100
 101 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
 102
 103 PUBLIC const char __driConfigOptions[] =
 104 DRI_CONF_BEGIN
 105     DRI_CONF_SECTION_PERFORMANCE
 106         DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
 107         DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
 108         DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
 109         DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
 110         DRI_CONF_HYPERZ(false)
 111     DRI_CONF_SECTION_END
 112     DRI_CONF_SECTION_QUALITY
 113         DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
 114         DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
 115         DRI_CONF_NO_NEG_LOD_BIAS(false)
 116         DRI_CONF_FORCE_S3TC_ENABLE(false)
 117         DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
 118         DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
 119         DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
 120         DRI_CONF_ALLOW_LARGE_TEXTURES(2)
 121         DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
 122     DRI_CONF_SECTION_END
 123     DRI_CONF_SECTION_DEBUG
 124         DRI_CONF_NO_RAST(false)
 125     DRI_CONF_SECTION_END
 126     DRI_CONF_SECTION_SOFTWARE
 127         DRI_CONF_NV_VERTEX_PROGRAM(false)
 128     DRI_CONF_SECTION_END
 129 DRI_CONF_END;
 130 static const GLuint __driNConfigOptions = 16;
 131
 132 extern const struct dri_extension blend_extensions[];
 133 extern const struct dri_extension ARB_vp_extension[];
 134 extern const struct dri_extension NV_vp_extension[];
 135 extern const struct dri_extension ATI_fs_extension[];
 136 extern const struct dri_extension point_extensions[];
 137
 138 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
 139
 140 /* TODO: integrate these into xmlpool.h! */
 141 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
 142 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
 143         DRI_CONF_DESC(en,"Number of texture image units") \
 144         DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
 145 DRI_CONF_OPT_END
 146
 147 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
 148 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
 149         DRI_CONF_DESC(en,"Number of texture coordinate units") \
 150         DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
 151 DRI_CONF_OPT_END
 152
 153 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
 154 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
 155         DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
 156         DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
 157 DRI_CONF_OPT_END
 158
 159 #define DRI_CONF_DISABLE_S3TC(def) \
 160 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
 161         DRI_CONF_DESC(en,"Disable S3TC compression") \
 162 DRI_CONF_OPT_END
 163
 164 #define DRI_CONF_DISABLE_FALLBACK(def) \
 165 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
 166         DRI_CONF_DESC(en,"Disable Low-impact fallback") \
 167 DRI_CONF_OPT_END
 168
 169 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
 170 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
 171         DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
 172 DRI_CONF_OPT_END
 173
 174 #define DRI_CONF_FP_OPTIMIZATION(def) \
 175 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
 176         DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
 177                 DRI_CONF_ENUM(0,"Optimize for Speed") \
 178                 DRI_CONF_ENUM(1,"Optimize for Quality") \
 179         DRI_CONF_DESC_END \
 180 DRI_CONF_OPT_END
 181
 182 PUBLIC const char __driConfigOptions[] =
 183 DRI_CONF_BEGIN
 184         DRI_CONF_SECTION_PERFORMANCE
 185                 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
 186                 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
 187                 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
 188                 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
 189                 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
 190                 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
 191                 DRI_CONF_DISABLE_FALLBACK(true)
 192                 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
 193         DRI_CONF_SECTION_END
 194         DRI_CONF_SECTION_QUALITY
 195                 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
 196                 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
 197                 DRI_CONF_FORCE_S3TC_ENABLE(false)
 198                 DRI_CONF_DISABLE_S3TC(false)
 199                 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
 200                 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
 201                 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
 202                 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
 203         DRI_CONF_SECTION_END
 204         DRI_CONF_SECTION_DEBUG
 205                 DRI_CONF_NO_RAST(false)
 206         DRI_CONF_SECTION_END
 207 DRI_CONF_END;
 208 static const GLuint __driNConfigOptions = 17;
 209
 210 #ifndef RADEON_DEBUG
 211 int RADEON_DEBUG = 0;
 212
 213 static const struct dri_debug_control debug_control[] = {
 214         {"fall", DEBUG_FALLBACKS},
 215         {"tex", DEBUG_TEXTURE},
 216         {"ioctl", DEBUG_IOCTL},
 217         {"prim", DEBUG_PRIMS},
 218         {"vert", DEBUG_VERTS},
 219         {"state", DEBUG_STATE},
 220         {"code", DEBUG_CODEGEN},
 221         {"vfmt", DEBUG_VFMT},
 222         {"vtxf", DEBUG_VFMT},
 223         {"verb", DEBUG_VERBOSE},
 224         {"dri", DEBUG_DRI},
 225         {"dma", DEBUG_DMA},
 226         {"san", DEBUG_SANITY},
 227         {"sync", DEBUG_SYNC},
 228         {"pix", DEBUG_PIXEL},
 229         {"mem", DEBUG_MEMORY},
 230         {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
 231         {NULL, 0}
 232 };
 233 #endif /* RADEON_DEBUG */
 234
 235 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
 236
 237 extern const struct dri_extension card_extensions[];
 238
 239 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
 240
 241 static int
 242 radeonGetParam(int fd, int param, void *value)
 243 {
 244   int ret;
 245   drm_radeon_getparam_t gp;
 246
 247   gp.param = param;
 248   gp.value = value;
 249
 250   ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
 251   return ret;
 252 }
 253
 254 static const __DRIconfig **
 255 radeonFillInModes( __DRIscreenPrivate *psp,
 256                    unsigned pixel_bits, unsigned depth_bits,
 257                    unsigned stencil_bits, GLboolean have_back_buffer )
 258 {
 259     __DRIconfig **configs;
 260     __GLcontextModes *m;
 261     unsigned depth_buffer_factor;
 262     unsigned back_buffer_factor;
 263     GLenum fb_format;
 264     GLenum fb_type;
 265     int i;
 266
 267     /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
 268      * enough to add support.  Basically, if a context is created with an
 269      * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
 270      * will never be used.
 271      */
 272     static const GLenum back_buffer_modes[] = {
 273         GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
 274     };
 275
 276     uint8_t depth_bits_array[2];
 277     uint8_t stencil_bits_array[2];
 278
 279
 280     depth_bits_array[0] = depth_bits;
 281     depth_bits_array[1] = depth_bits;
 282
 283     /* Just like with the accumulation buffer, always provide some modes
 284      * with a stencil buffer.  It will be a sw fallback, but some apps won't
 285      * care about that.
 286      */
 287     stencil_bits_array[0] = 0;
 288     stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
 289
 290     depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
 291     back_buffer_factor  = (have_back_buffer) ? 2 : 1;
 292
 293     if ( pixel_bits == 16 ) {
 294         fb_format = GL_RGB;
 295         fb_type = GL_UNSIGNED_SHORT_5_6_5;
 296     }
 297     else {
 298         fb_format = GL_BGRA;
 299         fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
 300     }
 301
 302     configs = driCreateConfigs(fb_format, fb_type,
 303                                depth_bits_array, stencil_bits_array,
 304                                depth_buffer_factor,
 305                                back_buffer_modes, back_buffer_factor);
 306     if (configs == NULL) {
 307         fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
 308                  __func__, __LINE__ );
 309         return NULL;
 310     }
 311
 312     /* Mark the visual as slow if there are "fake" stencil bits.
 313      */
 314     for (i = 0; configs[i]; i++) {
 315         m = &configs[i]->modes;
 316         if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
 317             m->visualRating = GLX_SLOW_CONFIG;
 318         }
 319     }
 320
 321     return (const __DRIconfig **) configs;
 322 }
 323
 324 #if !RADEON_COMMON
 325 static const __DRItexOffsetExtension radeonTexOffsetExtension = {
 326     { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
 327     radeonSetTexOffset,
 328 };
 329 #endif
 330
 331 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
 332 static const __DRIallocateExtension r200AllocateExtension = {
 333     { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
 334     r200AllocateMemoryMESA,
 335     r200FreeMemoryMESA,
 336     r200GetMemoryOffsetMESA
 337 };
 338
 339 static const __DRItexOffsetExtension r200texOffsetExtension = {
 340     { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
 341    r200SetTexOffset,
 342 };
 343 #endif
 344
 345 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
 346 static const __DRItexOffsetExtension r300texOffsetExtension = {
 347     { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
 348    r300SetTexOffset,
 349 };
 350 #endif
 351
 352 /* Create the device specific screen private data struct.
 353  */
 354 static radeonScreenPtr
 355 radeonCreateScreen( __DRIscreenPrivate *sPriv )
 356 {
 357    radeonScreenPtr screen;
 358    RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
 359    unsigned char *RADEONMMIO;
 360    int i;
 361    int ret;
 362    uint32_t temp;
 363
 364    if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
 365       fprintf(stderr,"\nERROR!  sizeof(RADEONDRIRec) does not match passed size from device driver\n");
 366       return GL_FALSE;
 367    }
 368
 369    /* Allocate the private area */
 370    screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
 371    if ( !screen ) {
 372       __driUtilMessage("%s: Could not allocate memory for screen structure",
 373                        __FUNCTION__);
 374       return NULL;
 375    }
 376
 377 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
 378         RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
 379 #endif
 380
 381    /* parse information in __driConfigOptions */
 382    driParseOptionInfo (&screen->optionCache,
 383                        __driConfigOptions, __driNConfigOptions);
 384
 385    /* This is first since which regions we map depends on whether or
 386     * not we are using a PCI card.
 387     */
 388    screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
 389    {
 390       int ret;
 391       ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET,
 392                             &screen->gart_buffer_offset);
 393
 394       if (ret) {
 395          FREE( screen );
 396          fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
 397          return NULL;
 398       }
 399
 400       ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE,
 401                             &screen->gart_base);
 402       if (ret) {
 403          FREE( screen );
 404          fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
 405          return NULL;
 406       }
 407
 408       ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
 409                             &screen->irq);
 410       if (ret) {
 411          FREE( screen );
 412          fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
 413          return NULL;
 414       }
 415       screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
 416       screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
 417       screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
 418       screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
 419       screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
 420       screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
 421       screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
 422    }
 423
 424    screen->mmio.handle = dri_priv->registerHandle;
 425    screen->mmio.size   = dri_priv->registerSize;
 426    if ( drmMap( sPriv->fd,
 427                 screen->mmio.handle,
 428                 screen->mmio.size,
 429                 &screen->mmio.map ) ) {
 430       FREE( screen );
 431       __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
 432       return NULL;
 433    }
 434
 435    RADEONMMIO = screen->mmio.map;
 436
 437    screen->status.handle = dri_priv->statusHandle;
 438    screen->status.size   = dri_priv->statusSize;
 439    if ( drmMap( sPriv->fd,
 440                 screen->status.handle,
 441                 screen->status.size,
 442                 &screen->status.map ) ) {
 443       drmUnmap( screen->mmio.map, screen->mmio.size );
 444       FREE( screen );
 445       __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
 446       return NULL;
 447    }
 448    screen->scratch = (__volatile__ uint32_t *)
 449       ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
 450
 451    screen->buffers = drmMapBufs( sPriv->fd );
 452    if ( !screen->buffers ) {
 453       drmUnmap( screen->status.map, screen->status.size );
 454       drmUnmap( screen->mmio.map, screen->mmio.size );
 455       FREE( screen );
 456       __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
 457       return NULL;
 458    }
 459
 460    if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
 461       screen->gartTextures.handle = dri_priv->gartTexHandle;
 462       screen->gartTextures.size   = dri_priv->gartTexMapSize;
 463       if ( drmMap( sPriv->fd,
 464                    screen->gartTextures.handle,
 465                    screen->gartTextures.size,
 466                    (drmAddressPtr)&screen->gartTextures.map ) ) {
 467          drmUnmapBufs( screen->buffers );
 468          drmUnmap( screen->status.map, screen->status.size );
 469          drmUnmap( screen->mmio.map, screen->mmio.size );
 470          FREE( screen );
 471          __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
 472          return NULL;
 473       }
 474
 475       screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
 476    }
 477
 478    screen->chip_flags = 0;
 479    /* XXX: add more chipsets */
 480    switch ( dri_priv->deviceID ) {
 481    case PCI_CHIP_RADEON_LY:
 482    case PCI_CHIP_RADEON_LZ:
 483    case PCI_CHIP_RADEON_QY:
 484    case PCI_CHIP_RADEON_QZ:
 485    case PCI_CHIP_RN50_515E:
 486    case PCI_CHIP_RN50_5969:
 487       screen->chip_family = CHIP_FAMILY_RV100;
 488       break;
 489
 490    case PCI_CHIP_RS100_4136:
 491    case PCI_CHIP_RS100_4336:
 492       screen->chip_family = CHIP_FAMILY_RS100;
 493       break;
 494
 495    case PCI_CHIP_RS200_4137:
 496    case PCI_CHIP_RS200_4337:
 497    case PCI_CHIP_RS250_4237:
 498    case PCI_CHIP_RS250_4437:
 499       screen->chip_family = CHIP_FAMILY_RS200;
 500       break;
 501
 502    case PCI_CHIP_RADEON_QD:
 503    case PCI_CHIP_RADEON_QE:
 504    case PCI_CHIP_RADEON_QF:
 505    case PCI_CHIP_RADEON_QG:
 506       /* all original radeons (7200) presumably have a stencil op bug */
 507       screen->chip_family = CHIP_FAMILY_R100;
 508       screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
 509       break;
 510
 511    case PCI_CHIP_RV200_QW:
 512    case PCI_CHIP_RV200_QX:
 513    case PCI_CHIP_RADEON_LW:
 514    case PCI_CHIP_RADEON_LX:
 515       screen->chip_family = CHIP_FAMILY_RV200;
 516       screen->chip_flags = RADEON_CHIPSET_TCL;
 517       break;
 518
 519    case PCI_CHIP_R200_BB:
 520    case PCI_CHIP_R200_BC:
 521    case PCI_CHIP_R200_QH:
 522    case PCI_CHIP_R200_QL:
 523    case PCI_CHIP_R200_QM:
 524       screen->chip_family = CHIP_FAMILY_R200;
 525       screen->chip_flags = RADEON_CHIPSET_TCL;
 526       break;
 527
 528    case PCI_CHIP_RV250_If:
 529    case PCI_CHIP_RV250_Ig:
 530    case PCI_CHIP_RV250_Ld:
 531    case PCI_CHIP_RV250_Lf:
 532    case PCI_CHIP_RV250_Lg:
 533       screen->chip_family = CHIP_FAMILY_RV250;
 534       screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
 535       break;
 536
 537    case PCI_CHIP_RV280_5960:
 538    case PCI_CHIP_RV280_5961:
 539    case PCI_CHIP_RV280_5962:
 540    case PCI_CHIP_RV280_5964:
 541    case PCI_CHIP_RV280_5965:
 542    case PCI_CHIP_RV280_5C61:
 543    case PCI_CHIP_RV280_5C63:
 544       screen->chip_family = CHIP_FAMILY_RV280;
 545       screen->chip_flags = RADEON_CHIPSET_TCL;
 546       break;
 547
 548    case PCI_CHIP_RS300_5834:
 549    case PCI_CHIP_RS300_5835:
 550    case PCI_CHIP_RS350_7834:
 551    case PCI_CHIP_RS350_7835:
 552       screen->chip_family = CHIP_FAMILY_RS300;
 553       break;
 554
 555       /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
 556    case PCI_CHIP_R300_AD:
 557       screen->chip_family = CHIP_FAMILY_RV350;
 558       screen->chip_flags = RADEON_CHIPSET_TCL;
 559       break;
 560    case PCI_CHIP_R300_AE:
 561    case PCI_CHIP_R300_AF:
 562    case PCI_CHIP_R300_AG:
 563    case PCI_CHIP_R300_ND:
 564    case PCI_CHIP_R300_NE:
 565    case PCI_CHIP_R300_NF:
 566    case PCI_CHIP_R300_NG:
 567       screen->chip_family = CHIP_FAMILY_R300;
 568       screen->chip_flags = RADEON_CHIPSET_TCL;
 569       break;
 570
 571    case PCI_CHIP_RV350_AP:
 572    case PCI_CHIP_RV350_AQ:
 573    case PCI_CHIP_RV350_AR:
 574    case PCI_CHIP_RV350_AS:
 575    case PCI_CHIP_RV350_AT:
 576    case PCI_CHIP_RV350_AV:
 577    case PCI_CHIP_RV350_AU:
 578    case PCI_CHIP_RV350_NP:
 579    case PCI_CHIP_RV350_NQ:
 580    case PCI_CHIP_RV350_NR:
 581    case PCI_CHIP_RV350_NS:
 582    case PCI_CHIP_RV350_NT:
 583    case PCI_CHIP_RV350_NV:
 584       screen->chip_family = CHIP_FAMILY_RV350;
 585       screen->chip_flags = RADEON_CHIPSET_TCL;
 586       break;
 587
 588    case PCI_CHIP_R350_AH:
 589    case PCI_CHIP_R350_AI:
 590    case PCI_CHIP_R350_AJ:
 591    case PCI_CHIP_R350_AK:
 592    case PCI_CHIP_R350_NH:
 593    case PCI_CHIP_R350_NI:
 594    case PCI_CHIP_R360_NJ:
 595    case PCI_CHIP_R350_NK:
 596       screen->chip_family = CHIP_FAMILY_R350;
 597       screen->chip_flags = RADEON_CHIPSET_TCL;
 598       break;
 599
 600    case PCI_CHIP_RV370_5460:
 601    case PCI_CHIP_RV370_5462:
 602    case PCI_CHIP_RV370_5464:
 603    case PCI_CHIP_RV370_5B60:
 604    case PCI_CHIP_RV370_5B62:
 605    case PCI_CHIP_RV370_5B63:
 606    case PCI_CHIP_RV370_5B64:
 607    case PCI_CHIP_RV370_5B65:
 608    case PCI_CHIP_RV380_3150:
 609    case PCI_CHIP_RV380_3152:
 610    case PCI_CHIP_RV380_3154:
 611    case PCI_CHIP_RV380_3E50:
 612    case PCI_CHIP_RV380_3E54:
 613       screen->chip_family = CHIP_FAMILY_RV380;
 614       screen->chip_flags = RADEON_CHIPSET_TCL;
 615       break;
 616
 617    case PCI_CHIP_R420_JN:
 618    case PCI_CHIP_R420_JH:
 619    case PCI_CHIP_R420_JI:
 620    case PCI_CHIP_R420_JJ:
 621    case PCI_CHIP_R420_JK:
 622    case PCI_CHIP_R420_JL:
 623    case PCI_CHIP_R420_JM:
 624    case PCI_CHIP_R420_JO:
 625    case PCI_CHIP_R420_JP:
 626    case PCI_CHIP_R420_JT:
 627    case PCI_CHIP_R481_4B49:
 628    case PCI_CHIP_R481_4B4A:
 629    case PCI_CHIP_R481_4B4B:
 630    case PCI_CHIP_R481_4B4C:
 631    case PCI_CHIP_R423_UH:
 632    case PCI_CHIP_R423_UI:
 633    case PCI_CHIP_R423_UJ:
 634    case PCI_CHIP_R423_UK:
 635    case PCI_CHIP_R430_554C:
 636    case PCI_CHIP_R430_554D:
 637    case PCI_CHIP_R430_554E:
 638    case PCI_CHIP_R430_554F:
 639    case PCI_CHIP_R423_5550:
 640    case PCI_CHIP_R423_UQ:
 641    case PCI_CHIP_R423_UR:
 642    case PCI_CHIP_R423_UT:
 643    case PCI_CHIP_R430_5D48:
 644    case PCI_CHIP_R430_5D49:
 645    case PCI_CHIP_R430_5D4A:
 646    case PCI_CHIP_R480_5D4C:
 647    case PCI_CHIP_R480_5D4D:
 648    case PCI_CHIP_R480_5D4E:
 649    case PCI_CHIP_R480_5D4F:
 650    case PCI_CHIP_R480_5D50:
 651    case PCI_CHIP_R480_5D52:
 652    case PCI_CHIP_R423_5D57:
 653       screen->chip_family = CHIP_FAMILY_R420;
 654       screen->chip_flags = RADEON_CHIPSET_TCL;
 655       break;
 656
 657    case PCI_CHIP_RV410_5E4C:
 658    case PCI_CHIP_RV410_5E4F:
 659    case PCI_CHIP_RV410_564A:
 660    case PCI_CHIP_RV410_564B:
 661    case PCI_CHIP_RV410_564F:
 662    case PCI_CHIP_RV410_5652:
 663    case PCI_CHIP_RV410_5653:
 664    case PCI_CHIP_RV410_5657:
 665    case PCI_CHIP_RV410_5E48:
 666    case PCI_CHIP_RV410_5E4A:
 667    case PCI_CHIP_RV410_5E4B:
 668    case PCI_CHIP_RV410_5E4D:
 669       screen->chip_family = CHIP_FAMILY_RV410;
 670       screen->chip_flags = RADEON_CHIPSET_TCL;
 671       break;
 672
 673    case PCI_CHIP_RS480_5954:
 674    case PCI_CHIP_RS480_5955:
 675    case PCI_CHIP_RS482_5974:
 676    case PCI_CHIP_RS482_5975:
 677    case PCI_CHIP_RS400_5A41:
 678    case PCI_CHIP_RS400_5A42:
 679    case PCI_CHIP_RC410_5A61:
 680    case PCI_CHIP_RC410_5A62:
 681       screen->chip_family = CHIP_FAMILY_RS400;
 682       break;
 683
 684    case PCI_CHIP_RS690_791E:
 685    case PCI_CHIP_RS690_791F:
 686       screen->chip_family = CHIP_FAMILY_RS690;
 687       break;
 688    case PCI_CHIP_RS740_796C:
 689    case PCI_CHIP_RS740_796D:
 690    case PCI_CHIP_RS740_796E:
 691    case PCI_CHIP_RS740_796F:
 692       screen->chip_family = CHIP_FAMILY_RS740;
 693       break;
 694
 695    case PCI_CHIP_R520_7100:
 696    case PCI_CHIP_R520_7101:
 697    case PCI_CHIP_R520_7102:
 698    case PCI_CHIP_R520_7103:
 699    case PCI_CHIP_R520_7104:
 700    case PCI_CHIP_R520_7105:
 701    case PCI_CHIP_R520_7106:
 702    case PCI_CHIP_R520_7108:
 703    case PCI_CHIP_R520_7109:
 704    case PCI_CHIP_R520_710A:
 705    case PCI_CHIP_R520_710B:
 706    case PCI_CHIP_R520_710C:
 707    case PCI_CHIP_R520_710E:
 708    case PCI_CHIP_R520_710F:
 709       screen->chip_family = CHIP_FAMILY_R520;
 710       screen->chip_flags = RADEON_CHIPSET_TCL;
 711       break;
 712
 713    case PCI_CHIP_RV515_7140:
 714    case PCI_CHIP_RV515_7141:
 715    case PCI_CHIP_RV515_7142:
 716    case PCI_CHIP_RV515_7143:
 717    case PCI_CHIP_RV515_7144:
 718    case PCI_CHIP_RV515_7145:
 719    case PCI_CHIP_RV515_7146:
 720    case PCI_CHIP_RV515_7147:
 721    case PCI_CHIP_RV515_7149:
 722    case PCI_CHIP_RV515_714A:
 723    case PCI_CHIP_RV515_714B:
 724    case PCI_CHIP_RV515_714C:
 725    case PCI_CHIP_RV515_714D:
 726    case PCI_CHIP_RV515_714E:
 727    case PCI_CHIP_RV515_714F:
 728    case PCI_CHIP_RV515_7151:
 729    case PCI_CHIP_RV515_7152:
 730    case PCI_CHIP_RV515_7153:
 731    case PCI_CHIP_RV515_715E:
 732    case PCI_CHIP_RV515_715F:
 733    case PCI_CHIP_RV515_7180:
 734    case PCI_CHIP_RV515_7181:
 735    case PCI_CHIP_RV515_7183:
 736    case PCI_CHIP_RV515_7186:
 737    case PCI_CHIP_RV515_7187:
 738    case PCI_CHIP_RV515_7188:
 739    case PCI_CHIP_RV515_718A:
 740    case PCI_CHIP_RV515_718B:
 741    case PCI_CHIP_RV515_718C:
 742    case PCI_CHIP_RV515_718D:
 743    case PCI_CHIP_RV515_718F:
 744    case PCI_CHIP_RV515_7193:
 745    case PCI_CHIP_RV515_7196:
 746    case PCI_CHIP_RV515_719B:
 747    case PCI_CHIP_RV515_719F:
 748    case PCI_CHIP_RV515_7200:
 749    case PCI_CHIP_RV515_7210:
 750    case PCI_CHIP_RV515_7211:
 751       screen->chip_family = CHIP_FAMILY_RV515;
 752       screen->chip_flags = RADEON_CHIPSET_TCL;
 753       break;
 754
 755    case PCI_CHIP_RV530_71C0:
 756    case PCI_CHIP_RV530_71C1:
 757    case PCI_CHIP_RV530_71C2:
 758    case PCI_CHIP_RV530_71C3:
 759    case PCI_CHIP_RV530_71C4:
 760    case PCI_CHIP_RV530_71C5:
 761    case PCI_CHIP_RV530_71C6:
 762    case PCI_CHIP_RV530_71C7:
 763    case PCI_CHIP_RV530_71CD:
 764    case PCI_CHIP_RV530_71CE:
 765    case PCI_CHIP_RV530_71D2:
 766    case PCI_CHIP_RV530_71D4:
 767    case PCI_CHIP_RV530_71D5:
 768    case PCI_CHIP_RV530_71D6:
 769    case PCI_CHIP_RV530_71DA:
 770    case PCI_CHIP_RV530_71DE:
 771       screen->chip_family = CHIP_FAMILY_RV530;
 772       screen->chip_flags = RADEON_CHIPSET_TCL;
 773       break;
 774
 775    case PCI_CHIP_R580_7240:
 776    case PCI_CHIP_R580_7243:
 777    case PCI_CHIP_R580_7244:
 778    case PCI_CHIP_R580_7245:
 779    case PCI_CHIP_R580_7246:
 780    case PCI_CHIP_R580_7247:
 781    case PCI_CHIP_R580_7248:
 782    case PCI_CHIP_R580_7249:
 783    case PCI_CHIP_R580_724A:
 784    case PCI_CHIP_R580_724B:
 785    case PCI_CHIP_R580_724C:
 786    case PCI_CHIP_R580_724D:
 787    case PCI_CHIP_R580_724E:
 788    case PCI_CHIP_R580_724F:
 789    case PCI_CHIP_R580_7284:
 790       screen->chip_family = CHIP_FAMILY_R580;
 791       screen->chip_flags = RADEON_CHIPSET_TCL;
 792       break;
 793
 794    case PCI_CHIP_RV570_7280:
 795    case PCI_CHIP_RV560_7281:
 796    case PCI_CHIP_RV560_7283:
 797    case PCI_CHIP_RV560_7287:
 798    case PCI_CHIP_RV570_7288:
 799    case PCI_CHIP_RV570_7289:
 800    case PCI_CHIP_RV570_728B:
 801    case PCI_CHIP_RV570_728C:
 802    case PCI_CHIP_RV560_7290:
 803    case PCI_CHIP_RV560_7291:
 804    case PCI_CHIP_RV560_7293:
 805    case PCI_CHIP_RV560_7297:
 806       screen->chip_family = CHIP_FAMILY_RV560;
 807       screen->chip_flags = RADEON_CHIPSET_TCL;
 808       break;
 809
 810    default:
 811       fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
 812               dri_priv->deviceID);
 813       return NULL;
 814    }
 815    if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
 816        sPriv->ddx_version.minor < 2) {
 817       fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
 818       return NULL;
 819    }
 820
 821    if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
 822       fprintf(stderr, "R500 support requires a newer drm.\n");
 823       return NULL;
 824    }
 825
 826    if (getenv("R300_NO_TCL"))
 827      screen->chip_flags &= ~RADEON_CHIPSET_TCL;
 828
 829    if (screen->chip_family <= CHIP_FAMILY_RS200)
 830       screen->chip_flags |= RADEON_CLASS_R100;
 831    else if (screen->chip_family <= CHIP_FAMILY_RV280)
 832       screen->chip_flags |= RADEON_CLASS_R200;
 833    else
 834       screen->chip_flags |= RADEON_CLASS_R300;
 835
 836    screen->cpp = dri_priv->bpp / 8;
 837    screen->AGPMode = dri_priv->AGPMode;
 838
 839    ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION,
 840                          &temp);
 841    if (ret) {
 842        if (screen->chip_family < CHIP_FAMILY_RS690)
 843            screen->fbLocation      = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
 844        else {
 845            FREE( screen );
 846            fprintf(stderr, "Unable to get fb location need newer drm\n");
 847            return NULL;
 848        }
 849    } else {
 850        screen->fbLocation = (temp & 0xffff) << 16;
 851    }
 852
 853    if (screen->chip_family >= CHIP_FAMILY_RV515) {
 854        ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES,
 855                              &temp);
 856        if (ret) {
 857            fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
 858            switch (screen->chip_family) {
 859            case CHIP_FAMILY_R300:
 860            case CHIP_FAMILY_R350:
 861                screen->num_gb_pipes = 2;
 862                break;
 863            case CHIP_FAMILY_R420:
 864            case CHIP_FAMILY_R520:
 865            case CHIP_FAMILY_R580:
 866            case CHIP_FAMILY_RV560:
 867            case CHIP_FAMILY_RV570:
 868                screen->num_gb_pipes = 4;
 869                break;
 870            case CHIP_FAMILY_RV350:
 871            case CHIP_FAMILY_RV515:
 872            case CHIP_FAMILY_RV530:
 873            case CHIP_FAMILY_RV410:
 874            default:
 875                screen->num_gb_pipes = 1;
 876                break;
 877            }
 878        } else {
 879            screen->num_gb_pipes = temp;
 880        }
 881    }
 882
 883    if ( sPriv->drm_version.minor >= 10 ) {
 884       drm_radeon_setparam_t sp;
 885
 886       sp.param = RADEON_SETPARAM_FB_LOCATION;
 887       sp.value = screen->fbLocation;
 888
 889       drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
 890                        &sp, sizeof( sp ) );
 891    }
 892
 893    screen->frontOffset  = dri_priv->frontOffset;
 894    screen->frontPitch   = dri_priv->frontPitch;
 895    screen->backOffset   = dri_priv->backOffset;
 896    screen->backPitch    = dri_priv->backPitch;
 897    screen->depthOffset  = dri_priv->depthOffset;
 898    screen->depthPitch   = dri_priv->depthPitch;
 899
 900    /* Check if ddx has set up a surface reg to cover depth buffer */
 901    screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
 902       /* these chips don't use tiled z without hyperz. So always pretend
 903          we have set up a surface which will cause linear reads/writes */
 904       ((screen->chip_family & RADEON_CLASS_R100) &&
 905       !(screen->chip_flags & RADEON_CHIPSET_TCL));
 906
 907    if ( dri_priv->textureSize == 0 ) {
 908       screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
 909       screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
 910       screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
 911          dri_priv->log2GARTTexGran;
 912    } else {
 913       screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
 914                                                + screen->fbLocation;
 915       screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
 916       screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
 917          dri_priv->log2TexGran;
 918    }
 919
 920    if ( !screen->gartTextures.map || dri_priv->textureSize == 0
 921         || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
 922       screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
 923       screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
 924       screen->texSize[RADEON_GART_TEX_HEAP] = 0;
 925       screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
 926    } else {
 927       screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
 928       screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
 929       screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
 930       screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
 931          dri_priv->log2GARTTexGran;
 932    }
 933
 934    i = 0;
 935    screen->extensions[i++] = &driCopySubBufferExtension.base;
 936    screen->extensions[i++] = &driFrameTrackingExtension.base;
 937    screen->extensions[i++] = &driReadDrawableExtension;
 938
 939    if ( screen->irq != 0 ) {
 940        screen->extensions[i++] = &driSwapControlExtension.base;
 941        screen->extensions[i++] = &driMediaStreamCounterExtension.base;
 942    }
 943
 944 #if !RADEON_COMMON
 945    screen->extensions[i++] = &radeonTexOffsetExtension.base;
 946 #endif
 947
 948 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
 949    if (IS_R200_CLASS(screen))
 950        screen->extensions[i++] = &r200AllocateExtension.base;
 951
 952    screen->extensions[i++] = &r200texOffsetExtension.base;
 953 #endif
 954
 955 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
 956    screen->extensions[i++] = &r300texOffsetExtension.base;
 957 #endif
 958
 959    screen->extensions[i++] = NULL;
 960    sPriv->extensions = screen->extensions;
 961
 962    screen->driScreen = sPriv;
 963    screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
 964    return screen;
 965 }
 966
 967 /* Destroy the device specific screen private data struct.
 968  */
 969 static void
 970 radeonDestroyScreen( __DRIscreenPrivate *sPriv )
 971 {
 972    radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
 973
 974    if (!screen)
 975       return;
 976
 977    if ( screen->gartTextures.map ) {
 978       drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
 979    }
 980    drmUnmapBufs( screen->buffers );
 981    drmUnmap( screen->status.map, screen->status.size );
 982    drmUnmap( screen->mmio.map, screen->mmio.size );
 983
 984    /* free all option information */
 985    driDestroyOptionInfo (&screen->optionCache);
 986
 987    FREE( screen );
 988    sPriv->private = NULL;
 989 }
 990
 991
 992 /* Initialize the driver specific screen private data.
 993  */
 994 static GLboolean
 995 radeonInitDriver( __DRIscreenPrivate *sPriv )
 996 {
 997    sPriv->private = (void *) radeonCreateScreen( sPriv );
 998    if ( !sPriv->private ) {
 999       radeonDestroyScreen( sPriv );
1000       return GL_FALSE;
1001    }
1002
1003    return GL_TRUE;
1004 }
1005
1006
1007 /**
1008  * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1009  *
1010  * \todo This function (and its interface) will need to be updated to support
1011  * pbuffers.
1012  */
1013 static GLboolean
1014 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
1015                     __DRIdrawablePrivate *driDrawPriv,
1016                     const __GLcontextModes *mesaVis,
1017                     GLboolean isPixmap )
1018 {
1019    radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1020
1021    if (isPixmap) {
1022       return GL_FALSE; /* not implemented */
1023    }
1024    else {
1025       const GLboolean swDepth = GL_FALSE;
1026       const GLboolean swAlpha = GL_FALSE;
1027       const GLboolean swAccum = mesaVis->accumRedBits > 0;
1028       const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1029          mesaVis->depthBits != 24;
1030       struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
1031
1032       /* front color renderbuffer */
1033       {
1034          driRenderbuffer *frontRb
1035             = driNewRenderbuffer(GL_RGBA,
1036                                  driScrnPriv->pFB + screen->frontOffset,
1037                                  screen->cpp,
1038                                  screen->frontOffset, screen->frontPitch,
1039                                  driDrawPriv);
1040          radeonSetSpanFunctions(frontRb, mesaVis);
1041          _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
1042       }
1043
1044       /* back color renderbuffer */
1045       if (mesaVis->doubleBufferMode) {
1046          driRenderbuffer *backRb
1047             = driNewRenderbuffer(GL_RGBA,
1048                                  driScrnPriv->pFB + screen->backOffset,
1049                                  screen->cpp,
1050                                  screen->backOffset, screen->backPitch,
1051                                  driDrawPriv);
1052          radeonSetSpanFunctions(backRb, mesaVis);
1053          _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
1054       }
1055
1056       /* depth renderbuffer */
1057       if (mesaVis->depthBits == 16) {
1058          driRenderbuffer *depthRb
1059             = driNewRenderbuffer(GL_DEPTH_COMPONENT16,
1060                                  driScrnPriv->pFB + screen->depthOffset,
1061                                  screen->cpp,
1062                                  screen->depthOffset, screen->depthPitch,
1063                                  driDrawPriv);
1064          radeonSetSpanFunctions(depthRb, mesaVis);
1065          _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
1066          depthRb->depthHasSurface = screen->depthHasSurface;
1067       }
1068       else if (mesaVis->depthBits == 24) {
1069          driRenderbuffer *depthRb
1070             = driNewRenderbuffer(GL_DEPTH_COMPONENT24,
1071                                  driScrnPriv->pFB + screen->depthOffset,
1072                                  screen->cpp,
1073                                  screen->depthOffset, screen->depthPitch,
1074                                  driDrawPriv);
1075          radeonSetSpanFunctions(depthRb, mesaVis);
1076          _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
1077          depthRb->depthHasSurface = screen->depthHasSurface;
1078       }
1079
1080       /* stencil renderbuffer */
1081       if (mesaVis->stencilBits > 0 && !swStencil) {
1082          driRenderbuffer *stencilRb
1083             = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT,
1084                                  driScrnPriv->pFB + screen->depthOffset,
1085                                  screen->cpp,
1086                                  screen->depthOffset, screen->depthPitch,
1087                                  driDrawPriv);
1088          radeonSetSpanFunctions(stencilRb, mesaVis);
1089          _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
1090          stencilRb->depthHasSurface = screen->depthHasSurface;
1091       }
1092
1093       _mesa_add_soft_renderbuffers(fb,
1094                                    GL_FALSE, /* color */
1095                                    swDepth,
1096                                    swStencil,
1097                                    swAccum,
1098                                    swAlpha,
1099                                    GL_FALSE /* aux */);
1100       driDrawPriv->driverPrivate = (void *) fb;
1101
1102       return (driDrawPriv->driverPrivate != NULL);
1103    }
1104 }
1105
1106
1107 static void
1108 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
1109 {
1110    _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)));
1111 }
1112
1113 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1114 /**
1115  * Choose the appropriate CreateContext function based on the chipset.
1116  * Eventually, all drivers will go through this process.
1117  */
1118 static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
1119                                      __DRIcontextPrivate * driContextPriv,
1120                                      void *sharedContextPriv)
1121 {
1122         __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
1123         radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
1124
1125         if (IS_R300_CLASS(screen))
1126                 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
1127         return GL_FALSE;
1128 }
1129
1130 /**
1131  * Choose the appropriate DestroyContext function based on the chipset.
1132  */
1133 static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
1134 {
1135         radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
1136
1137         if (IS_R300_CLASS(radeon->radeonScreen))
1138                 return r300DestroyContext(driContextPriv);
1139 }
1140
1141
1142 #endif
1143
1144 /**
1145  * This is the driver specific part of the createNewScreen entry point.
1146  *
1147  * \todo maybe fold this into intelInitDriver
1148  *
1149  * \return the __GLcontextModes supported by this driver
1150  */
1151 static const __DRIconfig **
1152 radeonInitScreen(__DRIscreenPrivate *psp)
1153 {
1154 #if !RADEON_COMMON
1155    static const char *driver_name = "Radeon";
1156    static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1157    static const __DRIversion dri_expected = { 4, 0, 0 };
1158    static const __DRIversion drm_expected = { 1, 6, 0 };
1159 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1160    static const char *driver_name = "R200";
1161    static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1162    static const __DRIversion dri_expected = { 4, 0, 0 };
1163    static const __DRIversion drm_expected = { 1, 6, 0 };
1164 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1165    static const char *driver_name = "R300";
1166    static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1167    static const __DRIversion dri_expected = { 4, 0, 0 };
1168    static const __DRIversion drm_expected = { 1, 24, 0 };
1169 #endif
1170    RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1171
1172    if ( ! driCheckDriDdxDrmVersions3( driver_name,
1173                                       &psp->dri_version, & dri_expected,
1174                                       &psp->ddx_version, & ddx_expected,
1175                                       &psp->drm_version, & drm_expected ) ) {
1176       return NULL;
1177    }
1178
1179    /* Calling driInitExtensions here, with a NULL context pointer,
1180     * does not actually enable the extensions.  It just makes sure
1181     * that all the dispatch offsets for all the extensions that
1182     * *might* be enables are known.  This is needed because the
1183     * dispatch offsets need to be known when _mesa_context_create
1184     * is called, but we can't enable the extensions until we have a
1185     * context pointer.
1186     *
1187     * Hello chicken.  Hello egg.  How are you two today?
1188     */
1189    driInitExtensions( NULL, card_extensions, GL_FALSE );
1190 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1191    driInitExtensions( NULL, blend_extensions, GL_FALSE );
1192    driInitSingleExtension( NULL, ARB_vp_extension );
1193    driInitSingleExtension( NULL, NV_vp_extension );
1194    driInitSingleExtension( NULL, ATI_fs_extension );
1195    driInitExtensions( NULL, point_extensions, GL_FALSE );
1196 #endif
1197
1198    if (!radeonInitDriver(psp))
1199        return NULL;
1200
1201    return radeonFillInModes( psp,
1202                              dri_priv->bpp,
1203                              (dri_priv->bpp == 16) ? 16 : 24,
1204                              (dri_priv->bpp == 16) ? 0  : 8,
1205                              (dri_priv->backOffset != dri_priv->depthOffset) );
1206 }
1207
1208
1209 /**
1210  * Get information about previous buffer swaps.
1211  */
1212 static int
1213 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1214 {
1215 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1216    radeonContextPtr  rmesa;
1217 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1218    r200ContextPtr  rmesa;
1219 #endif
1220
1221    if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1222         || (dPriv->driContextPriv->driverPrivate == NULL)
1223         || (sInfo == NULL) ) {
1224       return -1;
1225    }
1226
1227    rmesa = dPriv->driContextPriv->driverPrivate;
1228    sInfo->swap_count = rmesa->swap_count;
1229    sInfo->swap_ust = rmesa->swap_ust;
1230    sInfo->swap_missed_count = rmesa->swap_missed_count;
1231
1232    sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1233        ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
1234        : 0.0;
1235
1236    return 0;
1237 }
1238
1239 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1240 const struct __DriverAPIRec driDriverAPI = {
1241    .InitScreen      = radeonInitScreen,
1242    .DestroyScreen   = radeonDestroyScreen,
1243    .CreateContext   = radeonCreateContext,
1244    .DestroyContext  = radeonDestroyContext,
1245    .CreateBuffer    = radeonCreateBuffer,
1246    .DestroyBuffer   = radeonDestroyBuffer,
1247    .SwapBuffers     = radeonSwapBuffers,
1248    .MakeCurrent     = radeonMakeCurrent,
1249    .UnbindContext   = radeonUnbindContext,
1250    .GetSwapInfo     = getSwapInfo,
1251    .GetDrawableMSC  = driDrawableGetMSC32,
1252    .WaitForMSC      = driWaitForMSC32,
1253    .WaitForSBC      = NULL,
1254    .SwapBuffersMSC  = NULL,
1255    .CopySubBuffer   = radeonCopySubBuffer,
1256 };
1257 #else
1258 const struct __DriverAPIRec driDriverAPI = {
1259    .InitScreen      = radeonInitScreen,
1260    .DestroyScreen   = radeonDestroyScreen,
1261    .CreateContext   = r200CreateContext,
1262    .DestroyContext  = r200DestroyContext,
1263    .CreateBuffer    = radeonCreateBuffer,
1264    .DestroyBuffer   = radeonDestroyBuffer,
1265    .SwapBuffers     = r200SwapBuffers,
1266    .MakeCurrent     = r200MakeCurrent,
1267    .UnbindContext   = r200UnbindContext,
1268    .GetSwapInfo     = getSwapInfo,
1269    .GetDrawableMSC  = driDrawableGetMSC32,
1270    .WaitForMSC      = driWaitForMSC32,
1271    .WaitForSBC      = NULL,
1272    .SwapBuffersMSC  = NULL,
1273    .CopySubBuffer   = r200CopySubBuffer,
1274 };
1275 #endif