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Merge remote branch 'origin/master' into radeon-rewrite
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
36 */
37
38 #include <errno.h>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
44
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #include "radeon_common.h"
50 #include "radeon_span.h"
51 #if !RADEON_COMMON
52 #include "radeon_context.h"
53 #include "radeon_tex.h"
54 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
55 #include "r200_context.h"
56 #include "r200_ioctl.h"
57 #include "r200_tex.h"
58 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
59 #include "r300_context.h"
60 #include "r300_fragprog.h"
61 #include "r300_tex.h"
62 #endif
63
64 #include "utils.h"
65 #include "vblank.h"
66 #include "drirenderbuffer.h"
67
68 #include "radeon_bocs_wrapper.h"
69
70 #include "GL/internal/dri_interface.h"
71
72 /* Radeon configuration
73 */
74 #include "xmlpool.h"
75
76 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
77 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
78 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
79 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
80 DRI_CONF_OPT_END
81
82 #if !RADEON_COMMON /* R100 */
83 PUBLIC const char __driConfigOptions[] =
84 DRI_CONF_BEGIN
85 DRI_CONF_SECTION_PERFORMANCE
86 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
87 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
88 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
89 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
90 DRI_CONF_HYPERZ(false)
91 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
92 DRI_CONF_SECTION_END
93 DRI_CONF_SECTION_QUALITY
94 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
95 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
96 DRI_CONF_NO_NEG_LOD_BIAS(false)
97 DRI_CONF_FORCE_S3TC_ENABLE(false)
98 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
99 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
100 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
101 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
102 DRI_CONF_SECTION_END
103 DRI_CONF_SECTION_DEBUG
104 DRI_CONF_NO_RAST(false)
105 DRI_CONF_SECTION_END
106 DRI_CONF_END;
107 static const GLuint __driNConfigOptions = 15;
108
109 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
110
111 PUBLIC const char __driConfigOptions[] =
112 DRI_CONF_BEGIN
113 DRI_CONF_SECTION_PERFORMANCE
114 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
115 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
116 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
117 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
118 DRI_CONF_HYPERZ(false)
119 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
120 DRI_CONF_SECTION_END
121 DRI_CONF_SECTION_QUALITY
122 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
123 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
124 DRI_CONF_NO_NEG_LOD_BIAS(false)
125 DRI_CONF_FORCE_S3TC_ENABLE(false)
126 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
127 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
128 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
129 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
130 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
131 DRI_CONF_SECTION_END
132 DRI_CONF_SECTION_DEBUG
133 DRI_CONF_NO_RAST(false)
134 DRI_CONF_SECTION_END
135 DRI_CONF_SECTION_SOFTWARE
136 DRI_CONF_NV_VERTEX_PROGRAM(false)
137 DRI_CONF_SECTION_END
138 DRI_CONF_END;
139 static const GLuint __driNConfigOptions = 17;
140
141 extern const struct dri_extension blend_extensions[];
142 extern const struct dri_extension ARB_vp_extension[];
143 extern const struct dri_extension NV_vp_extension[];
144 extern const struct dri_extension ATI_fs_extension[];
145 extern const struct dri_extension point_extensions[];
146
147 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
148
149 /* TODO: integrate these into xmlpool.h! */
150 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
151 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
152 DRI_CONF_DESC(en,"Number of texture image units") \
153 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
154 DRI_CONF_OPT_END
155
156 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
157 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
158 DRI_CONF_DESC(en,"Number of texture coordinate units") \
159 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
160 DRI_CONF_OPT_END
161
162
163
164 #define DRI_CONF_DISABLE_S3TC(def) \
165 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
166 DRI_CONF_DESC(en,"Disable S3TC compression") \
167 DRI_CONF_OPT_END
168
169 #define DRI_CONF_DISABLE_FALLBACK(def) \
170 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
171 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
172 DRI_CONF_OPT_END
173
174 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
175 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
176 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
177 DRI_CONF_OPT_END
178
179 #define DRI_CONF_FP_OPTIMIZATION(def) \
180 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
181 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
182 DRI_CONF_ENUM(0,"Optimize for Speed") \
183 DRI_CONF_ENUM(1,"Optimize for Quality") \
184 DRI_CONF_DESC_END \
185 DRI_CONF_OPT_END
186
187 PUBLIC const char __driConfigOptions[] =
188 DRI_CONF_BEGIN
189 DRI_CONF_SECTION_PERFORMANCE
190 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
191 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
192 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
193 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
194 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
195 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
196 DRI_CONF_DISABLE_FALLBACK(true)
197 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
198 DRI_CONF_SECTION_END
199 DRI_CONF_SECTION_QUALITY
200 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
201 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
202 DRI_CONF_FORCE_S3TC_ENABLE(false)
203 DRI_CONF_DISABLE_S3TC(false)
204 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
205 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
206 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
207 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
208 DRI_CONF_SECTION_END
209 DRI_CONF_SECTION_DEBUG
210 DRI_CONF_NO_RAST(false)
211 DRI_CONF_SECTION_END
212 DRI_CONF_END;
213 static const GLuint __driNConfigOptions = 17;
214
215 extern const struct dri_extension gl_20_extension[];
216
217 #ifndef RADEON_DEBUG
218
219 static const struct dri_debug_control debug_control[] = {
220 {"fall", DEBUG_FALLBACKS},
221 {"tex", DEBUG_TEXTURE},
222 {"ioctl", DEBUG_IOCTL},
223 {"prim", DEBUG_PRIMS},
224 {"vert", DEBUG_VERTS},
225 {"state", DEBUG_STATE},
226 {"code", DEBUG_CODEGEN},
227 {"vfmt", DEBUG_VFMT},
228 {"vtxf", DEBUG_VFMT},
229 {"verb", DEBUG_VERBOSE},
230 {"dri", DEBUG_DRI},
231 {"dma", DEBUG_DMA},
232 {"san", DEBUG_SANITY},
233 {"sync", DEBUG_SYNC},
234 {"pix", DEBUG_PIXEL},
235 {"mem", DEBUG_MEMORY},
236 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
237 {NULL, 0}
238 };
239 #endif /* RADEON_DEBUG */
240
241 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
242
243 extern const struct dri_extension card_extensions[];
244
245 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
246
247 static int
248 radeonGetParam(int fd, int param, void *value)
249 {
250 int ret;
251 drm_radeon_getparam_t gp;
252
253 gp.param = param;
254 gp.value = value;
255
256 ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
257 return ret;
258 }
259
260 static const __DRIconfig **
261 radeonFillInModes( __DRIscreenPrivate *psp,
262 unsigned pixel_bits, unsigned depth_bits,
263 unsigned stencil_bits, GLboolean have_back_buffer )
264 {
265 __DRIconfig **configs;
266 __GLcontextModes *m;
267 unsigned depth_buffer_factor;
268 unsigned back_buffer_factor;
269 GLenum fb_format;
270 GLenum fb_type;
271 int i;
272
273 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
274 * enough to add support. Basically, if a context is created with an
275 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
276 * will never be used.
277 */
278 static const GLenum back_buffer_modes[] = {
279 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
280 };
281
282 uint8_t depth_bits_array[2];
283 uint8_t stencil_bits_array[2];
284 uint8_t msaa_samples_array[1];
285
286 depth_bits_array[0] = depth_bits;
287 depth_bits_array[1] = depth_bits;
288
289 /* Just like with the accumulation buffer, always provide some modes
290 * with a stencil buffer. It will be a sw fallback, but some apps won't
291 * care about that.
292 */
293 stencil_bits_array[0] = 0;
294 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
295
296 msaa_samples_array[0] = 0;
297
298 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
299 back_buffer_factor = (have_back_buffer) ? 2 : 1;
300
301 if ( pixel_bits == 16 ) {
302 fb_format = GL_RGB;
303 fb_type = GL_UNSIGNED_SHORT_5_6_5;
304 }
305 else {
306 fb_format = GL_BGRA;
307 fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
308 }
309
310 configs = driCreateConfigs(fb_format, fb_type,
311 depth_bits_array, stencil_bits_array,
312 depth_buffer_factor,
313 back_buffer_modes, back_buffer_factor,
314 msaa_samples_array, 1);
315 if (configs == NULL) {
316 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
317 __func__, __LINE__ );
318 return NULL;
319 }
320
321 /* Mark the visual as slow if there are "fake" stencil bits.
322 */
323 for (i = 0; configs[i]; i++) {
324 m = &configs[i]->modes;
325 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
326 m->visualRating = GLX_SLOW_CONFIG;
327 }
328 }
329
330 return (const __DRIconfig **) configs;
331 }
332
333 #if !RADEON_COMMON
334 static const __DRItexOffsetExtension radeonTexOffsetExtension = {
335 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
336 radeonSetTexOffset,
337 };
338 #endif
339
340 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
341 static const __DRIallocateExtension r200AllocateExtension = {
342 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
343 r200AllocateMemoryMESA,
344 r200FreeMemoryMESA,
345 r200GetMemoryOffsetMESA
346 };
347
348 static const __DRItexOffsetExtension r200texOffsetExtension = {
349 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
350 r200SetTexOffset,
351 };
352 #endif
353
354 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
355 static const __DRItexOffsetExtension r300texOffsetExtension = {
356 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
357 r300SetTexOffset,
358 };
359
360 void r300SetTexBuffer(__DRIcontext *pDRICtx,
361 GLint target,
362 __DRIdrawable *dPriv);
363 static const __DRItexBufferExtension r300TexBufferExtension = {
364 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
365 r300SetTexBuffer,
366 };
367 #endif
368
369 static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
370 {
371 screen->chip_flags = 0;
372 switch ( device_id ) {
373 case PCI_CHIP_RADEON_LY:
374 case PCI_CHIP_RADEON_LZ:
375 case PCI_CHIP_RADEON_QY:
376 case PCI_CHIP_RADEON_QZ:
377 case PCI_CHIP_RN50_515E:
378 case PCI_CHIP_RN50_5969:
379 screen->chip_family = CHIP_FAMILY_RV100;
380 break;
381
382 case PCI_CHIP_RS100_4136:
383 case PCI_CHIP_RS100_4336:
384 screen->chip_family = CHIP_FAMILY_RS100;
385 break;
386
387 case PCI_CHIP_RS200_4137:
388 case PCI_CHIP_RS200_4337:
389 case PCI_CHIP_RS250_4237:
390 case PCI_CHIP_RS250_4437:
391 screen->chip_family = CHIP_FAMILY_RS200;
392 break;
393
394 case PCI_CHIP_RADEON_QD:
395 case PCI_CHIP_RADEON_QE:
396 case PCI_CHIP_RADEON_QF:
397 case PCI_CHIP_RADEON_QG:
398 /* all original radeons (7200) presumably have a stencil op bug */
399 screen->chip_family = CHIP_FAMILY_R100;
400 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
401 break;
402
403 case PCI_CHIP_RV200_QW:
404 case PCI_CHIP_RV200_QX:
405 case PCI_CHIP_RADEON_LW:
406 case PCI_CHIP_RADEON_LX:
407 screen->chip_family = CHIP_FAMILY_RV200;
408 screen->chip_flags = RADEON_CHIPSET_TCL;
409 break;
410
411 case PCI_CHIP_R200_BB:
412 case PCI_CHIP_R200_BC:
413 case PCI_CHIP_R200_QH:
414 case PCI_CHIP_R200_QL:
415 case PCI_CHIP_R200_QM:
416 screen->chip_family = CHIP_FAMILY_R200;
417 screen->chip_flags = RADEON_CHIPSET_TCL;
418 break;
419
420 case PCI_CHIP_RV250_If:
421 case PCI_CHIP_RV250_Ig:
422 case PCI_CHIP_RV250_Ld:
423 case PCI_CHIP_RV250_Lf:
424 case PCI_CHIP_RV250_Lg:
425 screen->chip_family = CHIP_FAMILY_RV250;
426 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
427 break;
428
429 case PCI_CHIP_RV280_5960:
430 case PCI_CHIP_RV280_5961:
431 case PCI_CHIP_RV280_5962:
432 case PCI_CHIP_RV280_5964:
433 case PCI_CHIP_RV280_5965:
434 case PCI_CHIP_RV280_5C61:
435 case PCI_CHIP_RV280_5C63:
436 screen->chip_family = CHIP_FAMILY_RV280;
437 screen->chip_flags = RADEON_CHIPSET_TCL;
438 break;
439
440 case PCI_CHIP_RS300_5834:
441 case PCI_CHIP_RS300_5835:
442 case PCI_CHIP_RS350_7834:
443 case PCI_CHIP_RS350_7835:
444 screen->chip_family = CHIP_FAMILY_RS300;
445 break;
446
447 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
448 case PCI_CHIP_R300_AD:
449 screen->chip_family = CHIP_FAMILY_RV350;
450 screen->chip_flags = RADEON_CHIPSET_TCL;
451 break;
452 case PCI_CHIP_R300_AE:
453 case PCI_CHIP_R300_AF:
454 case PCI_CHIP_R300_AG:
455 case PCI_CHIP_R300_ND:
456 case PCI_CHIP_R300_NE:
457 case PCI_CHIP_R300_NF:
458 case PCI_CHIP_R300_NG:
459 screen->chip_family = CHIP_FAMILY_R300;
460 screen->chip_flags = RADEON_CHIPSET_TCL;
461 break;
462
463 case PCI_CHIP_RV350_AP:
464 case PCI_CHIP_RV350_AQ:
465 case PCI_CHIP_RV350_AR:
466 case PCI_CHIP_RV350_AS:
467 case PCI_CHIP_RV350_AT:
468 case PCI_CHIP_RV350_AV:
469 case PCI_CHIP_RV350_AU:
470 case PCI_CHIP_RV350_NP:
471 case PCI_CHIP_RV350_NQ:
472 case PCI_CHIP_RV350_NR:
473 case PCI_CHIP_RV350_NS:
474 case PCI_CHIP_RV350_NT:
475 case PCI_CHIP_RV350_NV:
476 screen->chip_family = CHIP_FAMILY_RV350;
477 screen->chip_flags = RADEON_CHIPSET_TCL;
478 break;
479
480 case PCI_CHIP_R350_AH:
481 case PCI_CHIP_R350_AI:
482 case PCI_CHIP_R350_AJ:
483 case PCI_CHIP_R350_AK:
484 case PCI_CHIP_R350_NH:
485 case PCI_CHIP_R350_NI:
486 case PCI_CHIP_R360_NJ:
487 case PCI_CHIP_R350_NK:
488 screen->chip_family = CHIP_FAMILY_R350;
489 screen->chip_flags = RADEON_CHIPSET_TCL;
490 break;
491
492 case PCI_CHIP_RV370_5460:
493 case PCI_CHIP_RV370_5462:
494 case PCI_CHIP_RV370_5464:
495 case PCI_CHIP_RV370_5B60:
496 case PCI_CHIP_RV370_5B62:
497 case PCI_CHIP_RV370_5B63:
498 case PCI_CHIP_RV370_5B64:
499 case PCI_CHIP_RV370_5B65:
500 case PCI_CHIP_RV380_3150:
501 case PCI_CHIP_RV380_3152:
502 case PCI_CHIP_RV380_3154:
503 case PCI_CHIP_RV380_3E50:
504 case PCI_CHIP_RV380_3E54:
505 screen->chip_family = CHIP_FAMILY_RV380;
506 screen->chip_flags = RADEON_CHIPSET_TCL;
507 break;
508
509 case PCI_CHIP_R420_JN:
510 case PCI_CHIP_R420_JH:
511 case PCI_CHIP_R420_JI:
512 case PCI_CHIP_R420_JJ:
513 case PCI_CHIP_R420_JK:
514 case PCI_CHIP_R420_JL:
515 case PCI_CHIP_R420_JM:
516 case PCI_CHIP_R420_JO:
517 case PCI_CHIP_R420_JP:
518 case PCI_CHIP_R420_JT:
519 case PCI_CHIP_R481_4B49:
520 case PCI_CHIP_R481_4B4A:
521 case PCI_CHIP_R481_4B4B:
522 case PCI_CHIP_R481_4B4C:
523 case PCI_CHIP_R423_UH:
524 case PCI_CHIP_R423_UI:
525 case PCI_CHIP_R423_UJ:
526 case PCI_CHIP_R423_UK:
527 case PCI_CHIP_R430_554C:
528 case PCI_CHIP_R430_554D:
529 case PCI_CHIP_R430_554E:
530 case PCI_CHIP_R430_554F:
531 case PCI_CHIP_R423_5550:
532 case PCI_CHIP_R423_UQ:
533 case PCI_CHIP_R423_UR:
534 case PCI_CHIP_R423_UT:
535 case PCI_CHIP_R430_5D48:
536 case PCI_CHIP_R430_5D49:
537 case PCI_CHIP_R430_5D4A:
538 case PCI_CHIP_R480_5D4C:
539 case PCI_CHIP_R480_5D4D:
540 case PCI_CHIP_R480_5D4E:
541 case PCI_CHIP_R480_5D4F:
542 case PCI_CHIP_R480_5D50:
543 case PCI_CHIP_R480_5D52:
544 case PCI_CHIP_R423_5D57:
545 screen->chip_family = CHIP_FAMILY_R420;
546 screen->chip_flags = RADEON_CHIPSET_TCL;
547 break;
548
549 case PCI_CHIP_RV410_5E4C:
550 case PCI_CHIP_RV410_5E4F:
551 case PCI_CHIP_RV410_564A:
552 case PCI_CHIP_RV410_564B:
553 case PCI_CHIP_RV410_564F:
554 case PCI_CHIP_RV410_5652:
555 case PCI_CHIP_RV410_5653:
556 case PCI_CHIP_RV410_5657:
557 case PCI_CHIP_RV410_5E48:
558 case PCI_CHIP_RV410_5E4A:
559 case PCI_CHIP_RV410_5E4B:
560 case PCI_CHIP_RV410_5E4D:
561 screen->chip_family = CHIP_FAMILY_RV410;
562 screen->chip_flags = RADEON_CHIPSET_TCL;
563 break;
564
565 case PCI_CHIP_RS480_5954:
566 case PCI_CHIP_RS480_5955:
567 case PCI_CHIP_RS482_5974:
568 case PCI_CHIP_RS482_5975:
569 case PCI_CHIP_RS400_5A41:
570 case PCI_CHIP_RS400_5A42:
571 case PCI_CHIP_RC410_5A61:
572 case PCI_CHIP_RC410_5A62:
573 screen->chip_family = CHIP_FAMILY_RS400;
574 break;
575
576 case PCI_CHIP_RS690_791E:
577 case PCI_CHIP_RS690_791F:
578 screen->chip_family = CHIP_FAMILY_RS690;
579 break;
580 case PCI_CHIP_RS740_796C:
581 case PCI_CHIP_RS740_796D:
582 case PCI_CHIP_RS740_796E:
583 case PCI_CHIP_RS740_796F:
584 screen->chip_family = CHIP_FAMILY_RS740;
585 break;
586
587 case PCI_CHIP_R520_7100:
588 case PCI_CHIP_R520_7101:
589 case PCI_CHIP_R520_7102:
590 case PCI_CHIP_R520_7103:
591 case PCI_CHIP_R520_7104:
592 case PCI_CHIP_R520_7105:
593 case PCI_CHIP_R520_7106:
594 case PCI_CHIP_R520_7108:
595 case PCI_CHIP_R520_7109:
596 case PCI_CHIP_R520_710A:
597 case PCI_CHIP_R520_710B:
598 case PCI_CHIP_R520_710C:
599 case PCI_CHIP_R520_710E:
600 case PCI_CHIP_R520_710F:
601 screen->chip_family = CHIP_FAMILY_R520;
602 screen->chip_flags = RADEON_CHIPSET_TCL;
603 break;
604
605 case PCI_CHIP_RV515_7140:
606 case PCI_CHIP_RV515_7141:
607 case PCI_CHIP_RV515_7142:
608 case PCI_CHIP_RV515_7143:
609 case PCI_CHIP_RV515_7144:
610 case PCI_CHIP_RV515_7145:
611 case PCI_CHIP_RV515_7146:
612 case PCI_CHIP_RV515_7147:
613 case PCI_CHIP_RV515_7149:
614 case PCI_CHIP_RV515_714A:
615 case PCI_CHIP_RV515_714B:
616 case PCI_CHIP_RV515_714C:
617 case PCI_CHIP_RV515_714D:
618 case PCI_CHIP_RV515_714E:
619 case PCI_CHIP_RV515_714F:
620 case PCI_CHIP_RV515_7151:
621 case PCI_CHIP_RV515_7152:
622 case PCI_CHIP_RV515_7153:
623 case PCI_CHIP_RV515_715E:
624 case PCI_CHIP_RV515_715F:
625 case PCI_CHIP_RV515_7180:
626 case PCI_CHIP_RV515_7181:
627 case PCI_CHIP_RV515_7183:
628 case PCI_CHIP_RV515_7186:
629 case PCI_CHIP_RV515_7187:
630 case PCI_CHIP_RV515_7188:
631 case PCI_CHIP_RV515_718A:
632 case PCI_CHIP_RV515_718B:
633 case PCI_CHIP_RV515_718C:
634 case PCI_CHIP_RV515_718D:
635 case PCI_CHIP_RV515_718F:
636 case PCI_CHIP_RV515_7193:
637 case PCI_CHIP_RV515_7196:
638 case PCI_CHIP_RV515_719B:
639 case PCI_CHIP_RV515_719F:
640 case PCI_CHIP_RV515_7200:
641 case PCI_CHIP_RV515_7210:
642 case PCI_CHIP_RV515_7211:
643 screen->chip_family = CHIP_FAMILY_RV515;
644 screen->chip_flags = RADEON_CHIPSET_TCL;
645 break;
646
647 case PCI_CHIP_RV530_71C0:
648 case PCI_CHIP_RV530_71C1:
649 case PCI_CHIP_RV530_71C2:
650 case PCI_CHIP_RV530_71C3:
651 case PCI_CHIP_RV530_71C4:
652 case PCI_CHIP_RV530_71C5:
653 case PCI_CHIP_RV530_71C6:
654 case PCI_CHIP_RV530_71C7:
655 case PCI_CHIP_RV530_71CD:
656 case PCI_CHIP_RV530_71CE:
657 case PCI_CHIP_RV530_71D2:
658 case PCI_CHIP_RV530_71D4:
659 case PCI_CHIP_RV530_71D5:
660 case PCI_CHIP_RV530_71D6:
661 case PCI_CHIP_RV530_71DA:
662 case PCI_CHIP_RV530_71DE:
663 screen->chip_family = CHIP_FAMILY_RV530;
664 screen->chip_flags = RADEON_CHIPSET_TCL;
665 break;
666
667 case PCI_CHIP_R580_7240:
668 case PCI_CHIP_R580_7243:
669 case PCI_CHIP_R580_7244:
670 case PCI_CHIP_R580_7245:
671 case PCI_CHIP_R580_7246:
672 case PCI_CHIP_R580_7247:
673 case PCI_CHIP_R580_7248:
674 case PCI_CHIP_R580_7249:
675 case PCI_CHIP_R580_724A:
676 case PCI_CHIP_R580_724B:
677 case PCI_CHIP_R580_724C:
678 case PCI_CHIP_R580_724D:
679 case PCI_CHIP_R580_724E:
680 case PCI_CHIP_R580_724F:
681 case PCI_CHIP_R580_7284:
682 screen->chip_family = CHIP_FAMILY_R580;
683 screen->chip_flags = RADEON_CHIPSET_TCL;
684 break;
685
686 case PCI_CHIP_RV570_7280:
687 case PCI_CHIP_RV560_7281:
688 case PCI_CHIP_RV560_7283:
689 case PCI_CHIP_RV560_7287:
690 case PCI_CHIP_RV570_7288:
691 case PCI_CHIP_RV570_7289:
692 case PCI_CHIP_RV570_728B:
693 case PCI_CHIP_RV570_728C:
694 case PCI_CHIP_RV560_7290:
695 case PCI_CHIP_RV560_7291:
696 case PCI_CHIP_RV560_7293:
697 case PCI_CHIP_RV560_7297:
698 screen->chip_family = CHIP_FAMILY_RV560;
699 screen->chip_flags = RADEON_CHIPSET_TCL;
700 break;
701
702 default:
703 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
704 device_id);
705 return -1;
706 }
707
708 return 0;
709 }
710
711
712 /* Create the device specific screen private data struct.
713 */
714 static radeonScreenPtr
715 radeonCreateScreen( __DRIscreenPrivate *sPriv )
716 {
717 radeonScreenPtr screen;
718 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
719 unsigned char *RADEONMMIO = NULL;
720 int i;
721 int ret;
722 uint32_t temp;
723
724 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
725 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
726 return GL_FALSE;
727 }
728
729 /* Allocate the private area */
730 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
731 if ( !screen ) {
732 __driUtilMessage("%s: Could not allocate memory for screen structure",
733 __FUNCTION__);
734 return NULL;
735 }
736
737 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
738 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
739 #endif
740
741 /* parse information in __driConfigOptions */
742 driParseOptionInfo (&screen->optionCache,
743 __driConfigOptions, __driNConfigOptions);
744
745 /* This is first since which regions we map depends on whether or
746 * not we are using a PCI card.
747 */
748 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
749 {
750 int ret;
751
752 #ifdef RADEON_PARAM_KERNEL_MM
753 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_KERNEL_MM,
754 &screen->kernel_mm);
755
756 if (ret && ret != -EINVAL) {
757 FREE( screen );
758 fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret);
759 return NULL;
760 }
761
762 if (ret == -EINVAL)
763 screen->kernel_mm = 0;
764 #endif
765
766 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET,
767 &screen->gart_buffer_offset);
768
769 if (ret) {
770 FREE( screen );
771 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
772 return NULL;
773 }
774
775 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE,
776 &screen->gart_base);
777 if (ret) {
778 FREE( screen );
779 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
780 return NULL;
781 }
782
783 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
784 &screen->irq);
785 if (ret) {
786 FREE( screen );
787 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
788 return NULL;
789 }
790 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
791 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
792 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
793 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
794 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
795 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
796 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
797 }
798
799 if (!screen->kernel_mm) {
800 screen->mmio.handle = dri_priv->registerHandle;
801 screen->mmio.size = dri_priv->registerSize;
802 if ( drmMap( sPriv->fd,
803 screen->mmio.handle,
804 screen->mmio.size,
805 &screen->mmio.map ) ) {
806 FREE( screen );
807 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
808 return NULL;
809 }
810
811 RADEONMMIO = screen->mmio.map;
812
813 screen->status.handle = dri_priv->statusHandle;
814 screen->status.size = dri_priv->statusSize;
815 if ( drmMap( sPriv->fd,
816 screen->status.handle,
817 screen->status.size,
818 &screen->status.map ) ) {
819 drmUnmap( screen->mmio.map, screen->mmio.size );
820 FREE( screen );
821 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
822 return NULL;
823 }
824 screen->scratch = (__volatile__ uint32_t *)
825 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
826
827 screen->buffers = drmMapBufs( sPriv->fd );
828 if ( !screen->buffers ) {
829 drmUnmap( screen->status.map, screen->status.size );
830 drmUnmap( screen->mmio.map, screen->mmio.size );
831 FREE( screen );
832 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
833 return NULL;
834 }
835
836 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
837 screen->gartTextures.handle = dri_priv->gartTexHandle;
838 screen->gartTextures.size = dri_priv->gartTexMapSize;
839 if ( drmMap( sPriv->fd,
840 screen->gartTextures.handle,
841 screen->gartTextures.size,
842 (drmAddressPtr)&screen->gartTextures.map ) ) {
843 drmUnmapBufs( screen->buffers );
844 drmUnmap( screen->status.map, screen->status.size );
845 drmUnmap( screen->mmio.map, screen->mmio.size );
846 FREE( screen );
847 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
848 return NULL;
849 }
850
851 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
852 }
853 }
854
855
856 ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
857 if (ret == -1)
858 return NULL;
859
860 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
861 sPriv->ddx_version.minor < 2) {
862 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
863 return NULL;
864 }
865
866 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
867 fprintf(stderr, "R500 support requires a newer drm.\n");
868 return NULL;
869 }
870
871 if (getenv("R300_NO_TCL"))
872 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
873
874 if (screen->chip_family <= CHIP_FAMILY_RS200)
875 screen->chip_flags |= RADEON_CLASS_R100;
876 else if (screen->chip_family <= CHIP_FAMILY_RV280)
877 screen->chip_flags |= RADEON_CLASS_R200;
878 else
879 screen->chip_flags |= RADEON_CLASS_R300;
880
881 screen->cpp = dri_priv->bpp / 8;
882 screen->AGPMode = dri_priv->AGPMode;
883
884 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION,
885 &temp);
886 if (ret) {
887 if (screen->chip_family < CHIP_FAMILY_RS690 && !screen->kernel_mm)
888 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
889 else {
890 FREE( screen );
891 fprintf(stderr, "Unable to get fb location need newer drm\n");
892 return NULL;
893 }
894 } else {
895 screen->fbLocation = (temp & 0xffff) << 16;
896 }
897
898 if (screen->chip_family >= CHIP_FAMILY_RV515) {
899 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES,
900 &temp);
901 if (ret) {
902 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
903 switch (screen->chip_family) {
904 case CHIP_FAMILY_R300:
905 case CHIP_FAMILY_R350:
906 screen->num_gb_pipes = 2;
907 break;
908 case CHIP_FAMILY_R420:
909 case CHIP_FAMILY_R520:
910 case CHIP_FAMILY_R580:
911 case CHIP_FAMILY_RV560:
912 case CHIP_FAMILY_RV570:
913 screen->num_gb_pipes = 4;
914 break;
915 case CHIP_FAMILY_RV350:
916 case CHIP_FAMILY_RV515:
917 case CHIP_FAMILY_RV530:
918 case CHIP_FAMILY_RV410:
919 default:
920 screen->num_gb_pipes = 1;
921 break;
922 }
923 } else {
924 screen->num_gb_pipes = temp;
925 }
926 }
927
928 if ( sPriv->drm_version.minor >= 10 ) {
929 drm_radeon_setparam_t sp;
930
931 sp.param = RADEON_SETPARAM_FB_LOCATION;
932 sp.value = screen->fbLocation;
933
934 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
935 &sp, sizeof( sp ) );
936 }
937
938 screen->frontOffset = dri_priv->frontOffset;
939 screen->frontPitch = dri_priv->frontPitch;
940 screen->backOffset = dri_priv->backOffset;
941 screen->backPitch = dri_priv->backPitch;
942 screen->depthOffset = dri_priv->depthOffset;
943 screen->depthPitch = dri_priv->depthPitch;
944
945 /* Check if ddx has set up a surface reg to cover depth buffer */
946 screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
947 /* these chips don't use tiled z without hyperz. So always pretend
948 we have set up a surface which will cause linear reads/writes */
949 (IS_R100_CLASS(screen) &&
950 !(screen->chip_flags & RADEON_CHIPSET_TCL));
951
952 if ( dri_priv->textureSize == 0 ) {
953 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
954 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
955 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
956 dri_priv->log2GARTTexGran;
957 } else {
958 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
959 + screen->fbLocation;
960 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
961 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
962 dri_priv->log2TexGran;
963 }
964
965 if ( !screen->gartTextures.map || dri_priv->textureSize == 0
966 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
967 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
968 screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
969 screen->texSize[RADEON_GART_TEX_HEAP] = 0;
970 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
971 } else {
972 screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
973 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
974 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
975 screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
976 dri_priv->log2GARTTexGran;
977 }
978
979 i = 0;
980 screen->extensions[i++] = &driCopySubBufferExtension.base;
981 screen->extensions[i++] = &driFrameTrackingExtension.base;
982 screen->extensions[i++] = &driReadDrawableExtension;
983
984 if ( screen->irq != 0 ) {
985 screen->extensions[i++] = &driSwapControlExtension.base;
986 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
987 }
988
989 #if !RADEON_COMMON
990 screen->extensions[i++] = &radeonTexOffsetExtension.base;
991 #endif
992
993 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
994 if (IS_R200_CLASS(screen))
995 screen->extensions[i++] = &r200AllocateExtension.base;
996
997 screen->extensions[i++] = &r200texOffsetExtension.base;
998 #endif
999
1000 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1001 //screen->extensions[i++] = &r300texOffsetExtension.base;
1002 #endif
1003
1004 screen->extensions[i++] = NULL;
1005 sPriv->extensions = screen->extensions;
1006
1007 screen->driScreen = sPriv;
1008 screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
1009 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
1010 screen->sarea_priv_offset);
1011
1012 if (screen->kernel_mm)
1013 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1014 else
1015 screen->bom = radeon_bo_manager_legacy_ctor(screen);
1016 if (screen->bom == NULL) {
1017 free(screen);
1018 return NULL;
1019 }
1020
1021 return screen;
1022 }
1023
1024 static radeonScreenPtr
1025 radeonCreateScreen2(__DRIscreenPrivate *sPriv)
1026 {
1027 radeonScreenPtr screen;
1028 int i;
1029 int ret;
1030 uint32_t device_id;
1031
1032 /* Allocate the private area */
1033 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1034 if ( !screen ) {
1035 __driUtilMessage("%s: Could not allocate memory for screen structure",
1036 __FUNCTION__);
1037 fprintf(stderr, "leaving here\n");
1038 return NULL;
1039 }
1040
1041 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1042 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
1043 #endif
1044
1045 /* parse information in __driConfigOptions */
1046 driParseOptionInfo (&screen->optionCache,
1047 __driConfigOptions, __driNConfigOptions);
1048
1049 screen->kernel_mm = 1;
1050 screen->chip_flags = 0;
1051
1052 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
1053 &screen->irq);
1054
1055 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_DEVICE_ID,
1056 &device_id);
1057 if (ret) {
1058 FREE( screen );
1059 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret);
1060 return NULL;
1061 }
1062
1063 ret = radeon_set_screen_flags(screen, device_id);
1064 if (ret == -1)
1065 return NULL;
1066
1067 if (screen->chip_family <= CHIP_FAMILY_RS200)
1068 screen->chip_flags |= RADEON_CLASS_R100;
1069 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1070 screen->chip_flags |= RADEON_CLASS_R200;
1071 else
1072 screen->chip_flags |= RADEON_CLASS_R300;
1073
1074 i = 0;
1075 screen->extensions[i++] = &driCopySubBufferExtension.base;
1076 screen->extensions[i++] = &driFrameTrackingExtension.base;
1077 screen->extensions[i++] = &driReadDrawableExtension;
1078
1079 if ( screen->irq != 0 ) {
1080 screen->extensions[i++] = &driSwapControlExtension.base;
1081 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1082 }
1083
1084 #if !RADEON_COMMON
1085 screen->extensions[i++] = &radeonTexOffsetExtension.base;
1086 #endif
1087
1088 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1089 if (IS_R200_CLASS(screen))
1090 screen->extensions[i++] = &r200AllocateExtension.base;
1091
1092 screen->extensions[i++] = &r200texOffsetExtension.base;
1093 #endif
1094
1095 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1096 screen->extensions[i++] = &r300texOffsetExtension.base;
1097 screen->extensions[i++] = &r300TexBufferExtension.base;
1098 #endif
1099
1100 screen->extensions[i++] = NULL;
1101 sPriv->extensions = screen->extensions;
1102
1103 screen->driScreen = sPriv;
1104 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1105 if (screen->bom == NULL) {
1106 free(screen);
1107 return NULL;
1108 }
1109 return screen;
1110 }
1111
1112 /* Destroy the device specific screen private data struct.
1113 */
1114 static void
1115 radeonDestroyScreen( __DRIscreenPrivate *sPriv )
1116 {
1117 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1118
1119 if (!screen)
1120 return;
1121
1122 if (screen->kernel_mm) {
1123 #ifdef RADEON_BO_TRACK
1124 radeon_tracker_print(&screen->bom->tracker, stderr);
1125 #endif
1126 radeon_bo_manager_gem_dtor(screen->bom);
1127 } else {
1128 radeon_bo_manager_legacy_dtor(screen->bom);
1129
1130 if ( screen->gartTextures.map ) {
1131 drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
1132 }
1133 drmUnmapBufs( screen->buffers );
1134 drmUnmap( screen->status.map, screen->status.size );
1135 drmUnmap( screen->mmio.map, screen->mmio.size );
1136 }
1137
1138 /* free all option information */
1139 driDestroyOptionInfo (&screen->optionCache);
1140
1141 FREE( screen );
1142 sPriv->private = NULL;
1143 }
1144
1145
1146 /* Initialize the driver specific screen private data.
1147 */
1148 static GLboolean
1149 radeonInitDriver( __DRIscreenPrivate *sPriv )
1150 {
1151 if (sPriv->dri2.enabled) {
1152 sPriv->private = (void *) radeonCreateScreen2( sPriv );
1153 } else {
1154 sPriv->private = (void *) radeonCreateScreen( sPriv );
1155 }
1156 if ( !sPriv->private ) {
1157 radeonDestroyScreen( sPriv );
1158 return GL_FALSE;
1159 }
1160
1161 return GL_TRUE;
1162 }
1163
1164 static GLboolean
1165 radeon_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb,
1166 GLenum intFormat, GLuint w, GLuint h)
1167 {
1168 rb->Width = w;
1169 rb->Height = h;
1170 rb->_ActualFormat = intFormat;
1171
1172 return GL_TRUE;
1173 }
1174
1175
1176 static struct radeon_renderbuffer *
1177 radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv)
1178 {
1179 struct radeon_renderbuffer *ret;
1180
1181 ret = CALLOC_STRUCT(radeon_renderbuffer);
1182 if (!ret)
1183 return NULL;
1184
1185 _mesa_init_renderbuffer(&ret->base, 0);
1186
1187 /* XXX format junk */
1188 switch (format) {
1189 case GL_RGB5:
1190 ret->base._ActualFormat = GL_RGB5;
1191 ret->base._BaseFormat = GL_RGBA;
1192 ret->base.RedBits = 5;
1193 ret->base.GreenBits = 6;
1194 ret->base.BlueBits = 5;
1195 ret->base.DataType = GL_UNSIGNED_BYTE;
1196 break;
1197 case GL_RGBA8:
1198 ret->base._ActualFormat = GL_RGBA8;
1199 ret->base._BaseFormat = GL_RGBA;
1200 ret->base.RedBits = 8;
1201 ret->base.GreenBits = 8;
1202 ret->base.BlueBits = 8;
1203 ret->base.AlphaBits = 8;
1204 ret->base.DataType = GL_UNSIGNED_BYTE;
1205 break;
1206 case GL_STENCIL_INDEX8_EXT:
1207 ret->base._ActualFormat = GL_STENCIL_INDEX8_EXT;
1208 ret->base._BaseFormat = GL_STENCIL_INDEX;
1209 ret->base.StencilBits = 8;
1210 ret->base.DataType = GL_UNSIGNED_BYTE;
1211 break;
1212 case GL_DEPTH_COMPONENT16:
1213 ret->base._ActualFormat = GL_DEPTH_COMPONENT16;
1214 ret->base._BaseFormat = GL_DEPTH_COMPONENT;
1215 ret->base.DepthBits = 16;
1216 ret->base.DataType = GL_UNSIGNED_SHORT;
1217 break;
1218 case GL_DEPTH_COMPONENT24:
1219 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT;
1220 ret->base._BaseFormat = GL_DEPTH_COMPONENT;
1221 ret->base.DepthBits = 24;
1222 ret->base.DataType = GL_UNSIGNED_INT;
1223 break;
1224 case GL_DEPTH24_STENCIL8_EXT:
1225 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT;
1226 ret->base._BaseFormat = GL_DEPTH_STENCIL_EXT;
1227 ret->base.DepthBits = 24;
1228 ret->base.StencilBits = 8;
1229 ret->base.DataType = GL_UNSIGNED_INT_24_8_EXT;
1230 break;
1231 default:
1232 fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format);
1233 _mesa_delete_renderbuffer(&ret->base);
1234 return NULL;
1235 }
1236
1237 ret->dPriv = driDrawPriv;
1238 ret->base.InternalFormat = format;
1239
1240 ret->base.AllocStorage = radeon_alloc_window_storage;
1241
1242 radeonSetSpanFunctions(ret);
1243
1244 ret->bo = NULL;
1245 return ret;
1246 }
1247
1248 /**
1249 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1250 *
1251 * \todo This function (and its interface) will need to be updated to support
1252 * pbuffers.
1253 */
1254 static GLboolean
1255 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
1256 __DRIdrawablePrivate *driDrawPriv,
1257 const __GLcontextModes *mesaVis,
1258 GLboolean isPixmap )
1259 {
1260 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1261
1262 const GLboolean swDepth = GL_FALSE;
1263 const GLboolean swAlpha = GL_FALSE;
1264 const GLboolean swAccum = mesaVis->accumRedBits > 0;
1265 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1266 mesaVis->depthBits != 24;
1267 GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8);
1268 GLenum depthFormat = GL_NONE;
1269 struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
1270
1271 if (mesaVis->depthBits == 16)
1272 depthFormat = GL_DEPTH_COMPONENT16;
1273 else if (mesaVis->depthBits == 24)
1274 depthFormat = GL_DEPTH_COMPONENT24;
1275
1276 /* front color renderbuffer */
1277 {
1278 struct radeon_renderbuffer *front =
1279 radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1280 _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &front->base);
1281 front->has_surface = 1;
1282 }
1283
1284 /* back color renderbuffer */
1285 if (mesaVis->doubleBufferMode) {
1286 struct radeon_renderbuffer *back =
1287 radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1288 _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &back->base);
1289 back->has_surface = 1;
1290 }
1291
1292 /* depth renderbuffer */
1293 if (depthFormat != GL_NONE) {
1294 struct radeon_renderbuffer *depth =
1295 radeon_create_renderbuffer(depthFormat, driDrawPriv);
1296 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth->base);
1297 depth->has_surface = screen->depthHasSurface;
1298 }
1299
1300 /* stencil renderbuffer */
1301 if (mesaVis->stencilBits > 0 && !swStencil) {
1302 struct radeon_renderbuffer *stencil =
1303 radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv);
1304 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencil->base);
1305 stencil->has_surface = screen->depthHasSurface;
1306 }
1307
1308 _mesa_add_soft_renderbuffers(fb,
1309 GL_FALSE, /* color */
1310 swDepth,
1311 swStencil,
1312 swAccum,
1313 swAlpha,
1314 GL_FALSE /* aux */);
1315 driDrawPriv->driverPrivate = (void *) fb;
1316
1317 return (driDrawPriv->driverPrivate != NULL);
1318 }
1319
1320 static void
1321 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
1322 {
1323 struct radeon_renderbuffer *rb;
1324 GLframebuffer *fb;
1325
1326 fb = (void*)driDrawPriv->driverPrivate;
1327 rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
1328 if (rb && rb->bo) {
1329 radeon_bo_unref(rb->bo);
1330 rb->bo = NULL;
1331 }
1332 rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
1333 if (rb && rb->bo) {
1334 radeon_bo_unref(rb->bo);
1335 rb->bo = NULL;
1336 }
1337 rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer;
1338 if (rb && rb->bo) {
1339 radeon_bo_unref(rb->bo);
1340 rb->bo = NULL;
1341 }
1342 _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)));
1343 }
1344
1345 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1346 /**
1347 * Choose the appropriate CreateContext function based on the chipset.
1348 * Eventually, all drivers will go through this process.
1349 */
1350 static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
1351 __DRIcontextPrivate * driContextPriv,
1352 void *sharedContextPriv)
1353 {
1354 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
1355 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
1356
1357 if (IS_R300_CLASS(screen))
1358 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
1359 return GL_FALSE;
1360 }
1361
1362 /**
1363 * Choose the appropriate DestroyContext function based on the chipset.
1364 */
1365 static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
1366 {
1367 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
1368
1369 if (IS_R300_CLASS(radeon->radeonScreen))
1370 return r300DestroyContext(driContextPriv);
1371 }
1372
1373
1374 #endif
1375
1376
1377 /**
1378 * This is the driver specific part of the createNewScreen entry point.
1379 *
1380 * \todo maybe fold this into intelInitDriver
1381 *
1382 * \return the __GLcontextModes supported by this driver
1383 */
1384 static const __DRIconfig **
1385 radeonInitScreen(__DRIscreenPrivate *psp)
1386 {
1387 #if !RADEON_COMMON
1388 static const char *driver_name = "Radeon";
1389 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1390 static const __DRIversion dri_expected = { 4, 0, 0 };
1391 static const __DRIversion drm_expected = { 1, 6, 0 };
1392 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1393 static const char *driver_name = "R200";
1394 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1395 static const __DRIversion dri_expected = { 4, 0, 0 };
1396 static const __DRIversion drm_expected = { 1, 6, 0 };
1397 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1398 static const char *driver_name = "R300";
1399 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1400 static const __DRIversion dri_expected = { 4, 0, 0 };
1401 static const __DRIversion drm_expected = { 1, 24, 0 };
1402 #endif
1403 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1404
1405 if ( ! driCheckDriDdxDrmVersions3( driver_name,
1406 &psp->dri_version, & dri_expected,
1407 &psp->ddx_version, & ddx_expected,
1408 &psp->drm_version, & drm_expected ) ) {
1409 return NULL;
1410 }
1411
1412 /* Calling driInitExtensions here, with a NULL context pointer,
1413 * does not actually enable the extensions. It just makes sure
1414 * that all the dispatch offsets for all the extensions that
1415 * *might* be enables are known. This is needed because the
1416 * dispatch offsets need to be known when _mesa_context_create
1417 * is called, but we can't enable the extensions until we have a
1418 * context pointer.
1419 *
1420 * Hello chicken. Hello egg. How are you two today?
1421 */
1422 driInitExtensions( NULL, card_extensions, GL_FALSE );
1423 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1424 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1425 driInitSingleExtension( NULL, ARB_vp_extension );
1426 driInitSingleExtension( NULL, NV_vp_extension );
1427 driInitSingleExtension( NULL, ATI_fs_extension );
1428 driInitExtensions( NULL, point_extensions, GL_FALSE );
1429 #elif defined(RADEON_COMMON_FOR_R300)
1430 driInitSingleExtension( NULL, gl_20_extension );
1431 #endif
1432
1433 if (!radeonInitDriver(psp))
1434 return NULL;
1435
1436 /* for now fill in all modes */
1437 return radeonFillInModes( psp,
1438 dri_priv->bpp,
1439 (dri_priv->bpp == 16) ? 16 : 24,
1440 (dri_priv->bpp == 16) ? 0 : 8, 1);
1441 }
1442
1443 /**
1444 * This is the driver specific part of the createNewScreen entry point.
1445 * Called when using DRI2.
1446 *
1447 * \return the __GLcontextModes supported by this driver
1448 */
1449 static const
1450 __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp)
1451 {
1452 /* Calling driInitExtensions here, with a NULL context pointer,
1453 * does not actually enable the extensions. It just makes sure
1454 * that all the dispatch offsets for all the extensions that
1455 * *might* be enables are known. This is needed because the
1456 * dispatch offsets need to be known when _mesa_context_create
1457 * is called, but we can't enable the extensions until we have a
1458 * context pointer.
1459 *
1460 * Hello chicken. Hello egg. How are you two today?
1461 */
1462 driInitExtensions( NULL, card_extensions, GL_FALSE );
1463 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1464 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1465 driInitSingleExtension( NULL, ARB_vp_extension );
1466 driInitSingleExtension( NULL, NV_vp_extension );
1467 driInitSingleExtension( NULL, ATI_fs_extension );
1468 driInitExtensions( NULL, point_extensions, GL_FALSE );
1469 #endif
1470
1471 if (!radeonInitDriver(psp)) {
1472 return NULL;
1473 }
1474
1475 /* for now fill in all modes */
1476 return radeonFillInModes( psp, 24, 24, 8, 1);
1477 }
1478
1479 /**
1480 * Get information about previous buffer swaps.
1481 */
1482 static int
1483 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1484 {
1485 radeonContextPtr rmesa;
1486
1487 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1488 || (dPriv->driContextPriv->driverPrivate == NULL)
1489 || (sInfo == NULL) ) {
1490 return -1;
1491 }
1492
1493 rmesa = dPriv->driContextPriv->driverPrivate;
1494 sInfo->swap_count = rmesa->swap_count;
1495 sInfo->swap_ust = rmesa->swap_ust;
1496 sInfo->swap_missed_count = rmesa->swap_missed_count;
1497
1498 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1499 ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
1500 : 0.0;
1501
1502 return 0;
1503 }
1504
1505 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1506 const struct __DriverAPIRec driDriverAPI = {
1507 .InitScreen = radeonInitScreen,
1508 .DestroyScreen = radeonDestroyScreen,
1509 .CreateContext = radeonCreateContext,
1510 .DestroyContext = radeonDestroyContext,
1511 .CreateBuffer = radeonCreateBuffer,
1512 .DestroyBuffer = radeonDestroyBuffer,
1513 .SwapBuffers = radeonSwapBuffers,
1514 .MakeCurrent = radeonMakeCurrent,
1515 .UnbindContext = radeonUnbindContext,
1516 .GetSwapInfo = getSwapInfo,
1517 .GetDrawableMSC = driDrawableGetMSC32,
1518 .WaitForMSC = driWaitForMSC32,
1519 .WaitForSBC = NULL,
1520 .SwapBuffersMSC = NULL,
1521 .CopySubBuffer = radeonCopySubBuffer,
1522 /* DRI2 */
1523 .InitScreen2 = radeonInitScreen2,
1524 };
1525 #else
1526 const struct __DriverAPIRec driDriverAPI = {
1527 .InitScreen = radeonInitScreen,
1528 .DestroyScreen = radeonDestroyScreen,
1529 .CreateContext = r200CreateContext,
1530 .DestroyContext = r200DestroyContext,
1531 .CreateBuffer = radeonCreateBuffer,
1532 .DestroyBuffer = radeonDestroyBuffer,
1533 .SwapBuffers = radeonSwapBuffers,
1534 .MakeCurrent = radeonMakeCurrent,
1535 .UnbindContext = radeonUnbindContext,
1536 .GetSwapInfo = getSwapInfo,
1537 .GetDrawableMSC = driDrawableGetMSC32,
1538 .WaitForMSC = driWaitForMSC32,
1539 .WaitForSBC = NULL,
1540 .SwapBuffersMSC = NULL,
1541 .CopySubBuffer = radeonCopySubBuffer,
1542 };
1543 #endif
1544