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radeon: update to libdrm-radeon API changes
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
36 */
37
38 #include "main/glheader.h"
39 #include "main/imports.h"
40 #include "main/mtypes.h"
41 #include "main/framebuffer.h"
42 #include "main/renderbuffer.h"
43
44 #define STANDALONE_MMIO
45 #include "radeon_chipset.h"
46 #include "radeon_macros.h"
47 #include "radeon_screen.h"
48 #include "radeon_buffer.h"
49 #if !RADEON_COMMON
50 #include "radeon_context.h"
51 #include "radeon_span.h"
52 #include "radeon_tex.h"
53 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
54 #include "r200_context.h"
55 #include "r200_ioctl.h"
56 #include "r200_span.h"
57 #include "r200_tex.h"
58 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
59 #include "r300_context.h"
60 #include "r300_fragprog.h"
61 #include "r300_tex.h"
62 #include "radeon_span.h"
63 #endif
64
65 #include "utils.h"
66 #include "vblank.h"
67 #include "drirenderbuffer.h"
68
69 #include "GL/internal/dri_interface.h"
70
71 /* Radeon configuration
72 */
73 #include "xmlpool.h"
74 #include "radeon_bo_legacy.h"
75 #include "radeon_bo_gem.h"
76
77 #if !RADEON_COMMON /* R100 */
78 PUBLIC const char __driConfigOptions[] =
79 DRI_CONF_BEGIN
80 DRI_CONF_SECTION_PERFORMANCE
81 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
82 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
83 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
84 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
85 DRI_CONF_HYPERZ(false)
86 DRI_CONF_SECTION_END
87 DRI_CONF_SECTION_QUALITY
88 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
89 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
90 DRI_CONF_NO_NEG_LOD_BIAS(false)
91 DRI_CONF_FORCE_S3TC_ENABLE(false)
92 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
93 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
94 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
95 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
96 DRI_CONF_SECTION_END
97 DRI_CONF_SECTION_DEBUG
98 DRI_CONF_NO_RAST(false)
99 DRI_CONF_SECTION_END
100 DRI_CONF_END;
101 static const GLuint __driNConfigOptions = 14;
102
103 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
104
105 PUBLIC const char __driConfigOptions[] =
106 DRI_CONF_BEGIN
107 DRI_CONF_SECTION_PERFORMANCE
108 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
109 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
110 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
111 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
112 DRI_CONF_HYPERZ(false)
113 DRI_CONF_SECTION_END
114 DRI_CONF_SECTION_QUALITY
115 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
116 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
117 DRI_CONF_NO_NEG_LOD_BIAS(false)
118 DRI_CONF_FORCE_S3TC_ENABLE(false)
119 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
120 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
121 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
122 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
123 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
124 DRI_CONF_SECTION_END
125 DRI_CONF_SECTION_DEBUG
126 DRI_CONF_NO_RAST(false)
127 DRI_CONF_SECTION_END
128 DRI_CONF_SECTION_SOFTWARE
129 DRI_CONF_NV_VERTEX_PROGRAM(false)
130 DRI_CONF_SECTION_END
131 DRI_CONF_END;
132 static const GLuint __driNConfigOptions = 16;
133
134 extern const struct dri_extension blend_extensions[];
135 extern const struct dri_extension ARB_vp_extension[];
136 extern const struct dri_extension NV_vp_extension[];
137 extern const struct dri_extension ATI_fs_extension[];
138 extern const struct dri_extension point_extensions[];
139
140 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
141
142 /* TODO: integrate these into xmlpool.h! */
143 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
144 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
145 DRI_CONF_DESC(en,"Number of texture image units") \
146 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
147 DRI_CONF_OPT_END
148
149 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
150 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
151 DRI_CONF_DESC(en,"Number of texture coordinate units") \
152 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
153 DRI_CONF_OPT_END
154
155 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
156 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
157 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
158 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
159 DRI_CONF_OPT_END
160
161 #define DRI_CONF_DISABLE_S3TC(def) \
162 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
163 DRI_CONF_DESC(en,"Disable S3TC compression") \
164 DRI_CONF_OPT_END
165
166 #define DRI_CONF_DISABLE_FALLBACK(def) \
167 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
168 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
169 DRI_CONF_OPT_END
170
171 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
172 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
173 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
174 DRI_CONF_OPT_END
175
176 #define DRI_CONF_FP_OPTIMIZATION(def) \
177 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
178 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
179 DRI_CONF_ENUM(0,"Optimize for Speed") \
180 DRI_CONF_ENUM(1,"Optimize for Quality") \
181 DRI_CONF_DESC_END \
182 DRI_CONF_OPT_END
183
184 PUBLIC const char __driConfigOptions[] =
185 DRI_CONF_BEGIN
186 DRI_CONF_SECTION_PERFORMANCE
187 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
188 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
189 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
190 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
191 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
192 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
193 DRI_CONF_DISABLE_FALLBACK(true)
194 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
195 DRI_CONF_SECTION_END
196 DRI_CONF_SECTION_QUALITY
197 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
198 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
199 DRI_CONF_FORCE_S3TC_ENABLE(false)
200 DRI_CONF_DISABLE_S3TC(false)
201 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
202 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
203 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
204 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
205 DRI_CONF_SECTION_END
206 DRI_CONF_SECTION_DEBUG
207 DRI_CONF_NO_RAST(false)
208 DRI_CONF_SECTION_END
209 DRI_CONF_END;
210 static const GLuint __driNConfigOptions = 17;
211
212 #ifndef RADEON_DEBUG
213 int RADEON_DEBUG = 0;
214
215 static const struct dri_debug_control debug_control[] = {
216 {"fall", DEBUG_FALLBACKS},
217 {"tex", DEBUG_TEXTURE},
218 {"ioctl", DEBUG_IOCTL},
219 {"prim", DEBUG_PRIMS},
220 {"vert", DEBUG_VERTS},
221 {"state", DEBUG_STATE},
222 {"code", DEBUG_CODEGEN},
223 {"vfmt", DEBUG_VFMT},
224 {"vtxf", DEBUG_VFMT},
225 {"verb", DEBUG_VERBOSE},
226 {"dri", DEBUG_DRI},
227 {"dma", DEBUG_DMA},
228 {"san", DEBUG_SANITY},
229 {"sync", DEBUG_SYNC},
230 {"pix", DEBUG_PIXEL},
231 {"mem", DEBUG_MEMORY},
232 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
233 {NULL, 0}
234 };
235 #endif /* RADEON_DEBUG */
236
237 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
238
239 extern const struct dri_extension card_extensions[];
240
241 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
242
243 static int
244 radeonGetParam(int fd, int param, void *value)
245 {
246 int ret;
247 drm_radeon_getparam_t gp;
248
249 gp.param = param;
250 gp.value = value;
251
252 ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
253 return ret;
254 }
255
256 static const __DRIconfig **
257 radeonFillInModes( __DRIscreenPrivate *psp,
258 unsigned pixel_bits, unsigned depth_bits,
259 unsigned stencil_bits, GLboolean have_back_buffer )
260 {
261 __DRIconfig **configs;
262 __GLcontextModes *m;
263 unsigned depth_buffer_factor;
264 unsigned back_buffer_factor;
265 GLenum fb_format;
266 GLenum fb_type;
267 int i;
268
269 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
270 * enough to add support. Basically, if a context is created with an
271 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
272 * will never be used.
273 */
274 static const GLenum back_buffer_modes[] = {
275 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
276 };
277
278 uint8_t depth_bits_array[2];
279 uint8_t stencil_bits_array[2];
280
281
282 depth_bits_array[0] = depth_bits;
283 depth_bits_array[1] = depth_bits;
284
285 /* Just like with the accumulation buffer, always provide some modes
286 * with a stencil buffer. It will be a sw fallback, but some apps won't
287 * care about that.
288 */
289 stencil_bits_array[0] = 0;
290 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
291
292 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
293 back_buffer_factor = (have_back_buffer) ? 2 : 1;
294
295 if ( pixel_bits == 16 ) {
296 fb_format = GL_RGB;
297 fb_type = GL_UNSIGNED_SHORT_5_6_5;
298 }
299 else {
300 fb_format = GL_BGRA;
301 fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
302 }
303
304 configs = driCreateConfigs(fb_format, fb_type,
305 depth_bits_array, stencil_bits_array,
306 depth_buffer_factor,
307 back_buffer_modes, back_buffer_factor);
308 if (configs == NULL) {
309 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
310 __func__, __LINE__ );
311 return NULL;
312 }
313
314 /* Mark the visual as slow if there are "fake" stencil bits.
315 */
316 for (i = 0; configs[i]; i++) {
317 m = &configs[i]->modes;
318 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
319 m->visualRating = GLX_SLOW_CONFIG;
320 }
321 }
322
323 return (const __DRIconfig **) configs;
324 }
325
326 #if !RADEON_COMMON
327 static const __DRItexOffsetExtension radeonTexOffsetExtension = {
328 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
329 radeonSetTexOffset,
330 };
331 #endif
332
333 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
334 static const __DRIallocateExtension r200AllocateExtension = {
335 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
336 r200AllocateMemoryMESA,
337 r200FreeMemoryMESA,
338 r200GetMemoryOffsetMESA
339 };
340
341 static const __DRItexOffsetExtension r200texOffsetExtension = {
342 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
343 r200SetTexOffset,
344 };
345 #endif
346
347 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
348 static const __DRItexOffsetExtension r300texOffsetExtension = {
349 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
350 r300SetTexOffset,
351 };
352
353 void r300SetTexBuffer(__DRIcontext *pDRICtx,
354 GLint target,
355 __DRIdrawable *dPriv);
356 static const __DRItexBufferExtension r300TexBufferExtension = {
357 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
358 r300SetTexBuffer,
359 };
360 #endif
361
362 /* Create the device specific screen private data struct.
363 */
364 static radeonScreenPtr
365 radeonCreateScreen( __DRIscreenPrivate *sPriv )
366 {
367 radeonScreenPtr screen;
368 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
369 unsigned char *RADEONMMIO;
370 int i;
371 int ret;
372 uint32_t temp;
373
374 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
375 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
376 return GL_FALSE;
377 }
378
379 /* Allocate the private area */
380 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
381 if ( !screen ) {
382 __driUtilMessage("%s: Could not allocate memory for screen structure",
383 __FUNCTION__);
384 return NULL;
385 }
386
387 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
388 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
389 #endif
390
391 /* parse information in __driConfigOptions */
392 driParseOptionInfo (&screen->optionCache,
393 __driConfigOptions, __driNConfigOptions);
394
395 /* This is first since which regions we map depends on whether or
396 * not we are using a PCI card.
397 */
398 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
399 {
400 int ret;
401 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET,
402 &screen->gart_buffer_offset);
403
404 if (ret) {
405 FREE( screen );
406 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
407 return NULL;
408 }
409
410 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE,
411 &screen->gart_base);
412 if (ret) {
413 FREE( screen );
414 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
415 return NULL;
416 }
417
418 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
419 &screen->irq);
420 if (ret) {
421 FREE( screen );
422 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
423 return NULL;
424 }
425 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
426 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
427 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
428 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
429 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
430 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
431 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
432 }
433
434 screen->mmio.handle = dri_priv->registerHandle;
435 screen->mmio.size = dri_priv->registerSize;
436 if ( drmMap( sPriv->fd,
437 screen->mmio.handle,
438 screen->mmio.size,
439 &screen->mmio.map ) ) {
440 FREE( screen );
441 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
442 return NULL;
443 }
444
445 RADEONMMIO = screen->mmio.map;
446
447 screen->status.handle = dri_priv->statusHandle;
448 screen->status.size = dri_priv->statusSize;
449 if ( drmMap( sPriv->fd,
450 screen->status.handle,
451 screen->status.size,
452 &screen->status.map ) ) {
453 drmUnmap( screen->mmio.map, screen->mmio.size );
454 FREE( screen );
455 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
456 return NULL;
457 }
458 screen->scratch = (__volatile__ uint32_t *)
459 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
460
461 screen->buffers = drmMapBufs( sPriv->fd );
462 if ( !screen->buffers ) {
463 drmUnmap( screen->status.map, screen->status.size );
464 drmUnmap( screen->mmio.map, screen->mmio.size );
465 FREE( screen );
466 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
467 return NULL;
468 }
469
470 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
471 screen->gartTextures.handle = dri_priv->gartTexHandle;
472 screen->gartTextures.size = dri_priv->gartTexMapSize;
473 if ( drmMap( sPriv->fd,
474 screen->gartTextures.handle,
475 screen->gartTextures.size,
476 (drmAddressPtr)&screen->gartTextures.map ) ) {
477 drmUnmapBufs( screen->buffers );
478 drmUnmap( screen->status.map, screen->status.size );
479 drmUnmap( screen->mmio.map, screen->mmio.size );
480 FREE( screen );
481 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
482 return NULL;
483 }
484
485 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
486 }
487
488 screen->chip_flags = 0;
489 /* XXX: add more chipsets */
490 switch ( dri_priv->deviceID ) {
491 case PCI_CHIP_RADEON_LY:
492 case PCI_CHIP_RADEON_LZ:
493 case PCI_CHIP_RADEON_QY:
494 case PCI_CHIP_RADEON_QZ:
495 case PCI_CHIP_RN50_515E:
496 case PCI_CHIP_RN50_5969:
497 screen->chip_family = CHIP_FAMILY_RV100;
498 break;
499
500 case PCI_CHIP_RS100_4136:
501 case PCI_CHIP_RS100_4336:
502 screen->chip_family = CHIP_FAMILY_RS100;
503 break;
504
505 case PCI_CHIP_RS200_4137:
506 case PCI_CHIP_RS200_4337:
507 case PCI_CHIP_RS250_4237:
508 case PCI_CHIP_RS250_4437:
509 screen->chip_family = CHIP_FAMILY_RS200;
510 break;
511
512 case PCI_CHIP_RADEON_QD:
513 case PCI_CHIP_RADEON_QE:
514 case PCI_CHIP_RADEON_QF:
515 case PCI_CHIP_RADEON_QG:
516 /* all original radeons (7200) presumably have a stencil op bug */
517 screen->chip_family = CHIP_FAMILY_R100;
518 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
519 break;
520
521 case PCI_CHIP_RV200_QW:
522 case PCI_CHIP_RV200_QX:
523 case PCI_CHIP_RADEON_LW:
524 case PCI_CHIP_RADEON_LX:
525 screen->chip_family = CHIP_FAMILY_RV200;
526 screen->chip_flags = RADEON_CHIPSET_TCL;
527 break;
528
529 case PCI_CHIP_R200_BB:
530 case PCI_CHIP_R200_BC:
531 case PCI_CHIP_R200_QH:
532 case PCI_CHIP_R200_QL:
533 case PCI_CHIP_R200_QM:
534 screen->chip_family = CHIP_FAMILY_R200;
535 screen->chip_flags = RADEON_CHIPSET_TCL;
536 break;
537
538 case PCI_CHIP_RV250_If:
539 case PCI_CHIP_RV250_Ig:
540 case PCI_CHIP_RV250_Ld:
541 case PCI_CHIP_RV250_Lf:
542 case PCI_CHIP_RV250_Lg:
543 screen->chip_family = CHIP_FAMILY_RV250;
544 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
545 break;
546
547 case PCI_CHIP_RV280_5960:
548 case PCI_CHIP_RV280_5961:
549 case PCI_CHIP_RV280_5962:
550 case PCI_CHIP_RV280_5964:
551 case PCI_CHIP_RV280_5965:
552 case PCI_CHIP_RV280_5C61:
553 case PCI_CHIP_RV280_5C63:
554 screen->chip_family = CHIP_FAMILY_RV280;
555 screen->chip_flags = RADEON_CHIPSET_TCL;
556 break;
557
558 case PCI_CHIP_RS300_5834:
559 case PCI_CHIP_RS300_5835:
560 case PCI_CHIP_RS350_7834:
561 case PCI_CHIP_RS350_7835:
562 screen->chip_family = CHIP_FAMILY_RS300;
563 break;
564
565 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
566 case PCI_CHIP_R300_AD:
567 screen->chip_family = CHIP_FAMILY_RV350;
568 screen->chip_flags = RADEON_CHIPSET_TCL;
569 break;
570 case PCI_CHIP_R300_AE:
571 case PCI_CHIP_R300_AF:
572 case PCI_CHIP_R300_AG:
573 case PCI_CHIP_R300_ND:
574 case PCI_CHIP_R300_NE:
575 case PCI_CHIP_R300_NF:
576 case PCI_CHIP_R300_NG:
577 screen->chip_family = CHIP_FAMILY_R300;
578 screen->chip_flags = RADEON_CHIPSET_TCL;
579 break;
580
581 case PCI_CHIP_RV350_AP:
582 case PCI_CHIP_RV350_AQ:
583 case PCI_CHIP_RV350_AR:
584 case PCI_CHIP_RV350_AS:
585 case PCI_CHIP_RV350_AT:
586 case PCI_CHIP_RV350_AV:
587 case PCI_CHIP_RV350_AU:
588 case PCI_CHIP_RV350_NP:
589 case PCI_CHIP_RV350_NQ:
590 case PCI_CHIP_RV350_NR:
591 case PCI_CHIP_RV350_NS:
592 case PCI_CHIP_RV350_NT:
593 case PCI_CHIP_RV350_NV:
594 screen->chip_family = CHIP_FAMILY_RV350;
595 screen->chip_flags = RADEON_CHIPSET_TCL;
596 break;
597
598 case PCI_CHIP_R350_AH:
599 case PCI_CHIP_R350_AI:
600 case PCI_CHIP_R350_AJ:
601 case PCI_CHIP_R350_AK:
602 case PCI_CHIP_R350_NH:
603 case PCI_CHIP_R350_NI:
604 case PCI_CHIP_R360_NJ:
605 case PCI_CHIP_R350_NK:
606 screen->chip_family = CHIP_FAMILY_R350;
607 screen->chip_flags = RADEON_CHIPSET_TCL;
608 break;
609
610 case PCI_CHIP_RV370_5460:
611 case PCI_CHIP_RV370_5462:
612 case PCI_CHIP_RV370_5464:
613 case PCI_CHIP_RV370_5B60:
614 case PCI_CHIP_RV370_5B62:
615 case PCI_CHIP_RV370_5B63:
616 case PCI_CHIP_RV370_5B64:
617 case PCI_CHIP_RV370_5B65:
618 case PCI_CHIP_RV380_3150:
619 case PCI_CHIP_RV380_3152:
620 case PCI_CHIP_RV380_3154:
621 case PCI_CHIP_RV380_3E50:
622 case PCI_CHIP_RV380_3E54:
623 screen->chip_family = CHIP_FAMILY_RV380;
624 screen->chip_flags = RADEON_CHIPSET_TCL;
625 break;
626
627 case PCI_CHIP_R420_JN:
628 case PCI_CHIP_R420_JH:
629 case PCI_CHIP_R420_JI:
630 case PCI_CHIP_R420_JJ:
631 case PCI_CHIP_R420_JK:
632 case PCI_CHIP_R420_JL:
633 case PCI_CHIP_R420_JM:
634 case PCI_CHIP_R420_JO:
635 case PCI_CHIP_R420_JP:
636 case PCI_CHIP_R420_JT:
637 case PCI_CHIP_R481_4B49:
638 case PCI_CHIP_R481_4B4A:
639 case PCI_CHIP_R481_4B4B:
640 case PCI_CHIP_R481_4B4C:
641 case PCI_CHIP_R423_UH:
642 case PCI_CHIP_R423_UI:
643 case PCI_CHIP_R423_UJ:
644 case PCI_CHIP_R423_UK:
645 case PCI_CHIP_R430_554C:
646 case PCI_CHIP_R430_554D:
647 case PCI_CHIP_R430_554E:
648 case PCI_CHIP_R430_554F:
649 case PCI_CHIP_R423_5550:
650 case PCI_CHIP_R423_UQ:
651 case PCI_CHIP_R423_UR:
652 case PCI_CHIP_R423_UT:
653 case PCI_CHIP_R430_5D48:
654 case PCI_CHIP_R430_5D49:
655 case PCI_CHIP_R430_5D4A:
656 case PCI_CHIP_R480_5D4C:
657 case PCI_CHIP_R480_5D4D:
658 case PCI_CHIP_R480_5D4E:
659 case PCI_CHIP_R480_5D4F:
660 case PCI_CHIP_R480_5D50:
661 case PCI_CHIP_R480_5D52:
662 case PCI_CHIP_R423_5D57:
663 screen->chip_family = CHIP_FAMILY_R420;
664 screen->chip_flags = RADEON_CHIPSET_TCL;
665 break;
666
667 case PCI_CHIP_RV410_5E4C:
668 case PCI_CHIP_RV410_5E4F:
669 case PCI_CHIP_RV410_564A:
670 case PCI_CHIP_RV410_564B:
671 case PCI_CHIP_RV410_564F:
672 case PCI_CHIP_RV410_5652:
673 case PCI_CHIP_RV410_5653:
674 case PCI_CHIP_RV410_5657:
675 case PCI_CHIP_RV410_5E48:
676 case PCI_CHIP_RV410_5E4A:
677 case PCI_CHIP_RV410_5E4B:
678 case PCI_CHIP_RV410_5E4D:
679 screen->chip_family = CHIP_FAMILY_RV410;
680 screen->chip_flags = RADEON_CHIPSET_TCL;
681 break;
682
683 case PCI_CHIP_RS480_5954:
684 case PCI_CHIP_RS480_5955:
685 case PCI_CHIP_RS482_5974:
686 case PCI_CHIP_RS482_5975:
687 case PCI_CHIP_RS400_5A41:
688 case PCI_CHIP_RS400_5A42:
689 case PCI_CHIP_RC410_5A61:
690 case PCI_CHIP_RC410_5A62:
691 screen->chip_family = CHIP_FAMILY_RS400;
692 break;
693
694 case PCI_CHIP_RS690_791E:
695 case PCI_CHIP_RS690_791F:
696 screen->chip_family = CHIP_FAMILY_RS690;
697 break;
698 case PCI_CHIP_RS740_796C:
699 case PCI_CHIP_RS740_796D:
700 case PCI_CHIP_RS740_796E:
701 case PCI_CHIP_RS740_796F:
702 screen->chip_family = CHIP_FAMILY_RS740;
703 break;
704
705 case PCI_CHIP_R520_7100:
706 case PCI_CHIP_R520_7101:
707 case PCI_CHIP_R520_7102:
708 case PCI_CHIP_R520_7103:
709 case PCI_CHIP_R520_7104:
710 case PCI_CHIP_R520_7105:
711 case PCI_CHIP_R520_7106:
712 case PCI_CHIP_R520_7108:
713 case PCI_CHIP_R520_7109:
714 case PCI_CHIP_R520_710A:
715 case PCI_CHIP_R520_710B:
716 case PCI_CHIP_R520_710C:
717 case PCI_CHIP_R520_710E:
718 case PCI_CHIP_R520_710F:
719 screen->chip_family = CHIP_FAMILY_R520;
720 screen->chip_flags = RADEON_CHIPSET_TCL;
721 break;
722
723 case PCI_CHIP_RV515_7140:
724 case PCI_CHIP_RV515_7141:
725 case PCI_CHIP_RV515_7142:
726 case PCI_CHIP_RV515_7143:
727 case PCI_CHIP_RV515_7144:
728 case PCI_CHIP_RV515_7145:
729 case PCI_CHIP_RV515_7146:
730 case PCI_CHIP_RV515_7147:
731 case PCI_CHIP_RV515_7149:
732 case PCI_CHIP_RV515_714A:
733 case PCI_CHIP_RV515_714B:
734 case PCI_CHIP_RV515_714C:
735 case PCI_CHIP_RV515_714D:
736 case PCI_CHIP_RV515_714E:
737 case PCI_CHIP_RV515_714F:
738 case PCI_CHIP_RV515_7151:
739 case PCI_CHIP_RV515_7152:
740 case PCI_CHIP_RV515_7153:
741 case PCI_CHIP_RV515_715E:
742 case PCI_CHIP_RV515_715F:
743 case PCI_CHIP_RV515_7180:
744 case PCI_CHIP_RV515_7181:
745 case PCI_CHIP_RV515_7183:
746 case PCI_CHIP_RV515_7186:
747 case PCI_CHIP_RV515_7187:
748 case PCI_CHIP_RV515_7188:
749 case PCI_CHIP_RV515_718A:
750 case PCI_CHIP_RV515_718B:
751 case PCI_CHIP_RV515_718C:
752 case PCI_CHIP_RV515_718D:
753 case PCI_CHIP_RV515_718F:
754 case PCI_CHIP_RV515_7193:
755 case PCI_CHIP_RV515_7196:
756 case PCI_CHIP_RV515_719B:
757 case PCI_CHIP_RV515_719F:
758 case PCI_CHIP_RV515_7200:
759 case PCI_CHIP_RV515_7210:
760 case PCI_CHIP_RV515_7211:
761 screen->chip_family = CHIP_FAMILY_RV515;
762 screen->chip_flags = RADEON_CHIPSET_TCL;
763 break;
764
765 case PCI_CHIP_RV530_71C0:
766 case PCI_CHIP_RV530_71C1:
767 case PCI_CHIP_RV530_71C2:
768 case PCI_CHIP_RV530_71C3:
769 case PCI_CHIP_RV530_71C4:
770 case PCI_CHIP_RV530_71C5:
771 case PCI_CHIP_RV530_71C6:
772 case PCI_CHIP_RV530_71C7:
773 case PCI_CHIP_RV530_71CD:
774 case PCI_CHIP_RV530_71CE:
775 case PCI_CHIP_RV530_71D2:
776 case PCI_CHIP_RV530_71D4:
777 case PCI_CHIP_RV530_71D5:
778 case PCI_CHIP_RV530_71D6:
779 case PCI_CHIP_RV530_71DA:
780 case PCI_CHIP_RV530_71DE:
781 screen->chip_family = CHIP_FAMILY_RV530;
782 screen->chip_flags = RADEON_CHIPSET_TCL;
783 break;
784
785 case PCI_CHIP_R580_7240:
786 case PCI_CHIP_R580_7243:
787 case PCI_CHIP_R580_7244:
788 case PCI_CHIP_R580_7245:
789 case PCI_CHIP_R580_7246:
790 case PCI_CHIP_R580_7247:
791 case PCI_CHIP_R580_7248:
792 case PCI_CHIP_R580_7249:
793 case PCI_CHIP_R580_724A:
794 case PCI_CHIP_R580_724B:
795 case PCI_CHIP_R580_724C:
796 case PCI_CHIP_R580_724D:
797 case PCI_CHIP_R580_724E:
798 case PCI_CHIP_R580_724F:
799 case PCI_CHIP_R580_7284:
800 screen->chip_family = CHIP_FAMILY_R580;
801 screen->chip_flags = RADEON_CHIPSET_TCL;
802 break;
803
804 case PCI_CHIP_RV570_7280:
805 case PCI_CHIP_RV560_7281:
806 case PCI_CHIP_RV560_7283:
807 case PCI_CHIP_RV560_7287:
808 case PCI_CHIP_RV570_7288:
809 case PCI_CHIP_RV570_7289:
810 case PCI_CHIP_RV570_728B:
811 case PCI_CHIP_RV570_728C:
812 case PCI_CHIP_RV560_7290:
813 case PCI_CHIP_RV560_7291:
814 case PCI_CHIP_RV560_7293:
815 case PCI_CHIP_RV560_7297:
816 screen->chip_family = CHIP_FAMILY_RV560;
817 screen->chip_flags = RADEON_CHIPSET_TCL;
818 break;
819
820 default:
821 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
822 dri_priv->deviceID);
823 return NULL;
824 }
825 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
826 sPriv->ddx_version.minor < 2) {
827 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
828 return NULL;
829 }
830
831 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
832 fprintf(stderr, "R500 support requires a newer drm.\n");
833 return NULL;
834 }
835
836 if (getenv("R300_NO_TCL"))
837 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
838
839 if (screen->chip_family <= CHIP_FAMILY_RS200)
840 screen->chip_flags |= RADEON_CLASS_R100;
841 else if (screen->chip_family <= CHIP_FAMILY_RV280)
842 screen->chip_flags |= RADEON_CLASS_R200;
843 else
844 screen->chip_flags |= RADEON_CLASS_R300;
845
846 screen->cpp = dri_priv->bpp / 8;
847 screen->AGPMode = dri_priv->AGPMode;
848
849 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION,
850 &temp);
851 if (ret) {
852 if (screen->chip_family < CHIP_FAMILY_RS690)
853 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
854 else {
855 FREE( screen );
856 fprintf(stderr, "Unable to get fb location need newer drm\n");
857 return NULL;
858 }
859 } else {
860 screen->fbLocation = (temp & 0xffff) << 16;
861 }
862
863 if (screen->chip_family >= CHIP_FAMILY_RV515) {
864 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES,
865 &temp);
866 if (ret) {
867 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
868 switch (screen->chip_family) {
869 case CHIP_FAMILY_R300:
870 case CHIP_FAMILY_R350:
871 screen->num_gb_pipes = 2;
872 break;
873 case CHIP_FAMILY_R420:
874 case CHIP_FAMILY_R520:
875 case CHIP_FAMILY_R580:
876 case CHIP_FAMILY_RV560:
877 case CHIP_FAMILY_RV570:
878 screen->num_gb_pipes = 4;
879 break;
880 case CHIP_FAMILY_RV350:
881 case CHIP_FAMILY_RV515:
882 case CHIP_FAMILY_RV530:
883 case CHIP_FAMILY_RV410:
884 default:
885 screen->num_gb_pipes = 1;
886 break;
887 }
888 } else {
889 screen->num_gb_pipes = temp;
890 }
891 }
892
893 if ( sPriv->drm_version.minor >= 10 ) {
894 drm_radeon_setparam_t sp;
895
896 sp.param = RADEON_SETPARAM_FB_LOCATION;
897 sp.value = screen->fbLocation;
898
899 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
900 &sp, sizeof( sp ) );
901 }
902
903 screen->frontOffset = dri_priv->frontOffset;
904 screen->frontPitch = dri_priv->frontPitch;
905 screen->backOffset = dri_priv->backOffset;
906 screen->backPitch = dri_priv->backPitch;
907 screen->depthOffset = dri_priv->depthOffset;
908 screen->depthPitch = dri_priv->depthPitch;
909
910 /* Check if ddx has set up a surface reg to cover depth buffer */
911 screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
912 /* these chips don't use tiled z without hyperz. So always pretend
913 we have set up a surface which will cause linear reads/writes */
914 (IS_R100_CLASS(screen) &&
915 !(screen->chip_flags & RADEON_CHIPSET_TCL));
916
917 if ( dri_priv->textureSize == 0 ) {
918 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
919 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
920 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
921 dri_priv->log2GARTTexGran;
922 } else {
923 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
924 + screen->fbLocation;
925 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
926 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
927 dri_priv->log2TexGran;
928 }
929
930 if ( !screen->gartTextures.map || dri_priv->textureSize == 0
931 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
932 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
933 screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
934 screen->texSize[RADEON_GART_TEX_HEAP] = 0;
935 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
936 } else {
937 screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
938 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
939 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
940 screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
941 dri_priv->log2GARTTexGran;
942 }
943
944 i = 0;
945 screen->extensions[i++] = &driCopySubBufferExtension.base;
946 screen->extensions[i++] = &driFrameTrackingExtension.base;
947 screen->extensions[i++] = &driReadDrawableExtension;
948
949 if ( screen->irq != 0 ) {
950 screen->extensions[i++] = &driSwapControlExtension.base;
951 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
952 }
953
954 #if !RADEON_COMMON
955 screen->extensions[i++] = &radeonTexOffsetExtension.base;
956 #endif
957
958 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
959 if (IS_R200_CLASS(screen))
960 screen->extensions[i++] = &r200AllocateExtension.base;
961
962 screen->extensions[i++] = &r200texOffsetExtension.base;
963 #endif
964
965 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
966 screen->extensions[i++] = &r300texOffsetExtension.base;
967 #endif
968
969 screen->extensions[i++] = NULL;
970 sPriv->extensions = screen->extensions;
971
972 screen->driScreen = sPriv;
973 screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
974 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
975 screen->sarea_priv_offset);
976 screen->bom = radeon_bo_manager_legacy_ctor(screen);
977 if (screen->bom == NULL) {
978 free(screen);
979 return NULL;
980 }
981 return screen;
982 }
983
984 static radeonScreenPtr
985 radeonCreateScreen2(__DRIscreenPrivate *sPriv)
986 {
987 radeonScreenPtr screen;
988 int i;
989
990 /* Allocate the private area */
991 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
992 if ( !screen ) {
993 __driUtilMessage("%s: Could not allocate memory for screen structure",
994 __FUNCTION__);
995 fprintf(stderr, "leaving here\n");
996 return NULL;
997 }
998
999 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1000 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
1001 #endif
1002
1003 /* parse information in __driConfigOptions */
1004 driParseOptionInfo (&screen->optionCache,
1005 __driConfigOptions, __driNConfigOptions);
1006
1007 screen->chip_flags = 0;
1008 /* FIXME: do either an ioctl (bad) or a sysfs file for driver to
1009 * information about which chipset is their */
1010 screen->chip_family = CHIP_FAMILY_RV350;
1011 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CLASS_R300;
1012
1013 i = 0;
1014 screen->extensions[i++] = &driCopySubBufferExtension.base;
1015 screen->extensions[i++] = &driFrameTrackingExtension.base;
1016 screen->extensions[i++] = &driReadDrawableExtension;
1017
1018 if ( screen->irq != 0 ) {
1019 screen->extensions[i++] = &driSwapControlExtension.base;
1020 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1021 }
1022
1023 #if !RADEON_COMMON
1024 screen->extensions[i++] = &radeonTexOffsetExtension.base;
1025 #endif
1026
1027 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1028 if (IS_R200_CLASS(screen))
1029 screen->extensions[i++] = &r200AllocateExtension.base;
1030
1031 screen->extensions[i++] = &r200texOffsetExtension.base;
1032 #endif
1033
1034 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1035 screen->extensions[i++] = &r300texOffsetExtension.base;
1036 screen->extensions[i++] = &r300TexBufferExtension.base;
1037 #endif
1038
1039 screen->extensions[i++] = NULL;
1040 sPriv->extensions = screen->extensions;
1041
1042 screen->driScreen = sPriv;
1043 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1044 if (screen->bom == NULL) {
1045 free(screen);
1046 return NULL;
1047 }
1048 return screen;
1049 }
1050
1051 /* Destroy the device specific screen private data struct.
1052 */
1053 static void
1054 radeonDestroyScreen( __DRIscreenPrivate *sPriv )
1055 {
1056 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1057
1058 if (!screen)
1059 return;
1060
1061 if (sPriv->dri2.enabled) {
1062 radeon_tracker_print(&screen->bom->tracker, stderr);
1063 radeon_bo_manager_gem_dtor(screen->bom);
1064 } else {
1065 radeon_bo_manager_legacy_dtor(screen->bom);
1066
1067 if ( screen->gartTextures.map ) {
1068 drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
1069 }
1070 drmUnmapBufs( screen->buffers );
1071 drmUnmap( screen->status.map, screen->status.size );
1072 drmUnmap( screen->mmio.map, screen->mmio.size );
1073 }
1074
1075 /* free all option information */
1076 driDestroyOptionInfo (&screen->optionCache);
1077
1078 FREE( screen );
1079 sPriv->private = NULL;
1080 }
1081
1082
1083 /* Initialize the driver specific screen private data.
1084 */
1085 static GLboolean
1086 radeonInitDriver( __DRIscreenPrivate *sPriv )
1087 {
1088 if (sPriv->dri2.enabled) {
1089 sPriv->private = (void *) radeonCreateScreen2( sPriv );
1090 } else {
1091 sPriv->private = (void *) radeonCreateScreen( sPriv );
1092 }
1093 if ( !sPriv->private ) {
1094 radeonDestroyScreen( sPriv );
1095 return GL_FALSE;
1096 }
1097
1098 return GL_TRUE;
1099 }
1100
1101 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1102 static GLboolean
1103 radeon_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb,
1104 GLenum intFormat, GLuint w, GLuint h)
1105 {
1106 rb->Width = w;
1107 rb->Height = h;
1108 rb->_ActualFormat = intFormat;
1109
1110 return GL_TRUE;
1111 }
1112
1113
1114 static struct radeon_renderbuffer *
1115 radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv)
1116 {
1117 struct radeon_renderbuffer *ret;
1118
1119 ret = CALLOC_STRUCT(radeon_renderbuffer);
1120 if (!ret)
1121 return NULL;
1122
1123 _mesa_init_renderbuffer(&ret->base, 0);
1124
1125 /* XXX format junk */
1126 switch (format) {
1127 case GL_RGB5:
1128 ret->base._ActualFormat = GL_RGB5;
1129 ret->base._BaseFormat = GL_RGBA;
1130 ret->base.RedBits = 5;
1131 ret->base.GreenBits = 6;
1132 ret->base.BlueBits = 5;
1133 ret->base.DataType = GL_UNSIGNED_BYTE;
1134 break;
1135 case GL_RGBA8:
1136 ret->base._ActualFormat = GL_RGBA8;
1137 ret->base._BaseFormat = GL_RGBA;
1138 ret->base.RedBits = 8;
1139 ret->base.GreenBits = 8;
1140 ret->base.BlueBits = 8;
1141 ret->base.AlphaBits = 8;
1142 ret->base.DataType = GL_UNSIGNED_BYTE;
1143 break;
1144 case GL_STENCIL_INDEX8_EXT:
1145 ret->base._ActualFormat = GL_STENCIL_INDEX8_EXT;
1146 ret->base._BaseFormat = GL_STENCIL_INDEX;
1147 ret->base.StencilBits = 8;
1148 ret->base.DataType = GL_UNSIGNED_BYTE;
1149 break;
1150 case GL_DEPTH_COMPONENT16:
1151 ret->base._ActualFormat = GL_DEPTH_COMPONENT16;
1152 ret->base._BaseFormat = GL_DEPTH_COMPONENT;
1153 ret->base.DepthBits = 16;
1154 ret->base.DataType = GL_UNSIGNED_SHORT;
1155 break;
1156 case GL_DEPTH_COMPONENT24:
1157 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT;
1158 ret->base._BaseFormat = GL_DEPTH_COMPONENT;
1159 ret->base.DepthBits = 24;
1160 ret->base.DataType = GL_UNSIGNED_INT;
1161 break;
1162 case GL_DEPTH24_STENCIL8_EXT:
1163 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT;
1164 ret->base._BaseFormat = GL_DEPTH_STENCIL_EXT;
1165 ret->base.DepthBits = 24;
1166 ret->base.StencilBits = 8;
1167 ret->base.DataType = GL_UNSIGNED_INT_24_8_EXT;
1168 break;
1169 default:
1170 fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format);
1171 _mesa_delete_renderbuffer(&ret->base);
1172 return NULL;
1173 }
1174
1175 ret->dPriv = driDrawPriv;
1176 ret->base.InternalFormat = format;
1177
1178 ret->base.AllocStorage = radeon_alloc_window_storage;
1179
1180 radeonSetSpanFunctions(ret);
1181
1182 return ret;
1183 }
1184
1185 /**
1186 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1187 *
1188 * \todo This function (and its interface) will need to be updated to support
1189 * pbuffers.
1190 */
1191 static GLboolean
1192 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
1193 __DRIdrawablePrivate *driDrawPriv,
1194 const __GLcontextModes *mesaVis,
1195 GLboolean isPixmap )
1196 {
1197 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1198
1199 const GLboolean swDepth = GL_FALSE;
1200 const GLboolean swAlpha = GL_FALSE;
1201 const GLboolean swAccum = mesaVis->accumRedBits > 0;
1202 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1203 mesaVis->depthBits != 24;
1204 GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8);
1205 GLenum depthFormat = GL_NONE;
1206 struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
1207
1208 if (mesaVis->depthBits == 16)
1209 depthFormat = GL_DEPTH_COMPONENT16;
1210 else if (mesaVis->depthBits == 24)
1211 depthFormat = GL_DEPTH_COMPONENT24;
1212
1213 /* front color renderbuffer */
1214 {
1215 struct radeon_renderbuffer *front =
1216 radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1217 _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &front->base);
1218 front->has_surface = 1;
1219 }
1220
1221 /* back color renderbuffer */
1222 if (mesaVis->doubleBufferMode) {
1223 struct radeon_renderbuffer *back =
1224 radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1225 _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &back->base);
1226 back->has_surface = 1;
1227 }
1228
1229 /* depth renderbuffer */
1230 if (depthFormat != GL_NONE) {
1231 struct radeon_renderbuffer *depth =
1232 radeon_create_renderbuffer(depthFormat, driDrawPriv);
1233 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth->base);
1234 depth->has_surface = screen->depthHasSurface;
1235 }
1236
1237 /* stencil renderbuffer */
1238 if (mesaVis->stencilBits > 0 && !swStencil) {
1239 struct radeon_renderbuffer *stencil =
1240 radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv);
1241 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencil->base);
1242 stencil->has_surface = screen->depthHasSurface;
1243 }
1244
1245 _mesa_add_soft_renderbuffers(fb,
1246 GL_FALSE, /* color */
1247 swDepth,
1248 swStencil,
1249 swAccum,
1250 swAlpha,
1251 GL_FALSE /* aux */);
1252 driDrawPriv->driverPrivate = (void *) fb;
1253
1254 return (driDrawPriv->driverPrivate != NULL);
1255 }
1256 #else
1257
1258 /**
1259 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1260 *
1261 * \todo This function (and its interface) will need to be updated to support
1262 * pbuffers.
1263 */
1264 static GLboolean
1265 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
1266 __DRIdrawablePrivate *driDrawPriv,
1267 const __GLcontextModes *mesaVis,
1268 GLboolean isPixmap )
1269 {
1270 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1271
1272 if (isPixmap) {
1273 return GL_FALSE; /* not implemented */
1274 }
1275 else {
1276 const GLboolean swDepth = GL_FALSE;
1277 const GLboolean swAlpha = GL_FALSE;
1278 const GLboolean swAccum = mesaVis->accumRedBits > 0;
1279 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1280 mesaVis->depthBits != 24;
1281 struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
1282
1283 /* front color renderbuffer */
1284 {
1285 driRenderbuffer *frontRb
1286 = driNewRenderbuffer(GL_RGBA,
1287 driScrnPriv->pFB + screen->frontOffset,
1288 screen->cpp,
1289 screen->frontOffset, screen->frontPitch,
1290 driDrawPriv);
1291 radeonSetSpanFunctions(frontRb, mesaVis);
1292 _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
1293 }
1294
1295 /* back color renderbuffer */
1296 if (mesaVis->doubleBufferMode) {
1297 driRenderbuffer *backRb
1298 = driNewRenderbuffer(GL_RGBA,
1299 driScrnPriv->pFB + screen->backOffset,
1300 screen->cpp,
1301 screen->backOffset, screen->backPitch,
1302 driDrawPriv);
1303 radeonSetSpanFunctions(backRb, mesaVis);
1304 _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
1305 }
1306
1307 /* depth renderbuffer */
1308 if (mesaVis->depthBits == 16) {
1309 driRenderbuffer *depthRb
1310 = driNewRenderbuffer(GL_DEPTH_COMPONENT16,
1311 driScrnPriv->pFB + screen->depthOffset,
1312 screen->cpp,
1313 screen->depthOffset, screen->depthPitch,
1314 driDrawPriv);
1315 radeonSetSpanFunctions(depthRb, mesaVis);
1316 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
1317 depthRb->has_surface = screen->depthHasSurface;
1318 }
1319 else if (mesaVis->depthBits == 24) {
1320 driRenderbuffer *depthRb
1321 = driNewRenderbuffer(GL_DEPTH_COMPONENT24,
1322 driScrnPriv->pFB + screen->depthOffset,
1323 screen->cpp,
1324 screen->depthOffset, screen->depthPitch,
1325 driDrawPriv);
1326 radeonSetSpanFunctions(depthRb, mesaVis);
1327 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
1328 depthRb->has_surface = screen->depthHasSurface;
1329 }
1330
1331 /* stencil renderbuffer */
1332 if (mesaVis->stencilBits > 0 && !swStencil) {
1333 driRenderbuffer *stencilRb
1334 = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT,
1335 driScrnPriv->pFB + screen->depthOffset,
1336 screen->cpp,
1337 screen->depthOffset, screen->depthPitch,
1338 driDrawPriv);
1339 radeonSetSpanFunctions(stencilRb, mesaVis);
1340 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
1341 stencilRb->has_surface = screen->depthHasSurface;
1342 }
1343
1344 _mesa_add_soft_renderbuffers(fb,
1345 GL_FALSE, /* color */
1346 swDepth,
1347 swStencil,
1348 swAccum,
1349 swAlpha,
1350 GL_FALSE /* aux */);
1351 driDrawPriv->driverPrivate = (void *) fb;
1352
1353 return (driDrawPriv->driverPrivate != NULL);
1354 }
1355 }
1356 #endif
1357
1358 static void
1359 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
1360 {
1361 struct radeon_renderbuffer *rb;
1362 GLframebuffer *fb;
1363
1364 fb = (void*)driDrawPriv->driverPrivate;
1365 rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
1366 if (rb && rb->bo) {
1367 radeon_bo_unref(rb->bo);
1368 }
1369 rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
1370 if (rb && rb->bo) {
1371 radeon_bo_unref(rb->bo);
1372 }
1373 rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer;
1374 if (rb && rb->bo) {
1375 radeon_bo_unref(rb->bo);
1376 }
1377 _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)));
1378 }
1379
1380 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1381 /**
1382 * Choose the appropriate CreateContext function based on the chipset.
1383 * Eventually, all drivers will go through this process.
1384 */
1385 static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
1386 __DRIcontextPrivate * driContextPriv,
1387 void *sharedContextPriv)
1388 {
1389 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
1390 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
1391
1392 if (IS_R300_CLASS(screen))
1393 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
1394 return GL_FALSE;
1395 }
1396
1397 /**
1398 * Choose the appropriate DestroyContext function based on the chipset.
1399 */
1400 static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
1401 {
1402 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
1403
1404 if (IS_R300_CLASS(radeon->radeonScreen))
1405 return r300DestroyContext(driContextPriv);
1406 }
1407
1408
1409 #endif
1410
1411 /**
1412 * This is the driver specific part of the createNewScreen entry point.
1413 *
1414 * \todo maybe fold this into intelInitDriver
1415 *
1416 * \return the __GLcontextModes supported by this driver
1417 */
1418 static const __DRIconfig **
1419 radeonInitScreen(__DRIscreenPrivate *psp)
1420 {
1421 #if !RADEON_COMMON
1422 static const char *driver_name = "Radeon";
1423 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1424 static const __DRIversion dri_expected = { 4, 0, 0 };
1425 static const __DRIversion drm_expected = { 1, 6, 0 };
1426 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1427 static const char *driver_name = "R200";
1428 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1429 static const __DRIversion dri_expected = { 4, 0, 0 };
1430 static const __DRIversion drm_expected = { 1, 6, 0 };
1431 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1432 static const char *driver_name = "R300";
1433 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1434 static const __DRIversion dri_expected = { 4, 0, 0 };
1435 static const __DRIversion drm_expected = { 1, 24, 0 };
1436 #endif
1437 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1438
1439 if ( ! driCheckDriDdxDrmVersions3( driver_name,
1440 &psp->dri_version, & dri_expected,
1441 &psp->ddx_version, & ddx_expected,
1442 &psp->drm_version, & drm_expected ) ) {
1443 return NULL;
1444 }
1445
1446 /* Calling driInitExtensions here, with a NULL context pointer,
1447 * does not actually enable the extensions. It just makes sure
1448 * that all the dispatch offsets for all the extensions that
1449 * *might* be enables are known. This is needed because the
1450 * dispatch offsets need to be known when _mesa_context_create
1451 * is called, but we can't enable the extensions until we have a
1452 * context pointer.
1453 *
1454 * Hello chicken. Hello egg. How are you two today?
1455 */
1456 driInitExtensions( NULL, card_extensions, GL_FALSE );
1457 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1458 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1459 driInitSingleExtension( NULL, ARB_vp_extension );
1460 driInitSingleExtension( NULL, NV_vp_extension );
1461 driInitSingleExtension( NULL, ATI_fs_extension );
1462 driInitExtensions( NULL, point_extensions, GL_FALSE );
1463 #endif
1464
1465 if (!radeonInitDriver(psp))
1466 return NULL;
1467
1468 /* for now fill in all modes */
1469 return radeonFillInModes( psp,
1470 dri_priv->bpp,
1471 (dri_priv->bpp == 16) ? 16 : 24,
1472 (dri_priv->bpp == 16) ? 0 : 8, 1);
1473 }
1474
1475 /**
1476 * This is the driver specific part of the createNewScreen entry point.
1477 * Called when using DRI2.
1478 *
1479 * \return the __GLcontextModes supported by this driver
1480 */
1481 static const
1482 __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp)
1483 {
1484 /* Calling driInitExtensions here, with a NULL context pointer,
1485 * does not actually enable the extensions. It just makes sure
1486 * that all the dispatch offsets for all the extensions that
1487 * *might* be enables are known. This is needed because the
1488 * dispatch offsets need to be known when _mesa_context_create
1489 * is called, but we can't enable the extensions until we have a
1490 * context pointer.
1491 *
1492 * Hello chicken. Hello egg. How are you two today?
1493 */
1494 driInitExtensions( NULL, card_extensions, GL_FALSE );
1495 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1496 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1497 driInitSingleExtension( NULL, ARB_vp_extension );
1498 driInitSingleExtension( NULL, NV_vp_extension );
1499 driInitSingleExtension( NULL, ATI_fs_extension );
1500 driInitExtensions( NULL, point_extensions, GL_FALSE );
1501 #endif
1502
1503 if (!radeonInitDriver(psp)) {
1504 return NULL;
1505 }
1506
1507 /* for now fill in all modes */
1508 return radeonFillInModes( psp, 24, 24, 8, 1);
1509 }
1510
1511 /**
1512 * Get information about previous buffer swaps.
1513 */
1514 static int
1515 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1516 {
1517 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1518 radeonContextPtr rmesa;
1519 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1520 r200ContextPtr rmesa;
1521 #endif
1522
1523 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1524 || (dPriv->driContextPriv->driverPrivate == NULL)
1525 || (sInfo == NULL) ) {
1526 return -1;
1527 }
1528
1529 rmesa = dPriv->driContextPriv->driverPrivate;
1530 sInfo->swap_count = rmesa->swap_count;
1531 sInfo->swap_ust = rmesa->swap_ust;
1532 sInfo->swap_missed_count = rmesa->swap_missed_count;
1533
1534 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1535 ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
1536 : 0.0;
1537
1538 return 0;
1539 }
1540
1541 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1542 const struct __DriverAPIRec driDriverAPI = {
1543 .InitScreen = radeonInitScreen,
1544 .DestroyScreen = radeonDestroyScreen,
1545 .CreateContext = radeonCreateContext,
1546 .DestroyContext = radeonDestroyContext,
1547 .CreateBuffer = radeonCreateBuffer,
1548 .DestroyBuffer = radeonDestroyBuffer,
1549 .SwapBuffers = radeonSwapBuffers,
1550 .MakeCurrent = radeonMakeCurrent,
1551 .UnbindContext = radeonUnbindContext,
1552 .GetSwapInfo = getSwapInfo,
1553 .GetDrawableMSC = driDrawableGetMSC32,
1554 .WaitForMSC = driWaitForMSC32,
1555 .WaitForSBC = NULL,
1556 .SwapBuffersMSC = NULL,
1557 .CopySubBuffer = radeonCopySubBuffer,
1558 /* DRI2 */
1559 .InitScreen2 = radeonInitScreen2,
1560 };
1561 #else
1562 const struct __DriverAPIRec driDriverAPI = {
1563 .InitScreen = radeonInitScreen,
1564 .DestroyScreen = radeonDestroyScreen,
1565 .CreateContext = r200CreateContext,
1566 .DestroyContext = r200DestroyContext,
1567 .CreateBuffer = radeonCreateBuffer,
1568 .DestroyBuffer = radeonDestroyBuffer,
1569 .SwapBuffers = r200SwapBuffers,
1570 .MakeCurrent = r200MakeCurrent,
1571 .UnbindContext = r200UnbindContext,
1572 .GetSwapInfo = getSwapInfo,
1573 .GetDrawableMSC = driDrawableGetMSC32,
1574 .WaitForMSC = driWaitForMSC32,
1575 .WaitForSBC = NULL,
1576 .SwapBuffersMSC = NULL,
1577 .CopySubBuffer = r200CopySubBuffer,
1578 };
1579 #endif
1580