1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #include "radeon_common.h"
50 #if defined(RADEON_R100)
51 #include "radeon_context.h"
52 #include "radeon_tex.h"
53 #elif defined(RADEON_R200)
54 #include "r200_context.h"
56 #elif defined(RADEON_R300)
57 #include "r300_context.h"
59 #elif defined(RADEON_R600)
60 #include "r600_context.h"
61 #include "r700_driconf.h" /* +r6/r7 */
62 #include "r600_tex.h" /* +r6/r7 */
68 #include "radeon_bocs_wrapper.h"
70 #include "GL/internal/dri_interface.h"
72 /* Radeon configuration
76 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
77 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
78 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
79 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
82 #if defined(RADEON_R100) /* R100 */
83 PUBLIC
const char __driConfigOptions
[] =
85 DRI_CONF_SECTION_PERFORMANCE
86 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
87 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
88 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
89 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
90 DRI_CONF_HYPERZ(false)
91 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
93 DRI_CONF_SECTION_QUALITY
94 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
95 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
96 DRI_CONF_NO_NEG_LOD_BIAS(false)
97 DRI_CONF_FORCE_S3TC_ENABLE(false)
98 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
99 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
100 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
101 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
103 DRI_CONF_SECTION_DEBUG
104 DRI_CONF_NO_RAST(false)
107 static const GLuint __driNConfigOptions
= 15;
109 #elif defined(RADEON_R200)
111 PUBLIC
const char __driConfigOptions
[] =
113 DRI_CONF_SECTION_PERFORMANCE
114 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
115 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
116 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
117 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
118 DRI_CONF_HYPERZ(false)
119 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
121 DRI_CONF_SECTION_QUALITY
122 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
123 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
124 DRI_CONF_NO_NEG_LOD_BIAS(false)
125 DRI_CONF_FORCE_S3TC_ENABLE(false)
126 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
127 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
128 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
129 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
130 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
132 DRI_CONF_SECTION_DEBUG
133 DRI_CONF_NO_RAST(false)
135 DRI_CONF_SECTION_SOFTWARE
136 DRI_CONF_NV_VERTEX_PROGRAM(false)
139 static const GLuint __driNConfigOptions
= 17;
141 #elif defined(RADEON_R300) || defined(RADEON_R600)
143 #define DRI_CONF_FP_OPTIMIZATION_SPEED 0
144 #define DRI_CONF_FP_OPTIMIZATION_QUALITY 1
146 /* TODO: integrate these into xmlpool.h! */
147 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
148 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
149 DRI_CONF_DESC(en,"Number of texture image units") \
150 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
153 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
154 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
155 DRI_CONF_DESC(en,"Number of texture coordinate units") \
156 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
161 #define DRI_CONF_DISABLE_S3TC(def) \
162 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
163 DRI_CONF_DESC(en,"Disable S3TC compression") \
166 #define DRI_CONF_DISABLE_FALLBACK(def) \
167 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
168 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
171 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
172 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
173 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
176 #define DRI_CONF_FP_OPTIMIZATION(def) \
177 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
178 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
179 DRI_CONF_ENUM(0,"Optimize for Speed") \
180 DRI_CONF_ENUM(1,"Optimize for Quality") \
184 PUBLIC
const char __driConfigOptions
[] =
186 DRI_CONF_SECTION_PERFORMANCE
187 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
188 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
189 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
190 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
191 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
192 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
193 DRI_CONF_DISABLE_FALLBACK(true)
194 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
196 DRI_CONF_SECTION_QUALITY
197 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
198 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
199 DRI_CONF_FORCE_S3TC_ENABLE(false)
200 DRI_CONF_DISABLE_S3TC(false)
201 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
202 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
203 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
204 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED
)
206 DRI_CONF_SECTION_DEBUG
207 DRI_CONF_NO_RAST(false)
210 static const GLuint __driNConfigOptions
= 17;
214 static int getSwapInfo( __DRIdrawable
*dPriv
, __DRIswapInfo
* sInfo
);
217 radeonGetParam(__DRIscreen
*sPriv
, int param
, void *value
)
220 drm_radeon_getparam_t gp
= { 0 };
221 struct drm_radeon_info info
= { 0 };
223 if (sPriv
->drm_version
.major
>= 2) {
224 info
.value
= (uint64_t)(uintptr_t)value
;
226 case RADEON_PARAM_DEVICE_ID
:
227 info
.request
= RADEON_INFO_DEVICE_ID
;
229 case RADEON_PARAM_NUM_GB_PIPES
:
230 info
.request
= RADEON_INFO_NUM_GB_PIPES
;
232 case RADEON_PARAM_NUM_Z_PIPES
:
233 info
.request
= RADEON_INFO_NUM_Z_PIPES
;
238 ret
= drmCommandWriteRead(sPriv
->fd
, DRM_RADEON_INFO
, &info
, sizeof(info
));
243 ret
= drmCommandWriteRead(sPriv
->fd
, DRM_RADEON_GETPARAM
, &gp
, sizeof(gp
));
248 static const __DRIconfig
**
249 radeonFillInModes( __DRIscreen
*psp
,
250 unsigned pixel_bits
, unsigned depth_bits
,
251 unsigned stencil_bits
, GLboolean have_back_buffer
)
253 __DRIconfig
**configs
;
255 unsigned depth_buffer_factor
;
256 unsigned back_buffer_factor
;
259 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
260 * enough to add support. Basically, if a context is created with an
261 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
262 * will never be used.
264 static const GLenum back_buffer_modes
[] = {
265 GLX_NONE
, GLX_SWAP_UNDEFINED_OML
/*, GLX_SWAP_COPY_OML */
268 uint8_t depth_bits_array
[2];
269 uint8_t stencil_bits_array
[2];
270 uint8_t msaa_samples_array
[1];
272 depth_bits_array
[0] = depth_bits
;
273 depth_bits_array
[1] = depth_bits
;
275 /* Just like with the accumulation buffer, always provide some modes
276 * with a stencil buffer. It will be a sw fallback, but some apps won't
279 stencil_bits_array
[0] = stencil_bits
;
280 stencil_bits_array
[1] = (stencil_bits
== 0) ? 8 : stencil_bits
;
282 msaa_samples_array
[0] = 0;
284 depth_buffer_factor
= (stencil_bits
== 0) ? 2 : 1;
285 back_buffer_factor
= (have_back_buffer
) ? 2 : 1;
287 if (pixel_bits
== 16) {
288 __DRIconfig
**configs_a8r8g8b8
;
289 __DRIconfig
**configs_r5g6b5
;
291 configs_r5g6b5
= driCreateConfigs(GL_RGB
, GL_UNSIGNED_SHORT_5_6_5
,
292 depth_bits_array
, stencil_bits_array
,
293 depth_buffer_factor
, back_buffer_modes
,
294 back_buffer_factor
, msaa_samples_array
,
296 configs_a8r8g8b8
= driCreateConfigs(GL_BGRA
, GL_UNSIGNED_INT_8_8_8_8_REV
,
297 depth_bits_array
, stencil_bits_array
,
298 1, back_buffer_modes
, 1,
299 msaa_samples_array
, 1, GL_TRUE
);
300 configs
= driConcatConfigs(configs_r5g6b5
, configs_a8r8g8b8
);
302 configs
= driCreateConfigs(GL_BGRA
, GL_UNSIGNED_INT_8_8_8_8_REV
,
303 depth_bits_array
, stencil_bits_array
,
305 back_buffer_modes
, back_buffer_factor
,
306 msaa_samples_array
, 1, GL_TRUE
);
308 if (configs
== NULL
) {
309 fprintf( stderr
, "[%s:%u] Error creating FBConfig!\n",
310 __func__
, __LINE__
);
314 /* Mark the visual as slow if there are "fake" stencil bits.
316 for (i
= 0; configs
[i
]; i
++) {
317 m
= &configs
[i
]->modes
;
318 if ((m
->stencilBits
!= 0) && (m
->stencilBits
!= stencil_bits
)) {
319 m
->visualRating
= GLX_SLOW_CONFIG
;
323 return (const __DRIconfig
**) configs
;
326 #if defined(RADEON_R100)
327 static const __DRItexOffsetExtension radeonTexOffsetExtension
= {
328 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
332 static const __DRItexBufferExtension radeonTexBufferExtension
= {
333 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
339 #if defined(RADEON_R200)
341 static const __DRItexOffsetExtension r200texOffsetExtension
= {
342 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
346 static const __DRItexBufferExtension r200TexBufferExtension
= {
347 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
353 #if defined(RADEON_R300)
354 static const __DRItexOffsetExtension r300texOffsetExtension
= {
355 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
359 static const __DRItexBufferExtension r300TexBufferExtension
= {
360 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
366 #if defined(RADEON_R600)
367 static const __DRItexOffsetExtension r600texOffsetExtension
= {
368 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
369 r600SetTexOffset
, /* +r6/r7 */
372 static const __DRItexBufferExtension r600TexBufferExtension
= {
373 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
374 r600SetTexBuffer
, /* +r6/r7 */
375 r600SetTexBuffer2
, /* +r6/r7 */
380 radeonDRI2Flush(__DRIdrawable
*drawable
)
382 radeonContextPtr rmesa
;
384 rmesa
= (radeonContextPtr
) drawable
->driContextPriv
->driverPrivate
;
385 radeonFlush(rmesa
->glCtx
);
388 static const struct __DRI2flushExtensionRec radeonFlushExtension
= {
389 { __DRI2_FLUSH
, __DRI2_FLUSH_VERSION
},
391 dri2InvalidateDrawable
,
394 static int radeon_set_screen_flags(radeonScreenPtr screen
, int device_id
)
396 screen
->device_id
= device_id
;
397 screen
->chip_flags
= 0;
398 switch ( device_id
) {
399 case PCI_CHIP_RN50_515E
:
400 case PCI_CHIP_RN50_5969
:
403 case PCI_CHIP_RADEON_LY
:
404 case PCI_CHIP_RADEON_LZ
:
405 case PCI_CHIP_RADEON_QY
:
406 case PCI_CHIP_RADEON_QZ
:
407 screen
->chip_family
= CHIP_FAMILY_RV100
;
410 case PCI_CHIP_RS100_4136
:
411 case PCI_CHIP_RS100_4336
:
412 screen
->chip_family
= CHIP_FAMILY_RS100
;
415 case PCI_CHIP_RS200_4137
:
416 case PCI_CHIP_RS200_4337
:
417 case PCI_CHIP_RS250_4237
:
418 case PCI_CHIP_RS250_4437
:
419 screen
->chip_family
= CHIP_FAMILY_RS200
;
422 case PCI_CHIP_RADEON_QD
:
423 case PCI_CHIP_RADEON_QE
:
424 case PCI_CHIP_RADEON_QF
:
425 case PCI_CHIP_RADEON_QG
:
426 /* all original radeons (7200) presumably have a stencil op bug */
427 screen
->chip_family
= CHIP_FAMILY_R100
;
428 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_BROKEN_STENCIL
;
431 case PCI_CHIP_RV200_QW
:
432 case PCI_CHIP_RV200_QX
:
433 case PCI_CHIP_RADEON_LW
:
434 case PCI_CHIP_RADEON_LX
:
435 screen
->chip_family
= CHIP_FAMILY_RV200
;
436 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
439 case PCI_CHIP_R200_BB
:
440 case PCI_CHIP_R200_BC
:
441 case PCI_CHIP_R200_QH
:
442 case PCI_CHIP_R200_QL
:
443 case PCI_CHIP_R200_QM
:
444 screen
->chip_family
= CHIP_FAMILY_R200
;
445 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
448 case PCI_CHIP_RV250_If
:
449 case PCI_CHIP_RV250_Ig
:
450 case PCI_CHIP_RV250_Ld
:
451 case PCI_CHIP_RV250_Lf
:
452 case PCI_CHIP_RV250_Lg
:
453 screen
->chip_family
= CHIP_FAMILY_RV250
;
454 screen
->chip_flags
= R200_CHIPSET_YCBCR_BROKEN
| RADEON_CHIPSET_TCL
;
457 case PCI_CHIP_RV280_5960
:
458 case PCI_CHIP_RV280_5961
:
459 case PCI_CHIP_RV280_5962
:
460 case PCI_CHIP_RV280_5964
:
461 case PCI_CHIP_RV280_5965
:
462 case PCI_CHIP_RV280_5C61
:
463 case PCI_CHIP_RV280_5C63
:
464 screen
->chip_family
= CHIP_FAMILY_RV280
;
465 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
468 case PCI_CHIP_RS300_5834
:
469 case PCI_CHIP_RS300_5835
:
470 case PCI_CHIP_RS350_7834
:
471 case PCI_CHIP_RS350_7835
:
472 screen
->chip_family
= CHIP_FAMILY_RS300
;
475 case PCI_CHIP_R300_AD
:
476 case PCI_CHIP_R300_AE
:
477 case PCI_CHIP_R300_AF
:
478 case PCI_CHIP_R300_AG
:
479 case PCI_CHIP_R300_ND
:
480 case PCI_CHIP_R300_NE
:
481 case PCI_CHIP_R300_NF
:
482 case PCI_CHIP_R300_NG
:
483 screen
->chip_family
= CHIP_FAMILY_R300
;
484 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
487 case PCI_CHIP_RV350_AP
:
488 case PCI_CHIP_RV350_AQ
:
489 case PCI_CHIP_RV350_AR
:
490 case PCI_CHIP_RV350_AS
:
491 case PCI_CHIP_RV350_AT
:
492 case PCI_CHIP_RV350_AV
:
493 case PCI_CHIP_RV350_AU
:
494 case PCI_CHIP_RV350_NP
:
495 case PCI_CHIP_RV350_NQ
:
496 case PCI_CHIP_RV350_NR
:
497 case PCI_CHIP_RV350_NS
:
498 case PCI_CHIP_RV350_NT
:
499 case PCI_CHIP_RV350_NV
:
500 screen
->chip_family
= CHIP_FAMILY_RV350
;
501 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
504 case PCI_CHIP_R350_AH
:
505 case PCI_CHIP_R350_AI
:
506 case PCI_CHIP_R350_AJ
:
507 case PCI_CHIP_R350_AK
:
508 case PCI_CHIP_R350_NH
:
509 case PCI_CHIP_R350_NI
:
510 case PCI_CHIP_R360_NJ
:
511 case PCI_CHIP_R350_NK
:
512 screen
->chip_family
= CHIP_FAMILY_R350
;
513 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
516 case PCI_CHIP_RV370_5460
:
517 case PCI_CHIP_RV370_5462
:
518 case PCI_CHIP_RV370_5464
:
519 case PCI_CHIP_RV370_5B60
:
520 case PCI_CHIP_RV370_5B62
:
521 case PCI_CHIP_RV370_5B63
:
522 case PCI_CHIP_RV370_5B64
:
523 case PCI_CHIP_RV370_5B65
:
524 case PCI_CHIP_RV380_3150
:
525 case PCI_CHIP_RV380_3152
:
526 case PCI_CHIP_RV380_3154
:
527 case PCI_CHIP_RV380_3155
:
528 case PCI_CHIP_RV380_3E50
:
529 case PCI_CHIP_RV380_3E54
:
530 screen
->chip_family
= CHIP_FAMILY_RV380
;
531 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
534 case PCI_CHIP_R420_JN
:
535 case PCI_CHIP_R420_JH
:
536 case PCI_CHIP_R420_JI
:
537 case PCI_CHIP_R420_JJ
:
538 case PCI_CHIP_R420_JK
:
539 case PCI_CHIP_R420_JL
:
540 case PCI_CHIP_R420_JM
:
541 case PCI_CHIP_R420_JO
:
542 case PCI_CHIP_R420_JP
:
543 case PCI_CHIP_R420_JT
:
544 case PCI_CHIP_R481_4B49
:
545 case PCI_CHIP_R481_4B4A
:
546 case PCI_CHIP_R481_4B4B
:
547 case PCI_CHIP_R481_4B4C
:
548 case PCI_CHIP_R423_UH
:
549 case PCI_CHIP_R423_UI
:
550 case PCI_CHIP_R423_UJ
:
551 case PCI_CHIP_R423_UK
:
552 case PCI_CHIP_R430_554C
:
553 case PCI_CHIP_R430_554D
:
554 case PCI_CHIP_R430_554E
:
555 case PCI_CHIP_R430_554F
:
556 case PCI_CHIP_R423_5550
:
557 case PCI_CHIP_R423_UQ
:
558 case PCI_CHIP_R423_UR
:
559 case PCI_CHIP_R423_UT
:
560 case PCI_CHIP_R430_5D48
:
561 case PCI_CHIP_R430_5D49
:
562 case PCI_CHIP_R430_5D4A
:
563 case PCI_CHIP_R480_5D4C
:
564 case PCI_CHIP_R480_5D4D
:
565 case PCI_CHIP_R480_5D4E
:
566 case PCI_CHIP_R480_5D4F
:
567 case PCI_CHIP_R480_5D50
:
568 case PCI_CHIP_R480_5D52
:
569 case PCI_CHIP_R423_5D57
:
570 screen
->chip_family
= CHIP_FAMILY_R420
;
571 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
574 case PCI_CHIP_RV410_5E4C
:
575 case PCI_CHIP_RV410_5E4F
:
576 case PCI_CHIP_RV410_564A
:
577 case PCI_CHIP_RV410_564B
:
578 case PCI_CHIP_RV410_564F
:
579 case PCI_CHIP_RV410_5652
:
580 case PCI_CHIP_RV410_5653
:
581 case PCI_CHIP_RV410_5657
:
582 case PCI_CHIP_RV410_5E48
:
583 case PCI_CHIP_RV410_5E4A
:
584 case PCI_CHIP_RV410_5E4B
:
585 case PCI_CHIP_RV410_5E4D
:
586 screen
->chip_family
= CHIP_FAMILY_RV410
;
587 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
590 case PCI_CHIP_RS480_5954
:
591 case PCI_CHIP_RS480_5955
:
592 case PCI_CHIP_RS482_5974
:
593 case PCI_CHIP_RS482_5975
:
594 case PCI_CHIP_RS400_5A41
:
595 case PCI_CHIP_RS400_5A42
:
596 case PCI_CHIP_RC410_5A61
:
597 case PCI_CHIP_RC410_5A62
:
598 screen
->chip_family
= CHIP_FAMILY_RS400
;
601 case PCI_CHIP_RS600_793F
:
602 case PCI_CHIP_RS600_7941
:
603 case PCI_CHIP_RS600_7942
:
604 screen
->chip_family
= CHIP_FAMILY_RS600
;
607 case PCI_CHIP_RS690_791E
:
608 case PCI_CHIP_RS690_791F
:
609 screen
->chip_family
= CHIP_FAMILY_RS690
;
611 case PCI_CHIP_RS740_796C
:
612 case PCI_CHIP_RS740_796D
:
613 case PCI_CHIP_RS740_796E
:
614 case PCI_CHIP_RS740_796F
:
615 screen
->chip_family
= CHIP_FAMILY_RS740
;
618 case PCI_CHIP_R520_7100
:
619 case PCI_CHIP_R520_7101
:
620 case PCI_CHIP_R520_7102
:
621 case PCI_CHIP_R520_7103
:
622 case PCI_CHIP_R520_7104
:
623 case PCI_CHIP_R520_7105
:
624 case PCI_CHIP_R520_7106
:
625 case PCI_CHIP_R520_7108
:
626 case PCI_CHIP_R520_7109
:
627 case PCI_CHIP_R520_710A
:
628 case PCI_CHIP_R520_710B
:
629 case PCI_CHIP_R520_710C
:
630 case PCI_CHIP_R520_710E
:
631 case PCI_CHIP_R520_710F
:
632 screen
->chip_family
= CHIP_FAMILY_R520
;
633 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
636 case PCI_CHIP_RV515_7140
:
637 case PCI_CHIP_RV515_7141
:
638 case PCI_CHIP_RV515_7142
:
639 case PCI_CHIP_RV515_7143
:
640 case PCI_CHIP_RV515_7144
:
641 case PCI_CHIP_RV515_7145
:
642 case PCI_CHIP_RV515_7146
:
643 case PCI_CHIP_RV515_7147
:
644 case PCI_CHIP_RV515_7149
:
645 case PCI_CHIP_RV515_714A
:
646 case PCI_CHIP_RV515_714B
:
647 case PCI_CHIP_RV515_714C
:
648 case PCI_CHIP_RV515_714D
:
649 case PCI_CHIP_RV515_714E
:
650 case PCI_CHIP_RV515_714F
:
651 case PCI_CHIP_RV515_7151
:
652 case PCI_CHIP_RV515_7152
:
653 case PCI_CHIP_RV515_7153
:
654 case PCI_CHIP_RV515_715E
:
655 case PCI_CHIP_RV515_715F
:
656 case PCI_CHIP_RV515_7180
:
657 case PCI_CHIP_RV515_7181
:
658 case PCI_CHIP_RV515_7183
:
659 case PCI_CHIP_RV515_7186
:
660 case PCI_CHIP_RV515_7187
:
661 case PCI_CHIP_RV515_7188
:
662 case PCI_CHIP_RV515_718A
:
663 case PCI_CHIP_RV515_718B
:
664 case PCI_CHIP_RV515_718C
:
665 case PCI_CHIP_RV515_718D
:
666 case PCI_CHIP_RV515_718F
:
667 case PCI_CHIP_RV515_7193
:
668 case PCI_CHIP_RV515_7196
:
669 case PCI_CHIP_RV515_719B
:
670 case PCI_CHIP_RV515_719F
:
671 case PCI_CHIP_RV515_7200
:
672 case PCI_CHIP_RV515_7210
:
673 case PCI_CHIP_RV515_7211
:
674 screen
->chip_family
= CHIP_FAMILY_RV515
;
675 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
678 case PCI_CHIP_RV530_71C0
:
679 case PCI_CHIP_RV530_71C1
:
680 case PCI_CHIP_RV530_71C2
:
681 case PCI_CHIP_RV530_71C3
:
682 case PCI_CHIP_RV530_71C4
:
683 case PCI_CHIP_RV530_71C5
:
684 case PCI_CHIP_RV530_71C6
:
685 case PCI_CHIP_RV530_71C7
:
686 case PCI_CHIP_RV530_71CD
:
687 case PCI_CHIP_RV530_71CE
:
688 case PCI_CHIP_RV530_71D2
:
689 case PCI_CHIP_RV530_71D4
:
690 case PCI_CHIP_RV530_71D5
:
691 case PCI_CHIP_RV530_71D6
:
692 case PCI_CHIP_RV530_71DA
:
693 case PCI_CHIP_RV530_71DE
:
694 screen
->chip_family
= CHIP_FAMILY_RV530
;
695 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
698 case PCI_CHIP_R580_7240
:
699 case PCI_CHIP_R580_7243
:
700 case PCI_CHIP_R580_7244
:
701 case PCI_CHIP_R580_7245
:
702 case PCI_CHIP_R580_7246
:
703 case PCI_CHIP_R580_7247
:
704 case PCI_CHIP_R580_7248
:
705 case PCI_CHIP_R580_7249
:
706 case PCI_CHIP_R580_724A
:
707 case PCI_CHIP_R580_724B
:
708 case PCI_CHIP_R580_724C
:
709 case PCI_CHIP_R580_724D
:
710 case PCI_CHIP_R580_724E
:
711 case PCI_CHIP_R580_724F
:
712 case PCI_CHIP_R580_7284
:
713 screen
->chip_family
= CHIP_FAMILY_R580
;
714 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
717 case PCI_CHIP_RV570_7280
:
718 case PCI_CHIP_RV560_7281
:
719 case PCI_CHIP_RV560_7283
:
720 case PCI_CHIP_RV560_7287
:
721 case PCI_CHIP_RV570_7288
:
722 case PCI_CHIP_RV570_7289
:
723 case PCI_CHIP_RV570_728B
:
724 case PCI_CHIP_RV570_728C
:
725 case PCI_CHIP_RV560_7290
:
726 case PCI_CHIP_RV560_7291
:
727 case PCI_CHIP_RV560_7293
:
728 case PCI_CHIP_RV560_7297
:
729 screen
->chip_family
= CHIP_FAMILY_RV560
;
730 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
733 case PCI_CHIP_R600_9400
:
734 case PCI_CHIP_R600_9401
:
735 case PCI_CHIP_R600_9402
:
736 case PCI_CHIP_R600_9403
:
737 case PCI_CHIP_R600_9405
:
738 case PCI_CHIP_R600_940A
:
739 case PCI_CHIP_R600_940B
:
740 case PCI_CHIP_R600_940F
:
741 screen
->chip_family
= CHIP_FAMILY_R600
;
742 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
745 case PCI_CHIP_RV610_94C0
:
746 case PCI_CHIP_RV610_94C1
:
747 case PCI_CHIP_RV610_94C3
:
748 case PCI_CHIP_RV610_94C4
:
749 case PCI_CHIP_RV610_94C5
:
750 case PCI_CHIP_RV610_94C6
:
751 case PCI_CHIP_RV610_94C7
:
752 case PCI_CHIP_RV610_94C8
:
753 case PCI_CHIP_RV610_94C9
:
754 case PCI_CHIP_RV610_94CB
:
755 case PCI_CHIP_RV610_94CC
:
756 case PCI_CHIP_RV610_94CD
:
757 screen
->chip_family
= CHIP_FAMILY_RV610
;
758 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
761 case PCI_CHIP_RV630_9580
:
762 case PCI_CHIP_RV630_9581
:
763 case PCI_CHIP_RV630_9583
:
764 case PCI_CHIP_RV630_9586
:
765 case PCI_CHIP_RV630_9587
:
766 case PCI_CHIP_RV630_9588
:
767 case PCI_CHIP_RV630_9589
:
768 case PCI_CHIP_RV630_958A
:
769 case PCI_CHIP_RV630_958B
:
770 case PCI_CHIP_RV630_958C
:
771 case PCI_CHIP_RV630_958D
:
772 case PCI_CHIP_RV630_958E
:
773 case PCI_CHIP_RV630_958F
:
774 screen
->chip_family
= CHIP_FAMILY_RV630
;
775 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
778 case PCI_CHIP_RV670_9500
:
779 case PCI_CHIP_RV670_9501
:
780 case PCI_CHIP_RV670_9504
:
781 case PCI_CHIP_RV670_9505
:
782 case PCI_CHIP_RV670_9506
:
783 case PCI_CHIP_RV670_9507
:
784 case PCI_CHIP_RV670_9508
:
785 case PCI_CHIP_RV670_9509
:
786 case PCI_CHIP_RV670_950F
:
787 case PCI_CHIP_RV670_9511
:
788 case PCI_CHIP_RV670_9515
:
789 case PCI_CHIP_RV670_9517
:
790 case PCI_CHIP_RV670_9519
:
791 screen
->chip_family
= CHIP_FAMILY_RV670
;
792 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
795 case PCI_CHIP_RV620_95C0
:
796 case PCI_CHIP_RV620_95C2
:
797 case PCI_CHIP_RV620_95C4
:
798 case PCI_CHIP_RV620_95C5
:
799 case PCI_CHIP_RV620_95C6
:
800 case PCI_CHIP_RV620_95C7
:
801 case PCI_CHIP_RV620_95C9
:
802 case PCI_CHIP_RV620_95CC
:
803 case PCI_CHIP_RV620_95CD
:
804 case PCI_CHIP_RV620_95CE
:
805 case PCI_CHIP_RV620_95CF
:
806 screen
->chip_family
= CHIP_FAMILY_RV620
;
807 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
810 case PCI_CHIP_RV635_9590
:
811 case PCI_CHIP_RV635_9591
:
812 case PCI_CHIP_RV635_9593
:
813 case PCI_CHIP_RV635_9595
:
814 case PCI_CHIP_RV635_9596
:
815 case PCI_CHIP_RV635_9597
:
816 case PCI_CHIP_RV635_9598
:
817 case PCI_CHIP_RV635_9599
:
818 case PCI_CHIP_RV635_959B
:
819 screen
->chip_family
= CHIP_FAMILY_RV635
;
820 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
823 case PCI_CHIP_RS780_9610
:
824 case PCI_CHIP_RS780_9611
:
825 case PCI_CHIP_RS780_9612
:
826 case PCI_CHIP_RS780_9613
:
827 case PCI_CHIP_RS780_9614
:
828 case PCI_CHIP_RS780_9615
:
829 case PCI_CHIP_RS780_9616
:
830 screen
->chip_family
= CHIP_FAMILY_RS780
;
831 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
833 case PCI_CHIP_RS880_9710
:
834 case PCI_CHIP_RS880_9711
:
835 case PCI_CHIP_RS880_9712
:
836 case PCI_CHIP_RS880_9713
:
837 case PCI_CHIP_RS880_9714
:
838 case PCI_CHIP_RS880_9715
:
839 screen
->chip_family
= CHIP_FAMILY_RS880
;
840 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
843 case PCI_CHIP_RV770_9440
:
844 case PCI_CHIP_RV770_9441
:
845 case PCI_CHIP_RV770_9442
:
846 case PCI_CHIP_RV770_9443
:
847 case PCI_CHIP_RV770_9444
:
848 case PCI_CHIP_RV770_9446
:
849 case PCI_CHIP_RV770_944A
:
850 case PCI_CHIP_RV770_944B
:
851 case PCI_CHIP_RV770_944C
:
852 case PCI_CHIP_RV770_944E
:
853 case PCI_CHIP_RV770_9450
:
854 case PCI_CHIP_RV770_9452
:
855 case PCI_CHIP_RV770_9456
:
856 case PCI_CHIP_RV770_945A
:
857 case PCI_CHIP_RV770_945B
:
858 case PCI_CHIP_RV770_945E
:
859 case PCI_CHIP_RV790_9460
:
860 case PCI_CHIP_RV790_9462
:
861 case PCI_CHIP_RV770_946A
:
862 case PCI_CHIP_RV770_946B
:
863 case PCI_CHIP_RV770_947A
:
864 case PCI_CHIP_RV770_947B
:
865 screen
->chip_family
= CHIP_FAMILY_RV770
;
866 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
869 case PCI_CHIP_RV730_9480
:
870 case PCI_CHIP_RV730_9487
:
871 case PCI_CHIP_RV730_9488
:
872 case PCI_CHIP_RV730_9489
:
873 case PCI_CHIP_RV730_948A
:
874 case PCI_CHIP_RV730_948F
:
875 case PCI_CHIP_RV730_9490
:
876 case PCI_CHIP_RV730_9491
:
877 case PCI_CHIP_RV730_9495
:
878 case PCI_CHIP_RV730_9498
:
879 case PCI_CHIP_RV730_949C
:
880 case PCI_CHIP_RV730_949E
:
881 case PCI_CHIP_RV730_949F
:
882 screen
->chip_family
= CHIP_FAMILY_RV730
;
883 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
886 case PCI_CHIP_RV710_9540
:
887 case PCI_CHIP_RV710_9541
:
888 case PCI_CHIP_RV710_9542
:
889 case PCI_CHIP_RV710_954E
:
890 case PCI_CHIP_RV710_954F
:
891 case PCI_CHIP_RV710_9552
:
892 case PCI_CHIP_RV710_9553
:
893 case PCI_CHIP_RV710_9555
:
894 case PCI_CHIP_RV710_9557
:
895 case PCI_CHIP_RV710_955F
:
896 screen
->chip_family
= CHIP_FAMILY_RV710
;
897 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
900 case PCI_CHIP_RV740_94A0
:
901 case PCI_CHIP_RV740_94A1
:
902 case PCI_CHIP_RV740_94A3
:
903 case PCI_CHIP_RV740_94B1
:
904 case PCI_CHIP_RV740_94B3
:
905 case PCI_CHIP_RV740_94B4
:
906 case PCI_CHIP_RV740_94B5
:
907 case PCI_CHIP_RV740_94B9
:
908 screen
->chip_family
= CHIP_FAMILY_RV740
;
909 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
913 fprintf(stderr
, "unknown chip id 0x%x, can't guess.\n",
922 /* Create the device specific screen private data struct.
924 static radeonScreenPtr
925 radeonCreateScreen( __DRIscreen
*sPriv
)
927 radeonScreenPtr screen
;
928 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
)sPriv
->pDevPriv
;
929 unsigned char *RADEONMMIO
= NULL
;
934 if (sPriv
->devPrivSize
!= sizeof(RADEONDRIRec
)) {
935 fprintf(stderr
,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
939 /* Allocate the private area */
940 screen
= (radeonScreenPtr
) CALLOC( sizeof(*screen
) );
942 __driUtilMessage("%s: Could not allocate memory for screen structure",
949 /* parse information in __driConfigOptions */
950 driParseOptionInfo (&screen
->optionCache
,
951 __driConfigOptions
, __driNConfigOptions
);
953 /* This is first since which regions we map depends on whether or
954 * not we are using a PCI card.
956 screen
->card_type
= (dri_priv
->IsPCI
? RADEON_CARD_PCI
: RADEON_CARD_AGP
);
960 ret
= radeonGetParam(sPriv
, RADEON_PARAM_GART_BUFFER_OFFSET
,
961 &screen
->gart_buffer_offset
);
965 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret
);
969 ret
= radeonGetParam(sPriv
, RADEON_PARAM_GART_BASE
,
973 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret
);
977 ret
= radeonGetParam(sPriv
, RADEON_PARAM_IRQ_NR
,
981 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret
);
984 screen
->drmSupportsCubeMapsR200
= (sPriv
->drm_version
.minor
>= 7);
985 screen
->drmSupportsBlendColor
= (sPriv
->drm_version
.minor
>= 11);
986 screen
->drmSupportsTriPerf
= (sPriv
->drm_version
.minor
>= 16);
987 screen
->drmSupportsFragShader
= (sPriv
->drm_version
.minor
>= 18);
988 screen
->drmSupportsPointSprites
= (sPriv
->drm_version
.minor
>= 13);
989 screen
->drmSupportsCubeMapsR100
= (sPriv
->drm_version
.minor
>= 15);
990 screen
->drmSupportsVertexProgram
= (sPriv
->drm_version
.minor
>= 25);
991 screen
->drmSupportsOcclusionQueries
= (sPriv
->drm_version
.minor
>= 30);
994 ret
= radeon_set_screen_flags(screen
, dri_priv
->deviceID
);
998 screen
->mmio
.handle
= dri_priv
->registerHandle
;
999 screen
->mmio
.size
= dri_priv
->registerSize
;
1000 if ( drmMap( sPriv
->fd
,
1001 screen
->mmio
.handle
,
1003 &screen
->mmio
.map
) ) {
1005 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__
);
1009 RADEONMMIO
= screen
->mmio
.map
;
1011 screen
->status
.handle
= dri_priv
->statusHandle
;
1012 screen
->status
.size
= dri_priv
->statusSize
;
1013 if ( drmMap( sPriv
->fd
,
1014 screen
->status
.handle
,
1015 screen
->status
.size
,
1016 &screen
->status
.map
) ) {
1017 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
1019 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__
);
1022 if (screen
->chip_family
< CHIP_FAMILY_R600
)
1023 screen
->scratch
= (__volatile__
uint32_t *)
1024 ((GLubyte
*)screen
->status
.map
+ RADEON_SCRATCH_REG_OFFSET
);
1026 screen
->scratch
= (__volatile__
uint32_t *)
1027 ((GLubyte
*)screen
->status
.map
+ R600_SCRATCH_REG_OFFSET
);
1029 screen
->buffers
= drmMapBufs( sPriv
->fd
);
1030 if ( !screen
->buffers
) {
1031 drmUnmap( screen
->status
.map
, screen
->status
.size
);
1032 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
1034 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__
);
1038 if ( dri_priv
->gartTexHandle
&& dri_priv
->gartTexMapSize
) {
1039 screen
->gartTextures
.handle
= dri_priv
->gartTexHandle
;
1040 screen
->gartTextures
.size
= dri_priv
->gartTexMapSize
;
1041 if ( drmMap( sPriv
->fd
,
1042 screen
->gartTextures
.handle
,
1043 screen
->gartTextures
.size
,
1044 (drmAddressPtr
)&screen
->gartTextures
.map
) ) {
1045 drmUnmapBufs( screen
->buffers
);
1046 drmUnmap( screen
->status
.map
, screen
->status
.size
);
1047 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
1049 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__
);
1053 screen
->gart_texture_offset
= dri_priv
->gartTexOffset
+ screen
->gart_base
;
1056 if ((screen
->chip_family
== CHIP_FAMILY_R350
|| screen
->chip_family
== CHIP_FAMILY_R300
) &&
1057 sPriv
->ddx_version
.minor
< 2) {
1058 fprintf(stderr
, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
1062 if ((sPriv
->drm_version
.minor
< 29) && (screen
->chip_family
>= CHIP_FAMILY_RV515
)) {
1063 fprintf(stderr
, "R500 support requires a newer drm.\n");
1067 if (getenv("R300_NO_TCL"))
1068 screen
->chip_flags
&= ~RADEON_CHIPSET_TCL
;
1070 if (screen
->chip_family
<= CHIP_FAMILY_RS200
)
1071 screen
->chip_flags
|= RADEON_CLASS_R100
;
1072 else if (screen
->chip_family
<= CHIP_FAMILY_RV280
)
1073 screen
->chip_flags
|= RADEON_CLASS_R200
;
1074 else if (screen
->chip_family
<= CHIP_FAMILY_RV570
)
1075 screen
->chip_flags
|= RADEON_CLASS_R300
;
1077 screen
->chip_flags
|= RADEON_CLASS_R600
;
1079 screen
->cpp
= dri_priv
->bpp
/ 8;
1080 screen
->AGPMode
= dri_priv
->AGPMode
;
1082 ret
= radeonGetParam(sPriv
, RADEON_PARAM_FB_LOCATION
, &temp
);
1085 if(screen
->chip_family
>= CHIP_FAMILY_R600
)
1090 fprintf(stderr
, "Unable to get fb location need newer drm\n");
1095 screen
->fbLocation
= (temp
& 0xffff) << 24;
1102 if (screen
->chip_family
< CHIP_FAMILY_RS600
&& !screen
->kernel_mm
)
1103 screen
->fbLocation
= ( INREG( RADEON_MC_FB_LOCATION
) & 0xffff) << 16;
1107 fprintf(stderr
, "Unable to get fb location need newer drm\n");
1113 screen
->fbLocation
= (temp
& 0xffff) << 16;
1117 if (IS_R300_CLASS(screen
)) {
1118 ret
= radeonGetParam(sPriv
, RADEON_PARAM_NUM_GB_PIPES
, &temp
);
1120 fprintf(stderr
, "Unable to get num_pipes, need newer drm\n");
1121 switch (screen
->chip_family
) {
1122 case CHIP_FAMILY_R300
:
1123 case CHIP_FAMILY_R350
:
1124 screen
->num_gb_pipes
= 2;
1126 case CHIP_FAMILY_R420
:
1127 case CHIP_FAMILY_R520
:
1128 case CHIP_FAMILY_R580
:
1129 case CHIP_FAMILY_RV560
:
1130 case CHIP_FAMILY_RV570
:
1131 screen
->num_gb_pipes
= 4;
1133 case CHIP_FAMILY_RV350
:
1134 case CHIP_FAMILY_RV515
:
1135 case CHIP_FAMILY_RV530
:
1136 case CHIP_FAMILY_RV410
:
1138 screen
->num_gb_pipes
= 1;
1142 screen
->num_gb_pipes
= temp
;
1145 /* pipe overrides */
1146 switch (dri_priv
->deviceID
) {
1147 case PCI_CHIP_R300_AD
: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1148 case PCI_CHIP_R350_AH
: /* 9800 SE only have 1 quadpipe */
1149 case PCI_CHIP_RV410_5E4C
: /* RV410 SE only have 1 quadpipe */
1150 case PCI_CHIP_RV410_5E4F
: /* RV410 SE only have 1 quadpipe */
1151 screen
->num_gb_pipes
= 1;
1157 if ( sPriv
->drm_version
.minor
>= 31 ) {
1158 ret
= radeonGetParam(sPriv
, RADEON_PARAM_NUM_Z_PIPES
, &temp
);
1160 screen
->num_z_pipes
= 2;
1162 screen
->num_z_pipes
= temp
;
1164 screen
->num_z_pipes
= 2;
1167 if ( sPriv
->drm_version
.minor
>= 10 ) {
1168 drm_radeon_setparam_t sp
;
1170 sp
.param
= RADEON_SETPARAM_FB_LOCATION
;
1171 sp
.value
= screen
->fbLocation
;
1173 drmCommandWrite( sPriv
->fd
, DRM_RADEON_SETPARAM
,
1174 &sp
, sizeof( sp
) );
1177 screen
->frontOffset
= dri_priv
->frontOffset
;
1178 screen
->frontPitch
= dri_priv
->frontPitch
;
1179 screen
->backOffset
= dri_priv
->backOffset
;
1180 screen
->backPitch
= dri_priv
->backPitch
;
1181 screen
->depthOffset
= dri_priv
->depthOffset
;
1182 screen
->depthPitch
= dri_priv
->depthPitch
;
1184 /* Check if ddx has set up a surface reg to cover depth buffer */
1185 screen
->depthHasSurface
= (sPriv
->ddx_version
.major
> 4) ||
1186 /* these chips don't use tiled z without hyperz. So always pretend
1187 we have set up a surface which will cause linear reads/writes */
1188 (IS_R100_CLASS(screen
) &&
1189 !(screen
->chip_flags
& RADEON_CHIPSET_TCL
));
1191 if ( dri_priv
->textureSize
== 0 ) {
1192 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = screen
->gart_texture_offset
;
1193 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
1194 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
1195 dri_priv
->log2GARTTexGran
;
1197 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureOffset
1198 + screen
->fbLocation
;
1199 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureSize
;
1200 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
1201 dri_priv
->log2TexGran
;
1204 if ( !screen
->gartTextures
.map
|| dri_priv
->textureSize
== 0
1205 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
1206 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
- 1;
1207 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = 0;
1208 screen
->texSize
[RADEON_GART_TEX_HEAP
] = 0;
1209 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] = 0;
1211 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
;
1212 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = screen
->gart_texture_offset
;
1213 screen
->texSize
[RADEON_GART_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
1214 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] =
1215 dri_priv
->log2GARTTexGran
;
1219 screen
->extensions
[i
++] = &driCopySubBufferExtension
.base
;
1220 screen
->extensions
[i
++] = &driReadDrawableExtension
;
1222 if ( screen
->irq
!= 0 ) {
1223 screen
->extensions
[i
++] = &driSwapControlExtension
.base
;
1224 screen
->extensions
[i
++] = &driMediaStreamCounterExtension
.base
;
1227 #if defined(RADEON_R100)
1228 screen
->extensions
[i
++] = &radeonTexOffsetExtension
.base
;
1231 #if defined(RADEON_R200)
1232 screen
->extensions
[i
++] = &r200texOffsetExtension
.base
;
1235 #if defined(RADEON_R300)
1236 screen
->extensions
[i
++] = &r300texOffsetExtension
.base
;
1239 #if defined(RADEON_R600)
1240 screen
->extensions
[i
++] = &r600texOffsetExtension
.base
;
1243 screen
->extensions
[i
++] = &dri2ConfigQueryExtension
.base
;
1245 screen
->extensions
[i
++] = NULL
;
1246 sPriv
->extensions
= screen
->extensions
;
1248 screen
->driScreen
= sPriv
;
1249 screen
->sarea_priv_offset
= dri_priv
->sarea_priv_offset
;
1250 screen
->sarea
= (drm_radeon_sarea_t
*) ((GLubyte
*) sPriv
->pSAREA
+
1251 screen
->sarea_priv_offset
);
1253 screen
->bom
= radeon_bo_manager_legacy_ctor(screen
);
1254 if (screen
->bom
== NULL
) {
1262 static radeonScreenPtr
1263 radeonCreateScreen2(__DRIscreen
*sPriv
)
1265 radeonScreenPtr screen
;
1268 uint32_t device_id
= 0;
1271 /* Allocate the private area */
1272 screen
= (radeonScreenPtr
) CALLOC( sizeof(*screen
) );
1274 __driUtilMessage("%s: Could not allocate memory for screen structure",
1276 fprintf(stderr
, "leaving here\n");
1280 radeon_init_debug();
1282 /* parse information in __driConfigOptions */
1283 driParseOptionInfo (&screen
->optionCache
,
1284 __driConfigOptions
, __driNConfigOptions
);
1286 screen
->kernel_mm
= 1;
1287 screen
->chip_flags
= 0;
1289 /* if we have kms we can support all of these */
1290 screen
->drmSupportsCubeMapsR200
= 1;
1291 screen
->drmSupportsBlendColor
= 1;
1292 screen
->drmSupportsTriPerf
= 1;
1293 screen
->drmSupportsFragShader
= 1;
1294 screen
->drmSupportsPointSprites
= 1;
1295 screen
->drmSupportsCubeMapsR100
= 1;
1296 screen
->drmSupportsVertexProgram
= 1;
1297 screen
->drmSupportsOcclusionQueries
= 1;
1300 ret
= radeonGetParam(sPriv
, RADEON_PARAM_DEVICE_ID
, &device_id
);
1303 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret
);
1307 ret
= radeon_set_screen_flags(screen
, device_id
);
1311 if (getenv("R300_NO_TCL"))
1312 screen
->chip_flags
&= ~RADEON_CHIPSET_TCL
;
1314 if (screen
->chip_family
<= CHIP_FAMILY_RS200
)
1315 screen
->chip_flags
|= RADEON_CLASS_R100
;
1316 else if (screen
->chip_family
<= CHIP_FAMILY_RV280
)
1317 screen
->chip_flags
|= RADEON_CLASS_R200
;
1318 else if (screen
->chip_family
<= CHIP_FAMILY_RV570
)
1319 screen
->chip_flags
|= RADEON_CLASS_R300
;
1321 screen
->chip_flags
|= RADEON_CLASS_R600
;
1323 if (IS_R300_CLASS(screen
)) {
1324 ret
= radeonGetParam(sPriv
, RADEON_PARAM_NUM_GB_PIPES
, &temp
);
1326 fprintf(stderr
, "Unable to get num_pipes, need newer drm\n");
1327 switch (screen
->chip_family
) {
1328 case CHIP_FAMILY_R300
:
1329 case CHIP_FAMILY_R350
:
1330 screen
->num_gb_pipes
= 2;
1332 case CHIP_FAMILY_R420
:
1333 case CHIP_FAMILY_R520
:
1334 case CHIP_FAMILY_R580
:
1335 case CHIP_FAMILY_RV560
:
1336 case CHIP_FAMILY_RV570
:
1337 screen
->num_gb_pipes
= 4;
1339 case CHIP_FAMILY_RV350
:
1340 case CHIP_FAMILY_RV515
:
1341 case CHIP_FAMILY_RV530
:
1342 case CHIP_FAMILY_RV410
:
1344 screen
->num_gb_pipes
= 1;
1348 screen
->num_gb_pipes
= temp
;
1351 /* pipe overrides */
1352 switch (device_id
) {
1353 case PCI_CHIP_R300_AD
: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1354 case PCI_CHIP_R350_AH
: /* 9800 SE only have 1 quadpipe */
1355 case PCI_CHIP_RV410_5E4C
: /* RV410 SE only have 1 quadpipe */
1356 case PCI_CHIP_RV410_5E4F
: /* RV410 SE only have 1 quadpipe */
1357 screen
->num_gb_pipes
= 1;
1363 ret
= radeonGetParam(sPriv
, RADEON_PARAM_NUM_Z_PIPES
, &temp
);
1365 screen
->num_z_pipes
= 2;
1367 screen
->num_z_pipes
= temp
;
1372 screen
->extensions
[i
++] = &driCopySubBufferExtension
.base
;
1373 screen
->extensions
[i
++] = &driReadDrawableExtension
;
1374 screen
->extensions
[i
++] = &dri2ConfigQueryExtension
.base
;
1376 if ( screen
->irq
!= 0 ) {
1377 screen
->extensions
[i
++] = &driSwapControlExtension
.base
;
1378 screen
->extensions
[i
++] = &driMediaStreamCounterExtension
.base
;
1381 #if defined(RADEON_R100)
1382 screen
->extensions
[i
++] = &radeonTexBufferExtension
.base
;
1385 #if defined(RADEON_R200)
1386 screen
->extensions
[i
++] = &r200TexBufferExtension
.base
;
1389 #if defined(RADEON_R300)
1390 screen
->extensions
[i
++] = &r300TexBufferExtension
.base
;
1393 #if defined(RADEON_R600)
1394 screen
->extensions
[i
++] = &r600TexBufferExtension
.base
;
1397 screen
->extensions
[i
++] = &radeonFlushExtension
.base
;
1399 screen
->extensions
[i
++] = NULL
;
1400 sPriv
->extensions
= screen
->extensions
;
1402 screen
->driScreen
= sPriv
;
1403 screen
->bom
= radeon_bo_manager_gem_ctor(sPriv
->fd
);
1404 if (screen
->bom
== NULL
) {
1411 /* Destroy the device specific screen private data struct.
1414 radeonDestroyScreen( __DRIscreen
*sPriv
)
1416 radeonScreenPtr screen
= (radeonScreenPtr
)sPriv
->private;
1421 if (screen
->kernel_mm
) {
1422 #ifdef RADEON_BO_TRACK
1423 radeon_tracker_print(&screen
->bom
->tracker
, stderr
);
1425 radeon_bo_manager_gem_dtor(screen
->bom
);
1427 radeon_bo_manager_legacy_dtor(screen
->bom
);
1429 if ( screen
->gartTextures
.map
) {
1430 drmUnmap( screen
->gartTextures
.map
, screen
->gartTextures
.size
);
1432 drmUnmapBufs( screen
->buffers
);
1433 drmUnmap( screen
->status
.map
, screen
->status
.size
);
1434 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
1437 /* free all option information */
1438 driDestroyOptionInfo (&screen
->optionCache
);
1441 sPriv
->private = NULL
;
1445 /* Initialize the driver specific screen private data.
1448 radeonInitDriver( __DRIscreen
*sPriv
)
1450 if (sPriv
->dri2
.enabled
) {
1451 sPriv
->private = (void *) radeonCreateScreen2( sPriv
);
1453 sPriv
->private = (void *) radeonCreateScreen( sPriv
);
1455 if ( !sPriv
->private ) {
1456 radeonDestroyScreen( sPriv
);
1466 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1468 * \todo This function (and its interface) will need to be updated to support
1472 radeonCreateBuffer( __DRIscreen
*driScrnPriv
,
1473 __DRIdrawable
*driDrawPriv
,
1474 const __GLcontextModes
*mesaVis
,
1475 GLboolean isPixmap
)
1477 radeonScreenPtr screen
= (radeonScreenPtr
) driScrnPriv
->private;
1479 const GLboolean swDepth
= GL_FALSE
;
1480 const GLboolean swAlpha
= GL_FALSE
;
1481 const GLboolean swAccum
= mesaVis
->accumRedBits
> 0;
1482 const GLboolean swStencil
= mesaVis
->stencilBits
> 0 &&
1483 mesaVis
->depthBits
!= 24;
1484 gl_format rgbFormat
;
1485 struct radeon_framebuffer
*rfb
;
1488 return GL_FALSE
; /* not implemented */
1490 rfb
= CALLOC_STRUCT(radeon_framebuffer
);
1494 _mesa_initialize_window_framebuffer(&rfb
->base
, mesaVis
);
1496 if (mesaVis
->redBits
== 5)
1497 rgbFormat
= _mesa_little_endian() ? MESA_FORMAT_RGB565
: MESA_FORMAT_RGB565_REV
;
1498 else if (mesaVis
->alphaBits
== 0)
1499 rgbFormat
= _mesa_little_endian() ? MESA_FORMAT_XRGB8888
: MESA_FORMAT_XRGB8888_REV
;
1501 rgbFormat
= _mesa_little_endian() ? MESA_FORMAT_ARGB8888
: MESA_FORMAT_ARGB8888_REV
;
1503 /* front color renderbuffer */
1504 rfb
->color_rb
[0] = radeon_create_renderbuffer(rgbFormat
, driDrawPriv
);
1505 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_FRONT_LEFT
, &rfb
->color_rb
[0]->base
);
1506 rfb
->color_rb
[0]->has_surface
= 1;
1508 /* back color renderbuffer */
1509 if (mesaVis
->doubleBufferMode
) {
1510 rfb
->color_rb
[1] = radeon_create_renderbuffer(rgbFormat
, driDrawPriv
);
1511 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_BACK_LEFT
, &rfb
->color_rb
[1]->base
);
1512 rfb
->color_rb
[1]->has_surface
= 1;
1515 if (mesaVis
->depthBits
== 24) {
1516 if (mesaVis
->stencilBits
== 8) {
1517 struct radeon_renderbuffer
*depthStencilRb
=
1518 radeon_create_renderbuffer(MESA_FORMAT_S8_Z24
, driDrawPriv
);
1519 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_DEPTH
, &depthStencilRb
->base
);
1520 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_STENCIL
, &depthStencilRb
->base
);
1521 depthStencilRb
->has_surface
= screen
->depthHasSurface
;
1523 /* depth renderbuffer */
1524 struct radeon_renderbuffer
*depth
=
1525 radeon_create_renderbuffer(MESA_FORMAT_X8_Z24
, driDrawPriv
);
1526 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_DEPTH
, &depth
->base
);
1527 depth
->has_surface
= screen
->depthHasSurface
;
1529 } else if (mesaVis
->depthBits
== 16) {
1530 /* just 16-bit depth buffer, no hw stencil */
1531 struct radeon_renderbuffer
*depth
=
1532 radeon_create_renderbuffer(MESA_FORMAT_Z16
, driDrawPriv
);
1533 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_DEPTH
, &depth
->base
);
1534 depth
->has_surface
= screen
->depthHasSurface
;
1537 _mesa_add_soft_renderbuffers(&rfb
->base
,
1538 GL_FALSE
, /* color */
1543 GL_FALSE
/* aux */);
1544 driDrawPriv
->driverPrivate
= (void *) rfb
;
1546 return (driDrawPriv
->driverPrivate
!= NULL
);
1550 static void radeon_cleanup_renderbuffers(struct radeon_framebuffer
*rfb
)
1552 struct radeon_renderbuffer
*rb
;
1554 rb
= rfb
->color_rb
[0];
1556 radeon_bo_unref(rb
->bo
);
1559 rb
= rfb
->color_rb
[1];
1561 radeon_bo_unref(rb
->bo
);
1564 rb
= radeon_get_renderbuffer(&rfb
->base
, BUFFER_DEPTH
);
1566 radeon_bo_unref(rb
->bo
);
1572 radeonDestroyBuffer(__DRIdrawable
*driDrawPriv
)
1574 struct radeon_framebuffer
*rfb
;
1578 rfb
= (void*)driDrawPriv
->driverPrivate
;
1581 radeon_cleanup_renderbuffers(rfb
);
1582 _mesa_reference_framebuffer((GLframebuffer
**)(&(driDrawPriv
->driverPrivate
)), NULL
);
1587 * This is the driver specific part of the createNewScreen entry point.
1589 * \todo maybe fold this into intelInitDriver
1591 * \return the __GLcontextModes supported by this driver
1593 static const __DRIconfig
**
1594 radeonInitScreen(__DRIscreen
*psp
)
1596 #if defined(RADEON_R100)
1597 static const char *driver_name
= "Radeon";
1598 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1599 static const __DRIversion dri_expected
= { 4, 0, 0 };
1600 static const __DRIversion drm_expected
= { 1, 6, 0 };
1601 #elif defined(RADEON_R200)
1602 static const char *driver_name
= "R200";
1603 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1604 static const __DRIversion dri_expected
= { 4, 0, 0 };
1605 static const __DRIversion drm_expected
= { 1, 6, 0 };
1606 #elif defined(RADEON_R300)
1607 static const char *driver_name
= "R300";
1608 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1609 static const __DRIversion dri_expected
= { 4, 0, 0 };
1610 static const __DRIversion drm_expected
= { 1, 24, 0 };
1611 #elif defined(RADEON_R600)
1612 static const char *driver_name
= "R600";
1613 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1614 static const __DRIversion dri_expected
= { 4, 0, 0 };
1615 static const __DRIversion drm_expected
= { 1, 24, 0 };
1617 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
) psp
->pDevPriv
;
1619 if ( ! driCheckDriDdxDrmVersions3( driver_name
,
1620 &psp
->dri_version
, & dri_expected
,
1621 &psp
->ddx_version
, & ddx_expected
,
1622 &psp
->drm_version
, & drm_expected
) ) {
1626 if (!radeonInitDriver(psp
))
1629 /* for now fill in all modes */
1630 return radeonFillInModes( psp
,
1632 (dri_priv
->bpp
== 16) ? 16 : 24,
1633 (dri_priv
->bpp
== 16) ? 0 : 8, 1);
1635 #define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
1638 * This is the driver specific part of the createNewScreen entry point.
1639 * Called when using DRI2.
1641 * \return the __GLcontextModes supported by this driver
1644 __DRIconfig
**radeonInitScreen2(__DRIscreen
*psp
)
1646 GLenum fb_format
[3];
1648 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
1649 * support pageflipping at all.
1651 static const GLenum back_buffer_modes
[] = {
1652 GLX_NONE
, GLX_SWAP_UNDEFINED_OML
, /*, GLX_SWAP_COPY_OML*/
1654 uint8_t depth_bits
[4], stencil_bits
[4], msaa_samples_array
[1];
1656 __DRIconfig
**configs
= NULL
;
1658 if (!radeonInitDriver(psp
)) {
1662 stencil_bits
[0] = 0;
1664 stencil_bits
[1] = 0;
1666 stencil_bits
[2] = 0;
1668 stencil_bits
[3] = 8;
1670 msaa_samples_array
[0] = 0;
1672 fb_format
[0] = GL_RGB
;
1673 fb_type
[0] = GL_UNSIGNED_SHORT_5_6_5
;
1675 fb_format
[1] = GL_BGR
;
1676 fb_type
[1] = GL_UNSIGNED_INT_8_8_8_8_REV
;
1678 fb_format
[2] = GL_BGRA
;
1679 fb_type
[2] = GL_UNSIGNED_INT_8_8_8_8_REV
;
1681 for (color
= 0; color
< ARRAY_SIZE(fb_format
); color
++) {
1682 __DRIconfig
**new_configs
;
1684 new_configs
= driCreateConfigs(fb_format
[color
], fb_type
[color
],
1687 ARRAY_SIZE(depth_bits
),
1689 ARRAY_SIZE(back_buffer_modes
),
1691 ARRAY_SIZE(msaa_samples_array
),
1693 if (configs
== NULL
)
1694 configs
= new_configs
;
1696 configs
= driConcatConfigs(configs
, new_configs
);
1699 if (configs
== NULL
) {
1700 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1705 return (const __DRIconfig
**)configs
;
1709 * Get information about previous buffer swaps.
1712 getSwapInfo( __DRIdrawable
*dPriv
, __DRIswapInfo
* sInfo
)
1714 struct radeon_framebuffer
*rfb
;
1716 if ( (dPriv
== NULL
) || (dPriv
->driContextPriv
== NULL
)
1717 || (dPriv
->driContextPriv
->driverPrivate
== NULL
)
1718 || (sInfo
== NULL
) ) {
1722 rfb
= dPriv
->driverPrivate
;
1723 sInfo
->swap_count
= rfb
->swap_count
;
1724 sInfo
->swap_ust
= rfb
->swap_ust
;
1725 sInfo
->swap_missed_count
= rfb
->swap_missed_count
;
1727 sInfo
->swap_missed_usage
= (sInfo
->swap_missed_count
!= 0)
1728 ? driCalculateSwapUsage( dPriv
, 0, rfb
->swap_missed_ust
)
1734 const struct __DriverAPIRec driDriverAPI
= {
1735 .InitScreen
= radeonInitScreen
,
1736 .DestroyScreen
= radeonDestroyScreen
,
1737 #if defined(RADEON_R200)
1738 .CreateContext
= r200CreateContext
,
1739 .DestroyContext
= r200DestroyContext
,
1740 #elif defined(RADEON_R600)
1741 .CreateContext
= r600CreateContext
,
1742 .DestroyContext
= radeonDestroyContext
,
1743 #elif defined(RADEON_R300)
1744 .CreateContext
= r300CreateContext
,
1745 .DestroyContext
= radeonDestroyContext
,
1747 .CreateContext
= r100CreateContext
,
1748 .DestroyContext
= radeonDestroyContext
,
1750 .CreateBuffer
= radeonCreateBuffer
,
1751 .DestroyBuffer
= radeonDestroyBuffer
,
1752 .SwapBuffers
= radeonSwapBuffers
,
1753 .MakeCurrent
= radeonMakeCurrent
,
1754 .UnbindContext
= radeonUnbindContext
,
1755 .GetSwapInfo
= getSwapInfo
,
1756 .GetDrawableMSC
= driDrawableGetMSC32
,
1757 .WaitForMSC
= driWaitForMSC32
,
1759 .SwapBuffersMSC
= NULL
,
1760 .CopySubBuffer
= radeonCopySubBuffer
,
1762 .InitScreen2
= radeonInitScreen2
,
1765 /* This is the table of extensions that the loader will dlsym() for. */
1766 PUBLIC
const __DRIextension
*__driDriverExtensions
[] = {
1767 &driCoreExtension
.base
,
1768 &driLegacyExtension
.base
,
1769 &driDRI2Extension
.base
,