1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #include "radeon_common.h"
50 #include "radeon_span.h"
52 #include "radeon_context.h"
53 #include "radeon_tex.h"
54 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
55 #include "r200_context.h"
56 #include "r200_ioctl.h"
58 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
59 #include "r300_context.h"
61 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
62 #include "r600_context.h"
63 #include "r700_driconf.h" /* +r6/r7 */
64 #include "r600_tex.h" /* +r6/r7 */
69 #include "drirenderbuffer.h"
71 #include "radeon_bocs_wrapper.h"
73 #include "GL/internal/dri_interface.h"
75 /* Radeon configuration
79 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
80 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
81 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
82 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
85 #if !RADEON_COMMON /* R100 */
86 PUBLIC
const char __driConfigOptions
[] =
88 DRI_CONF_SECTION_PERFORMANCE
89 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
90 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
91 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
92 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
93 DRI_CONF_HYPERZ(false)
94 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
96 DRI_CONF_SECTION_QUALITY
97 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
98 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
99 DRI_CONF_NO_NEG_LOD_BIAS(false)
100 DRI_CONF_FORCE_S3TC_ENABLE(false)
101 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
102 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
103 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
104 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
106 DRI_CONF_SECTION_DEBUG
107 DRI_CONF_NO_RAST(false)
110 static const GLuint __driNConfigOptions
= 15;
112 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
114 PUBLIC
const char __driConfigOptions
[] =
116 DRI_CONF_SECTION_PERFORMANCE
117 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
118 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
119 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
120 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
121 DRI_CONF_HYPERZ(false)
122 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
124 DRI_CONF_SECTION_QUALITY
125 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
126 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
127 DRI_CONF_NO_NEG_LOD_BIAS(false)
128 DRI_CONF_FORCE_S3TC_ENABLE(false)
129 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
130 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
131 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
132 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
133 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
135 DRI_CONF_SECTION_DEBUG
136 DRI_CONF_NO_RAST(false)
138 DRI_CONF_SECTION_SOFTWARE
139 DRI_CONF_NV_VERTEX_PROGRAM(false)
142 static const GLuint __driNConfigOptions
= 17;
144 extern const struct dri_extension blend_extensions
[];
145 extern const struct dri_extension ARB_vp_extension
[];
146 extern const struct dri_extension NV_vp_extension
[];
147 extern const struct dri_extension ATI_fs_extension
[];
148 extern const struct dri_extension point_extensions
[];
150 #elif RADEON_COMMON && (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600))
152 #define DRI_CONF_FP_OPTIMIZATION_SPEED 0
153 #define DRI_CONF_FP_OPTIMIZATION_QUALITY 1
155 /* TODO: integrate these into xmlpool.h! */
156 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
157 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
158 DRI_CONF_DESC(en,"Number of texture image units") \
159 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
162 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
163 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
164 DRI_CONF_DESC(en,"Number of texture coordinate units") \
165 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
170 #define DRI_CONF_DISABLE_S3TC(def) \
171 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
172 DRI_CONF_DESC(en,"Disable S3TC compression") \
175 #define DRI_CONF_DISABLE_FALLBACK(def) \
176 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
177 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
180 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
181 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
182 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
185 #define DRI_CONF_FP_OPTIMIZATION(def) \
186 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
187 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
188 DRI_CONF_ENUM(0,"Optimize for Speed") \
189 DRI_CONF_ENUM(1,"Optimize for Quality") \
193 PUBLIC
const char __driConfigOptions
[] =
195 DRI_CONF_SECTION_PERFORMANCE
196 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
197 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
198 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
199 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
200 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
201 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
202 DRI_CONF_DISABLE_FALLBACK(true)
203 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
205 DRI_CONF_SECTION_QUALITY
206 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
207 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
208 DRI_CONF_FORCE_S3TC_ENABLE(false)
209 DRI_CONF_DISABLE_S3TC(false)
210 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
211 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
212 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
213 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED
)
215 DRI_CONF_SECTION_DEBUG
216 DRI_CONF_NO_RAST(false)
219 static const GLuint __driNConfigOptions
= 17;
221 extern const struct dri_extension gl_20_extension
[];
223 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
225 extern const struct dri_extension card_extensions
[];
226 extern const struct dri_extension mm_extensions
[];
228 static int getSwapInfo( __DRIdrawablePrivate
*dPriv
, __DRIswapInfo
* sInfo
);
231 radeonGetParam(__DRIscreenPrivate
*sPriv
, int param
, void *value
)
234 drm_radeon_getparam_t gp
= { 0 };
235 struct drm_radeon_info info
= { 0 };
237 if (sPriv
->drm_version
.major
>= 2) {
238 info
.value
= (uint64_t)(uintptr_t)value
;
240 case RADEON_PARAM_DEVICE_ID
:
241 info
.request
= RADEON_INFO_DEVICE_ID
;
243 case RADEON_PARAM_NUM_GB_PIPES
:
244 info
.request
= RADEON_INFO_NUM_GB_PIPES
;
246 case RADEON_PARAM_NUM_Z_PIPES
:
247 info
.request
= RADEON_INFO_NUM_Z_PIPES
;
252 ret
= drmCommandWriteRead(sPriv
->fd
, DRM_RADEON_INFO
, &info
, sizeof(info
));
257 ret
= drmCommandWriteRead(sPriv
->fd
, DRM_RADEON_GETPARAM
, &gp
, sizeof(gp
));
262 static const __DRIconfig
**
263 radeonFillInModes( __DRIscreenPrivate
*psp
,
264 unsigned pixel_bits
, unsigned depth_bits
,
265 unsigned stencil_bits
, GLboolean have_back_buffer
)
267 __DRIconfig
**configs
;
269 unsigned depth_buffer_factor
;
270 unsigned back_buffer_factor
;
273 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
274 * enough to add support. Basically, if a context is created with an
275 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
276 * will never be used.
278 static const GLenum back_buffer_modes
[] = {
279 GLX_NONE
, GLX_SWAP_UNDEFINED_OML
/*, GLX_SWAP_COPY_OML */
282 uint8_t depth_bits_array
[2];
283 uint8_t stencil_bits_array
[2];
284 uint8_t msaa_samples_array
[1];
286 depth_bits_array
[0] = depth_bits
;
287 depth_bits_array
[1] = depth_bits
;
289 /* Just like with the accumulation buffer, always provide some modes
290 * with a stencil buffer. It will be a sw fallback, but some apps won't
293 stencil_bits_array
[0] = stencil_bits
;
294 stencil_bits_array
[1] = (stencil_bits
== 0) ? 8 : stencil_bits
;
296 msaa_samples_array
[0] = 0;
298 depth_buffer_factor
= (stencil_bits
== 0) ? 2 : 1;
299 back_buffer_factor
= (have_back_buffer
) ? 2 : 1;
301 if (pixel_bits
== 16) {
302 __DRIconfig
**configs_a8r8g8b8
;
303 __DRIconfig
**configs_r5g6b5
;
305 configs_r5g6b5
= driCreateConfigs(GL_RGB
, GL_UNSIGNED_SHORT_5_6_5
,
306 depth_bits_array
, stencil_bits_array
,
307 depth_buffer_factor
, back_buffer_modes
,
308 back_buffer_factor
, msaa_samples_array
,
310 configs_a8r8g8b8
= driCreateConfigs(GL_BGRA
, GL_UNSIGNED_INT_8_8_8_8_REV
,
311 depth_bits_array
, stencil_bits_array
,
312 1, back_buffer_modes
, 1,
313 msaa_samples_array
, 1);
314 configs
= driConcatConfigs(configs_r5g6b5
, configs_a8r8g8b8
);
316 configs
= driCreateConfigs(GL_BGRA
, GL_UNSIGNED_INT_8_8_8_8_REV
,
317 depth_bits_array
, stencil_bits_array
,
319 back_buffer_modes
, back_buffer_factor
,
320 msaa_samples_array
, 1);
322 if (configs
== NULL
) {
323 fprintf( stderr
, "[%s:%u] Error creating FBConfig!\n",
324 __func__
, __LINE__
);
328 /* Mark the visual as slow if there are "fake" stencil bits.
330 for (i
= 0; configs
[i
]; i
++) {
331 m
= &configs
[i
]->modes
;
332 if ((m
->stencilBits
!= 0) && (m
->stencilBits
!= stencil_bits
)) {
333 m
->visualRating
= GLX_SLOW_CONFIG
;
337 return (const __DRIconfig
**) configs
;
341 static const __DRItexOffsetExtension radeonTexOffsetExtension
= {
342 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
346 static const __DRItexBufferExtension radeonTexBufferExtension
= {
347 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
353 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
354 static const __DRIallocateExtension r200AllocateExtension
= {
355 { __DRI_ALLOCATE
, __DRI_ALLOCATE_VERSION
},
356 r200AllocateMemoryMESA
,
358 r200GetMemoryOffsetMESA
361 static const __DRItexOffsetExtension r200texOffsetExtension
= {
362 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
366 static const __DRItexBufferExtension r200TexBufferExtension
= {
367 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
373 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
374 static const __DRItexOffsetExtension r300texOffsetExtension
= {
375 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
379 static const __DRItexBufferExtension r300TexBufferExtension
= {
380 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
386 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
387 static const __DRItexOffsetExtension r600texOffsetExtension
= {
388 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
389 r600SetTexOffset
, /* +r6/r7 */
392 static const __DRItexBufferExtension r600TexBufferExtension
= {
393 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
394 r600SetTexBuffer
, /* +r6/r7 */
395 r600SetTexBuffer2
, /* +r6/r7 */
399 static int radeon_set_screen_flags(radeonScreenPtr screen
, int device_id
)
401 screen
->device_id
= device_id
;
402 screen
->chip_flags
= 0;
403 switch ( device_id
) {
404 case PCI_CHIP_RADEON_LY
:
405 case PCI_CHIP_RADEON_LZ
:
406 case PCI_CHIP_RADEON_QY
:
407 case PCI_CHIP_RADEON_QZ
:
408 case PCI_CHIP_RN50_515E
:
409 case PCI_CHIP_RN50_5969
:
410 screen
->chip_family
= CHIP_FAMILY_RV100
;
413 case PCI_CHIP_RS100_4136
:
414 case PCI_CHIP_RS100_4336
:
415 screen
->chip_family
= CHIP_FAMILY_RS100
;
418 case PCI_CHIP_RS200_4137
:
419 case PCI_CHIP_RS200_4337
:
420 case PCI_CHIP_RS250_4237
:
421 case PCI_CHIP_RS250_4437
:
422 screen
->chip_family
= CHIP_FAMILY_RS200
;
425 case PCI_CHIP_RADEON_QD
:
426 case PCI_CHIP_RADEON_QE
:
427 case PCI_CHIP_RADEON_QF
:
428 case PCI_CHIP_RADEON_QG
:
429 /* all original radeons (7200) presumably have a stencil op bug */
430 screen
->chip_family
= CHIP_FAMILY_R100
;
431 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_BROKEN_STENCIL
;
434 case PCI_CHIP_RV200_QW
:
435 case PCI_CHIP_RV200_QX
:
436 case PCI_CHIP_RADEON_LW
:
437 case PCI_CHIP_RADEON_LX
:
438 screen
->chip_family
= CHIP_FAMILY_RV200
;
439 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
442 case PCI_CHIP_R200_BB
:
443 case PCI_CHIP_R200_BC
:
444 case PCI_CHIP_R200_QH
:
445 case PCI_CHIP_R200_QL
:
446 case PCI_CHIP_R200_QM
:
447 screen
->chip_family
= CHIP_FAMILY_R200
;
448 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
451 case PCI_CHIP_RV250_If
:
452 case PCI_CHIP_RV250_Ig
:
453 case PCI_CHIP_RV250_Ld
:
454 case PCI_CHIP_RV250_Lf
:
455 case PCI_CHIP_RV250_Lg
:
456 screen
->chip_family
= CHIP_FAMILY_RV250
;
457 screen
->chip_flags
= R200_CHIPSET_YCBCR_BROKEN
| RADEON_CHIPSET_TCL
;
460 case PCI_CHIP_RV280_5960
:
461 case PCI_CHIP_RV280_5961
:
462 case PCI_CHIP_RV280_5962
:
463 case PCI_CHIP_RV280_5964
:
464 case PCI_CHIP_RV280_5965
:
465 case PCI_CHIP_RV280_5C61
:
466 case PCI_CHIP_RV280_5C63
:
467 screen
->chip_family
= CHIP_FAMILY_RV280
;
468 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
471 case PCI_CHIP_RS300_5834
:
472 case PCI_CHIP_RS300_5835
:
473 case PCI_CHIP_RS350_7834
:
474 case PCI_CHIP_RS350_7835
:
475 screen
->chip_family
= CHIP_FAMILY_RS300
;
478 case PCI_CHIP_R300_AD
:
479 case PCI_CHIP_R300_AE
:
480 case PCI_CHIP_R300_AF
:
481 case PCI_CHIP_R300_AG
:
482 case PCI_CHIP_R300_ND
:
483 case PCI_CHIP_R300_NE
:
484 case PCI_CHIP_R300_NF
:
485 case PCI_CHIP_R300_NG
:
486 screen
->chip_family
= CHIP_FAMILY_R300
;
487 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
490 case PCI_CHIP_RV350_AP
:
491 case PCI_CHIP_RV350_AQ
:
492 case PCI_CHIP_RV350_AR
:
493 case PCI_CHIP_RV350_AS
:
494 case PCI_CHIP_RV350_AT
:
495 case PCI_CHIP_RV350_AV
:
496 case PCI_CHIP_RV350_AU
:
497 case PCI_CHIP_RV350_NP
:
498 case PCI_CHIP_RV350_NQ
:
499 case PCI_CHIP_RV350_NR
:
500 case PCI_CHIP_RV350_NS
:
501 case PCI_CHIP_RV350_NT
:
502 case PCI_CHIP_RV350_NV
:
503 screen
->chip_family
= CHIP_FAMILY_RV350
;
504 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
507 case PCI_CHIP_R350_AH
:
508 case PCI_CHIP_R350_AI
:
509 case PCI_CHIP_R350_AJ
:
510 case PCI_CHIP_R350_AK
:
511 case PCI_CHIP_R350_NH
:
512 case PCI_CHIP_R350_NI
:
513 case PCI_CHIP_R360_NJ
:
514 case PCI_CHIP_R350_NK
:
515 screen
->chip_family
= CHIP_FAMILY_R350
;
516 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
519 case PCI_CHIP_RV370_5460
:
520 case PCI_CHIP_RV370_5462
:
521 case PCI_CHIP_RV370_5464
:
522 case PCI_CHIP_RV370_5B60
:
523 case PCI_CHIP_RV370_5B62
:
524 case PCI_CHIP_RV370_5B63
:
525 case PCI_CHIP_RV370_5B64
:
526 case PCI_CHIP_RV370_5B65
:
527 case PCI_CHIP_RV380_3150
:
528 case PCI_CHIP_RV380_3152
:
529 case PCI_CHIP_RV380_3154
:
530 case PCI_CHIP_RV380_3E50
:
531 case PCI_CHIP_RV380_3E54
:
532 screen
->chip_family
= CHIP_FAMILY_RV380
;
533 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
536 case PCI_CHIP_R420_JN
:
537 case PCI_CHIP_R420_JH
:
538 case PCI_CHIP_R420_JI
:
539 case PCI_CHIP_R420_JJ
:
540 case PCI_CHIP_R420_JK
:
541 case PCI_CHIP_R420_JL
:
542 case PCI_CHIP_R420_JM
:
543 case PCI_CHIP_R420_JO
:
544 case PCI_CHIP_R420_JP
:
545 case PCI_CHIP_R420_JT
:
546 case PCI_CHIP_R481_4B49
:
547 case PCI_CHIP_R481_4B4A
:
548 case PCI_CHIP_R481_4B4B
:
549 case PCI_CHIP_R481_4B4C
:
550 case PCI_CHIP_R423_UH
:
551 case PCI_CHIP_R423_UI
:
552 case PCI_CHIP_R423_UJ
:
553 case PCI_CHIP_R423_UK
:
554 case PCI_CHIP_R430_554C
:
555 case PCI_CHIP_R430_554D
:
556 case PCI_CHIP_R430_554E
:
557 case PCI_CHIP_R430_554F
:
558 case PCI_CHIP_R423_5550
:
559 case PCI_CHIP_R423_UQ
:
560 case PCI_CHIP_R423_UR
:
561 case PCI_CHIP_R423_UT
:
562 case PCI_CHIP_R430_5D48
:
563 case PCI_CHIP_R430_5D49
:
564 case PCI_CHIP_R430_5D4A
:
565 case PCI_CHIP_R480_5D4C
:
566 case PCI_CHIP_R480_5D4D
:
567 case PCI_CHIP_R480_5D4E
:
568 case PCI_CHIP_R480_5D4F
:
569 case PCI_CHIP_R480_5D50
:
570 case PCI_CHIP_R480_5D52
:
571 case PCI_CHIP_R423_5D57
:
572 screen
->chip_family
= CHIP_FAMILY_R420
;
573 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
576 case PCI_CHIP_RV410_5E4C
:
577 case PCI_CHIP_RV410_5E4F
:
578 case PCI_CHIP_RV410_564A
:
579 case PCI_CHIP_RV410_564B
:
580 case PCI_CHIP_RV410_564F
:
581 case PCI_CHIP_RV410_5652
:
582 case PCI_CHIP_RV410_5653
:
583 case PCI_CHIP_RV410_5657
:
584 case PCI_CHIP_RV410_5E48
:
585 case PCI_CHIP_RV410_5E4A
:
586 case PCI_CHIP_RV410_5E4B
:
587 case PCI_CHIP_RV410_5E4D
:
588 screen
->chip_family
= CHIP_FAMILY_RV410
;
589 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
592 case PCI_CHIP_RS480_5954
:
593 case PCI_CHIP_RS480_5955
:
594 case PCI_CHIP_RS482_5974
:
595 case PCI_CHIP_RS482_5975
:
596 case PCI_CHIP_RS400_5A41
:
597 case PCI_CHIP_RS400_5A42
:
598 case PCI_CHIP_RC410_5A61
:
599 case PCI_CHIP_RC410_5A62
:
600 screen
->chip_family
= CHIP_FAMILY_RS400
;
603 case PCI_CHIP_RS600_793F
:
604 case PCI_CHIP_RS600_7941
:
605 case PCI_CHIP_RS600_7942
:
606 screen
->chip_family
= CHIP_FAMILY_RS600
;
609 case PCI_CHIP_RS690_791E
:
610 case PCI_CHIP_RS690_791F
:
611 screen
->chip_family
= CHIP_FAMILY_RS690
;
613 case PCI_CHIP_RS740_796C
:
614 case PCI_CHIP_RS740_796D
:
615 case PCI_CHIP_RS740_796E
:
616 case PCI_CHIP_RS740_796F
:
617 screen
->chip_family
= CHIP_FAMILY_RS740
;
620 case PCI_CHIP_R520_7100
:
621 case PCI_CHIP_R520_7101
:
622 case PCI_CHIP_R520_7102
:
623 case PCI_CHIP_R520_7103
:
624 case PCI_CHIP_R520_7104
:
625 case PCI_CHIP_R520_7105
:
626 case PCI_CHIP_R520_7106
:
627 case PCI_CHIP_R520_7108
:
628 case PCI_CHIP_R520_7109
:
629 case PCI_CHIP_R520_710A
:
630 case PCI_CHIP_R520_710B
:
631 case PCI_CHIP_R520_710C
:
632 case PCI_CHIP_R520_710E
:
633 case PCI_CHIP_R520_710F
:
634 screen
->chip_family
= CHIP_FAMILY_R520
;
635 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
638 case PCI_CHIP_RV515_7140
:
639 case PCI_CHIP_RV515_7141
:
640 case PCI_CHIP_RV515_7142
:
641 case PCI_CHIP_RV515_7143
:
642 case PCI_CHIP_RV515_7144
:
643 case PCI_CHIP_RV515_7145
:
644 case PCI_CHIP_RV515_7146
:
645 case PCI_CHIP_RV515_7147
:
646 case PCI_CHIP_RV515_7149
:
647 case PCI_CHIP_RV515_714A
:
648 case PCI_CHIP_RV515_714B
:
649 case PCI_CHIP_RV515_714C
:
650 case PCI_CHIP_RV515_714D
:
651 case PCI_CHIP_RV515_714E
:
652 case PCI_CHIP_RV515_714F
:
653 case PCI_CHIP_RV515_7151
:
654 case PCI_CHIP_RV515_7152
:
655 case PCI_CHIP_RV515_7153
:
656 case PCI_CHIP_RV515_715E
:
657 case PCI_CHIP_RV515_715F
:
658 case PCI_CHIP_RV515_7180
:
659 case PCI_CHIP_RV515_7181
:
660 case PCI_CHIP_RV515_7183
:
661 case PCI_CHIP_RV515_7186
:
662 case PCI_CHIP_RV515_7187
:
663 case PCI_CHIP_RV515_7188
:
664 case PCI_CHIP_RV515_718A
:
665 case PCI_CHIP_RV515_718B
:
666 case PCI_CHIP_RV515_718C
:
667 case PCI_CHIP_RV515_718D
:
668 case PCI_CHIP_RV515_718F
:
669 case PCI_CHIP_RV515_7193
:
670 case PCI_CHIP_RV515_7196
:
671 case PCI_CHIP_RV515_719B
:
672 case PCI_CHIP_RV515_719F
:
673 case PCI_CHIP_RV515_7200
:
674 case PCI_CHIP_RV515_7210
:
675 case PCI_CHIP_RV515_7211
:
676 screen
->chip_family
= CHIP_FAMILY_RV515
;
677 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
680 case PCI_CHIP_RV530_71C0
:
681 case PCI_CHIP_RV530_71C1
:
682 case PCI_CHIP_RV530_71C2
:
683 case PCI_CHIP_RV530_71C3
:
684 case PCI_CHIP_RV530_71C4
:
685 case PCI_CHIP_RV530_71C5
:
686 case PCI_CHIP_RV530_71C6
:
687 case PCI_CHIP_RV530_71C7
:
688 case PCI_CHIP_RV530_71CD
:
689 case PCI_CHIP_RV530_71CE
:
690 case PCI_CHIP_RV530_71D2
:
691 case PCI_CHIP_RV530_71D4
:
692 case PCI_CHIP_RV530_71D5
:
693 case PCI_CHIP_RV530_71D6
:
694 case PCI_CHIP_RV530_71DA
:
695 case PCI_CHIP_RV530_71DE
:
696 screen
->chip_family
= CHIP_FAMILY_RV530
;
697 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
700 case PCI_CHIP_R580_7240
:
701 case PCI_CHIP_R580_7243
:
702 case PCI_CHIP_R580_7244
:
703 case PCI_CHIP_R580_7245
:
704 case PCI_CHIP_R580_7246
:
705 case PCI_CHIP_R580_7247
:
706 case PCI_CHIP_R580_7248
:
707 case PCI_CHIP_R580_7249
:
708 case PCI_CHIP_R580_724A
:
709 case PCI_CHIP_R580_724B
:
710 case PCI_CHIP_R580_724C
:
711 case PCI_CHIP_R580_724D
:
712 case PCI_CHIP_R580_724E
:
713 case PCI_CHIP_R580_724F
:
714 case PCI_CHIP_R580_7284
:
715 screen
->chip_family
= CHIP_FAMILY_R580
;
716 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
719 case PCI_CHIP_RV570_7280
:
720 case PCI_CHIP_RV560_7281
:
721 case PCI_CHIP_RV560_7283
:
722 case PCI_CHIP_RV560_7287
:
723 case PCI_CHIP_RV570_7288
:
724 case PCI_CHIP_RV570_7289
:
725 case PCI_CHIP_RV570_728B
:
726 case PCI_CHIP_RV570_728C
:
727 case PCI_CHIP_RV560_7290
:
728 case PCI_CHIP_RV560_7291
:
729 case PCI_CHIP_RV560_7293
:
730 case PCI_CHIP_RV560_7297
:
731 screen
->chip_family
= CHIP_FAMILY_RV560
;
732 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
735 case PCI_CHIP_R600_9400
:
736 case PCI_CHIP_R600_9401
:
737 case PCI_CHIP_R600_9402
:
738 case PCI_CHIP_R600_9403
:
739 case PCI_CHIP_R600_9405
:
740 case PCI_CHIP_R600_940A
:
741 case PCI_CHIP_R600_940B
:
742 case PCI_CHIP_R600_940F
:
743 screen
->chip_family
= CHIP_FAMILY_R600
;
744 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
747 case PCI_CHIP_RV610_94C0
:
748 case PCI_CHIP_RV610_94C1
:
749 case PCI_CHIP_RV610_94C3
:
750 case PCI_CHIP_RV610_94C4
:
751 case PCI_CHIP_RV610_94C5
:
752 case PCI_CHIP_RV610_94C6
:
753 case PCI_CHIP_RV610_94C7
:
754 case PCI_CHIP_RV610_94C8
:
755 case PCI_CHIP_RV610_94C9
:
756 case PCI_CHIP_RV610_94CB
:
757 case PCI_CHIP_RV610_94CC
:
758 case PCI_CHIP_RV610_94CD
:
759 screen
->chip_family
= CHIP_FAMILY_RV610
;
760 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
763 case PCI_CHIP_RV630_9580
:
764 case PCI_CHIP_RV630_9581
:
765 case PCI_CHIP_RV630_9583
:
766 case PCI_CHIP_RV630_9586
:
767 case PCI_CHIP_RV630_9587
:
768 case PCI_CHIP_RV630_9588
:
769 case PCI_CHIP_RV630_9589
:
770 case PCI_CHIP_RV630_958A
:
771 case PCI_CHIP_RV630_958B
:
772 case PCI_CHIP_RV630_958C
:
773 case PCI_CHIP_RV630_958D
:
774 case PCI_CHIP_RV630_958E
:
775 case PCI_CHIP_RV630_958F
:
776 screen
->chip_family
= CHIP_FAMILY_RV630
;
777 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
780 case PCI_CHIP_RV670_9500
:
781 case PCI_CHIP_RV670_9501
:
782 case PCI_CHIP_RV670_9504
:
783 case PCI_CHIP_RV670_9505
:
784 case PCI_CHIP_RV670_9506
:
785 case PCI_CHIP_RV670_9507
:
786 case PCI_CHIP_RV670_9508
:
787 case PCI_CHIP_RV670_9509
:
788 case PCI_CHIP_RV670_950F
:
789 case PCI_CHIP_RV670_9511
:
790 case PCI_CHIP_RV670_9515
:
791 case PCI_CHIP_RV670_9517
:
792 case PCI_CHIP_RV670_9519
:
793 screen
->chip_family
= CHIP_FAMILY_RV670
;
794 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
797 case PCI_CHIP_RV620_95C0
:
798 case PCI_CHIP_RV620_95C2
:
799 case PCI_CHIP_RV620_95C4
:
800 case PCI_CHIP_RV620_95C5
:
801 case PCI_CHIP_RV620_95C6
:
802 case PCI_CHIP_RV620_95C7
:
803 case PCI_CHIP_RV620_95C9
:
804 case PCI_CHIP_RV620_95CC
:
805 case PCI_CHIP_RV620_95CD
:
806 case PCI_CHIP_RV620_95CE
:
807 case PCI_CHIP_RV620_95CF
:
808 screen
->chip_family
= CHIP_FAMILY_RV620
;
809 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
812 case PCI_CHIP_RV635_9590
:
813 case PCI_CHIP_RV635_9591
:
814 case PCI_CHIP_RV635_9593
:
815 case PCI_CHIP_RV635_9595
:
816 case PCI_CHIP_RV635_9596
:
817 case PCI_CHIP_RV635_9597
:
818 case PCI_CHIP_RV635_9598
:
819 case PCI_CHIP_RV635_9599
:
820 case PCI_CHIP_RV635_959B
:
821 screen
->chip_family
= CHIP_FAMILY_RV635
;
822 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
825 case PCI_CHIP_RS780_9610
:
826 case PCI_CHIP_RS780_9611
:
827 case PCI_CHIP_RS780_9612
:
828 case PCI_CHIP_RS780_9613
:
829 case PCI_CHIP_RS780_9614
:
830 case PCI_CHIP_RS780_9615
:
831 case PCI_CHIP_RS780_9616
:
832 screen
->chip_family
= CHIP_FAMILY_RS780
;
833 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
835 case PCI_CHIP_RS880_9710
:
836 case PCI_CHIP_RS880_9711
:
837 case PCI_CHIP_RS880_9712
:
838 case PCI_CHIP_RS880_9713
:
839 case PCI_CHIP_RS880_9714
:
840 screen
->chip_family
= CHIP_FAMILY_RS880
;
841 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
844 case PCI_CHIP_RV770_9440
:
845 case PCI_CHIP_RV770_9441
:
846 case PCI_CHIP_RV770_9442
:
847 case PCI_CHIP_RV770_9443
:
848 case PCI_CHIP_RV770_9444
:
849 case PCI_CHIP_RV770_9446
:
850 case PCI_CHIP_RV770_944A
:
851 case PCI_CHIP_RV770_944B
:
852 case PCI_CHIP_RV770_944C
:
853 case PCI_CHIP_RV770_944E
:
854 case PCI_CHIP_RV770_9450
:
855 case PCI_CHIP_RV770_9452
:
856 case PCI_CHIP_RV770_9456
:
857 case PCI_CHIP_RV770_945A
:
858 case PCI_CHIP_RV770_945B
:
859 case PCI_CHIP_RV790_9460
:
860 case PCI_CHIP_RV790_9462
:
861 case PCI_CHIP_RV770_946A
:
862 case PCI_CHIP_RV770_946B
:
863 case PCI_CHIP_RV770_947A
:
864 case PCI_CHIP_RV770_947B
:
865 screen
->chip_family
= CHIP_FAMILY_RV770
;
866 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
869 case PCI_CHIP_RV730_9480
:
870 case PCI_CHIP_RV730_9487
:
871 case PCI_CHIP_RV730_9488
:
872 case PCI_CHIP_RV730_9489
:
873 case PCI_CHIP_RV730_948F
:
874 case PCI_CHIP_RV730_9490
:
875 case PCI_CHIP_RV730_9491
:
876 case PCI_CHIP_RV730_9495
:
877 case PCI_CHIP_RV730_9498
:
878 case PCI_CHIP_RV730_949C
:
879 case PCI_CHIP_RV730_949E
:
880 case PCI_CHIP_RV730_949F
:
881 screen
->chip_family
= CHIP_FAMILY_RV730
;
882 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
885 case PCI_CHIP_RV710_9540
:
886 case PCI_CHIP_RV710_9541
:
887 case PCI_CHIP_RV710_9542
:
888 case PCI_CHIP_RV710_954E
:
889 case PCI_CHIP_RV710_954F
:
890 case PCI_CHIP_RV710_9552
:
891 case PCI_CHIP_RV710_9553
:
892 case PCI_CHIP_RV710_9555
:
893 case PCI_CHIP_RV710_9557
:
894 screen
->chip_family
= CHIP_FAMILY_RV710
;
895 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
898 case PCI_CHIP_RV740_94A0
:
899 case PCI_CHIP_RV740_94A1
:
900 case PCI_CHIP_RV740_94A3
:
901 case PCI_CHIP_RV740_94B1
:
902 case PCI_CHIP_RV740_94B3
:
903 case PCI_CHIP_RV740_94B4
:
904 case PCI_CHIP_RV740_94B5
:
905 case PCI_CHIP_RV740_94B9
:
906 screen
->chip_family
= CHIP_FAMILY_RV740
;
907 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
911 fprintf(stderr
, "unknown chip id 0x%x, can't guess.\n",
920 /* Create the device specific screen private data struct.
922 static radeonScreenPtr
923 radeonCreateScreen( __DRIscreenPrivate
*sPriv
)
925 radeonScreenPtr screen
;
926 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
)sPriv
->pDevPriv
;
927 unsigned char *RADEONMMIO
= NULL
;
932 if (sPriv
->devPrivSize
!= sizeof(RADEONDRIRec
)) {
933 fprintf(stderr
,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
937 /* Allocate the private area */
938 screen
= (radeonScreenPtr
) CALLOC( sizeof(*screen
) );
940 __driUtilMessage("%s: Could not allocate memory for screen structure",
947 /* parse information in __driConfigOptions */
948 driParseOptionInfo (&screen
->optionCache
,
949 __driConfigOptions
, __driNConfigOptions
);
951 /* This is first since which regions we map depends on whether or
952 * not we are using a PCI card.
954 screen
->card_type
= (dri_priv
->IsPCI
? RADEON_CARD_PCI
: RADEON_CARD_AGP
);
958 ret
= radeonGetParam(sPriv
, RADEON_PARAM_GART_BUFFER_OFFSET
,
959 &screen
->gart_buffer_offset
);
963 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret
);
967 ret
= radeonGetParam(sPriv
, RADEON_PARAM_GART_BASE
,
971 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret
);
975 ret
= radeonGetParam(sPriv
, RADEON_PARAM_IRQ_NR
,
979 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret
);
982 screen
->drmSupportsCubeMapsR200
= (sPriv
->drm_version
.minor
>= 7);
983 screen
->drmSupportsBlendColor
= (sPriv
->drm_version
.minor
>= 11);
984 screen
->drmSupportsTriPerf
= (sPriv
->drm_version
.minor
>= 16);
985 screen
->drmSupportsFragShader
= (sPriv
->drm_version
.minor
>= 18);
986 screen
->drmSupportsPointSprites
= (sPriv
->drm_version
.minor
>= 13);
987 screen
->drmSupportsCubeMapsR100
= (sPriv
->drm_version
.minor
>= 15);
988 screen
->drmSupportsVertexProgram
= (sPriv
->drm_version
.minor
>= 25);
989 screen
->drmSupportsOcclusionQueries
= (sPriv
->drm_version
.minor
>= 30);
992 ret
= radeon_set_screen_flags(screen
, dri_priv
->deviceID
);
996 screen
->mmio
.handle
= dri_priv
->registerHandle
;
997 screen
->mmio
.size
= dri_priv
->registerSize
;
998 if ( drmMap( sPriv
->fd
,
1001 &screen
->mmio
.map
) ) {
1003 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__
);
1007 RADEONMMIO
= screen
->mmio
.map
;
1009 screen
->status
.handle
= dri_priv
->statusHandle
;
1010 screen
->status
.size
= dri_priv
->statusSize
;
1011 if ( drmMap( sPriv
->fd
,
1012 screen
->status
.handle
,
1013 screen
->status
.size
,
1014 &screen
->status
.map
) ) {
1015 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
1017 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__
);
1020 if (screen
->chip_family
< CHIP_FAMILY_R600
)
1021 screen
->scratch
= (__volatile__
uint32_t *)
1022 ((GLubyte
*)screen
->status
.map
+ RADEON_SCRATCH_REG_OFFSET
);
1024 screen
->scratch
= (__volatile__
uint32_t *)
1025 ((GLubyte
*)screen
->status
.map
+ R600_SCRATCH_REG_OFFSET
);
1027 screen
->buffers
= drmMapBufs( sPriv
->fd
);
1028 if ( !screen
->buffers
) {
1029 drmUnmap( screen
->status
.map
, screen
->status
.size
);
1030 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
1032 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__
);
1036 if ( dri_priv
->gartTexHandle
&& dri_priv
->gartTexMapSize
) {
1037 screen
->gartTextures
.handle
= dri_priv
->gartTexHandle
;
1038 screen
->gartTextures
.size
= dri_priv
->gartTexMapSize
;
1039 if ( drmMap( sPriv
->fd
,
1040 screen
->gartTextures
.handle
,
1041 screen
->gartTextures
.size
,
1042 (drmAddressPtr
)&screen
->gartTextures
.map
) ) {
1043 drmUnmapBufs( screen
->buffers
);
1044 drmUnmap( screen
->status
.map
, screen
->status
.size
);
1045 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
1047 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__
);
1051 screen
->gart_texture_offset
= dri_priv
->gartTexOffset
+ screen
->gart_base
;
1054 if ((screen
->chip_family
== CHIP_FAMILY_R350
|| screen
->chip_family
== CHIP_FAMILY_R300
) &&
1055 sPriv
->ddx_version
.minor
< 2) {
1056 fprintf(stderr
, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
1060 if ((sPriv
->drm_version
.minor
< 29) && (screen
->chip_family
>= CHIP_FAMILY_RV515
)) {
1061 fprintf(stderr
, "R500 support requires a newer drm.\n");
1065 if (getenv("R300_NO_TCL"))
1066 screen
->chip_flags
&= ~RADEON_CHIPSET_TCL
;
1068 if (screen
->chip_family
<= CHIP_FAMILY_RS200
)
1069 screen
->chip_flags
|= RADEON_CLASS_R100
;
1070 else if (screen
->chip_family
<= CHIP_FAMILY_RV280
)
1071 screen
->chip_flags
|= RADEON_CLASS_R200
;
1072 else if (screen
->chip_family
<= CHIP_FAMILY_RV570
)
1073 screen
->chip_flags
|= RADEON_CLASS_R300
;
1075 screen
->chip_flags
|= RADEON_CLASS_R600
;
1077 screen
->cpp
= dri_priv
->bpp
/ 8;
1078 screen
->AGPMode
= dri_priv
->AGPMode
;
1080 ret
= radeonGetParam(sPriv
, RADEON_PARAM_FB_LOCATION
, &temp
);
1083 if(screen
->chip_family
>= CHIP_FAMILY_R600
)
1088 fprintf(stderr
, "Unable to get fb location need newer drm\n");
1093 screen
->fbLocation
= (temp
& 0xffff) << 24;
1100 if (screen
->chip_family
< CHIP_FAMILY_RS600
&& !screen
->kernel_mm
)
1101 screen
->fbLocation
= ( INREG( RADEON_MC_FB_LOCATION
) & 0xffff) << 16;
1105 fprintf(stderr
, "Unable to get fb location need newer drm\n");
1111 screen
->fbLocation
= (temp
& 0xffff) << 16;
1115 if (IS_R300_CLASS(screen
)) {
1116 ret
= radeonGetParam(sPriv
, RADEON_PARAM_NUM_GB_PIPES
, &temp
);
1118 fprintf(stderr
, "Unable to get num_pipes, need newer drm\n");
1119 switch (screen
->chip_family
) {
1120 case CHIP_FAMILY_R300
:
1121 case CHIP_FAMILY_R350
:
1122 screen
->num_gb_pipes
= 2;
1124 case CHIP_FAMILY_R420
:
1125 case CHIP_FAMILY_R520
:
1126 case CHIP_FAMILY_R580
:
1127 case CHIP_FAMILY_RV560
:
1128 case CHIP_FAMILY_RV570
:
1129 screen
->num_gb_pipes
= 4;
1131 case CHIP_FAMILY_RV350
:
1132 case CHIP_FAMILY_RV515
:
1133 case CHIP_FAMILY_RV530
:
1134 case CHIP_FAMILY_RV410
:
1136 screen
->num_gb_pipes
= 1;
1140 screen
->num_gb_pipes
= temp
;
1143 /* pipe overrides */
1144 switch (dri_priv
->deviceID
) {
1145 case PCI_CHIP_R300_AD
: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1146 case PCI_CHIP_RV410_5E4C
: /* RV410 SE only have 1 quadpipe */
1147 case PCI_CHIP_RV410_5E4F
: /* RV410 SE only have 1 quadpipe */
1148 screen
->num_gb_pipes
= 1;
1154 if ( sPriv
->drm_version
.minor
>= 31 ) {
1155 ret
= radeonGetParam(sPriv
, RADEON_PARAM_NUM_Z_PIPES
, &temp
);
1157 screen
->num_z_pipes
= 2;
1159 screen
->num_z_pipes
= temp
;
1161 screen
->num_z_pipes
= 2;
1164 if ( sPriv
->drm_version
.minor
>= 10 ) {
1165 drm_radeon_setparam_t sp
;
1167 sp
.param
= RADEON_SETPARAM_FB_LOCATION
;
1168 sp
.value
= screen
->fbLocation
;
1170 drmCommandWrite( sPriv
->fd
, DRM_RADEON_SETPARAM
,
1171 &sp
, sizeof( sp
) );
1174 screen
->frontOffset
= dri_priv
->frontOffset
;
1175 screen
->frontPitch
= dri_priv
->frontPitch
;
1176 screen
->backOffset
= dri_priv
->backOffset
;
1177 screen
->backPitch
= dri_priv
->backPitch
;
1178 screen
->depthOffset
= dri_priv
->depthOffset
;
1179 screen
->depthPitch
= dri_priv
->depthPitch
;
1181 /* Check if ddx has set up a surface reg to cover depth buffer */
1182 screen
->depthHasSurface
= (sPriv
->ddx_version
.major
> 4) ||
1183 /* these chips don't use tiled z without hyperz. So always pretend
1184 we have set up a surface which will cause linear reads/writes */
1185 (IS_R100_CLASS(screen
) &&
1186 !(screen
->chip_flags
& RADEON_CHIPSET_TCL
));
1188 if ( dri_priv
->textureSize
== 0 ) {
1189 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = screen
->gart_texture_offset
;
1190 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
1191 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
1192 dri_priv
->log2GARTTexGran
;
1194 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureOffset
1195 + screen
->fbLocation
;
1196 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureSize
;
1197 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
1198 dri_priv
->log2TexGran
;
1201 if ( !screen
->gartTextures
.map
|| dri_priv
->textureSize
== 0
1202 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
1203 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
- 1;
1204 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = 0;
1205 screen
->texSize
[RADEON_GART_TEX_HEAP
] = 0;
1206 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] = 0;
1208 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
;
1209 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = screen
->gart_texture_offset
;
1210 screen
->texSize
[RADEON_GART_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
1211 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] =
1212 dri_priv
->log2GARTTexGran
;
1216 screen
->extensions
[i
++] = &driCopySubBufferExtension
.base
;
1217 screen
->extensions
[i
++] = &driFrameTrackingExtension
.base
;
1218 screen
->extensions
[i
++] = &driReadDrawableExtension
;
1220 if ( screen
->irq
!= 0 ) {
1221 screen
->extensions
[i
++] = &driSwapControlExtension
.base
;
1222 screen
->extensions
[i
++] = &driMediaStreamCounterExtension
.base
;
1226 screen
->extensions
[i
++] = &radeonTexOffsetExtension
.base
;
1229 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1230 if (IS_R200_CLASS(screen
))
1231 screen
->extensions
[i
++] = &r200AllocateExtension
.base
;
1233 screen
->extensions
[i
++] = &r200texOffsetExtension
.base
;
1236 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1237 screen
->extensions
[i
++] = &r300texOffsetExtension
.base
;
1240 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
1241 screen
->extensions
[i
++] = &r600texOffsetExtension
.base
;
1244 screen
->extensions
[i
++] = NULL
;
1245 sPriv
->extensions
= screen
->extensions
;
1247 screen
->driScreen
= sPriv
;
1248 screen
->sarea_priv_offset
= dri_priv
->sarea_priv_offset
;
1249 screen
->sarea
= (drm_radeon_sarea_t
*) ((GLubyte
*) sPriv
->pSAREA
+
1250 screen
->sarea_priv_offset
);
1252 screen
->bom
= radeon_bo_manager_legacy_ctor(screen
);
1253 if (screen
->bom
== NULL
) {
1261 static radeonScreenPtr
1262 radeonCreateScreen2(__DRIscreenPrivate
*sPriv
)
1264 radeonScreenPtr screen
;
1267 uint32_t device_id
= 0;
1270 /* Allocate the private area */
1271 screen
= (radeonScreenPtr
) CALLOC( sizeof(*screen
) );
1273 __driUtilMessage("%s: Could not allocate memory for screen structure",
1275 fprintf(stderr
, "leaving here\n");
1279 radeon_init_debug();
1281 /* parse information in __driConfigOptions */
1282 driParseOptionInfo (&screen
->optionCache
,
1283 __driConfigOptions
, __driNConfigOptions
);
1285 screen
->kernel_mm
= 1;
1286 screen
->chip_flags
= 0;
1288 /* if we have kms we can support all of these */
1289 screen
->drmSupportsCubeMapsR200
= 1;
1290 screen
->drmSupportsBlendColor
= 1;
1291 screen
->drmSupportsTriPerf
= 1;
1292 screen
->drmSupportsFragShader
= 1;
1293 screen
->drmSupportsPointSprites
= 1;
1294 screen
->drmSupportsCubeMapsR100
= 1;
1295 screen
->drmSupportsVertexProgram
= 1;
1296 screen
->drmSupportsOcclusionQueries
= 1;
1299 ret
= radeonGetParam(sPriv
, RADEON_PARAM_DEVICE_ID
, &device_id
);
1302 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret
);
1306 ret
= radeon_set_screen_flags(screen
, device_id
);
1310 if (getenv("R300_NO_TCL"))
1311 screen
->chip_flags
&= ~RADEON_CHIPSET_TCL
;
1313 if (screen
->chip_family
<= CHIP_FAMILY_RS200
)
1314 screen
->chip_flags
|= RADEON_CLASS_R100
;
1315 else if (screen
->chip_family
<= CHIP_FAMILY_RV280
)
1316 screen
->chip_flags
|= RADEON_CLASS_R200
;
1317 else if (screen
->chip_family
<= CHIP_FAMILY_RV570
)
1318 screen
->chip_flags
|= RADEON_CLASS_R300
;
1320 screen
->chip_flags
|= RADEON_CLASS_R600
;
1322 if (IS_R300_CLASS(screen
)) {
1323 ret
= radeonGetParam(sPriv
, RADEON_PARAM_NUM_GB_PIPES
, &temp
);
1325 fprintf(stderr
, "Unable to get num_pipes, need newer drm\n");
1326 switch (screen
->chip_family
) {
1327 case CHIP_FAMILY_R300
:
1328 case CHIP_FAMILY_R350
:
1329 screen
->num_gb_pipes
= 2;
1331 case CHIP_FAMILY_R420
:
1332 case CHIP_FAMILY_R520
:
1333 case CHIP_FAMILY_R580
:
1334 case CHIP_FAMILY_RV560
:
1335 case CHIP_FAMILY_RV570
:
1336 screen
->num_gb_pipes
= 4;
1338 case CHIP_FAMILY_RV350
:
1339 case CHIP_FAMILY_RV515
:
1340 case CHIP_FAMILY_RV530
:
1341 case CHIP_FAMILY_RV410
:
1343 screen
->num_gb_pipes
= 1;
1347 screen
->num_gb_pipes
= temp
;
1350 /* pipe overrides */
1351 switch (device_id
) {
1352 case PCI_CHIP_R300_AD
: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1353 case PCI_CHIP_RV410_5E4C
: /* RV410 SE only have 1 quadpipe */
1354 case PCI_CHIP_RV410_5E4F
: /* RV410 SE only have 1 quadpipe */
1355 screen
->num_gb_pipes
= 1;
1361 ret
= radeonGetParam(sPriv
, RADEON_PARAM_NUM_Z_PIPES
, &temp
);
1363 screen
->num_z_pipes
= 2;
1365 screen
->num_z_pipes
= temp
;
1370 screen
->extensions
[i
++] = &driCopySubBufferExtension
.base
;
1371 screen
->extensions
[i
++] = &driFrameTrackingExtension
.base
;
1372 screen
->extensions
[i
++] = &driReadDrawableExtension
;
1374 if ( screen
->irq
!= 0 ) {
1375 screen
->extensions
[i
++] = &driSwapControlExtension
.base
;
1376 screen
->extensions
[i
++] = &driMediaStreamCounterExtension
.base
;
1380 screen
->extensions
[i
++] = &radeonTexBufferExtension
.base
;
1383 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1384 if (IS_R200_CLASS(screen
))
1385 screen
->extensions
[i
++] = &r200AllocateExtension
.base
;
1387 screen
->extensions
[i
++] = &r200TexBufferExtension
.base
;
1390 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1391 screen
->extensions
[i
++] = &r300TexBufferExtension
.base
;
1394 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
1395 screen
->extensions
[i
++] = &r600TexBufferExtension
.base
;
1398 screen
->extensions
[i
++] = NULL
;
1399 sPriv
->extensions
= screen
->extensions
;
1401 screen
->driScreen
= sPriv
;
1402 screen
->bom
= radeon_bo_manager_gem_ctor(sPriv
->fd
);
1403 if (screen
->bom
== NULL
) {
1410 /* Destroy the device specific screen private data struct.
1413 radeonDestroyScreen( __DRIscreenPrivate
*sPriv
)
1415 radeonScreenPtr screen
= (radeonScreenPtr
)sPriv
->private;
1420 if (screen
->kernel_mm
) {
1421 #ifdef RADEON_BO_TRACK
1422 radeon_tracker_print(&screen
->bom
->tracker
, stderr
);
1424 radeon_bo_manager_gem_dtor(screen
->bom
);
1426 radeon_bo_manager_legacy_dtor(screen
->bom
);
1428 if ( screen
->gartTextures
.map
) {
1429 drmUnmap( screen
->gartTextures
.map
, screen
->gartTextures
.size
);
1431 drmUnmapBufs( screen
->buffers
);
1432 drmUnmap( screen
->status
.map
, screen
->status
.size
);
1433 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
1436 /* free all option information */
1437 driDestroyOptionInfo (&screen
->optionCache
);
1440 sPriv
->private = NULL
;
1444 /* Initialize the driver specific screen private data.
1447 radeonInitDriver( __DRIscreenPrivate
*sPriv
)
1449 if (sPriv
->dri2
.enabled
) {
1450 sPriv
->private = (void *) radeonCreateScreen2( sPriv
);
1452 sPriv
->private = (void *) radeonCreateScreen( sPriv
);
1454 if ( !sPriv
->private ) {
1455 radeonDestroyScreen( sPriv
);
1465 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1467 * \todo This function (and its interface) will need to be updated to support
1471 radeonCreateBuffer( __DRIscreenPrivate
*driScrnPriv
,
1472 __DRIdrawablePrivate
*driDrawPriv
,
1473 const __GLcontextModes
*mesaVis
,
1474 GLboolean isPixmap
)
1476 radeonScreenPtr screen
= (radeonScreenPtr
) driScrnPriv
->private;
1478 const GLboolean swDepth
= GL_FALSE
;
1479 const GLboolean swAlpha
= GL_FALSE
;
1480 const GLboolean swAccum
= mesaVis
->accumRedBits
> 0;
1481 const GLboolean swStencil
= mesaVis
->stencilBits
> 0 &&
1482 mesaVis
->depthBits
!= 24;
1484 struct radeon_framebuffer
*rfb
;
1487 return GL_FALSE
; /* not implemented */
1489 rfb
= CALLOC_STRUCT(radeon_framebuffer
);
1493 _mesa_initialize_framebuffer(&rfb
->base
, mesaVis
);
1495 if (mesaVis
->redBits
== 5)
1496 rgbFormat
= GL_RGB5
;
1497 else if (mesaVis
->alphaBits
== 0)
1498 rgbFormat
= GL_RGB8
;
1500 rgbFormat
= GL_RGBA8
;
1502 /* front color renderbuffer */
1503 rfb
->color_rb
[0] = radeon_create_renderbuffer(rgbFormat
, driDrawPriv
);
1504 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_FRONT_LEFT
, &rfb
->color_rb
[0]->base
);
1505 rfb
->color_rb
[0]->has_surface
= 1;
1507 /* back color renderbuffer */
1508 if (mesaVis
->doubleBufferMode
) {
1509 rfb
->color_rb
[1] = radeon_create_renderbuffer(rgbFormat
, driDrawPriv
);
1510 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_BACK_LEFT
, &rfb
->color_rb
[1]->base
);
1511 rfb
->color_rb
[1]->has_surface
= 1;
1514 if (mesaVis
->depthBits
== 24) {
1515 if (mesaVis
->stencilBits
== 8) {
1516 struct radeon_renderbuffer
*depthStencilRb
= radeon_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT
, driDrawPriv
);
1517 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_DEPTH
, &depthStencilRb
->base
);
1518 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_STENCIL
, &depthStencilRb
->base
);
1519 depthStencilRb
->has_surface
= screen
->depthHasSurface
;
1521 /* depth renderbuffer */
1522 struct radeon_renderbuffer
*depth
= radeon_create_renderbuffer(GL_DEPTH_COMPONENT24
, driDrawPriv
);
1523 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_DEPTH
, &depth
->base
);
1524 depth
->has_surface
= screen
->depthHasSurface
;
1526 } else if (mesaVis
->depthBits
== 16) {
1527 /* just 16-bit depth buffer, no hw stencil */
1528 struct radeon_renderbuffer
*depth
= radeon_create_renderbuffer(GL_DEPTH_COMPONENT16
, driDrawPriv
);
1529 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_DEPTH
, &depth
->base
);
1530 depth
->has_surface
= screen
->depthHasSurface
;
1533 _mesa_add_soft_renderbuffers(&rfb
->base
,
1534 GL_FALSE
, /* color */
1539 GL_FALSE
/* aux */);
1540 driDrawPriv
->driverPrivate
= (void *) rfb
;
1542 return (driDrawPriv
->driverPrivate
!= NULL
);
1546 static void radeon_cleanup_renderbuffers(struct radeon_framebuffer
*rfb
)
1548 struct radeon_renderbuffer
*rb
;
1550 rb
= rfb
->color_rb
[0];
1552 radeon_bo_unref(rb
->bo
);
1555 rb
= rfb
->color_rb
[1];
1557 radeon_bo_unref(rb
->bo
);
1560 rb
= radeon_get_renderbuffer(&rfb
->base
, BUFFER_DEPTH
);
1562 radeon_bo_unref(rb
->bo
);
1568 radeonDestroyBuffer(__DRIdrawablePrivate
*driDrawPriv
)
1570 struct radeon_framebuffer
*rfb
;
1574 rfb
= (void*)driDrawPriv
->driverPrivate
;
1577 radeon_cleanup_renderbuffers(rfb
);
1578 _mesa_reference_framebuffer((GLframebuffer
**)(&(driDrawPriv
->driverPrivate
)), NULL
);
1583 * This is the driver specific part of the createNewScreen entry point.
1585 * \todo maybe fold this into intelInitDriver
1587 * \return the __GLcontextModes supported by this driver
1589 static const __DRIconfig
**
1590 radeonInitScreen(__DRIscreenPrivate
*psp
)
1593 static const char *driver_name
= "Radeon";
1594 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1595 static const __DRIversion dri_expected
= { 4, 0, 0 };
1596 static const __DRIversion drm_expected
= { 1, 6, 0 };
1597 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1598 static const char *driver_name
= "R200";
1599 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1600 static const __DRIversion dri_expected
= { 4, 0, 0 };
1601 static const __DRIversion drm_expected
= { 1, 6, 0 };
1602 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1603 static const char *driver_name
= "R300";
1604 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1605 static const __DRIversion dri_expected
= { 4, 0, 0 };
1606 static const __DRIversion drm_expected
= { 1, 24, 0 };
1607 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
1608 static const char *driver_name
= "R600";
1609 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1610 static const __DRIversion dri_expected
= { 4, 0, 0 };
1611 static const __DRIversion drm_expected
= { 1, 24, 0 };
1613 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
) psp
->pDevPriv
;
1615 if ( ! driCheckDriDdxDrmVersions3( driver_name
,
1616 &psp
->dri_version
, & dri_expected
,
1617 &psp
->ddx_version
, & ddx_expected
,
1618 &psp
->drm_version
, & drm_expected
) ) {
1622 /* Calling driInitExtensions here, with a NULL context pointer,
1623 * does not actually enable the extensions. It just makes sure
1624 * that all the dispatch offsets for all the extensions that
1625 * *might* be enables are known. This is needed because the
1626 * dispatch offsets need to be known when _mesa_context_create
1627 * is called, but we can't enable the extensions until we have a
1630 * Hello chicken. Hello egg. How are you two today?
1632 driInitExtensions( NULL
, card_extensions
, GL_FALSE
);
1633 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1634 driInitExtensions( NULL
, blend_extensions
, GL_FALSE
);
1635 driInitSingleExtension( NULL
, ARB_vp_extension
);
1636 driInitSingleExtension( NULL
, NV_vp_extension
);
1637 driInitSingleExtension( NULL
, ATI_fs_extension
);
1638 driInitExtensions( NULL
, point_extensions
, GL_FALSE
);
1639 #elif (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600))
1640 driInitSingleExtension( NULL
, gl_20_extension
);
1643 if (!radeonInitDriver(psp
))
1646 /* for now fill in all modes */
1647 return radeonFillInModes( psp
,
1649 (dri_priv
->bpp
== 16) ? 16 : 24,
1650 (dri_priv
->bpp
== 16) ? 0 : 8, 1);
1652 #define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
1655 * This is the driver specific part of the createNewScreen entry point.
1656 * Called when using DRI2.
1658 * \return the __GLcontextModes supported by this driver
1661 __DRIconfig
**radeonInitScreen2(__DRIscreenPrivate
*psp
)
1663 GLenum fb_format
[3];
1665 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
1666 * support pageflipping at all.
1668 static const GLenum back_buffer_modes
[] = {
1669 GLX_NONE
, GLX_SWAP_UNDEFINED_OML
, /*, GLX_SWAP_COPY_OML*/
1671 uint8_t depth_bits
[4], stencil_bits
[4], msaa_samples_array
[1];
1673 __DRIconfig
**configs
= NULL
;
1675 /* Calling driInitExtensions here, with a NULL context pointer,
1676 * does not actually enable the extensions. It just makes sure
1677 * that all the dispatch offsets for all the extensions that
1678 * *might* be enables are known. This is needed because the
1679 * dispatch offsets need to be known when _mesa_context_create
1680 * is called, but we can't enable the extensions until we have a
1683 * Hello chicken. Hello egg. How are you two today?
1685 driInitExtensions( NULL
, card_extensions
, GL_FALSE
);
1686 driInitExtensions( NULL
, mm_extensions
, GL_FALSE
);
1687 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1688 driInitExtensions( NULL
, blend_extensions
, GL_FALSE
);
1689 driInitSingleExtension( NULL
, ARB_vp_extension
);
1690 driInitSingleExtension( NULL
, NV_vp_extension
);
1691 driInitSingleExtension( NULL
, ATI_fs_extension
);
1692 driInitExtensions( NULL
, point_extensions
, GL_FALSE
);
1693 #elif (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600))
1694 driInitSingleExtension( NULL
, gl_20_extension
);
1697 if (!radeonInitDriver(psp
)) {
1701 stencil_bits
[0] = 0;
1703 stencil_bits
[1] = 0;
1705 stencil_bits
[2] = 0;
1707 stencil_bits
[3] = 8;
1709 msaa_samples_array
[0] = 0;
1711 fb_format
[0] = GL_RGB
;
1712 fb_type
[0] = GL_UNSIGNED_SHORT_5_6_5
;
1714 fb_format
[1] = GL_BGR
;
1715 fb_type
[1] = GL_UNSIGNED_INT_8_8_8_8_REV
;
1717 fb_format
[2] = GL_BGRA
;
1718 fb_type
[2] = GL_UNSIGNED_INT_8_8_8_8_REV
;
1720 for (color
= 0; color
< ARRAY_SIZE(fb_format
); color
++) {
1721 __DRIconfig
**new_configs
;
1723 new_configs
= driCreateConfigs(fb_format
[color
], fb_type
[color
],
1726 ARRAY_SIZE(depth_bits
),
1728 ARRAY_SIZE(back_buffer_modes
),
1730 ARRAY_SIZE(msaa_samples_array
));
1731 if (configs
== NULL
)
1732 configs
= new_configs
;
1734 configs
= driConcatConfigs(configs
, new_configs
);
1737 if (configs
== NULL
) {
1738 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1743 return (const __DRIconfig
**)configs
;
1747 * Get information about previous buffer swaps.
1750 getSwapInfo( __DRIdrawablePrivate
*dPriv
, __DRIswapInfo
* sInfo
)
1752 struct radeon_framebuffer
*rfb
;
1754 if ( (dPriv
== NULL
) || (dPriv
->driContextPriv
== NULL
)
1755 || (dPriv
->driContextPriv
->driverPrivate
== NULL
)
1756 || (sInfo
== NULL
) ) {
1760 rfb
= dPriv
->driverPrivate
;
1761 sInfo
->swap_count
= rfb
->swap_count
;
1762 sInfo
->swap_ust
= rfb
->swap_ust
;
1763 sInfo
->swap_missed_count
= rfb
->swap_missed_count
;
1765 sInfo
->swap_missed_usage
= (sInfo
->swap_missed_count
!= 0)
1766 ? driCalculateSwapUsage( dPriv
, 0, rfb
->swap_missed_ust
)
1772 const struct __DriverAPIRec driDriverAPI
= {
1773 .InitScreen
= radeonInitScreen
,
1774 .DestroyScreen
= radeonDestroyScreen
,
1775 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1776 .CreateContext
= r200CreateContext
,
1777 .DestroyContext
= r200DestroyContext
,
1778 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
1779 .CreateContext
= r600CreateContext
,
1780 .DestroyContext
= radeonDestroyContext
,
1781 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1782 .CreateContext
= r300CreateContext
,
1783 .DestroyContext
= radeonDestroyContext
,
1785 .CreateContext
= r100CreateContext
,
1786 .DestroyContext
= radeonDestroyContext
,
1788 .CreateBuffer
= radeonCreateBuffer
,
1789 .DestroyBuffer
= radeonDestroyBuffer
,
1790 .SwapBuffers
= radeonSwapBuffers
,
1791 .MakeCurrent
= radeonMakeCurrent
,
1792 .UnbindContext
= radeonUnbindContext
,
1793 .GetSwapInfo
= getSwapInfo
,
1794 .GetDrawableMSC
= driDrawableGetMSC32
,
1795 .WaitForMSC
= driWaitForMSC32
,
1797 .SwapBuffersMSC
= NULL
,
1798 .CopySubBuffer
= radeonCopySubBuffer
,
1800 .InitScreen2
= radeonInitScreen2
,