1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
38 #include "main/glheader.h"
39 #include "main/imports.h"
40 #include "main/mtypes.h"
41 #include "main/framebuffer.h"
42 #include "main/renderbuffer.h"
44 #define STANDALONE_MMIO
45 #include "radeon_chipset.h"
46 #include "radeon_macros.h"
47 #include "radeon_screen.h"
49 #include "radeon_context.h"
50 #include "radeon_span.h"
51 #include "radeon_tex.h"
52 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
53 #include "r200_context.h"
54 #include "r200_ioctl.h"
55 #include "r200_span.h"
57 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
58 #include "r300_context.h"
59 #include "r300_fragprog.h"
61 #include "radeon_span.h"
66 #include "drirenderbuffer.h"
68 #include "GL/internal/dri_interface.h"
70 /* Radeon configuration
74 #if !RADEON_COMMON /* R100 */
75 PUBLIC
const char __driConfigOptions
[] =
77 DRI_CONF_SECTION_PERFORMANCE
78 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
79 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
80 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
81 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
82 DRI_CONF_HYPERZ(false)
84 DRI_CONF_SECTION_QUALITY
85 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
86 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
87 DRI_CONF_NO_NEG_LOD_BIAS(false)
88 DRI_CONF_FORCE_S3TC_ENABLE(false)
89 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
90 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
91 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
92 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
94 DRI_CONF_SECTION_DEBUG
95 DRI_CONF_NO_RAST(false)
98 static const GLuint __driNConfigOptions
= 14;
100 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
102 PUBLIC
const char __driConfigOptions
[] =
104 DRI_CONF_SECTION_PERFORMANCE
105 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
106 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
107 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
108 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
109 DRI_CONF_HYPERZ(false)
111 DRI_CONF_SECTION_QUALITY
112 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
113 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
114 DRI_CONF_NO_NEG_LOD_BIAS(false)
115 DRI_CONF_FORCE_S3TC_ENABLE(false)
116 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
117 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
118 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
119 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
120 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
122 DRI_CONF_SECTION_DEBUG
123 DRI_CONF_NO_RAST(false)
125 DRI_CONF_SECTION_SOFTWARE
126 DRI_CONF_NV_VERTEX_PROGRAM(false)
129 static const GLuint __driNConfigOptions
= 16;
131 extern const struct dri_extension blend_extensions
[];
132 extern const struct dri_extension ARB_vp_extension
[];
133 extern const struct dri_extension NV_vp_extension
[];
134 extern const struct dri_extension ATI_fs_extension
[];
135 extern const struct dri_extension point_extensions
[];
137 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
139 /* TODO: integrate these into xmlpool.h! */
140 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
141 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
142 DRI_CONF_DESC(en,"Number of texture image units") \
143 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
146 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
147 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
148 DRI_CONF_DESC(en,"Number of texture coordinate units") \
149 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
152 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
153 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
154 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
155 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
158 #define DRI_CONF_DISABLE_S3TC(def) \
159 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
160 DRI_CONF_DESC(en,"Disable S3TC compression") \
163 #define DRI_CONF_DISABLE_FALLBACK(def) \
164 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
165 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
168 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
169 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
170 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
173 #define DRI_CONF_FP_OPTIMIZATION(def) \
174 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
175 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
176 DRI_CONF_ENUM(0,"Optimize for Speed") \
177 DRI_CONF_ENUM(1,"Optimize for Quality") \
181 PUBLIC
const char __driConfigOptions
[] =
183 DRI_CONF_SECTION_PERFORMANCE
184 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
185 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
186 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
187 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
188 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
189 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
190 DRI_CONF_DISABLE_FALLBACK(true)
191 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
193 DRI_CONF_SECTION_QUALITY
194 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
195 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
196 DRI_CONF_FORCE_S3TC_ENABLE(false)
197 DRI_CONF_DISABLE_S3TC(false)
198 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
199 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
200 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
201 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED
)
203 DRI_CONF_SECTION_DEBUG
204 DRI_CONF_NO_RAST(false)
207 static const GLuint __driNConfigOptions
= 17;
210 int RADEON_DEBUG
= 0;
212 static const struct dri_debug_control debug_control
[] = {
213 {"fall", DEBUG_FALLBACKS
},
214 {"tex", DEBUG_TEXTURE
},
215 {"ioctl", DEBUG_IOCTL
},
216 {"prim", DEBUG_PRIMS
},
217 {"vert", DEBUG_VERTS
},
218 {"state", DEBUG_STATE
},
219 {"code", DEBUG_CODEGEN
},
220 {"vfmt", DEBUG_VFMT
},
221 {"vtxf", DEBUG_VFMT
},
222 {"verb", DEBUG_VERBOSE
},
225 {"san", DEBUG_SANITY
},
226 {"sync", DEBUG_SYNC
},
227 {"pix", DEBUG_PIXEL
},
228 {"mem", DEBUG_MEMORY
},
229 {"allmsg", ~DEBUG_SYNC
}, /* avoid the term "sync" because the parser uses strstr */
232 #endif /* RADEON_DEBUG */
234 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
236 extern const struct dri_extension card_extensions
[];
238 static int getSwapInfo( __DRIdrawablePrivate
*dPriv
, __DRIswapInfo
* sInfo
);
241 radeonGetParam(int fd
, int param
, void *value
)
244 drm_radeon_getparam_t gp
;
249 ret
= drmCommandWriteRead( fd
, DRM_RADEON_GETPARAM
, &gp
, sizeof(gp
));
253 static const __DRIconfig
**
254 radeonFillInModes( __DRIscreenPrivate
*psp
,
255 unsigned pixel_bits
, unsigned depth_bits
,
256 unsigned stencil_bits
, GLboolean have_back_buffer
)
258 __DRIconfig
**configs
;
260 unsigned depth_buffer_factor
;
261 unsigned back_buffer_factor
;
266 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
267 * enough to add support. Basically, if a context is created with an
268 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
269 * will never be used.
271 static const GLenum back_buffer_modes
[] = {
272 GLX_NONE
, GLX_SWAP_UNDEFINED_OML
/*, GLX_SWAP_COPY_OML */
275 uint8_t depth_bits_array
[2];
276 uint8_t stencil_bits_array
[2];
279 depth_bits_array
[0] = depth_bits
;
280 depth_bits_array
[1] = depth_bits
;
282 /* Just like with the accumulation buffer, always provide some modes
283 * with a stencil buffer. It will be a sw fallback, but some apps won't
286 stencil_bits_array
[0] = 0;
287 stencil_bits_array
[1] = (stencil_bits
== 0) ? 8 : stencil_bits
;
289 depth_buffer_factor
= ((depth_bits
!= 0) || (stencil_bits
!= 0)) ? 2 : 1;
290 back_buffer_factor
= (have_back_buffer
) ? 2 : 1;
292 if ( pixel_bits
== 16 ) {
294 fb_type
= GL_UNSIGNED_SHORT_5_6_5
;
298 fb_type
= GL_UNSIGNED_INT_8_8_8_8_REV
;
301 configs
= driCreateConfigs(fb_format
, fb_type
,
302 depth_bits_array
, stencil_bits_array
,
304 back_buffer_modes
, back_buffer_factor
);
305 if (configs
== NULL
) {
306 fprintf( stderr
, "[%s:%u] Error creating FBConfig!\n",
307 __func__
, __LINE__
);
311 /* Mark the visual as slow if there are "fake" stencil bits.
313 for (i
= 0; configs
[i
]; i
++) {
314 m
= &configs
[i
]->modes
;
315 if ((m
->stencilBits
!= 0) && (m
->stencilBits
!= stencil_bits
)) {
316 m
->visualRating
= GLX_SLOW_CONFIG
;
320 return (const __DRIconfig
**) configs
;
324 static const __DRItexOffsetExtension radeonTexOffsetExtension
= {
325 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
330 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
331 static const __DRIallocateExtension r200AllocateExtension
= {
332 { __DRI_ALLOCATE
, __DRI_ALLOCATE_VERSION
},
333 r200AllocateMemoryMESA
,
335 r200GetMemoryOffsetMESA
338 static const __DRItexOffsetExtension r200texOffsetExtension
= {
339 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
344 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
345 static const __DRItexOffsetExtension r300texOffsetExtension
= {
346 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
351 /* Create the device specific screen private data struct.
353 static radeonScreenPtr
354 radeonCreateScreen( __DRIscreenPrivate
*sPriv
)
356 radeonScreenPtr screen
;
357 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
)sPriv
->pDevPriv
;
358 unsigned char *RADEONMMIO
;
363 if (sPriv
->devPrivSize
!= sizeof(RADEONDRIRec
)) {
364 fprintf(stderr
,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
368 /* Allocate the private area */
369 screen
= (radeonScreenPtr
) CALLOC( sizeof(*screen
) );
371 __driUtilMessage("%s: Could not allocate memory for screen structure",
376 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
377 RADEON_DEBUG
= driParseDebugString(getenv("RADEON_DEBUG"), debug_control
);
380 /* parse information in __driConfigOptions */
381 driParseOptionInfo (&screen
->optionCache
,
382 __driConfigOptions
, __driNConfigOptions
);
384 /* This is first since which regions we map depends on whether or
385 * not we are using a PCI card.
387 screen
->card_type
= (dri_priv
->IsPCI
? RADEON_CARD_PCI
: RADEON_CARD_AGP
);
390 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_GART_BUFFER_OFFSET
,
391 &screen
->gart_buffer_offset
);
395 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret
);
399 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_GART_BASE
,
403 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret
);
407 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_IRQ_NR
,
411 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret
);
414 screen
->drmSupportsCubeMapsR200
= (sPriv
->drm_version
.minor
>= 7);
415 screen
->drmSupportsBlendColor
= (sPriv
->drm_version
.minor
>= 11);
416 screen
->drmSupportsTriPerf
= (sPriv
->drm_version
.minor
>= 16);
417 screen
->drmSupportsFragShader
= (sPriv
->drm_version
.minor
>= 18);
418 screen
->drmSupportsPointSprites
= (sPriv
->drm_version
.minor
>= 13);
419 screen
->drmSupportsCubeMapsR100
= (sPriv
->drm_version
.minor
>= 15);
420 screen
->drmSupportsVertexProgram
= (sPriv
->drm_version
.minor
>= 25);
423 screen
->mmio
.handle
= dri_priv
->registerHandle
;
424 screen
->mmio
.size
= dri_priv
->registerSize
;
425 if ( drmMap( sPriv
->fd
,
428 &screen
->mmio
.map
) ) {
430 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__
);
434 RADEONMMIO
= screen
->mmio
.map
;
436 screen
->status
.handle
= dri_priv
->statusHandle
;
437 screen
->status
.size
= dri_priv
->statusSize
;
438 if ( drmMap( sPriv
->fd
,
439 screen
->status
.handle
,
441 &screen
->status
.map
) ) {
442 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
444 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__
);
447 screen
->scratch
= (__volatile__
uint32_t *)
448 ((GLubyte
*)screen
->status
.map
+ RADEON_SCRATCH_REG_OFFSET
);
450 screen
->buffers
= drmMapBufs( sPriv
->fd
);
451 if ( !screen
->buffers
) {
452 drmUnmap( screen
->status
.map
, screen
->status
.size
);
453 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
455 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__
);
459 if ( dri_priv
->gartTexHandle
&& dri_priv
->gartTexMapSize
) {
460 screen
->gartTextures
.handle
= dri_priv
->gartTexHandle
;
461 screen
->gartTextures
.size
= dri_priv
->gartTexMapSize
;
462 if ( drmMap( sPriv
->fd
,
463 screen
->gartTextures
.handle
,
464 screen
->gartTextures
.size
,
465 (drmAddressPtr
)&screen
->gartTextures
.map
) ) {
466 drmUnmapBufs( screen
->buffers
);
467 drmUnmap( screen
->status
.map
, screen
->status
.size
);
468 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
470 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__
);
474 screen
->gart_texture_offset
= dri_priv
->gartTexOffset
+ screen
->gart_base
;
477 screen
->chip_flags
= 0;
478 /* XXX: add more chipsets */
479 switch ( dri_priv
->deviceID
) {
480 case PCI_CHIP_RADEON_LY
:
481 case PCI_CHIP_RADEON_LZ
:
482 case PCI_CHIP_RADEON_QY
:
483 case PCI_CHIP_RADEON_QZ
:
484 case PCI_CHIP_RN50_515E
:
485 case PCI_CHIP_RN50_5969
:
486 screen
->chip_family
= CHIP_FAMILY_RV100
;
489 case PCI_CHIP_RS100_4136
:
490 case PCI_CHIP_RS100_4336
:
491 screen
->chip_family
= CHIP_FAMILY_RS100
;
494 case PCI_CHIP_RS200_4137
:
495 case PCI_CHIP_RS200_4337
:
496 case PCI_CHIP_RS250_4237
:
497 case PCI_CHIP_RS250_4437
:
498 screen
->chip_family
= CHIP_FAMILY_RS200
;
501 case PCI_CHIP_RADEON_QD
:
502 case PCI_CHIP_RADEON_QE
:
503 case PCI_CHIP_RADEON_QF
:
504 case PCI_CHIP_RADEON_QG
:
505 /* all original radeons (7200) presumably have a stencil op bug */
506 screen
->chip_family
= CHIP_FAMILY_R100
;
507 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_BROKEN_STENCIL
;
510 case PCI_CHIP_RV200_QW
:
511 case PCI_CHIP_RV200_QX
:
512 case PCI_CHIP_RADEON_LW
:
513 case PCI_CHIP_RADEON_LX
:
514 screen
->chip_family
= CHIP_FAMILY_RV200
;
515 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
518 case PCI_CHIP_R200_BB
:
519 case PCI_CHIP_R200_BC
:
520 case PCI_CHIP_R200_QH
:
521 case PCI_CHIP_R200_QL
:
522 case PCI_CHIP_R200_QM
:
523 screen
->chip_family
= CHIP_FAMILY_R200
;
524 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
527 case PCI_CHIP_RV250_If
:
528 case PCI_CHIP_RV250_Ig
:
529 case PCI_CHIP_RV250_Ld
:
530 case PCI_CHIP_RV250_Lf
:
531 case PCI_CHIP_RV250_Lg
:
532 screen
->chip_family
= CHIP_FAMILY_RV250
;
533 screen
->chip_flags
= R200_CHIPSET_YCBCR_BROKEN
| RADEON_CHIPSET_TCL
;
536 case PCI_CHIP_RV280_5960
:
537 case PCI_CHIP_RV280_5961
:
538 case PCI_CHIP_RV280_5962
:
539 case PCI_CHIP_RV280_5964
:
540 case PCI_CHIP_RV280_5965
:
541 case PCI_CHIP_RV280_5C61
:
542 case PCI_CHIP_RV280_5C63
:
543 screen
->chip_family
= CHIP_FAMILY_RV280
;
544 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
547 case PCI_CHIP_RS300_5834
:
548 case PCI_CHIP_RS300_5835
:
549 case PCI_CHIP_RS350_7834
:
550 case PCI_CHIP_RS350_7835
:
551 screen
->chip_family
= CHIP_FAMILY_RS300
;
554 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
555 case PCI_CHIP_R300_AD
:
556 screen
->chip_family
= CHIP_FAMILY_RV350
;
557 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
559 case PCI_CHIP_R300_AE
:
560 case PCI_CHIP_R300_AF
:
561 case PCI_CHIP_R300_AG
:
562 case PCI_CHIP_R300_ND
:
563 case PCI_CHIP_R300_NE
:
564 case PCI_CHIP_R300_NF
:
565 case PCI_CHIP_R300_NG
:
566 screen
->chip_family
= CHIP_FAMILY_R300
;
567 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
570 case PCI_CHIP_RV350_AP
:
571 case PCI_CHIP_RV350_AQ
:
572 case PCI_CHIP_RV350_AR
:
573 case PCI_CHIP_RV350_AS
:
574 case PCI_CHIP_RV350_AT
:
575 case PCI_CHIP_RV350_AV
:
576 case PCI_CHIP_RV350_AU
:
577 case PCI_CHIP_RV350_NP
:
578 case PCI_CHIP_RV350_NQ
:
579 case PCI_CHIP_RV350_NR
:
580 case PCI_CHIP_RV350_NS
:
581 case PCI_CHIP_RV350_NT
:
582 case PCI_CHIP_RV350_NV
:
583 screen
->chip_family
= CHIP_FAMILY_RV350
;
584 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
587 case PCI_CHIP_R350_AH
:
588 case PCI_CHIP_R350_AI
:
589 case PCI_CHIP_R350_AJ
:
590 case PCI_CHIP_R350_AK
:
591 case PCI_CHIP_R350_NH
:
592 case PCI_CHIP_R350_NI
:
593 case PCI_CHIP_R360_NJ
:
594 case PCI_CHIP_R350_NK
:
595 screen
->chip_family
= CHIP_FAMILY_R350
;
596 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
599 case PCI_CHIP_RV370_5460
:
600 case PCI_CHIP_RV370_5462
:
601 case PCI_CHIP_RV370_5464
:
602 case PCI_CHIP_RV370_5B60
:
603 case PCI_CHIP_RV370_5B62
:
604 case PCI_CHIP_RV370_5B63
:
605 case PCI_CHIP_RV370_5B64
:
606 case PCI_CHIP_RV370_5B65
:
607 case PCI_CHIP_RV380_3150
:
608 case PCI_CHIP_RV380_3152
:
609 case PCI_CHIP_RV380_3154
:
610 case PCI_CHIP_RV380_3E50
:
611 case PCI_CHIP_RV380_3E54
:
612 screen
->chip_family
= CHIP_FAMILY_RV380
;
613 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
616 case PCI_CHIP_R420_JN
:
617 case PCI_CHIP_R420_JH
:
618 case PCI_CHIP_R420_JI
:
619 case PCI_CHIP_R420_JJ
:
620 case PCI_CHIP_R420_JK
:
621 case PCI_CHIP_R420_JL
:
622 case PCI_CHIP_R420_JM
:
623 case PCI_CHIP_R420_JO
:
624 case PCI_CHIP_R420_JP
:
625 case PCI_CHIP_R420_JT
:
626 case PCI_CHIP_R481_4B49
:
627 case PCI_CHIP_R481_4B4A
:
628 case PCI_CHIP_R481_4B4B
:
629 case PCI_CHIP_R481_4B4C
:
630 case PCI_CHIP_R423_UH
:
631 case PCI_CHIP_R423_UI
:
632 case PCI_CHIP_R423_UJ
:
633 case PCI_CHIP_R423_UK
:
634 case PCI_CHIP_R430_554C
:
635 case PCI_CHIP_R430_554D
:
636 case PCI_CHIP_R430_554E
:
637 case PCI_CHIP_R430_554F
:
638 case PCI_CHIP_R423_5550
:
639 case PCI_CHIP_R423_UQ
:
640 case PCI_CHIP_R423_UR
:
641 case PCI_CHIP_R423_UT
:
642 case PCI_CHIP_R430_5D48
:
643 case PCI_CHIP_R430_5D49
:
644 case PCI_CHIP_R430_5D4A
:
645 case PCI_CHIP_R480_5D4C
:
646 case PCI_CHIP_R480_5D4D
:
647 case PCI_CHIP_R480_5D4E
:
648 case PCI_CHIP_R480_5D4F
:
649 case PCI_CHIP_R480_5D50
:
650 case PCI_CHIP_R480_5D52
:
651 case PCI_CHIP_R423_5D57
:
652 screen
->chip_family
= CHIP_FAMILY_R420
;
653 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
656 case PCI_CHIP_RV410_5E4C
:
657 case PCI_CHIP_RV410_5E4F
:
658 case PCI_CHIP_RV410_564A
:
659 case PCI_CHIP_RV410_564B
:
660 case PCI_CHIP_RV410_564F
:
661 case PCI_CHIP_RV410_5652
:
662 case PCI_CHIP_RV410_5653
:
663 case PCI_CHIP_RV410_5657
:
664 case PCI_CHIP_RV410_5E48
:
665 case PCI_CHIP_RV410_5E4A
:
666 case PCI_CHIP_RV410_5E4B
:
667 case PCI_CHIP_RV410_5E4D
:
668 screen
->chip_family
= CHIP_FAMILY_RV410
;
669 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
672 case PCI_CHIP_RS480_5954
:
673 case PCI_CHIP_RS480_5955
:
674 case PCI_CHIP_RS482_5974
:
675 case PCI_CHIP_RS482_5975
:
676 case PCI_CHIP_RS400_5A41
:
677 case PCI_CHIP_RS400_5A42
:
678 case PCI_CHIP_RC410_5A61
:
679 case PCI_CHIP_RC410_5A62
:
680 screen
->chip_family
= CHIP_FAMILY_RS400
;
683 case PCI_CHIP_RS690_791E
:
684 case PCI_CHIP_RS690_791F
:
685 screen
->chip_family
= CHIP_FAMILY_RS690
;
687 case PCI_CHIP_RS740_796C
:
688 case PCI_CHIP_RS740_796D
:
689 case PCI_CHIP_RS740_796E
:
690 case PCI_CHIP_RS740_796F
:
691 screen
->chip_family
= CHIP_FAMILY_RS740
;
694 case PCI_CHIP_R520_7100
:
695 case PCI_CHIP_R520_7101
:
696 case PCI_CHIP_R520_7102
:
697 case PCI_CHIP_R520_7103
:
698 case PCI_CHIP_R520_7104
:
699 case PCI_CHIP_R520_7105
:
700 case PCI_CHIP_R520_7106
:
701 case PCI_CHIP_R520_7108
:
702 case PCI_CHIP_R520_7109
:
703 case PCI_CHIP_R520_710A
:
704 case PCI_CHIP_R520_710B
:
705 case PCI_CHIP_R520_710C
:
706 case PCI_CHIP_R520_710E
:
707 case PCI_CHIP_R520_710F
:
708 screen
->chip_family
= CHIP_FAMILY_R520
;
709 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
712 case PCI_CHIP_RV515_7140
:
713 case PCI_CHIP_RV515_7141
:
714 case PCI_CHIP_RV515_7142
:
715 case PCI_CHIP_RV515_7143
:
716 case PCI_CHIP_RV515_7144
:
717 case PCI_CHIP_RV515_7145
:
718 case PCI_CHIP_RV515_7146
:
719 case PCI_CHIP_RV515_7147
:
720 case PCI_CHIP_RV515_7149
:
721 case PCI_CHIP_RV515_714A
:
722 case PCI_CHIP_RV515_714B
:
723 case PCI_CHIP_RV515_714C
:
724 case PCI_CHIP_RV515_714D
:
725 case PCI_CHIP_RV515_714E
:
726 case PCI_CHIP_RV515_714F
:
727 case PCI_CHIP_RV515_7151
:
728 case PCI_CHIP_RV515_7152
:
729 case PCI_CHIP_RV515_7153
:
730 case PCI_CHIP_RV515_715E
:
731 case PCI_CHIP_RV515_715F
:
732 case PCI_CHIP_RV515_7180
:
733 case PCI_CHIP_RV515_7181
:
734 case PCI_CHIP_RV515_7183
:
735 case PCI_CHIP_RV515_7186
:
736 case PCI_CHIP_RV515_7187
:
737 case PCI_CHIP_RV515_7188
:
738 case PCI_CHIP_RV515_718A
:
739 case PCI_CHIP_RV515_718B
:
740 case PCI_CHIP_RV515_718C
:
741 case PCI_CHIP_RV515_718D
:
742 case PCI_CHIP_RV515_718F
:
743 case PCI_CHIP_RV515_7193
:
744 case PCI_CHIP_RV515_7196
:
745 case PCI_CHIP_RV515_719B
:
746 case PCI_CHIP_RV515_719F
:
747 case PCI_CHIP_RV515_7200
:
748 case PCI_CHIP_RV515_7210
:
749 case PCI_CHIP_RV515_7211
:
750 screen
->chip_family
= CHIP_FAMILY_RV515
;
751 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
754 case PCI_CHIP_RV530_71C0
:
755 case PCI_CHIP_RV530_71C1
:
756 case PCI_CHIP_RV530_71C2
:
757 case PCI_CHIP_RV530_71C3
:
758 case PCI_CHIP_RV530_71C4
:
759 case PCI_CHIP_RV530_71C5
:
760 case PCI_CHIP_RV530_71C6
:
761 case PCI_CHIP_RV530_71C7
:
762 case PCI_CHIP_RV530_71CD
:
763 case PCI_CHIP_RV530_71CE
:
764 case PCI_CHIP_RV530_71D2
:
765 case PCI_CHIP_RV530_71D4
:
766 case PCI_CHIP_RV530_71D5
:
767 case PCI_CHIP_RV530_71D6
:
768 case PCI_CHIP_RV530_71DA
:
769 case PCI_CHIP_RV530_71DE
:
770 screen
->chip_family
= CHIP_FAMILY_RV530
;
771 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
774 case PCI_CHIP_R580_7240
:
775 case PCI_CHIP_R580_7243
:
776 case PCI_CHIP_R580_7244
:
777 case PCI_CHIP_R580_7245
:
778 case PCI_CHIP_R580_7246
:
779 case PCI_CHIP_R580_7247
:
780 case PCI_CHIP_R580_7248
:
781 case PCI_CHIP_R580_7249
:
782 case PCI_CHIP_R580_724A
:
783 case PCI_CHIP_R580_724B
:
784 case PCI_CHIP_R580_724C
:
785 case PCI_CHIP_R580_724D
:
786 case PCI_CHIP_R580_724E
:
787 case PCI_CHIP_R580_724F
:
788 case PCI_CHIP_R580_7284
:
789 screen
->chip_family
= CHIP_FAMILY_R580
;
790 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
793 case PCI_CHIP_RV570_7280
:
794 case PCI_CHIP_RV560_7281
:
795 case PCI_CHIP_RV560_7283
:
796 case PCI_CHIP_RV560_7287
:
797 case PCI_CHIP_RV570_7288
:
798 case PCI_CHIP_RV570_7289
:
799 case PCI_CHIP_RV570_728B
:
800 case PCI_CHIP_RV570_728C
:
801 case PCI_CHIP_RV560_7290
:
802 case PCI_CHIP_RV560_7291
:
803 case PCI_CHIP_RV560_7293
:
804 case PCI_CHIP_RV560_7297
:
805 screen
->chip_family
= CHIP_FAMILY_RV560
;
806 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
810 fprintf(stderr
, "unknown chip id 0x%x, can't guess.\n",
814 if ((screen
->chip_family
== CHIP_FAMILY_R350
|| screen
->chip_family
== CHIP_FAMILY_R300
) &&
815 sPriv
->ddx_version
.minor
< 2) {
816 fprintf(stderr
, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
820 if ((sPriv
->drm_version
.minor
< 29) && (screen
->chip_family
>= CHIP_FAMILY_RV515
)) {
821 fprintf(stderr
, "R500 support requires a newer drm.\n");
825 if (getenv("R300_NO_TCL"))
826 screen
->chip_flags
&= ~RADEON_CHIPSET_TCL
;
828 if (screen
->chip_family
<= CHIP_FAMILY_RS200
)
829 screen
->chip_flags
|= RADEON_CLASS_R100
;
830 else if (screen
->chip_family
<= CHIP_FAMILY_RV280
)
831 screen
->chip_flags
|= RADEON_CLASS_R200
;
833 screen
->chip_flags
|= RADEON_CLASS_R300
;
835 screen
->cpp
= dri_priv
->bpp
/ 8;
836 screen
->AGPMode
= dri_priv
->AGPMode
;
838 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_FB_LOCATION
,
841 if (screen
->chip_family
< CHIP_FAMILY_RS690
)
842 screen
->fbLocation
= ( INREG( RADEON_MC_FB_LOCATION
) & 0xffff) << 16;
845 fprintf(stderr
, "Unable to get fb location need newer drm\n");
849 screen
->fbLocation
= (temp
& 0xffff) << 16;
852 if (screen
->chip_family
>= CHIP_FAMILY_RV515
) {
853 ret
= radeonGetParam( sPriv
->fd
, RADEON_PARAM_NUM_GB_PIPES
,
856 fprintf(stderr
, "Unable to get num_pipes, need newer drm\n");
857 switch (screen
->chip_family
) {
858 case CHIP_FAMILY_R300
:
859 case CHIP_FAMILY_R350
:
860 screen
->num_gb_pipes
= 2;
862 case CHIP_FAMILY_R420
:
863 case CHIP_FAMILY_R520
:
864 case CHIP_FAMILY_R580
:
865 case CHIP_FAMILY_RV560
:
866 case CHIP_FAMILY_RV570
:
867 screen
->num_gb_pipes
= 4;
869 case CHIP_FAMILY_RV350
:
870 case CHIP_FAMILY_RV515
:
871 case CHIP_FAMILY_RV530
:
872 case CHIP_FAMILY_RV410
:
874 screen
->num_gb_pipes
= 1;
878 screen
->num_gb_pipes
= temp
;
882 if ( sPriv
->drm_version
.minor
>= 10 ) {
883 drm_radeon_setparam_t sp
;
885 sp
.param
= RADEON_SETPARAM_FB_LOCATION
;
886 sp
.value
= screen
->fbLocation
;
888 drmCommandWrite( sPriv
->fd
, DRM_RADEON_SETPARAM
,
892 screen
->frontOffset
= dri_priv
->frontOffset
;
893 screen
->frontPitch
= dri_priv
->frontPitch
;
894 screen
->backOffset
= dri_priv
->backOffset
;
895 screen
->backPitch
= dri_priv
->backPitch
;
896 screen
->depthOffset
= dri_priv
->depthOffset
;
897 screen
->depthPitch
= dri_priv
->depthPitch
;
899 /* Check if ddx has set up a surface reg to cover depth buffer */
900 screen
->depthHasSurface
= (sPriv
->ddx_version
.major
> 4) ||
901 /* these chips don't use tiled z without hyperz. So always pretend
902 we have set up a surface which will cause linear reads/writes */
903 ((screen
->chip_family
& RADEON_CLASS_R100
) &&
904 !(screen
->chip_flags
& RADEON_CHIPSET_TCL
));
906 if ( dri_priv
->textureSize
== 0 ) {
907 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = screen
->gart_texture_offset
;
908 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
909 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
910 dri_priv
->log2GARTTexGran
;
912 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureOffset
913 + screen
->fbLocation
;
914 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureSize
;
915 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
916 dri_priv
->log2TexGran
;
919 if ( !screen
->gartTextures
.map
|| dri_priv
->textureSize
== 0
920 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
921 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
- 1;
922 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = 0;
923 screen
->texSize
[RADEON_GART_TEX_HEAP
] = 0;
924 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] = 0;
926 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
;
927 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = screen
->gart_texture_offset
;
928 screen
->texSize
[RADEON_GART_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
929 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] =
930 dri_priv
->log2GARTTexGran
;
934 screen
->extensions
[i
++] = &driCopySubBufferExtension
.base
;
935 screen
->extensions
[i
++] = &driFrameTrackingExtension
.base
;
936 screen
->extensions
[i
++] = &driReadDrawableExtension
;
938 if ( screen
->irq
!= 0 ) {
939 screen
->extensions
[i
++] = &driSwapControlExtension
.base
;
940 screen
->extensions
[i
++] = &driMediaStreamCounterExtension
.base
;
944 screen
->extensions
[i
++] = &radeonTexOffsetExtension
.base
;
947 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
948 if (IS_R200_CLASS(screen
))
949 screen
->extensions
[i
++] = &r200AllocateExtension
.base
;
951 screen
->extensions
[i
++] = &r200texOffsetExtension
.base
;
954 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
955 screen
->extensions
[i
++] = &r300texOffsetExtension
.base
;
958 screen
->extensions
[i
++] = NULL
;
959 sPriv
->extensions
= screen
->extensions
;
961 screen
->driScreen
= sPriv
;
962 screen
->sarea_priv_offset
= dri_priv
->sarea_priv_offset
;
966 /* Destroy the device specific screen private data struct.
969 radeonDestroyScreen( __DRIscreenPrivate
*sPriv
)
971 radeonScreenPtr screen
= (radeonScreenPtr
)sPriv
->private;
976 if ( screen
->gartTextures
.map
) {
977 drmUnmap( screen
->gartTextures
.map
, screen
->gartTextures
.size
);
979 drmUnmapBufs( screen
->buffers
);
980 drmUnmap( screen
->status
.map
, screen
->status
.size
);
981 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
983 /* free all option information */
984 driDestroyOptionInfo (&screen
->optionCache
);
987 sPriv
->private = NULL
;
991 /* Initialize the driver specific screen private data.
994 radeonInitDriver( __DRIscreenPrivate
*sPriv
)
996 sPriv
->private = (void *) radeonCreateScreen( sPriv
);
997 if ( !sPriv
->private ) {
998 radeonDestroyScreen( sPriv
);
1007 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1009 * \todo This function (and its interface) will need to be updated to support
1013 radeonCreateBuffer( __DRIscreenPrivate
*driScrnPriv
,
1014 __DRIdrawablePrivate
*driDrawPriv
,
1015 const __GLcontextModes
*mesaVis
,
1016 GLboolean isPixmap
)
1018 radeonScreenPtr screen
= (radeonScreenPtr
) driScrnPriv
->private;
1021 return GL_FALSE
; /* not implemented */
1024 const GLboolean swDepth
= GL_FALSE
;
1025 const GLboolean swAlpha
= GL_FALSE
;
1026 const GLboolean swAccum
= mesaVis
->accumRedBits
> 0;
1027 const GLboolean swStencil
= mesaVis
->stencilBits
> 0 &&
1028 mesaVis
->depthBits
!= 24;
1029 struct gl_framebuffer
*fb
= _mesa_create_framebuffer(mesaVis
);
1031 /* front color renderbuffer */
1033 driRenderbuffer
*frontRb
1034 = driNewRenderbuffer(GL_RGBA
,
1035 driScrnPriv
->pFB
+ screen
->frontOffset
,
1037 screen
->frontOffset
, screen
->frontPitch
,
1039 radeonSetSpanFunctions(frontRb
, mesaVis
);
1040 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &frontRb
->Base
);
1043 /* back color renderbuffer */
1044 if (mesaVis
->doubleBufferMode
) {
1045 driRenderbuffer
*backRb
1046 = driNewRenderbuffer(GL_RGBA
,
1047 driScrnPriv
->pFB
+ screen
->backOffset
,
1049 screen
->backOffset
, screen
->backPitch
,
1051 radeonSetSpanFunctions(backRb
, mesaVis
);
1052 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &backRb
->Base
);
1055 /* depth renderbuffer */
1056 if (mesaVis
->depthBits
== 16) {
1057 driRenderbuffer
*depthRb
1058 = driNewRenderbuffer(GL_DEPTH_COMPONENT16
,
1059 driScrnPriv
->pFB
+ screen
->depthOffset
,
1061 screen
->depthOffset
, screen
->depthPitch
,
1063 radeonSetSpanFunctions(depthRb
, mesaVis
);
1064 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &depthRb
->Base
);
1065 depthRb
->depthHasSurface
= screen
->depthHasSurface
;
1067 else if (mesaVis
->depthBits
== 24) {
1068 driRenderbuffer
*depthRb
1069 = driNewRenderbuffer(GL_DEPTH_COMPONENT24
,
1070 driScrnPriv
->pFB
+ screen
->depthOffset
,
1072 screen
->depthOffset
, screen
->depthPitch
,
1074 radeonSetSpanFunctions(depthRb
, mesaVis
);
1075 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &depthRb
->Base
);
1076 depthRb
->depthHasSurface
= screen
->depthHasSurface
;
1079 /* stencil renderbuffer */
1080 if (mesaVis
->stencilBits
> 0 && !swStencil
) {
1081 driRenderbuffer
*stencilRb
1082 = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT
,
1083 driScrnPriv
->pFB
+ screen
->depthOffset
,
1085 screen
->depthOffset
, screen
->depthPitch
,
1087 radeonSetSpanFunctions(stencilRb
, mesaVis
);
1088 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &stencilRb
->Base
);
1089 stencilRb
->depthHasSurface
= screen
->depthHasSurface
;
1092 _mesa_add_soft_renderbuffers(fb
,
1093 GL_FALSE
, /* color */
1098 GL_FALSE
/* aux */);
1099 driDrawPriv
->driverPrivate
= (void *) fb
;
1101 return (driDrawPriv
->driverPrivate
!= NULL
);
1107 radeonDestroyBuffer(__DRIdrawablePrivate
*driDrawPriv
)
1109 _mesa_unreference_framebuffer((GLframebuffer
**)(&(driDrawPriv
->driverPrivate
)));
1112 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1114 * Choose the appropriate CreateContext function based on the chipset.
1115 * Eventually, all drivers will go through this process.
1117 static GLboolean
radeonCreateContext(const __GLcontextModes
* glVisual
,
1118 __DRIcontextPrivate
* driContextPriv
,
1119 void *sharedContextPriv
)
1121 __DRIscreenPrivate
*sPriv
= driContextPriv
->driScreenPriv
;
1122 radeonScreenPtr screen
= (radeonScreenPtr
) (sPriv
->private);
1124 if (IS_R300_CLASS(screen
))
1125 return r300CreateContext(glVisual
, driContextPriv
, sharedContextPriv
);
1130 * Choose the appropriate DestroyContext function based on the chipset.
1132 static void radeonDestroyContext(__DRIcontextPrivate
* driContextPriv
)
1134 radeonContextPtr radeon
= (radeonContextPtr
) driContextPriv
->driverPrivate
;
1136 if (IS_R300_CLASS(radeon
->radeonScreen
))
1137 return r300DestroyContext(driContextPriv
);
1144 * This is the driver specific part of the createNewScreen entry point.
1146 * \todo maybe fold this into intelInitDriver
1148 * \return the __GLcontextModes supported by this driver
1150 static const __DRIconfig
**
1151 radeonInitScreen(__DRIscreenPrivate
*psp
)
1154 static const char *driver_name
= "Radeon";
1155 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1156 static const __DRIversion dri_expected
= { 4, 0, 0 };
1157 static const __DRIversion drm_expected
= { 1, 6, 0 };
1158 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1159 static const char *driver_name
= "R200";
1160 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1161 static const __DRIversion dri_expected
= { 4, 0, 0 };
1162 static const __DRIversion drm_expected
= { 1, 6, 0 };
1163 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1164 static const char *driver_name
= "R300";
1165 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1166 static const __DRIversion dri_expected
= { 4, 0, 0 };
1167 static const __DRIversion drm_expected
= { 1, 24, 0 };
1169 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
) psp
->pDevPriv
;
1171 if ( ! driCheckDriDdxDrmVersions3( driver_name
,
1172 &psp
->dri_version
, & dri_expected
,
1173 &psp
->ddx_version
, & ddx_expected
,
1174 &psp
->drm_version
, & drm_expected
) ) {
1178 /* Calling driInitExtensions here, with a NULL context pointer,
1179 * does not actually enable the extensions. It just makes sure
1180 * that all the dispatch offsets for all the extensions that
1181 * *might* be enables are known. This is needed because the
1182 * dispatch offsets need to be known when _mesa_context_create
1183 * is called, but we can't enable the extensions until we have a
1186 * Hello chicken. Hello egg. How are you two today?
1188 driInitExtensions( NULL
, card_extensions
, GL_FALSE
);
1189 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1190 driInitExtensions( NULL
, blend_extensions
, GL_FALSE
);
1191 driInitSingleExtension( NULL
, ARB_vp_extension
);
1192 driInitSingleExtension( NULL
, NV_vp_extension
);
1193 driInitSingleExtension( NULL
, ATI_fs_extension
);
1194 driInitExtensions( NULL
, point_extensions
, GL_FALSE
);
1197 if (!radeonInitDriver(psp
))
1200 return radeonFillInModes( psp
,
1202 (dri_priv
->bpp
== 16) ? 16 : 24,
1203 (dri_priv
->bpp
== 16) ? 0 : 8,
1204 (dri_priv
->backOffset
!= dri_priv
->depthOffset
) );
1209 * Get information about previous buffer swaps.
1212 getSwapInfo( __DRIdrawablePrivate
*dPriv
, __DRIswapInfo
* sInfo
)
1214 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1215 radeonContextPtr rmesa
;
1216 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1217 r200ContextPtr rmesa
;
1220 if ( (dPriv
== NULL
) || (dPriv
->driContextPriv
== NULL
)
1221 || (dPriv
->driContextPriv
->driverPrivate
== NULL
)
1222 || (sInfo
== NULL
) ) {
1226 rmesa
= dPriv
->driContextPriv
->driverPrivate
;
1227 sInfo
->swap_count
= rmesa
->swap_count
;
1228 sInfo
->swap_ust
= rmesa
->swap_ust
;
1229 sInfo
->swap_missed_count
= rmesa
->swap_missed_count
;
1231 sInfo
->swap_missed_usage
= (sInfo
->swap_missed_count
!= 0)
1232 ? driCalculateSwapUsage( dPriv
, 0, rmesa
->swap_missed_ust
)
1238 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1239 const struct __DriverAPIRec driDriverAPI
= {
1240 .InitScreen
= radeonInitScreen
,
1241 .DestroyScreen
= radeonDestroyScreen
,
1242 .CreateContext
= radeonCreateContext
,
1243 .DestroyContext
= radeonDestroyContext
,
1244 .CreateBuffer
= radeonCreateBuffer
,
1245 .DestroyBuffer
= radeonDestroyBuffer
,
1246 .SwapBuffers
= radeonSwapBuffers
,
1247 .MakeCurrent
= radeonMakeCurrent
,
1248 .UnbindContext
= radeonUnbindContext
,
1249 .GetSwapInfo
= getSwapInfo
,
1250 .GetDrawableMSC
= driDrawableGetMSC32
,
1251 .WaitForMSC
= driWaitForMSC32
,
1253 .SwapBuffersMSC
= NULL
,
1254 .CopySubBuffer
= radeonCopySubBuffer
,
1257 const struct __DriverAPIRec driDriverAPI
= {
1258 .InitScreen
= radeonInitScreen
,
1259 .DestroyScreen
= radeonDestroyScreen
,
1260 .CreateContext
= r200CreateContext
,
1261 .DestroyContext
= r200DestroyContext
,
1262 .CreateBuffer
= radeonCreateBuffer
,
1263 .DestroyBuffer
= radeonDestroyBuffer
,
1264 .SwapBuffers
= r200SwapBuffers
,
1265 .MakeCurrent
= r200MakeCurrent
,
1266 .UnbindContext
= r200UnbindContext
,
1267 .GetSwapInfo
= getSwapInfo
,
1268 .GetDrawableMSC
= driDrawableGetMSC32
,
1269 .WaitForMSC
= driWaitForMSC32
,
1271 .SwapBuffersMSC
= NULL
,
1272 .CopySubBuffer
= r200CopySubBuffer
,