projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Merge remote branch 'origin/master' into pipe-video
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
36 */
37
38 #include <errno.h>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
44 #include "main/fbobject.h"
45
46 #define STANDALONE_MMIO
47 #include "radeon_chipset.h"
48 #include "radeon_macros.h"
49 #include "radeon_screen.h"
50 #include "radeon_common.h"
51 #include "radeon_common_context.h"
52 #if defined(RADEON_R100)
53 #include "radeon_context.h"
54 #include "radeon_tex.h"
55 #elif defined(RADEON_R200)
56 #include "r200_context.h"
57 #include "r200_tex.h"
58 #elif defined(RADEON_R300)
59 #include "r300_context.h"
60 #include "r300_tex.h"
61 #elif defined(RADEON_R600)
62 #include "r600_context.h"
63 #include "r700_driconf.h" /* +r6/r7 */
64 #include "r600_tex.h" /* +r6/r7 */
65 #endif
66
67 #include "utils.h"
68 #include "vblank.h"
69
70 #include "radeon_bocs_wrapper.h"
71
72 #include "GL/internal/dri_interface.h"
73
74 /* Radeon configuration
75 */
76 #include "xmlpool.h"
77
78 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
79 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
80 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
81 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
82 DRI_CONF_OPT_END
83
84 #if defined(RADEON_R100) /* R100 */
85 PUBLIC const char __driConfigOptions[] =
86 DRI_CONF_BEGIN
87 DRI_CONF_SECTION_PERFORMANCE
88 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
89 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
90 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
91 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
92 DRI_CONF_HYPERZ(false)
93 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
94 DRI_CONF_SECTION_END
95 DRI_CONF_SECTION_QUALITY
96 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
97 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
98 DRI_CONF_NO_NEG_LOD_BIAS(false)
99 DRI_CONF_FORCE_S3TC_ENABLE(false)
100 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
101 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
102 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
103 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
104 DRI_CONF_SECTION_END
105 DRI_CONF_SECTION_DEBUG
106 DRI_CONF_NO_RAST(false)
107 DRI_CONF_SECTION_END
108 DRI_CONF_END;
109 static const GLuint __driNConfigOptions = 15;
110
111 #elif defined(RADEON_R200)
112
113 PUBLIC const char __driConfigOptions[] =
114 DRI_CONF_BEGIN
115 DRI_CONF_SECTION_PERFORMANCE
116 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
117 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
118 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
119 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
120 DRI_CONF_HYPERZ(false)
121 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
122 DRI_CONF_SECTION_END
123 DRI_CONF_SECTION_QUALITY
124 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
125 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
126 DRI_CONF_NO_NEG_LOD_BIAS(false)
127 DRI_CONF_FORCE_S3TC_ENABLE(false)
128 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
129 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
130 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
131 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
132 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
133 DRI_CONF_SECTION_END
134 DRI_CONF_SECTION_DEBUG
135 DRI_CONF_NO_RAST(false)
136 DRI_CONF_SECTION_END
137 DRI_CONF_SECTION_SOFTWARE
138 DRI_CONF_NV_VERTEX_PROGRAM(false)
139 DRI_CONF_SECTION_END
140 DRI_CONF_END;
141 static const GLuint __driNConfigOptions = 17;
142
143 #elif defined(RADEON_R300) || defined(RADEON_R600)
144
145 #define DRI_CONF_FP_OPTIMIZATION_SPEED 0
146 #define DRI_CONF_FP_OPTIMIZATION_QUALITY 1
147
148 /* TODO: integrate these into xmlpool.h! */
149 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
150 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
151 DRI_CONF_DESC(en,"Number of texture image units") \
152 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
153 DRI_CONF_OPT_END
154
155 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
156 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
157 DRI_CONF_DESC(en,"Number of texture coordinate units") \
158 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
159 DRI_CONF_OPT_END
160
161
162
163 #define DRI_CONF_DISABLE_S3TC(def) \
164 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
165 DRI_CONF_DESC(en,"Disable S3TC compression") \
166 DRI_CONF_OPT_END
167
168 #define DRI_CONF_DISABLE_FALLBACK(def) \
169 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
170 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
171 DRI_CONF_OPT_END
172
173 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
174 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
175 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
176 DRI_CONF_OPT_END
177
178 #define DRI_CONF_FP_OPTIMIZATION(def) \
179 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
180 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
181 DRI_CONF_ENUM(0,"Optimize for Speed") \
182 DRI_CONF_ENUM(1,"Optimize for Quality") \
183 DRI_CONF_DESC_END \
184 DRI_CONF_OPT_END
185
186 PUBLIC const char __driConfigOptions[] =
187 DRI_CONF_BEGIN
188 DRI_CONF_SECTION_PERFORMANCE
189 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
190 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
191 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
192 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
193 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
194 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
195 DRI_CONF_DISABLE_FALLBACK(true)
196 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
197 DRI_CONF_SECTION_END
198 DRI_CONF_SECTION_QUALITY
199 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
200 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
201 DRI_CONF_FORCE_S3TC_ENABLE(false)
202 DRI_CONF_DISABLE_S3TC(false)
203 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
204 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
205 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
206 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
207 DRI_CONF_SECTION_END
208 DRI_CONF_SECTION_DEBUG
209 DRI_CONF_NO_RAST(false)
210 DRI_CONF_SECTION_END
211 DRI_CONF_END;
212 static const GLuint __driNConfigOptions = 17;
213
214 #endif
215
216 static int getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo );
217
218 #ifndef RADEON_INFO_TILE_CONFIG
219 #define RADEON_INFO_TILE_CONFIG 0x6
220 #endif
221
222 static int
223 radeonGetParam(__DRIscreen *sPriv, int param, void *value)
224 {
225 int ret;
226 drm_radeon_getparam_t gp = { 0 };
227 struct drm_radeon_info info = { 0 };
228
229 if (sPriv->drm_version.major >= 2) {
230 info.value = (uint64_t)(uintptr_t)value;
231 switch (param) {
232 case RADEON_PARAM_DEVICE_ID:
233 info.request = RADEON_INFO_DEVICE_ID;
234 break;
235 case RADEON_PARAM_NUM_GB_PIPES:
236 info.request = RADEON_INFO_NUM_GB_PIPES;
237 break;
238 case RADEON_PARAM_NUM_Z_PIPES:
239 info.request = RADEON_INFO_NUM_Z_PIPES;
240 break;
241 case RADEON_INFO_TILE_CONFIG:
242 info.request = RADEON_INFO_TILE_CONFIG;
243 break;
244 default:
245 return -EINVAL;
246 }
247 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info));
248 } else {
249 gp.param = param;
250 gp.value = value;
251
252 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
253 }
254 return ret;
255 }
256
257 static const __DRIconfig **
258 radeonFillInModes( __DRIscreen *psp,
259 unsigned pixel_bits, unsigned depth_bits,
260 unsigned stencil_bits, GLboolean have_back_buffer )
261 {
262 __DRIconfig **configs;
263 struct gl_config *m;
264 unsigned depth_buffer_factor;
265 unsigned back_buffer_factor;
266 int i;
267
268 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
269 * enough to add support. Basically, if a context is created with an
270 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
271 * will never be used.
272 */
273 static const GLenum back_buffer_modes[] = {
274 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
275 };
276
277 uint8_t depth_bits_array[2];
278 uint8_t stencil_bits_array[2];
279 uint8_t msaa_samples_array[1];
280
281 depth_bits_array[0] = depth_bits;
282 depth_bits_array[1] = depth_bits;
283
284 /* Just like with the accumulation buffer, always provide some modes
285 * with a stencil buffer. It will be a sw fallback, but some apps won't
286 * care about that.
287 */
288 stencil_bits_array[0] = stencil_bits;
289 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
290
291 msaa_samples_array[0] = 0;
292
293 depth_buffer_factor = (stencil_bits == 0) ? 2 : 1;
294 back_buffer_factor = (have_back_buffer) ? 2 : 1;
295
296 if (pixel_bits == 16) {
297 __DRIconfig **configs_a8r8g8b8;
298 __DRIconfig **configs_r5g6b5;
299
300 configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5,
301 depth_bits_array, stencil_bits_array,
302 depth_buffer_factor, back_buffer_modes,
303 back_buffer_factor, msaa_samples_array,
304 1, GL_TRUE);
305 configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
306 depth_bits_array, stencil_bits_array,
307 1, back_buffer_modes, 1,
308 msaa_samples_array, 1, GL_TRUE);
309 configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8);
310 } else
311 configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
312 depth_bits_array, stencil_bits_array,
313 depth_buffer_factor,
314 back_buffer_modes, back_buffer_factor,
315 msaa_samples_array, 1, GL_TRUE);
316
317 if (configs == NULL) {
318 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
319 __func__, __LINE__ );
320 return NULL;
321 }
322
323 /* Mark the visual as slow if there are "fake" stencil bits.
324 */
325 for (i = 0; configs[i]; i++) {
326 m = &configs[i]->modes;
327 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
328 m->visualRating = GLX_SLOW_CONFIG;
329 }
330 }
331
332 return (const __DRIconfig **) configs;
333 }
334
335 #if defined(RADEON_R100)
336 static const __DRItexOffsetExtension radeonTexOffsetExtension = {
337 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
338 radeonSetTexOffset,
339 };
340
341 static const __DRItexBufferExtension radeonTexBufferExtension = {
342 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
343 radeonSetTexBuffer,
344 radeonSetTexBuffer2,
345 };
346 #endif
347
348 #if defined(RADEON_R200)
349
350 static const __DRItexOffsetExtension r200texOffsetExtension = {
351 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
352 r200SetTexOffset,
353 };
354
355 static const __DRItexBufferExtension r200TexBufferExtension = {
356 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
357 r200SetTexBuffer,
358 r200SetTexBuffer2,
359 };
360 #endif
361
362 #if defined(RADEON_R300)
363 static const __DRItexOffsetExtension r300texOffsetExtension = {
364 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
365 r300SetTexOffset,
366 };
367
368 static const __DRItexBufferExtension r300TexBufferExtension = {
369 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
370 r300SetTexBuffer,
371 r300SetTexBuffer2,
372 };
373 #endif
374
375 #if defined(RADEON_R600)
376 static const __DRItexOffsetExtension r600texOffsetExtension = {
377 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
378 r600SetTexOffset, /* +r6/r7 */
379 };
380
381 static const __DRItexBufferExtension r600TexBufferExtension = {
382 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
383 r600SetTexBuffer, /* +r6/r7 */
384 r600SetTexBuffer2, /* +r6/r7 */
385 };
386 #endif
387
388 static void
389 radeonDRI2Flush(__DRIdrawable *drawable)
390 {
391 radeonContextPtr rmesa;
392
393 rmesa = (radeonContextPtr) drawable->driContextPriv->driverPrivate;
394 radeonFlush(rmesa->glCtx);
395 }
396
397 static const struct __DRI2flushExtensionRec radeonFlushExtension = {
398 { __DRI2_FLUSH, __DRI2_FLUSH_VERSION },
399 radeonDRI2Flush,
400 dri2InvalidateDrawable,
401 };
402
403 static __DRIimage *
404 radeon_create_image_from_name(__DRIcontext *context,
405 int width, int height, int format,
406 int name, int pitch, void *loaderPrivate)
407 {
408 __DRIimage *image;
409 radeonContextPtr radeon = context->driverPrivate;
410
411 if (name == 0)
412 return NULL;
413
414 image = CALLOC(sizeof *image);
415 if (image == NULL)
416 return NULL;
417
418 switch (format) {
419 case __DRI_IMAGE_FORMAT_RGB565:
420 image->format = MESA_FORMAT_RGB565;
421 image->internal_format = GL_RGB;
422 image->data_type = GL_UNSIGNED_BYTE;
423 break;
424 case __DRI_IMAGE_FORMAT_XRGB8888:
425 image->format = MESA_FORMAT_XRGB8888;
426 image->internal_format = GL_RGB;
427 image->data_type = GL_UNSIGNED_BYTE;
428 break;
429 case __DRI_IMAGE_FORMAT_ARGB8888:
430 image->format = MESA_FORMAT_ARGB8888;
431 image->internal_format = GL_RGBA;
432 image->data_type = GL_UNSIGNED_BYTE;
433 break;
434 default:
435 free(image);
436 return NULL;
437 }
438
439 image->data = loaderPrivate;
440 image->cpp = _mesa_get_format_bytes(image->format);
441 image->width = width;
442 image->pitch = pitch;
443 image->height = height;
444
445 image->bo = radeon_bo_open(radeon->radeonScreen->bom,
446 (uint32_t)name,
447 image->pitch * image->height * image->cpp,
448 0,
449 RADEON_GEM_DOMAIN_VRAM,
450 0);
451
452 if (image->bo == NULL) {
453 FREE(image);
454 return NULL;
455 }
456
457 return image;
458 }
459
460 static __DRIimage *
461 radeon_create_image_from_renderbuffer(__DRIcontext *context,
462 int renderbuffer, void *loaderPrivate)
463 {
464 __DRIimage *image;
465 radeonContextPtr radeon = context->driverPrivate;
466 struct gl_renderbuffer *rb;
467 struct radeon_renderbuffer *rrb;
468
469 rb = _mesa_lookup_renderbuffer(radeon->glCtx, renderbuffer);
470 if (!rb) {
471 _mesa_error(radeon->glCtx,
472 GL_INVALID_OPERATION, "glRenderbufferExternalMESA");
473 return NULL;
474 }
475
476 rrb = radeon_renderbuffer(rb);
477 image = CALLOC(sizeof *image);
478 if (image == NULL)
479 return NULL;
480
481 image->internal_format = rb->InternalFormat;
482 image->format = rb->Format;
483 image->cpp = rrb->cpp;
484 image->data_type = rb->DataType;
485 image->data = loaderPrivate;
486 radeon_bo_ref(rrb->bo);
487 image->bo = rrb->bo;
488
489 image->width = rb->Width;
490 image->height = rb->Height;
491 image->pitch = rrb->pitch / image->cpp;
492
493 return image;
494 }
495
496 static void
497 radeon_destroy_image(__DRIimage *image)
498 {
499 radeon_bo_unref(image->bo);
500 FREE(image);
501 }
502
503 static __DRIimage *
504 radeon_create_image(__DRIscreen *screen,
505 int width, int height, int format,
506 unsigned int use,
507 void *loaderPrivate)
508 {
509 __DRIimage *image;
510 radeonScreenPtr radeonScreen = screen->private;
511
512 image = CALLOC(sizeof *image);
513 if (image == NULL)
514 return NULL;
515
516 switch (format) {
517 case __DRI_IMAGE_FORMAT_RGB565:
518 image->format = MESA_FORMAT_RGB565;
519 image->internal_format = GL_RGB;
520 image->data_type = GL_UNSIGNED_BYTE;
521 break;
522 case __DRI_IMAGE_FORMAT_XRGB8888:
523 image->format = MESA_FORMAT_XRGB8888;
524 image->internal_format = GL_RGB;
525 image->data_type = GL_UNSIGNED_BYTE;
526 break;
527 case __DRI_IMAGE_FORMAT_ARGB8888:
528 image->format = MESA_FORMAT_ARGB8888;
529 image->internal_format = GL_RGBA;
530 image->data_type = GL_UNSIGNED_BYTE;
531 break;
532 default:
533 free(image);
534 return NULL;
535 }
536
537 image->data = loaderPrivate;
538 image->cpp = _mesa_get_format_bytes(image->format);
539 image->width = width;
540 image->height = height;
541 image->pitch = ((image->cpp * image->width + 255) & ~255) / image->cpp;
542
543 image->bo = radeon_bo_open(radeonScreen->bom,
544 0,
545 image->pitch * image->height * image->cpp,
546 0,
547 RADEON_GEM_DOMAIN_VRAM,
548 0);
549
550 if (image->bo == NULL) {
551 FREE(image);
552 return NULL;
553 }
554
555 return image;
556 }
557
558 static GLboolean
559 radeon_query_image(__DRIimage *image, int attrib, int *value)
560 {
561 switch (attrib) {
562 case __DRI_IMAGE_ATTRIB_STRIDE:
563 *value = image->pitch * image->cpp;
564 return GL_TRUE;
565 case __DRI_IMAGE_ATTRIB_HANDLE:
566 *value = image->bo->handle;
567 return GL_TRUE;
568 case __DRI_IMAGE_ATTRIB_NAME:
569 radeon_gem_get_kernel_name(image->bo, (uint32_t *) value);
570 return GL_TRUE;
571 default:
572 return GL_FALSE;
573 }
574 }
575
576 static struct __DRIimageExtensionRec radeonImageExtension = {
577 { __DRI_IMAGE, __DRI_IMAGE_VERSION },
578 radeon_create_image_from_name,
579 radeon_create_image_from_renderbuffer,
580 radeon_destroy_image,
581 radeon_create_image,
582 radeon_query_image
583 };
584
585 static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
586 {
587 screen->device_id = device_id;
588 screen->chip_flags = 0;
589 switch ( device_id ) {
590 case PCI_CHIP_RN50_515E:
591 case PCI_CHIP_RN50_5969:
592 return -1;
593
594 case PCI_CHIP_RADEON_LY:
595 case PCI_CHIP_RADEON_LZ:
596 case PCI_CHIP_RADEON_QY:
597 case PCI_CHIP_RADEON_QZ:
598 screen->chip_family = CHIP_FAMILY_RV100;
599 break;
600
601 case PCI_CHIP_RS100_4136:
602 case PCI_CHIP_RS100_4336:
603 screen->chip_family = CHIP_FAMILY_RS100;
604 break;
605
606 case PCI_CHIP_RS200_4137:
607 case PCI_CHIP_RS200_4337:
608 case PCI_CHIP_RS250_4237:
609 case PCI_CHIP_RS250_4437:
610 screen->chip_family = CHIP_FAMILY_RS200;
611 break;
612
613 case PCI_CHIP_RADEON_QD:
614 case PCI_CHIP_RADEON_QE:
615 case PCI_CHIP_RADEON_QF:
616 case PCI_CHIP_RADEON_QG:
617 /* all original radeons (7200) presumably have a stencil op bug */
618 screen->chip_family = CHIP_FAMILY_R100;
619 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
620 break;
621
622 case PCI_CHIP_RV200_QW:
623 case PCI_CHIP_RV200_QX:
624 case PCI_CHIP_RADEON_LW:
625 case PCI_CHIP_RADEON_LX:
626 screen->chip_family = CHIP_FAMILY_RV200;
627 screen->chip_flags = RADEON_CHIPSET_TCL;
628 break;
629
630 case PCI_CHIP_R200_BB:
631 case PCI_CHIP_R200_BC:
632 case PCI_CHIP_R200_QH:
633 case PCI_CHIP_R200_QL:
634 case PCI_CHIP_R200_QM:
635 screen->chip_family = CHIP_FAMILY_R200;
636 screen->chip_flags = RADEON_CHIPSET_TCL;
637 break;
638
639 case PCI_CHIP_RV250_If:
640 case PCI_CHIP_RV250_Ig:
641 case PCI_CHIP_RV250_Ld:
642 case PCI_CHIP_RV250_Lf:
643 case PCI_CHIP_RV250_Lg:
644 screen->chip_family = CHIP_FAMILY_RV250;
645 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
646 break;
647
648 case PCI_CHIP_RV280_5960:
649 case PCI_CHIP_RV280_5961:
650 case PCI_CHIP_RV280_5962:
651 case PCI_CHIP_RV280_5964:
652 case PCI_CHIP_RV280_5965:
653 case PCI_CHIP_RV280_5C61:
654 case PCI_CHIP_RV280_5C63:
655 screen->chip_family = CHIP_FAMILY_RV280;
656 screen->chip_flags = RADEON_CHIPSET_TCL;
657 break;
658
659 case PCI_CHIP_RS300_5834:
660 case PCI_CHIP_RS300_5835:
661 case PCI_CHIP_RS350_7834:
662 case PCI_CHIP_RS350_7835:
663 screen->chip_family = CHIP_FAMILY_RS300;
664 break;
665
666 case PCI_CHIP_R300_AD:
667 case PCI_CHIP_R300_AE:
668 case PCI_CHIP_R300_AF:
669 case PCI_CHIP_R300_AG:
670 case PCI_CHIP_R300_ND:
671 case PCI_CHIP_R300_NE:
672 case PCI_CHIP_R300_NF:
673 case PCI_CHIP_R300_NG:
674 screen->chip_family = CHIP_FAMILY_R300;
675 screen->chip_flags = RADEON_CHIPSET_TCL;
676 break;
677
678 case PCI_CHIP_RV350_AP:
679 case PCI_CHIP_RV350_AQ:
680 case PCI_CHIP_RV350_AR:
681 case PCI_CHIP_RV350_AS:
682 case PCI_CHIP_RV350_AT:
683 case PCI_CHIP_RV350_AV:
684 case PCI_CHIP_RV350_AU:
685 case PCI_CHIP_RV350_NP:
686 case PCI_CHIP_RV350_NQ:
687 case PCI_CHIP_RV350_NR:
688 case PCI_CHIP_RV350_NS:
689 case PCI_CHIP_RV350_NT:
690 case PCI_CHIP_RV350_NV:
691 screen->chip_family = CHIP_FAMILY_RV350;
692 screen->chip_flags = RADEON_CHIPSET_TCL;
693 break;
694
695 case PCI_CHIP_R350_AH:
696 case PCI_CHIP_R350_AI:
697 case PCI_CHIP_R350_AJ:
698 case PCI_CHIP_R350_AK:
699 case PCI_CHIP_R350_NH:
700 case PCI_CHIP_R350_NI:
701 case PCI_CHIP_R360_NJ:
702 case PCI_CHIP_R350_NK:
703 screen->chip_family = CHIP_FAMILY_R350;
704 screen->chip_flags = RADEON_CHIPSET_TCL;
705 break;
706
707 case PCI_CHIP_RV370_5460:
708 case PCI_CHIP_RV370_5462:
709 case PCI_CHIP_RV370_5464:
710 case PCI_CHIP_RV370_5B60:
711 case PCI_CHIP_RV370_5B62:
712 case PCI_CHIP_RV370_5B63:
713 case PCI_CHIP_RV370_5B64:
714 case PCI_CHIP_RV370_5B65:
715 case PCI_CHIP_RV380_3150:
716 case PCI_CHIP_RV380_3152:
717 case PCI_CHIP_RV380_3154:
718 case PCI_CHIP_RV380_3155:
719 case PCI_CHIP_RV380_3E50:
720 case PCI_CHIP_RV380_3E54:
721 screen->chip_family = CHIP_FAMILY_RV380;
722 screen->chip_flags = RADEON_CHIPSET_TCL;
723 break;
724
725 case PCI_CHIP_R420_JN:
726 case PCI_CHIP_R420_JH:
727 case PCI_CHIP_R420_JI:
728 case PCI_CHIP_R420_JJ:
729 case PCI_CHIP_R420_JK:
730 case PCI_CHIP_R420_JL:
731 case PCI_CHIP_R420_JM:
732 case PCI_CHIP_R420_JO:
733 case PCI_CHIP_R420_JP:
734 case PCI_CHIP_R420_JT:
735 case PCI_CHIP_R481_4B49:
736 case PCI_CHIP_R481_4B4A:
737 case PCI_CHIP_R481_4B4B:
738 case PCI_CHIP_R481_4B4C:
739 case PCI_CHIP_R423_UH:
740 case PCI_CHIP_R423_UI:
741 case PCI_CHIP_R423_UJ:
742 case PCI_CHIP_R423_UK:
743 case PCI_CHIP_R430_554C:
744 case PCI_CHIP_R430_554D:
745 case PCI_CHIP_R430_554E:
746 case PCI_CHIP_R430_554F:
747 case PCI_CHIP_R423_5550:
748 case PCI_CHIP_R423_UQ:
749 case PCI_CHIP_R423_UR:
750 case PCI_CHIP_R423_UT:
751 case PCI_CHIP_R430_5D48:
752 case PCI_CHIP_R430_5D49:
753 case PCI_CHIP_R430_5D4A:
754 case PCI_CHIP_R480_5D4C:
755 case PCI_CHIP_R480_5D4D:
756 case PCI_CHIP_R480_5D4E:
757 case PCI_CHIP_R480_5D4F:
758 case PCI_CHIP_R480_5D50:
759 case PCI_CHIP_R480_5D52:
760 case PCI_CHIP_R423_5D57:
761 screen->chip_family = CHIP_FAMILY_R420;
762 screen->chip_flags = RADEON_CHIPSET_TCL;
763 break;
764
765 case PCI_CHIP_RV410_5E4C:
766 case PCI_CHIP_RV410_5E4F:
767 case PCI_CHIP_RV410_564A:
768 case PCI_CHIP_RV410_564B:
769 case PCI_CHIP_RV410_564F:
770 case PCI_CHIP_RV410_5652:
771 case PCI_CHIP_RV410_5653:
772 case PCI_CHIP_RV410_5657:
773 case PCI_CHIP_RV410_5E48:
774 case PCI_CHIP_RV410_5E4A:
775 case PCI_CHIP_RV410_5E4B:
776 case PCI_CHIP_RV410_5E4D:
777 screen->chip_family = CHIP_FAMILY_RV410;
778 screen->chip_flags = RADEON_CHIPSET_TCL;
779 break;
780
781 case PCI_CHIP_RS480_5954:
782 case PCI_CHIP_RS480_5955:
783 case PCI_CHIP_RS482_5974:
784 case PCI_CHIP_RS482_5975:
785 case PCI_CHIP_RS400_5A41:
786 case PCI_CHIP_RS400_5A42:
787 case PCI_CHIP_RC410_5A61:
788 case PCI_CHIP_RC410_5A62:
789 screen->chip_family = CHIP_FAMILY_RS400;
790 break;
791
792 case PCI_CHIP_RS600_793F:
793 case PCI_CHIP_RS600_7941:
794 case PCI_CHIP_RS600_7942:
795 screen->chip_family = CHIP_FAMILY_RS600;
796 break;
797
798 case PCI_CHIP_RS690_791E:
799 case PCI_CHIP_RS690_791F:
800 screen->chip_family = CHIP_FAMILY_RS690;
801 break;
802 case PCI_CHIP_RS740_796C:
803 case PCI_CHIP_RS740_796D:
804 case PCI_CHIP_RS740_796E:
805 case PCI_CHIP_RS740_796F:
806 screen->chip_family = CHIP_FAMILY_RS740;
807 break;
808
809 case PCI_CHIP_R520_7100:
810 case PCI_CHIP_R520_7101:
811 case PCI_CHIP_R520_7102:
812 case PCI_CHIP_R520_7103:
813 case PCI_CHIP_R520_7104:
814 case PCI_CHIP_R520_7105:
815 case PCI_CHIP_R520_7106:
816 case PCI_CHIP_R520_7108:
817 case PCI_CHIP_R520_7109:
818 case PCI_CHIP_R520_710A:
819 case PCI_CHIP_R520_710B:
820 case PCI_CHIP_R520_710C:
821 case PCI_CHIP_R520_710E:
822 case PCI_CHIP_R520_710F:
823 screen->chip_family = CHIP_FAMILY_R520;
824 screen->chip_flags = RADEON_CHIPSET_TCL;
825 break;
826
827 case PCI_CHIP_RV515_7140:
828 case PCI_CHIP_RV515_7141:
829 case PCI_CHIP_RV515_7142:
830 case PCI_CHIP_RV515_7143:
831 case PCI_CHIP_RV515_7144:
832 case PCI_CHIP_RV515_7145:
833 case PCI_CHIP_RV515_7146:
834 case PCI_CHIP_RV515_7147:
835 case PCI_CHIP_RV515_7149:
836 case PCI_CHIP_RV515_714A:
837 case PCI_CHIP_RV515_714B:
838 case PCI_CHIP_RV515_714C:
839 case PCI_CHIP_RV515_714D:
840 case PCI_CHIP_RV515_714E:
841 case PCI_CHIP_RV515_714F:
842 case PCI_CHIP_RV515_7151:
843 case PCI_CHIP_RV515_7152:
844 case PCI_CHIP_RV515_7153:
845 case PCI_CHIP_RV515_715E:
846 case PCI_CHIP_RV515_715F:
847 case PCI_CHIP_RV515_7180:
848 case PCI_CHIP_RV515_7181:
849 case PCI_CHIP_RV515_7183:
850 case PCI_CHIP_RV515_7186:
851 case PCI_CHIP_RV515_7187:
852 case PCI_CHIP_RV515_7188:
853 case PCI_CHIP_RV515_718A:
854 case PCI_CHIP_RV515_718B:
855 case PCI_CHIP_RV515_718C:
856 case PCI_CHIP_RV515_718D:
857 case PCI_CHIP_RV515_718F:
858 case PCI_CHIP_RV515_7193:
859 case PCI_CHIP_RV515_7196:
860 case PCI_CHIP_RV515_719B:
861 case PCI_CHIP_RV515_719F:
862 case PCI_CHIP_RV515_7200:
863 case PCI_CHIP_RV515_7210:
864 case PCI_CHIP_RV515_7211:
865 screen->chip_family = CHIP_FAMILY_RV515;
866 screen->chip_flags = RADEON_CHIPSET_TCL;
867 break;
868
869 case PCI_CHIP_RV530_71C0:
870 case PCI_CHIP_RV530_71C1:
871 case PCI_CHIP_RV530_71C2:
872 case PCI_CHIP_RV530_71C3:
873 case PCI_CHIP_RV530_71C4:
874 case PCI_CHIP_RV530_71C5:
875 case PCI_CHIP_RV530_71C6:
876 case PCI_CHIP_RV530_71C7:
877 case PCI_CHIP_RV530_71CD:
878 case PCI_CHIP_RV530_71CE:
879 case PCI_CHIP_RV530_71D2:
880 case PCI_CHIP_RV530_71D4:
881 case PCI_CHIP_RV530_71D5:
882 case PCI_CHIP_RV530_71D6:
883 case PCI_CHIP_RV530_71DA:
884 case PCI_CHIP_RV530_71DE:
885 screen->chip_family = CHIP_FAMILY_RV530;
886 screen->chip_flags = RADEON_CHIPSET_TCL;
887 break;
888
889 case PCI_CHIP_R580_7240:
890 case PCI_CHIP_R580_7243:
891 case PCI_CHIP_R580_7244:
892 case PCI_CHIP_R580_7245:
893 case PCI_CHIP_R580_7246:
894 case PCI_CHIP_R580_7247:
895 case PCI_CHIP_R580_7248:
896 case PCI_CHIP_R580_7249:
897 case PCI_CHIP_R580_724A:
898 case PCI_CHIP_R580_724B:
899 case PCI_CHIP_R580_724C:
900 case PCI_CHIP_R580_724D:
901 case PCI_CHIP_R580_724E:
902 case PCI_CHIP_R580_724F:
903 case PCI_CHIP_R580_7284:
904 screen->chip_family = CHIP_FAMILY_R580;
905 screen->chip_flags = RADEON_CHIPSET_TCL;
906 break;
907
908 case PCI_CHIP_RV570_7280:
909 case PCI_CHIP_RV560_7281:
910 case PCI_CHIP_RV560_7283:
911 case PCI_CHIP_RV560_7287:
912 case PCI_CHIP_RV570_7288:
913 case PCI_CHIP_RV570_7289:
914 case PCI_CHIP_RV570_728B:
915 case PCI_CHIP_RV570_728C:
916 case PCI_CHIP_RV560_7290:
917 case PCI_CHIP_RV560_7291:
918 case PCI_CHIP_RV560_7293:
919 case PCI_CHIP_RV560_7297:
920 screen->chip_family = CHIP_FAMILY_RV560;
921 screen->chip_flags = RADEON_CHIPSET_TCL;
922 break;
923
924 case PCI_CHIP_R600_9400:
925 case PCI_CHIP_R600_9401:
926 case PCI_CHIP_R600_9402:
927 case PCI_CHIP_R600_9403:
928 case PCI_CHIP_R600_9405:
929 case PCI_CHIP_R600_940A:
930 case PCI_CHIP_R600_940B:
931 case PCI_CHIP_R600_940F:
932 screen->chip_family = CHIP_FAMILY_R600;
933 screen->chip_flags = RADEON_CHIPSET_TCL;
934 break;
935
936 case PCI_CHIP_RV610_94C0:
937 case PCI_CHIP_RV610_94C1:
938 case PCI_CHIP_RV610_94C3:
939 case PCI_CHIP_RV610_94C4:
940 case PCI_CHIP_RV610_94C5:
941 case PCI_CHIP_RV610_94C6:
942 case PCI_CHIP_RV610_94C7:
943 case PCI_CHIP_RV610_94C8:
944 case PCI_CHIP_RV610_94C9:
945 case PCI_CHIP_RV610_94CB:
946 case PCI_CHIP_RV610_94CC:
947 case PCI_CHIP_RV610_94CD:
948 screen->chip_family = CHIP_FAMILY_RV610;
949 screen->chip_flags = RADEON_CHIPSET_TCL;
950 break;
951
952 case PCI_CHIP_RV630_9580:
953 case PCI_CHIP_RV630_9581:
954 case PCI_CHIP_RV630_9583:
955 case PCI_CHIP_RV630_9586:
956 case PCI_CHIP_RV630_9587:
957 case PCI_CHIP_RV630_9588:
958 case PCI_CHIP_RV630_9589:
959 case PCI_CHIP_RV630_958A:
960 case PCI_CHIP_RV630_958B:
961 case PCI_CHIP_RV630_958C:
962 case PCI_CHIP_RV630_958D:
963 case PCI_CHIP_RV630_958E:
964 case PCI_CHIP_RV630_958F:
965 screen->chip_family = CHIP_FAMILY_RV630;
966 screen->chip_flags = RADEON_CHIPSET_TCL;
967 break;
968
969 case PCI_CHIP_RV670_9500:
970 case PCI_CHIP_RV670_9501:
971 case PCI_CHIP_RV670_9504:
972 case PCI_CHIP_RV670_9505:
973 case PCI_CHIP_RV670_9506:
974 case PCI_CHIP_RV670_9507:
975 case PCI_CHIP_RV670_9508:
976 case PCI_CHIP_RV670_9509:
977 case PCI_CHIP_RV670_950F:
978 case PCI_CHIP_RV670_9511:
979 case PCI_CHIP_RV670_9515:
980 case PCI_CHIP_RV670_9517:
981 case PCI_CHIP_RV670_9519:
982 screen->chip_family = CHIP_FAMILY_RV670;
983 screen->chip_flags = RADEON_CHIPSET_TCL;
984 break;
985
986 case PCI_CHIP_RV620_95C0:
987 case PCI_CHIP_RV620_95C2:
988 case PCI_CHIP_RV620_95C4:
989 case PCI_CHIP_RV620_95C5:
990 case PCI_CHIP_RV620_95C6:
991 case PCI_CHIP_RV620_95C7:
992 case PCI_CHIP_RV620_95C9:
993 case PCI_CHIP_RV620_95CC:
994 case PCI_CHIP_RV620_95CD:
995 case PCI_CHIP_RV620_95CE:
996 case PCI_CHIP_RV620_95CF:
997 screen->chip_family = CHIP_FAMILY_RV620;
998 screen->chip_flags = RADEON_CHIPSET_TCL;
999 break;
1000
1001 case PCI_CHIP_RV635_9590:
1002 case PCI_CHIP_RV635_9591:
1003 case PCI_CHIP_RV635_9593:
1004 case PCI_CHIP_RV635_9595:
1005 case PCI_CHIP_RV635_9596:
1006 case PCI_CHIP_RV635_9597:
1007 case PCI_CHIP_RV635_9598:
1008 case PCI_CHIP_RV635_9599:
1009 case PCI_CHIP_RV635_959B:
1010 screen->chip_family = CHIP_FAMILY_RV635;
1011 screen->chip_flags = RADEON_CHIPSET_TCL;
1012 break;
1013
1014 case PCI_CHIP_RS780_9610:
1015 case PCI_CHIP_RS780_9611:
1016 case PCI_CHIP_RS780_9612:
1017 case PCI_CHIP_RS780_9613:
1018 case PCI_CHIP_RS780_9614:
1019 case PCI_CHIP_RS780_9615:
1020 case PCI_CHIP_RS780_9616:
1021 screen->chip_family = CHIP_FAMILY_RS780;
1022 screen->chip_flags = RADEON_CHIPSET_TCL;
1023 break;
1024 case PCI_CHIP_RS880_9710:
1025 case PCI_CHIP_RS880_9711:
1026 case PCI_CHIP_RS880_9712:
1027 case PCI_CHIP_RS880_9713:
1028 case PCI_CHIP_RS880_9714:
1029 case PCI_CHIP_RS880_9715:
1030 screen->chip_family = CHIP_FAMILY_RS880;
1031 screen->chip_flags = RADEON_CHIPSET_TCL;
1032 break;
1033
1034 case PCI_CHIP_RV770_9440:
1035 case PCI_CHIP_RV770_9441:
1036 case PCI_CHIP_RV770_9442:
1037 case PCI_CHIP_RV770_9443:
1038 case PCI_CHIP_RV770_9444:
1039 case PCI_CHIP_RV770_9446:
1040 case PCI_CHIP_RV770_944A:
1041 case PCI_CHIP_RV770_944B:
1042 case PCI_CHIP_RV770_944C:
1043 case PCI_CHIP_RV770_944E:
1044 case PCI_CHIP_RV770_9450:
1045 case PCI_CHIP_RV770_9452:
1046 case PCI_CHIP_RV770_9456:
1047 case PCI_CHIP_RV770_945A:
1048 case PCI_CHIP_RV770_945B:
1049 case PCI_CHIP_RV770_945E:
1050 case PCI_CHIP_RV790_9460:
1051 case PCI_CHIP_RV790_9462:
1052 case PCI_CHIP_RV770_946A:
1053 case PCI_CHIP_RV770_946B:
1054 case PCI_CHIP_RV770_947A:
1055 case PCI_CHIP_RV770_947B:
1056 screen->chip_family = CHIP_FAMILY_RV770;
1057 screen->chip_flags = RADEON_CHIPSET_TCL;
1058 break;
1059
1060 case PCI_CHIP_RV730_9480:
1061 case PCI_CHIP_RV730_9487:
1062 case PCI_CHIP_RV730_9488:
1063 case PCI_CHIP_RV730_9489:
1064 case PCI_CHIP_RV730_948A:
1065 case PCI_CHIP_RV730_948F:
1066 case PCI_CHIP_RV730_9490:
1067 case PCI_CHIP_RV730_9491:
1068 case PCI_CHIP_RV730_9495:
1069 case PCI_CHIP_RV730_9498:
1070 case PCI_CHIP_RV730_949C:
1071 case PCI_CHIP_RV730_949E:
1072 case PCI_CHIP_RV730_949F:
1073 screen->chip_family = CHIP_FAMILY_RV730;
1074 screen->chip_flags = RADEON_CHIPSET_TCL;
1075 break;
1076
1077 case PCI_CHIP_RV710_9540:
1078 case PCI_CHIP_RV710_9541:
1079 case PCI_CHIP_RV710_9542:
1080 case PCI_CHIP_RV710_954E:
1081 case PCI_CHIP_RV710_954F:
1082 case PCI_CHIP_RV710_9552:
1083 case PCI_CHIP_RV710_9553:
1084 case PCI_CHIP_RV710_9555:
1085 case PCI_CHIP_RV710_9557:
1086 case PCI_CHIP_RV710_955F:
1087 screen->chip_family = CHIP_FAMILY_RV710;
1088 screen->chip_flags = RADEON_CHIPSET_TCL;
1089 break;
1090
1091 case PCI_CHIP_RV740_94A0:
1092 case PCI_CHIP_RV740_94A1:
1093 case PCI_CHIP_RV740_94A3:
1094 case PCI_CHIP_RV740_94B1:
1095 case PCI_CHIP_RV740_94B3:
1096 case PCI_CHIP_RV740_94B4:
1097 case PCI_CHIP_RV740_94B5:
1098 case PCI_CHIP_RV740_94B9:
1099 screen->chip_family = CHIP_FAMILY_RV740;
1100 screen->chip_flags = RADEON_CHIPSET_TCL;
1101 break;
1102
1103 case PCI_CHIP_CEDAR_68E0:
1104 case PCI_CHIP_CEDAR_68E1:
1105 case PCI_CHIP_CEDAR_68E4:
1106 case PCI_CHIP_CEDAR_68E5:
1107 case PCI_CHIP_CEDAR_68E8:
1108 case PCI_CHIP_CEDAR_68E9:
1109 case PCI_CHIP_CEDAR_68F1:
1110 case PCI_CHIP_CEDAR_68F8:
1111 case PCI_CHIP_CEDAR_68F9:
1112 case PCI_CHIP_CEDAR_68FE:
1113 screen->chip_family = CHIP_FAMILY_CEDAR;
1114 screen->chip_flags = RADEON_CHIPSET_TCL;
1115 break;
1116
1117 case PCI_CHIP_REDWOOD_68C0:
1118 case PCI_CHIP_REDWOOD_68C1:
1119 case PCI_CHIP_REDWOOD_68C8:
1120 case PCI_CHIP_REDWOOD_68C9:
1121 case PCI_CHIP_REDWOOD_68D8:
1122 case PCI_CHIP_REDWOOD_68D9:
1123 case PCI_CHIP_REDWOOD_68DA:
1124 case PCI_CHIP_REDWOOD_68DE:
1125 screen->chip_family = CHIP_FAMILY_REDWOOD;
1126 screen->chip_flags = RADEON_CHIPSET_TCL;
1127 break;
1128
1129 case PCI_CHIP_JUNIPER_68A0:
1130 case PCI_CHIP_JUNIPER_68A1:
1131 case PCI_CHIP_JUNIPER_68A8:
1132 case PCI_CHIP_JUNIPER_68A9:
1133 case PCI_CHIP_JUNIPER_68B0:
1134 case PCI_CHIP_JUNIPER_68B8:
1135 case PCI_CHIP_JUNIPER_68B9:
1136 case PCI_CHIP_JUNIPER_68BE:
1137 screen->chip_family = CHIP_FAMILY_JUNIPER;
1138 screen->chip_flags = RADEON_CHIPSET_TCL;
1139 break;
1140
1141 case PCI_CHIP_CYPRESS_6880:
1142 case PCI_CHIP_CYPRESS_6888:
1143 case PCI_CHIP_CYPRESS_6889:
1144 case PCI_CHIP_CYPRESS_688A:
1145 case PCI_CHIP_CYPRESS_6898:
1146 case PCI_CHIP_CYPRESS_6899:
1147 case PCI_CHIP_CYPRESS_689E:
1148 screen->chip_family = CHIP_FAMILY_CYPRESS;
1149 screen->chip_flags = RADEON_CHIPSET_TCL;
1150 break;
1151
1152 case PCI_CHIP_HEMLOCK_689C:
1153 case PCI_CHIP_HEMLOCK_689D:
1154 screen->chip_family = CHIP_FAMILY_HEMLOCK;
1155 screen->chip_flags = RADEON_CHIPSET_TCL;
1156 break;
1157
1158 case PCI_CHIP_PALM_9802:
1159 case PCI_CHIP_PALM_9803:
1160 case PCI_CHIP_PALM_9804:
1161 case PCI_CHIP_PALM_9805:
1162 screen->chip_family = CHIP_FAMILY_PALM;
1163 screen->chip_flags = RADEON_CHIPSET_TCL;
1164 break;
1165
1166 default:
1167 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
1168 device_id);
1169 return -1;
1170 }
1171
1172 return 0;
1173 }
1174
1175
1176 /* Create the device specific screen private data struct.
1177 */
1178 static radeonScreenPtr
1179 radeonCreateScreen( __DRIscreen *sPriv )
1180 {
1181 radeonScreenPtr screen;
1182 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
1183 unsigned char *RADEONMMIO = NULL;
1184 int i;
1185 int ret;
1186 uint32_t temp = 0;
1187
1188 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
1189 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
1190 return GL_FALSE;
1191 }
1192
1193 /* Allocate the private area */
1194 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1195 if ( !screen ) {
1196 __driUtilMessage("%s: Could not allocate memory for screen structure",
1197 __FUNCTION__);
1198 return NULL;
1199 }
1200
1201 radeon_init_debug();
1202
1203 /* parse information in __driConfigOptions */
1204 driParseOptionInfo (&screen->optionCache,
1205 __driConfigOptions, __driNConfigOptions);
1206
1207 /* This is first since which regions we map depends on whether or
1208 * not we are using a PCI card.
1209 */
1210 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
1211 {
1212 int ret;
1213
1214 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET,
1215 &screen->gart_buffer_offset);
1216
1217 if (ret) {
1218 FREE( screen );
1219 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
1220 return NULL;
1221 }
1222
1223 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE,
1224 &screen->gart_base);
1225 if (ret) {
1226 FREE( screen );
1227 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
1228 return NULL;
1229 }
1230
1231 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR,
1232 &screen->irq);
1233 if (ret) {
1234 FREE( screen );
1235 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
1236 return NULL;
1237 }
1238 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
1239 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
1240 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
1241 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
1242 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
1243 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
1244 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
1245 screen->drmSupportsOcclusionQueries = (sPriv->drm_version.minor >= 30);
1246 }
1247
1248 ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
1249 if (ret == -1)
1250 return NULL;
1251
1252 screen->mmio.handle = dri_priv->registerHandle;
1253 screen->mmio.size = dri_priv->registerSize;
1254 if ( drmMap( sPriv->fd,
1255 screen->mmio.handle,
1256 screen->mmio.size,
1257 &screen->mmio.map ) ) {
1258 FREE( screen );
1259 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
1260 return NULL;
1261 }
1262
1263 RADEONMMIO = screen->mmio.map;
1264
1265 screen->status.handle = dri_priv->statusHandle;
1266 screen->status.size = dri_priv->statusSize;
1267 if ( drmMap( sPriv->fd,
1268 screen->status.handle,
1269 screen->status.size,
1270 &screen->status.map ) ) {
1271 drmUnmap( screen->mmio.map, screen->mmio.size );
1272 FREE( screen );
1273 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
1274 return NULL;
1275 }
1276 if (screen->chip_family < CHIP_FAMILY_R600)
1277 screen->scratch = (__volatile__ uint32_t *)
1278 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
1279 else
1280 screen->scratch = (__volatile__ uint32_t *)
1281 ((GLubyte *)screen->status.map + R600_SCRATCH_REG_OFFSET);
1282
1283 screen->buffers = drmMapBufs( sPriv->fd );
1284 if ( !screen->buffers ) {
1285 drmUnmap( screen->status.map, screen->status.size );
1286 drmUnmap( screen->mmio.map, screen->mmio.size );
1287 FREE( screen );
1288 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
1289 return NULL;
1290 }
1291
1292 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
1293 screen->gartTextures.handle = dri_priv->gartTexHandle;
1294 screen->gartTextures.size = dri_priv->gartTexMapSize;
1295 if ( drmMap( sPriv->fd,
1296 screen->gartTextures.handle,
1297 screen->gartTextures.size,
1298 (drmAddressPtr)&screen->gartTextures.map ) ) {
1299 drmUnmapBufs( screen->buffers );
1300 drmUnmap( screen->status.map, screen->status.size );
1301 drmUnmap( screen->mmio.map, screen->mmio.size );
1302 FREE( screen );
1303 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
1304 return NULL;
1305 }
1306
1307 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
1308 }
1309
1310 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
1311 sPriv->ddx_version.minor < 2) {
1312 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
1313 return NULL;
1314 }
1315
1316 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
1317 fprintf(stderr, "R500 support requires a newer drm.\n");
1318 return NULL;
1319 }
1320
1321 if (getenv("R300_NO_TCL"))
1322 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1323
1324 if (screen->chip_family <= CHIP_FAMILY_RS200)
1325 screen->chip_flags |= RADEON_CLASS_R100;
1326 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1327 screen->chip_flags |= RADEON_CLASS_R200;
1328 else if (screen->chip_family <= CHIP_FAMILY_RV570)
1329 screen->chip_flags |= RADEON_CLASS_R300;
1330 else
1331 screen->chip_flags |= RADEON_CLASS_R600;
1332
1333 /* set group bytes for r6xx+ */
1334 if (screen->chip_family >= CHIP_FAMILY_CEDAR)
1335 screen->group_bytes = 512;
1336 else
1337 screen->group_bytes = 256;
1338
1339 screen->cpp = dri_priv->bpp / 8;
1340 screen->AGPMode = dri_priv->AGPMode;
1341
1342 ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp);
1343
1344 /* +r6/r7 */
1345 if(screen->chip_family >= CHIP_FAMILY_R600)
1346 {
1347 if (ret)
1348 {
1349 FREE( screen );
1350 fprintf(stderr, "Unable to get fb location need newer drm\n");
1351 return NULL;
1352 }
1353 else
1354 {
1355 screen->fbLocation = (temp & 0xffff) << 24;
1356 }
1357 }
1358 else
1359 {
1360 if (ret)
1361 {
1362 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm)
1363 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
1364 else
1365 {
1366 FREE( screen );
1367 fprintf(stderr, "Unable to get fb location need newer drm\n");
1368 return NULL;
1369 }
1370 }
1371 else
1372 {
1373 screen->fbLocation = (temp & 0xffff) << 16;
1374 }
1375 }
1376
1377 if (IS_R300_CLASS(screen)) {
1378 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1379 if (ret) {
1380 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1381 switch (screen->chip_family) {
1382 case CHIP_FAMILY_R300:
1383 case CHIP_FAMILY_R350:
1384 screen->num_gb_pipes = 2;
1385 break;
1386 case CHIP_FAMILY_R420:
1387 case CHIP_FAMILY_R520:
1388 case CHIP_FAMILY_R580:
1389 case CHIP_FAMILY_RV560:
1390 case CHIP_FAMILY_RV570:
1391 screen->num_gb_pipes = 4;
1392 break;
1393 case CHIP_FAMILY_RV350:
1394 case CHIP_FAMILY_RV515:
1395 case CHIP_FAMILY_RV530:
1396 case CHIP_FAMILY_RV410:
1397 default:
1398 screen->num_gb_pipes = 1;
1399 break;
1400 }
1401 } else {
1402 screen->num_gb_pipes = temp;
1403 }
1404
1405 /* pipe overrides */
1406 switch (dri_priv->deviceID) {
1407 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1408 case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */
1409 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
1410 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
1411 screen->num_gb_pipes = 1;
1412 break;
1413 default:
1414 break;
1415 }
1416
1417 if ( sPriv->drm_version.minor >= 31 ) {
1418 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp);
1419 if (ret)
1420 screen->num_z_pipes = 2;
1421 else
1422 screen->num_z_pipes = temp;
1423 } else
1424 screen->num_z_pipes = 2;
1425 }
1426
1427 if ( sPriv->drm_version.minor >= 10 ) {
1428 drm_radeon_setparam_t sp;
1429
1430 sp.param = RADEON_SETPARAM_FB_LOCATION;
1431 sp.value = screen->fbLocation;
1432
1433 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
1434 &sp, sizeof( sp ) );
1435 }
1436
1437 screen->frontOffset = dri_priv->frontOffset;
1438 screen->frontPitch = dri_priv->frontPitch;
1439 screen->backOffset = dri_priv->backOffset;
1440 screen->backPitch = dri_priv->backPitch;
1441 screen->depthOffset = dri_priv->depthOffset;
1442 screen->depthPitch = dri_priv->depthPitch;
1443
1444 /* Check if ddx has set up a surface reg to cover depth buffer */
1445 screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
1446 /* these chips don't use tiled z without hyperz. So always pretend
1447 we have set up a surface which will cause linear reads/writes */
1448 (IS_R100_CLASS(screen) &&
1449 !(screen->chip_flags & RADEON_CHIPSET_TCL));
1450
1451 if ( dri_priv->textureSize == 0 ) {
1452 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
1453 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
1454 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
1455 dri_priv->log2GARTTexGran;
1456 } else {
1457 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
1458 + screen->fbLocation;
1459 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
1460 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
1461 dri_priv->log2TexGran;
1462 }
1463
1464 if ( !screen->gartTextures.map || dri_priv->textureSize == 0
1465 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
1466 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
1467 screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
1468 screen->texSize[RADEON_GART_TEX_HEAP] = 0;
1469 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
1470 } else {
1471 screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
1472 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
1473 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
1474 screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
1475 dri_priv->log2GARTTexGran;
1476 }
1477
1478 i = 0;
1479 screen->extensions[i++] = &driCopySubBufferExtension.base;
1480 screen->extensions[i++] = &driReadDrawableExtension;
1481
1482 if ( screen->irq != 0 ) {
1483 screen->extensions[i++] = &driSwapControlExtension.base;
1484 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1485 }
1486
1487 #if defined(RADEON_R100)
1488 screen->extensions[i++] = &radeonTexOffsetExtension.base;
1489 #endif
1490
1491 #if defined(RADEON_R200)
1492 screen->extensions[i++] = &r200texOffsetExtension.base;
1493 #endif
1494
1495 #if defined(RADEON_R300)
1496 screen->extensions[i++] = &r300texOffsetExtension.base;
1497 #endif
1498
1499 #if defined(RADEON_R600)
1500 screen->extensions[i++] = &r600texOffsetExtension.base;
1501 #endif
1502
1503 screen->extensions[i++] = &dri2ConfigQueryExtension.base;
1504
1505 screen->extensions[i++] = NULL;
1506 sPriv->extensions = screen->extensions;
1507
1508 screen->driScreen = sPriv;
1509 screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
1510 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
1511 screen->sarea_priv_offset);
1512
1513 screen->bom = radeon_bo_manager_legacy_ctor(screen);
1514 if (screen->bom == NULL) {
1515 free(screen);
1516 return NULL;
1517 }
1518
1519 return screen;
1520 }
1521
1522 static radeonScreenPtr
1523 radeonCreateScreen2(__DRIscreen *sPriv)
1524 {
1525 radeonScreenPtr screen;
1526 int i;
1527 int ret;
1528 uint32_t device_id = 0;
1529 uint32_t temp = 0;
1530
1531 /* Allocate the private area */
1532 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1533 if ( !screen ) {
1534 __driUtilMessage("%s: Could not allocate memory for screen structure",
1535 __FUNCTION__);
1536 fprintf(stderr, "leaving here\n");
1537 return NULL;
1538 }
1539
1540 radeon_init_debug();
1541
1542 /* parse information in __driConfigOptions */
1543 driParseOptionInfo (&screen->optionCache,
1544 __driConfigOptions, __driNConfigOptions);
1545
1546 screen->kernel_mm = 1;
1547 screen->chip_flags = 0;
1548
1549 /* if we have kms we can support all of these */
1550 screen->drmSupportsCubeMapsR200 = 1;
1551 screen->drmSupportsBlendColor = 1;
1552 screen->drmSupportsTriPerf = 1;
1553 screen->drmSupportsFragShader = 1;
1554 screen->drmSupportsPointSprites = 1;
1555 screen->drmSupportsCubeMapsR100 = 1;
1556 screen->drmSupportsVertexProgram = 1;
1557 screen->drmSupportsOcclusionQueries = 1;
1558 screen->irq = 1;
1559
1560 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id);
1561 if (ret) {
1562 FREE( screen );
1563 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret);
1564 return NULL;
1565 }
1566
1567 ret = radeon_set_screen_flags(screen, device_id);
1568 if (ret == -1)
1569 return NULL;
1570
1571 if (getenv("R300_NO_TCL"))
1572 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1573
1574 if (screen->chip_family <= CHIP_FAMILY_RS200)
1575 screen->chip_flags |= RADEON_CLASS_R100;
1576 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1577 screen->chip_flags |= RADEON_CLASS_R200;
1578 else if (screen->chip_family <= CHIP_FAMILY_RV570)
1579 screen->chip_flags |= RADEON_CLASS_R300;
1580 else
1581 screen->chip_flags |= RADEON_CLASS_R600;
1582
1583 /* r6xx+ tiling, default group bytes */
1584 if (screen->chip_family >= CHIP_FAMILY_CEDAR)
1585 screen->group_bytes = 512;
1586 else
1587 screen->group_bytes = 256;
1588 if (IS_R600_CLASS(screen) && (sPriv->drm_version.minor >= 6) &&
1589 (screen->chip_family < CHIP_FAMILY_CEDAR)) {
1590 ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
1591 if (ret)
1592 fprintf(stderr, "failed to get tiling info\n");
1593 else {
1594 screen->tile_config = temp;
1595 screen->r7xx_bank_op = 0;
1596 switch((screen->tile_config & 0xe) >> 1) {
1597 case 0:
1598 screen->num_channels = 1;
1599 break;
1600 case 1:
1601 screen->num_channels = 2;
1602 break;
1603 case 2:
1604 screen->num_channels = 4;
1605 break;
1606 case 3:
1607 screen->num_channels = 8;
1608 break;
1609 default:
1610 fprintf(stderr, "bad channels\n");
1611 break;
1612 }
1613 switch((screen->tile_config & 0x30) >> 4) {
1614 case 0:
1615 screen->num_banks = 4;
1616 break;
1617 case 1:
1618 screen->num_banks = 8;
1619 break;
1620 default:
1621 fprintf(stderr, "bad banks\n");
1622 break;
1623 }
1624 switch((screen->tile_config & 0xc0) >> 6) {
1625 case 0:
1626 screen->group_bytes = 256;
1627 break;
1628 case 1:
1629 screen->group_bytes = 512;
1630 break;
1631 default:
1632 fprintf(stderr, "bad group_bytes\n");
1633 break;
1634 }
1635 }
1636 }
1637
1638 if (IS_R300_CLASS(screen)) {
1639 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1640 if (ret) {
1641 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1642 switch (screen->chip_family) {
1643 case CHIP_FAMILY_R300:
1644 case CHIP_FAMILY_R350:
1645 screen->num_gb_pipes = 2;
1646 break;
1647 case CHIP_FAMILY_R420:
1648 case CHIP_FAMILY_R520:
1649 case CHIP_FAMILY_R580:
1650 case CHIP_FAMILY_RV560:
1651 case CHIP_FAMILY_RV570:
1652 screen->num_gb_pipes = 4;
1653 break;
1654 case CHIP_FAMILY_RV350:
1655 case CHIP_FAMILY_RV515:
1656 case CHIP_FAMILY_RV530:
1657 case CHIP_FAMILY_RV410:
1658 default:
1659 screen->num_gb_pipes = 1;
1660 break;
1661 }
1662 } else {
1663 screen->num_gb_pipes = temp;
1664 }
1665
1666 /* pipe overrides */
1667 switch (device_id) {
1668 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1669 case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */
1670 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
1671 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
1672 screen->num_gb_pipes = 1;
1673 break;
1674 default:
1675 break;
1676 }
1677
1678 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp);
1679 if (ret)
1680 screen->num_z_pipes = 2;
1681 else
1682 screen->num_z_pipes = temp;
1683
1684 }
1685
1686 i = 0;
1687 screen->extensions[i++] = &driCopySubBufferExtension.base;
1688 screen->extensions[i++] = &driReadDrawableExtension;
1689 screen->extensions[i++] = &dri2ConfigQueryExtension.base;
1690
1691 if ( screen->irq != 0 ) {
1692 screen->extensions[i++] = &driSwapControlExtension.base;
1693 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1694 }
1695
1696 #if defined(RADEON_R100)
1697 screen->extensions[i++] = &radeonTexBufferExtension.base;
1698 #endif
1699
1700 #if defined(RADEON_R200)
1701 screen->extensions[i++] = &r200TexBufferExtension.base;
1702 #endif
1703
1704 #if defined(RADEON_R300)
1705 screen->extensions[i++] = &r300TexBufferExtension.base;
1706 #endif
1707
1708 #if defined(RADEON_R600)
1709 screen->extensions[i++] = &r600TexBufferExtension.base;
1710 #endif
1711
1712 screen->extensions[i++] = &radeonFlushExtension.base;
1713 screen->extensions[i++] = &radeonImageExtension.base;
1714
1715 screen->extensions[i++] = NULL;
1716 sPriv->extensions = screen->extensions;
1717
1718 screen->driScreen = sPriv;
1719 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1720 if (screen->bom == NULL) {
1721 free(screen);
1722 return NULL;
1723 }
1724 return screen;
1725 }
1726
1727 /* Destroy the device specific screen private data struct.
1728 */
1729 static void
1730 radeonDestroyScreen( __DRIscreen *sPriv )
1731 {
1732 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1733
1734 if (!screen)
1735 return;
1736
1737 if (screen->kernel_mm) {
1738 #ifdef RADEON_BO_TRACK
1739 radeon_tracker_print(&screen->bom->tracker, stderr);
1740 #endif
1741 radeon_bo_manager_gem_dtor(screen->bom);
1742 } else {
1743 radeon_bo_manager_legacy_dtor(screen->bom);
1744
1745 if ( screen->gartTextures.map ) {
1746 drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
1747 }
1748 drmUnmapBufs( screen->buffers );
1749 drmUnmap( screen->status.map, screen->status.size );
1750 drmUnmap( screen->mmio.map, screen->mmio.size );
1751 }
1752
1753 /* free all option information */
1754 driDestroyOptionInfo (&screen->optionCache);
1755
1756 FREE( screen );
1757 sPriv->private = NULL;
1758 }
1759
1760
1761 /* Initialize the driver specific screen private data.
1762 */
1763 static GLboolean
1764 radeonInitDriver( __DRIscreen *sPriv )
1765 {
1766 if (sPriv->dri2.enabled) {
1767 sPriv->private = (void *) radeonCreateScreen2( sPriv );
1768 } else {
1769 sPriv->private = (void *) radeonCreateScreen( sPriv );
1770 }
1771 if ( !sPriv->private ) {
1772 radeonDestroyScreen( sPriv );
1773 return GL_FALSE;
1774 }
1775
1776 return GL_TRUE;
1777 }
1778
1779
1780
1781 /**
1782 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1783 *
1784 * \todo This function (and its interface) will need to be updated to support
1785 * pbuffers.
1786 */
1787 static GLboolean
1788 radeonCreateBuffer( __DRIscreen *driScrnPriv,
1789 __DRIdrawable *driDrawPriv,
1790 const struct gl_config *mesaVis,
1791 GLboolean isPixmap )
1792 {
1793 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1794
1795 const GLboolean swDepth = GL_FALSE;
1796 const GLboolean swAlpha = GL_FALSE;
1797 const GLboolean swAccum = mesaVis->accumRedBits > 0;
1798 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1799 mesaVis->depthBits != 24;
1800 gl_format rgbFormat;
1801 struct radeon_framebuffer *rfb;
1802
1803 if (isPixmap)
1804 return GL_FALSE; /* not implemented */
1805
1806 rfb = CALLOC_STRUCT(radeon_framebuffer);
1807 if (!rfb)
1808 return GL_FALSE;
1809
1810 _mesa_initialize_window_framebuffer(&rfb->base, mesaVis);
1811
1812 if (mesaVis->redBits == 5)
1813 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_RGB565 : MESA_FORMAT_RGB565_REV;
1814 else if (mesaVis->alphaBits == 0)
1815 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_XRGB8888 : MESA_FORMAT_XRGB8888_REV;
1816 else
1817 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB8888_REV;
1818
1819 /* front color renderbuffer */
1820 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1821 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base);
1822 rfb->color_rb[0]->has_surface = 1;
1823
1824 /* back color renderbuffer */
1825 if (mesaVis->doubleBufferMode) {
1826 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1827 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base);
1828 rfb->color_rb[1]->has_surface = 1;
1829 }
1830
1831 if (mesaVis->depthBits == 24) {
1832 if (mesaVis->stencilBits == 8) {
1833 struct radeon_renderbuffer *depthStencilRb =
1834 radeon_create_renderbuffer(MESA_FORMAT_S8_Z24, driDrawPriv);
1835 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base);
1836 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base);
1837 depthStencilRb->has_surface = screen->depthHasSurface;
1838 } else {
1839 /* depth renderbuffer */
1840 struct radeon_renderbuffer *depth =
1841 radeon_create_renderbuffer(MESA_FORMAT_X8_Z24, driDrawPriv);
1842 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1843 depth->has_surface = screen->depthHasSurface;
1844 }
1845 } else if (mesaVis->depthBits == 16) {
1846 /* just 16-bit depth buffer, no hw stencil */
1847 struct radeon_renderbuffer *depth =
1848 radeon_create_renderbuffer(MESA_FORMAT_Z16, driDrawPriv);
1849 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1850 depth->has_surface = screen->depthHasSurface;
1851 }
1852
1853 _mesa_add_soft_renderbuffers(&rfb->base,
1854 GL_FALSE, /* color */
1855 swDepth,
1856 swStencil,
1857 swAccum,
1858 swAlpha,
1859 GL_FALSE /* aux */);
1860 driDrawPriv->driverPrivate = (void *) rfb;
1861
1862 return (driDrawPriv->driverPrivate != NULL);
1863 }
1864
1865
1866 static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb)
1867 {
1868 struct radeon_renderbuffer *rb;
1869
1870 rb = rfb->color_rb[0];
1871 if (rb && rb->bo) {
1872 radeon_bo_unref(rb->bo);
1873 rb->bo = NULL;
1874 }
1875 rb = rfb->color_rb[1];
1876 if (rb && rb->bo) {
1877 radeon_bo_unref(rb->bo);
1878 rb->bo = NULL;
1879 }
1880 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
1881 if (rb && rb->bo) {
1882 radeon_bo_unref(rb->bo);
1883 rb->bo = NULL;
1884 }
1885 }
1886
1887 void
1888 radeonDestroyBuffer(__DRIdrawable *driDrawPriv)
1889 {
1890 struct radeon_framebuffer *rfb;
1891 if (!driDrawPriv)
1892 return;
1893
1894 rfb = (void*)driDrawPriv->driverPrivate;
1895 if (!rfb)
1896 return;
1897 radeon_cleanup_renderbuffers(rfb);
1898 _mesa_reference_framebuffer((struct gl_framebuffer **)(&(driDrawPriv->driverPrivate)), NULL);
1899 }
1900
1901
1902 /**
1903 * This is the driver specific part of the createNewScreen entry point.
1904 *
1905 * \todo maybe fold this into intelInitDriver
1906 *
1907 * \return the struct gl_config supported by this driver
1908 */
1909 static const __DRIconfig **
1910 radeonInitScreen(__DRIscreen *psp)
1911 {
1912 #if defined(RADEON_R100)
1913 static const char *driver_name = "Radeon";
1914 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1915 static const __DRIversion dri_expected = { 4, 0, 0 };
1916 static const __DRIversion drm_expected = { 1, 6, 0 };
1917 #elif defined(RADEON_R200)
1918 static const char *driver_name = "R200";
1919 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1920 static const __DRIversion dri_expected = { 4, 0, 0 };
1921 static const __DRIversion drm_expected = { 1, 6, 0 };
1922 #elif defined(RADEON_R300)
1923 static const char *driver_name = "R300";
1924 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1925 static const __DRIversion dri_expected = { 4, 0, 0 };
1926 static const __DRIversion drm_expected = { 1, 24, 0 };
1927 #elif defined(RADEON_R600)
1928 static const char *driver_name = "R600";
1929 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1930 static const __DRIversion dri_expected = { 4, 0, 0 };
1931 static const __DRIversion drm_expected = { 1, 24, 0 };
1932 #endif
1933 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1934
1935 if ( ! driCheckDriDdxDrmVersions3( driver_name,
1936 &psp->dri_version, & dri_expected,
1937 &psp->ddx_version, & ddx_expected,
1938 &psp->drm_version, & drm_expected ) ) {
1939 return NULL;
1940 }
1941
1942 if (!radeonInitDriver(psp))
1943 return NULL;
1944
1945 /* for now fill in all modes */
1946 return radeonFillInModes( psp,
1947 dri_priv->bpp,
1948 (dri_priv->bpp == 16) ? 16 : 24,
1949 (dri_priv->bpp == 16) ? 0 : 8, 1);
1950 }
1951 #define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
1952
1953 /**
1954 * This is the driver specific part of the createNewScreen entry point.
1955 * Called when using DRI2.
1956 *
1957 * \return the struct gl_config supported by this driver
1958 */
1959 static const
1960 __DRIconfig **radeonInitScreen2(__DRIscreen *psp)
1961 {
1962 GLenum fb_format[3];
1963 GLenum fb_type[3];
1964 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
1965 * support pageflipping at all.
1966 */
1967 static const GLenum back_buffer_modes[] = {
1968 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/
1969 };
1970 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
1971 int color;
1972 __DRIconfig **configs = NULL;
1973
1974 if (!radeonInitDriver(psp)) {
1975 return NULL;
1976 }
1977 depth_bits[0] = 0;
1978 stencil_bits[0] = 0;
1979 depth_bits[1] = 16;
1980 stencil_bits[1] = 0;
1981 depth_bits[2] = 24;
1982 stencil_bits[2] = 0;
1983 depth_bits[3] = 24;
1984 stencil_bits[3] = 8;
1985
1986 msaa_samples_array[0] = 0;
1987
1988 fb_format[0] = GL_RGB;
1989 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5;
1990
1991 fb_format[1] = GL_BGR;
1992 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV;
1993
1994 fb_format[2] = GL_BGRA;
1995 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
1996
1997 for (color = 0; color < ARRAY_SIZE(fb_format); color++) {
1998 __DRIconfig **new_configs;
1999
2000 new_configs = driCreateConfigs(fb_format[color], fb_type[color],
2001 depth_bits,
2002 stencil_bits,
2003 ARRAY_SIZE(depth_bits),
2004 back_buffer_modes,
2005 ARRAY_SIZE(back_buffer_modes),
2006 msaa_samples_array,
2007 ARRAY_SIZE(msaa_samples_array),
2008 GL_TRUE);
2009 if (configs == NULL)
2010 configs = new_configs;
2011 else
2012 configs = driConcatConfigs(configs, new_configs);
2013 }
2014
2015 if (configs == NULL) {
2016 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
2017 __LINE__);
2018 return NULL;
2019 }
2020
2021 return (const __DRIconfig **)configs;
2022 }
2023
2024 /**
2025 * Get information about previous buffer swaps.
2026 */
2027 static int
2028 getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo )
2029 {
2030 struct radeon_framebuffer *rfb;
2031
2032 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
2033 || (dPriv->driContextPriv->driverPrivate == NULL)
2034 || (sInfo == NULL) ) {
2035 return -1;
2036 }
2037
2038 rfb = dPriv->driverPrivate;
2039 sInfo->swap_count = rfb->swap_count;
2040 sInfo->swap_ust = rfb->swap_ust;
2041 sInfo->swap_missed_count = rfb->swap_missed_count;
2042
2043 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
2044 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust )
2045 : 0.0;
2046
2047 return 0;
2048 }
2049
2050 const struct __DriverAPIRec driDriverAPI = {
2051 .InitScreen = radeonInitScreen,
2052 .DestroyScreen = radeonDestroyScreen,
2053 #if defined(RADEON_R200)
2054 .CreateContext = r200CreateContext,
2055 .DestroyContext = r200DestroyContext,
2056 #elif defined(RADEON_R600)
2057 .CreateContext = r600CreateContext,
2058 .DestroyContext = radeonDestroyContext,
2059 #elif defined(RADEON_R300)
2060 .CreateContext = r300CreateContext,
2061 .DestroyContext = radeonDestroyContext,
2062 #else
2063 .CreateContext = r100CreateContext,
2064 .DestroyContext = radeonDestroyContext,
2065 #endif
2066 .CreateBuffer = radeonCreateBuffer,
2067 .DestroyBuffer = radeonDestroyBuffer,
2068 .SwapBuffers = radeonSwapBuffers,
2069 .MakeCurrent = radeonMakeCurrent,
2070 .UnbindContext = radeonUnbindContext,
2071 .GetSwapInfo = getSwapInfo,
2072 .GetDrawableMSC = driDrawableGetMSC32,
2073 .WaitForMSC = driWaitForMSC32,
2074 .WaitForSBC = NULL,
2075 .SwapBuffersMSC = NULL,
2076 .CopySubBuffer = radeonCopySubBuffer,
2077 /* DRI2 */
2078 .InitScreen2 = radeonInitScreen2,
2079 };
2080
2081 /* This is the table of extensions that the loader will dlsym() for. */
2082 PUBLIC const __DRIextension *__driDriverExtensions[] = {
2083 &driCoreExtension.base,
2084 &driLegacyExtension.base,
2085 &driDRI2Extension.base,
2086 NULL
2087 };