1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
44 #include "main/fbobject.h"
45 #include "swrast/s_renderbuffer.h"
47 #include "radeon_chipset.h"
48 #include "radeon_screen.h"
49 #include "radeon_common.h"
50 #include "radeon_common_context.h"
51 #if defined(RADEON_R100)
52 #include "radeon_context.h"
53 #include "radeon_tex.h"
54 #elif defined(RADEON_R200)
55 #include "r200_context.h"
61 #include "GL/internal/dri_interface.h"
63 /* Radeon configuration
65 #include "util/xmlpool.h"
67 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
68 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
69 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
70 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
73 #define DRI_CONF_MAX_TEXTURE_UNITS(def,min,max) \
74 DRI_CONF_OPT_BEGIN_V(texture_units,int,def, # min ":" # max ) \
75 DRI_CONF_DESC(en,"Number of texture units used") \
78 #define DRI_CONF_HYPERZ(def) \
79 DRI_CONF_OPT_BEGIN_B(hyperz, def) \
80 DRI_CONF_DESC(en,"Use HyperZ to boost performance") \
83 #if defined(RADEON_R100) /* R100 */
84 static const __DRIconfigOptionsExtension radeon_config_options
= {
85 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
88 DRI_CONF_SECTION_PERFORMANCE
89 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
90 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
91 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
92 DRI_CONF_HYPERZ("false")
93 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
95 DRI_CONF_SECTION_QUALITY
96 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
97 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
98 DRI_CONF_NO_NEG_LOD_BIAS("false")
99 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
100 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
101 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
106 #elif defined(RADEON_R200)
108 #define DRI_CONF_TEXTURE_BLEND_QUALITY(def,range) \
109 DRI_CONF_OPT_BEGIN_V(texture_blend_quality,float,def,range) \
110 DRI_CONF_DESC(en,"Texture filtering quality vs. speed, AKA “brilinear” texture filtering") \
113 static const __DRIconfigOptionsExtension radeon_config_options
= {
114 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
117 DRI_CONF_SECTION_PERFORMANCE
118 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
119 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
120 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
121 DRI_CONF_HYPERZ("false")
122 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
124 DRI_CONF_SECTION_QUALITY
125 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
126 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
127 DRI_CONF_NO_NEG_LOD_BIAS("false")
128 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
129 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
130 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
131 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
138 radeonGetParam(__DRIscreen
*sPriv
, int param
, void *value
)
140 struct drm_radeon_info info
= { 0 };
142 info
.value
= (uint64_t)(uintptr_t)value
;
144 case RADEON_PARAM_DEVICE_ID
:
145 info
.request
= RADEON_INFO_DEVICE_ID
;
147 case RADEON_PARAM_NUM_GB_PIPES
:
148 info
.request
= RADEON_INFO_NUM_GB_PIPES
;
150 case RADEON_PARAM_NUM_Z_PIPES
:
151 info
.request
= RADEON_INFO_NUM_Z_PIPES
;
153 case RADEON_INFO_TILING_CONFIG
:
154 info
.request
= RADEON_INFO_TILING_CONFIG
;
159 return drmCommandWriteRead(sPriv
->fd
, DRM_RADEON_INFO
, &info
, sizeof(info
));
162 #if defined(RADEON_R100)
163 static const __DRItexBufferExtension radeonTexBufferExtension
= {
164 .base
= { __DRI_TEX_BUFFER
, 3 },
166 .setTexBuffer
= radeonSetTexBuffer
,
167 .setTexBuffer2
= radeonSetTexBuffer2
,
168 .releaseTexBuffer
= NULL
,
170 #elif defined(RADEON_R200)
171 static const __DRItexBufferExtension r200TexBufferExtension
= {
172 .base
= { __DRI_TEX_BUFFER
, 3 },
174 .setTexBuffer
= r200SetTexBuffer
,
175 .setTexBuffer2
= r200SetTexBuffer2
,
176 .releaseTexBuffer
= NULL
,
181 radeonDRI2Flush(__DRIdrawable
*drawable
)
183 radeonContextPtr rmesa
;
185 rmesa
= (radeonContextPtr
) drawable
->driContextPriv
->driverPrivate
;
186 radeonFlush(&rmesa
->glCtx
);
189 static const struct __DRI2flushExtensionRec radeonFlushExtension
= {
190 .base
= { __DRI2_FLUSH
, 3 },
192 .flush
= radeonDRI2Flush
,
193 .invalidate
= dri2InvalidateDrawable
,
197 radeon_create_image_from_name(__DRIscreen
*screen
,
198 int width
, int height
, int format
,
199 int name
, int pitch
, void *loaderPrivate
)
202 radeonScreenPtr radeonScreen
= screen
->driverPrivate
;
207 image
= calloc(1, sizeof *image
);
212 case __DRI_IMAGE_FORMAT_RGB565
:
213 image
->format
= MESA_FORMAT_B5G6R5_UNORM
;
214 image
->internal_format
= GL_RGB
;
215 image
->data_type
= GL_UNSIGNED_BYTE
;
217 case __DRI_IMAGE_FORMAT_XRGB8888
:
218 image
->format
= MESA_FORMAT_B8G8R8X8_UNORM
;
219 image
->internal_format
= GL_RGB
;
220 image
->data_type
= GL_UNSIGNED_BYTE
;
222 case __DRI_IMAGE_FORMAT_ARGB8888
:
223 image
->format
= MESA_FORMAT_B8G8R8A8_UNORM
;
224 image
->internal_format
= GL_RGBA
;
225 image
->data_type
= GL_UNSIGNED_BYTE
;
232 image
->data
= loaderPrivate
;
233 image
->cpp
= _mesa_get_format_bytes(image
->format
);
234 image
->width
= width
;
235 image
->pitch
= pitch
;
236 image
->height
= height
;
238 image
->bo
= radeon_bo_open(radeonScreen
->bom
,
240 image
->pitch
* image
->height
* image
->cpp
,
242 RADEON_GEM_DOMAIN_VRAM
,
245 if (image
->bo
== NULL
) {
254 radeon_create_image_from_renderbuffer(__DRIcontext
*context
,
255 int renderbuffer
, void *loaderPrivate
)
258 radeonContextPtr radeon
= context
->driverPrivate
;
259 struct gl_renderbuffer
*rb
;
260 struct radeon_renderbuffer
*rrb
;
262 rb
= _mesa_lookup_renderbuffer(&radeon
->glCtx
, renderbuffer
);
264 _mesa_error(&radeon
->glCtx
,
265 GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
269 rrb
= radeon_renderbuffer(rb
);
270 image
= calloc(1, sizeof *image
);
274 image
->internal_format
= rb
->InternalFormat
;
275 image
->format
= rb
->Format
;
276 image
->cpp
= rrb
->cpp
;
277 image
->data_type
= GL_UNSIGNED_BYTE
;
278 image
->data
= loaderPrivate
;
279 radeon_bo_ref(rrb
->bo
);
282 image
->width
= rb
->Width
;
283 image
->height
= rb
->Height
;
284 image
->pitch
= rrb
->pitch
/ image
->cpp
;
290 radeon_destroy_image(__DRIimage
*image
)
292 radeon_bo_unref(image
->bo
);
297 radeon_create_image(__DRIscreen
*screen
,
298 int width
, int height
, int format
,
303 radeonScreenPtr radeonScreen
= screen
->driverPrivate
;
305 image
= calloc(1, sizeof *image
);
309 image
->dri_format
= format
;
312 case __DRI_IMAGE_FORMAT_RGB565
:
313 image
->format
= MESA_FORMAT_B5G6R5_UNORM
;
314 image
->internal_format
= GL_RGB
;
315 image
->data_type
= GL_UNSIGNED_BYTE
;
317 case __DRI_IMAGE_FORMAT_XRGB8888
:
318 image
->format
= MESA_FORMAT_B8G8R8X8_UNORM
;
319 image
->internal_format
= GL_RGB
;
320 image
->data_type
= GL_UNSIGNED_BYTE
;
322 case __DRI_IMAGE_FORMAT_ARGB8888
:
323 image
->format
= MESA_FORMAT_B8G8R8A8_UNORM
;
324 image
->internal_format
= GL_RGBA
;
325 image
->data_type
= GL_UNSIGNED_BYTE
;
332 image
->data
= loaderPrivate
;
333 image
->cpp
= _mesa_get_format_bytes(image
->format
);
334 image
->width
= width
;
335 image
->height
= height
;
336 image
->pitch
= ((image
->cpp
* image
->width
+ 255) & ~255) / image
->cpp
;
338 image
->bo
= radeon_bo_open(radeonScreen
->bom
,
340 image
->pitch
* image
->height
* image
->cpp
,
342 RADEON_GEM_DOMAIN_VRAM
,
345 if (image
->bo
== NULL
) {
354 radeon_query_image(__DRIimage
*image
, int attrib
, int *value
)
357 case __DRI_IMAGE_ATTRIB_STRIDE
:
358 *value
= image
->pitch
* image
->cpp
;
360 case __DRI_IMAGE_ATTRIB_HANDLE
:
361 *value
= image
->bo
->handle
;
363 case __DRI_IMAGE_ATTRIB_NAME
:
364 radeon_gem_get_kernel_name(image
->bo
, (uint32_t *) value
);
371 static const __DRIimageExtension radeonImageExtension
= {
372 .base
= { __DRI_IMAGE
, 1 },
374 .createImageFromName
= radeon_create_image_from_name
,
375 .createImageFromRenderbuffer
= radeon_create_image_from_renderbuffer
,
376 .destroyImage
= radeon_destroy_image
,
377 .createImage
= radeon_create_image
,
378 .queryImage
= radeon_query_image
381 static int radeon_set_screen_flags(radeonScreenPtr screen
, int device_id
)
383 screen
->device_id
= device_id
;
384 screen
->chip_flags
= 0;
385 switch ( device_id
) {
386 #if defined(RADEON_R100)
387 case PCI_CHIP_RN50_515E
:
388 case PCI_CHIP_RN50_5969
:
391 case PCI_CHIP_RADEON_LY
:
392 case PCI_CHIP_RADEON_LZ
:
393 case PCI_CHIP_RADEON_QY
:
394 case PCI_CHIP_RADEON_QZ
:
395 screen
->chip_family
= CHIP_FAMILY_RV100
;
398 case PCI_CHIP_RS100_4136
:
399 case PCI_CHIP_RS100_4336
:
400 screen
->chip_family
= CHIP_FAMILY_RS100
;
403 case PCI_CHIP_RS200_4137
:
404 case PCI_CHIP_RS200_4337
:
405 case PCI_CHIP_RS250_4237
:
406 case PCI_CHIP_RS250_4437
:
407 screen
->chip_family
= CHIP_FAMILY_RS200
;
410 case PCI_CHIP_RADEON_QD
:
411 case PCI_CHIP_RADEON_QE
:
412 case PCI_CHIP_RADEON_QF
:
413 case PCI_CHIP_RADEON_QG
:
414 /* all original radeons (7200) presumably have a stencil op bug */
415 screen
->chip_family
= CHIP_FAMILY_R100
;
416 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_BROKEN_STENCIL
| RADEON_CHIPSET_DEPTH_ALWAYS_TILED
;
419 case PCI_CHIP_RV200_QW
:
420 case PCI_CHIP_RV200_QX
:
421 case PCI_CHIP_RADEON_LW
:
422 case PCI_CHIP_RADEON_LX
:
423 screen
->chip_family
= CHIP_FAMILY_RV200
;
424 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_DEPTH_ALWAYS_TILED
;
427 #elif defined(RADEON_R200)
428 case PCI_CHIP_R200_BB
:
429 case PCI_CHIP_R200_QH
:
430 case PCI_CHIP_R200_QL
:
431 case PCI_CHIP_R200_QM
:
432 screen
->chip_family
= CHIP_FAMILY_R200
;
433 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_DEPTH_ALWAYS_TILED
;
436 case PCI_CHIP_RV250_If
:
437 case PCI_CHIP_RV250_Ig
:
438 case PCI_CHIP_RV250_Ld
:
439 case PCI_CHIP_RV250_Lf
:
440 case PCI_CHIP_RV250_Lg
:
441 screen
->chip_family
= CHIP_FAMILY_RV250
;
442 screen
->chip_flags
= R200_CHIPSET_YCBCR_BROKEN
| RADEON_CHIPSET_TCL
| RADEON_CHIPSET_DEPTH_ALWAYS_TILED
;
445 case PCI_CHIP_RV280_4C6E
:
446 case PCI_CHIP_RV280_5960
:
447 case PCI_CHIP_RV280_5961
:
448 case PCI_CHIP_RV280_5962
:
449 case PCI_CHIP_RV280_5964
:
450 case PCI_CHIP_RV280_5965
:
451 case PCI_CHIP_RV280_5C61
:
452 case PCI_CHIP_RV280_5C63
:
453 screen
->chip_family
= CHIP_FAMILY_RV280
;
454 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_DEPTH_ALWAYS_TILED
;
457 case PCI_CHIP_RS300_5834
:
458 case PCI_CHIP_RS300_5835
:
459 case PCI_CHIP_RS350_7834
:
460 case PCI_CHIP_RS350_7835
:
461 screen
->chip_family
= CHIP_FAMILY_RS300
;
462 screen
->chip_flags
= RADEON_CHIPSET_DEPTH_ALWAYS_TILED
;
467 fprintf(stderr
, "unknown chip id 0x%x, can't guess.\n",
476 radeonQueryRendererInteger(__DRIscreen
*psp
, int param
,
479 radeonScreenPtr screen
= (radeonScreenPtr
)psp
->driverPrivate
;
482 case __DRI2_RENDERER_VENDOR_ID
:
485 case __DRI2_RENDERER_DEVICE_ID
:
486 value
[0] = screen
->device_id
;
488 case __DRI2_RENDERER_ACCELERATED
:
491 case __DRI2_RENDERER_VIDEO_MEMORY
: {
492 struct drm_radeon_gem_info gem_info
;
494 memset(&gem_info
, 0, sizeof(gem_info
));
497 retval
= drmCommandWriteRead(psp
->fd
, DRM_RADEON_GEM_INFO
, &gem_info
,
501 fprintf(stderr
, "radeon: Failed to get MM info, error number %d\n",
506 /* XXX: Do we want to return vram_size or vram_visible ? */
507 value
[0] = gem_info
.vram_size
>> 20;
510 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
514 return driQueryRendererIntegerCommon(psp
, param
, value
);
519 radeonQueryRendererString(__DRIscreen
*psp
, int param
, const char **value
)
521 radeonScreenPtr screen
= (radeonScreenPtr
)psp
->driverPrivate
;
524 case __DRI2_RENDERER_VENDOR_ID
:
525 value
[0] = radeonVendorString
;
527 case __DRI2_RENDERER_DEVICE_ID
:
528 value
[0] = radeonGetRendererString(screen
);
535 static const __DRI2rendererQueryExtension radeonRendererQueryExtension
= {
536 .base
= { __DRI2_RENDERER_QUERY
, 1 },
538 .queryInteger
= radeonQueryRendererInteger
,
539 .queryString
= radeonQueryRendererString
543 static const __DRIextension
*radeon_screen_extensions
[] = {
544 &dri2ConfigQueryExtension
.base
,
545 #if defined(RADEON_R100)
546 &radeonTexBufferExtension
.base
,
547 #elif defined(RADEON_R200)
548 &r200TexBufferExtension
.base
,
550 &radeonFlushExtension
.base
,
551 &radeonImageExtension
.base
,
552 &radeonRendererQueryExtension
.base
,
553 &dri2NoErrorExtension
.base
,
557 static radeonScreenPtr
558 radeonCreateScreen2(__DRIscreen
*sPriv
)
560 radeonScreenPtr screen
;
562 uint32_t device_id
= 0;
564 /* Allocate the private area */
565 screen
= calloc(1, sizeof(*screen
));
567 fprintf(stderr
, "%s: Could not allocate memory for screen structure", __func__
);
568 fprintf(stderr
, "leaving here\n");
574 /* parse information in __driConfigOptions */
575 driParseOptionInfo (&screen
->optionCache
, radeon_config_options
.xml
);
577 screen
->chip_flags
= 0;
581 ret
= radeonGetParam(sPriv
, RADEON_PARAM_DEVICE_ID
, &device_id
);
584 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret
);
588 ret
= radeon_set_screen_flags(screen
, device_id
);
594 if (getenv("RADEON_NO_TCL"))
595 screen
->chip_flags
&= ~RADEON_CHIPSET_TCL
;
597 sPriv
->extensions
= radeon_screen_extensions
;
599 screen
->driScreen
= sPriv
;
600 screen
->bom
= radeon_bo_manager_gem_ctor(sPriv
->fd
);
601 if (screen
->bom
== NULL
) {
608 /* Destroy the device specific screen private data struct.
611 radeonDestroyScreen( __DRIscreen
*sPriv
)
613 radeonScreenPtr screen
= (radeonScreenPtr
)sPriv
->driverPrivate
;
618 #ifdef RADEON_BO_TRACK
619 radeon_tracker_print(&screen
->bom
->tracker
, stderr
);
621 radeon_bo_manager_gem_dtor(screen
->bom
);
623 /* free all option information */
624 driDestroyOptionInfo (&screen
->optionCache
);
627 sPriv
->driverPrivate
= NULL
;
631 /* Initialize the driver specific screen private data.
634 radeonInitDriver( __DRIscreen
*sPriv
)
636 sPriv
->driverPrivate
= (void *) radeonCreateScreen2( sPriv
);
637 if ( !sPriv
->driverPrivate
) {
638 radeonDestroyScreen( sPriv
);
648 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
650 * \todo This function (and its interface) will need to be updated to support
654 radeonCreateBuffer( __DRIscreen
*driScrnPriv
,
655 __DRIdrawable
*driDrawPriv
,
656 const struct gl_config
*mesaVis
,
659 radeonScreenPtr screen
= (radeonScreenPtr
) driScrnPriv
->driverPrivate
;
661 const GLboolean swDepth
= GL_FALSE
;
662 const GLboolean swAlpha
= GL_FALSE
;
663 const GLboolean swAccum
= mesaVis
->accumRedBits
> 0;
664 const GLboolean swStencil
= mesaVis
->stencilBits
> 0 &&
665 mesaVis
->depthBits
!= 24;
666 mesa_format rgbFormat
;
667 struct radeon_framebuffer
*rfb
;
670 return GL_FALSE
; /* not implemented */
672 rfb
= CALLOC_STRUCT(radeon_framebuffer
);
676 _mesa_initialize_window_framebuffer(&rfb
->base
, mesaVis
);
678 if (mesaVis
->redBits
== 5)
679 rgbFormat
= _mesa_little_endian() ? MESA_FORMAT_B5G6R5_UNORM
: MESA_FORMAT_R5G6B5_UNORM
;
680 else if (mesaVis
->alphaBits
== 0)
681 rgbFormat
= _mesa_little_endian() ? MESA_FORMAT_B8G8R8X8_UNORM
: MESA_FORMAT_X8R8G8B8_UNORM
;
683 rgbFormat
= _mesa_little_endian() ? MESA_FORMAT_B8G8R8A8_UNORM
: MESA_FORMAT_A8R8G8B8_UNORM
;
685 /* front color renderbuffer */
686 rfb
->color_rb
[0] = radeon_create_renderbuffer(rgbFormat
, driDrawPriv
);
687 _mesa_attach_and_own_rb(&rfb
->base
, BUFFER_FRONT_LEFT
, &rfb
->color_rb
[0]->base
.Base
);
688 rfb
->color_rb
[0]->has_surface
= 1;
690 /* back color renderbuffer */
691 if (mesaVis
->doubleBufferMode
) {
692 rfb
->color_rb
[1] = radeon_create_renderbuffer(rgbFormat
, driDrawPriv
);
693 _mesa_attach_and_own_rb(&rfb
->base
, BUFFER_BACK_LEFT
, &rfb
->color_rb
[1]->base
.Base
);
694 rfb
->color_rb
[1]->has_surface
= 1;
697 if (mesaVis
->depthBits
== 24) {
698 if (mesaVis
->stencilBits
== 8) {
699 struct radeon_renderbuffer
*depthStencilRb
=
700 radeon_create_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
, driDrawPriv
);
701 _mesa_attach_and_own_rb(&rfb
->base
, BUFFER_DEPTH
, &depthStencilRb
->base
.Base
);
702 _mesa_attach_and_reference_rb(&rfb
->base
, BUFFER_STENCIL
, &depthStencilRb
->base
.Base
);
703 depthStencilRb
->has_surface
= screen
->depthHasSurface
;
705 /* depth renderbuffer */
706 struct radeon_renderbuffer
*depth
=
707 radeon_create_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
, driDrawPriv
);
708 _mesa_attach_and_own_rb(&rfb
->base
, BUFFER_DEPTH
, &depth
->base
.Base
);
709 depth
->has_surface
= screen
->depthHasSurface
;
711 } else if (mesaVis
->depthBits
== 16) {
712 /* just 16-bit depth buffer, no hw stencil */
713 struct radeon_renderbuffer
*depth
=
714 radeon_create_renderbuffer(MESA_FORMAT_Z_UNORM16
, driDrawPriv
);
715 _mesa_attach_and_own_rb(&rfb
->base
, BUFFER_DEPTH
, &depth
->base
.Base
);
716 depth
->has_surface
= screen
->depthHasSurface
;
719 _swrast_add_soft_renderbuffers(&rfb
->base
,
720 GL_FALSE
, /* color */
726 driDrawPriv
->driverPrivate
= (void *) rfb
;
728 return (driDrawPriv
->driverPrivate
!= NULL
);
732 static void radeon_cleanup_renderbuffers(struct radeon_framebuffer
*rfb
)
734 struct radeon_renderbuffer
*rb
;
736 rb
= rfb
->color_rb
[0];
738 radeon_bo_unref(rb
->bo
);
741 rb
= rfb
->color_rb
[1];
743 radeon_bo_unref(rb
->bo
);
746 rb
= radeon_get_renderbuffer(&rfb
->base
, BUFFER_DEPTH
);
748 radeon_bo_unref(rb
->bo
);
754 radeonDestroyBuffer(__DRIdrawable
*driDrawPriv
)
756 struct radeon_framebuffer
*rfb
;
760 rfb
= (void*)driDrawPriv
->driverPrivate
;
763 radeon_cleanup_renderbuffers(rfb
);
764 _mesa_reference_framebuffer((struct gl_framebuffer
**)(&(driDrawPriv
->driverPrivate
)), NULL
);
768 * This is the driver specific part of the createNewScreen entry point.
769 * Called when using DRI2.
771 * \return the struct gl_config supported by this driver
774 __DRIconfig
**radeonInitScreen2(__DRIscreen
*psp
)
776 static const mesa_format formats
[3] = {
777 MESA_FORMAT_B5G6R5_UNORM
,
778 MESA_FORMAT_B8G8R8X8_UNORM
,
779 MESA_FORMAT_B8G8R8A8_UNORM
782 static const GLenum back_buffer_modes
[] = {
783 __DRI_ATTRIB_SWAP_NONE
, __DRI_ATTRIB_SWAP_UNDEFINED
785 uint8_t depth_bits
[4], stencil_bits
[4], msaa_samples_array
[1];
787 __DRIconfig
**configs
= NULL
;
789 psp
->max_gl_compat_version
= 13;
790 psp
->max_gl_es1_version
= 11;
792 if (!radeonInitDriver(psp
)) {
804 msaa_samples_array
[0] = 0;
806 for (color
= 0; color
< ARRAY_SIZE(formats
); color
++) {
807 __DRIconfig
**new_configs
;
809 new_configs
= driCreateConfigs(formats
[color
],
812 ARRAY_SIZE(depth_bits
),
814 ARRAY_SIZE(back_buffer_modes
),
816 ARRAY_SIZE(msaa_samples_array
),
817 GL_TRUE
, GL_FALSE
, GL_FALSE
);
818 configs
= driConcatConfigs(configs
, new_configs
);
821 if (configs
== NULL
) {
822 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
827 return (const __DRIconfig
**)configs
;
830 static const struct __DriverAPIRec radeon_driver_api
= {
831 .InitScreen
= radeonInitScreen2
,
832 .DestroyScreen
= radeonDestroyScreen
,
833 #if defined(RADEON_R200)
834 .CreateContext
= r200CreateContext
,
835 .DestroyContext
= r200DestroyContext
,
837 .CreateContext
= r100CreateContext
,
838 .DestroyContext
= radeonDestroyContext
,
840 .CreateBuffer
= radeonCreateBuffer
,
841 .DestroyBuffer
= radeonDestroyBuffer
,
842 .MakeCurrent
= radeonMakeCurrent
,
843 .UnbindContext
= radeonUnbindContext
,
846 static const struct __DRIDriverVtableExtensionRec radeon_vtable
= {
847 .base
= { __DRI_DRIVER_VTABLE
, 1 },
848 .vtable
= &radeon_driver_api
,
851 /* This is the table of extensions that the loader will dlsym() for. */
852 static const __DRIextension
*radeon_driver_extensions
[] = {
853 &driCoreExtension
.base
,
854 &driDRI2Extension
.base
,
855 &radeon_config_options
.base
,
861 PUBLIC
const __DRIextension
**__driDriverGetExtensions_r200(void)
863 globalDriverAPI
= &radeon_driver_api
;
865 return radeon_driver_extensions
;
868 PUBLIC
const __DRIextension
**__driDriverGetExtensions_radeon(void)
870 globalDriverAPI
= &radeon_driver_api
;
872 return radeon_driver_extensions
;