1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #include "radeon_common.h"
50 #include "radeon_span.h"
52 #include "radeon_context.h"
53 #include "radeon_tex.h"
54 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
55 #include "r200_context.h"
56 #include "r200_ioctl.h"
58 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
59 #include "r300_context.h"
60 #include "r300_fragprog.h"
66 #include "drirenderbuffer.h"
68 #include "radeon_bocs_wrapper.h"
70 #include "GL/internal/dri_interface.h"
72 /* Radeon configuration
76 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
77 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
78 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
79 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
82 #if !RADEON_COMMON /* R100 */
83 PUBLIC
const char __driConfigOptions
[] =
85 DRI_CONF_SECTION_PERFORMANCE
86 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
87 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
88 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
89 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
90 DRI_CONF_HYPERZ(false)
91 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
93 DRI_CONF_SECTION_QUALITY
94 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
95 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
96 DRI_CONF_NO_NEG_LOD_BIAS(false)
97 DRI_CONF_FORCE_S3TC_ENABLE(false)
98 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
99 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
100 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
101 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
103 DRI_CONF_SECTION_DEBUG
104 DRI_CONF_NO_RAST(false)
107 static const GLuint __driNConfigOptions
= 15;
109 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
111 PUBLIC
const char __driConfigOptions
[] =
113 DRI_CONF_SECTION_PERFORMANCE
114 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
115 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
116 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
117 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
118 DRI_CONF_HYPERZ(false)
119 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
121 DRI_CONF_SECTION_QUALITY
122 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
123 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
124 DRI_CONF_NO_NEG_LOD_BIAS(false)
125 DRI_CONF_FORCE_S3TC_ENABLE(false)
126 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
127 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
128 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
129 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
130 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
132 DRI_CONF_SECTION_DEBUG
133 DRI_CONF_NO_RAST(false)
135 DRI_CONF_SECTION_SOFTWARE
136 DRI_CONF_NV_VERTEX_PROGRAM(false)
139 static const GLuint __driNConfigOptions
= 17;
141 extern const struct dri_extension blend_extensions
[];
142 extern const struct dri_extension ARB_vp_extension
[];
143 extern const struct dri_extension NV_vp_extension
[];
144 extern const struct dri_extension ATI_fs_extension
[];
145 extern const struct dri_extension point_extensions
[];
147 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
149 /* TODO: integrate these into xmlpool.h! */
150 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
151 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
152 DRI_CONF_DESC(en,"Number of texture image units") \
153 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
156 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
157 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
158 DRI_CONF_DESC(en,"Number of texture coordinate units") \
159 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
164 #define DRI_CONF_DISABLE_S3TC(def) \
165 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
166 DRI_CONF_DESC(en,"Disable S3TC compression") \
169 #define DRI_CONF_DISABLE_FALLBACK(def) \
170 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
171 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
174 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
175 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
176 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
179 #define DRI_CONF_FP_OPTIMIZATION(def) \
180 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
181 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
182 DRI_CONF_ENUM(0,"Optimize for Speed") \
183 DRI_CONF_ENUM(1,"Optimize for Quality") \
187 PUBLIC
const char __driConfigOptions
[] =
189 DRI_CONF_SECTION_PERFORMANCE
190 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
191 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
192 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
193 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
194 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
195 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
196 DRI_CONF_DISABLE_FALLBACK(true)
197 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
199 DRI_CONF_SECTION_QUALITY
200 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
201 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
202 DRI_CONF_FORCE_S3TC_ENABLE(false)
203 DRI_CONF_DISABLE_S3TC(false)
204 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
205 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
206 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
207 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED
)
209 DRI_CONF_SECTION_DEBUG
210 DRI_CONF_NO_RAST(false)
213 static const GLuint __driNConfigOptions
= 17;
215 extern const struct dri_extension gl_20_extension
[];
219 static const struct dri_debug_control debug_control
[] = {
220 {"fall", DEBUG_FALLBACKS
},
221 {"tex", DEBUG_TEXTURE
},
222 {"ioctl", DEBUG_IOCTL
},
223 {"prim", DEBUG_PRIMS
},
224 {"vert", DEBUG_VERTS
},
225 {"state", DEBUG_STATE
},
226 {"code", DEBUG_CODEGEN
},
227 {"vfmt", DEBUG_VFMT
},
228 {"vtxf", DEBUG_VFMT
},
229 {"verb", DEBUG_VERBOSE
},
232 {"san", DEBUG_SANITY
},
233 {"sync", DEBUG_SYNC
},
234 {"pix", DEBUG_PIXEL
},
235 {"mem", DEBUG_MEMORY
},
236 {"allmsg", ~DEBUG_SYNC
}, /* avoid the term "sync" because the parser uses strstr */
239 #endif /* RADEON_DEBUG */
241 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
243 extern const struct dri_extension card_extensions
[];
244 extern const struct dri_extension mm_extensions
[];
246 static int getSwapInfo( __DRIdrawablePrivate
*dPriv
, __DRIswapInfo
* sInfo
);
249 radeonGetParam(__DRIscreenPrivate
*sPriv
, int param
, void *value
)
252 drm_radeon_getparam_t gp
= { 0 };
253 struct drm_radeon_info info
= { 0 };
255 if (sPriv
->drm_version
.major
>= 2) {
256 info
.value
= (uint64_t)value
;
258 case RADEON_PARAM_DEVICE_ID
:
259 info
.request
= RADEON_INFO_DEVICE_ID
;
261 case RADEON_PARAM_NUM_GB_PIPES
:
262 info
.request
= RADEON_INFO_NUM_GB_PIPES
;
267 ret
= drmCommandWriteRead(sPriv
->fd
, DRM_RADEON_INFO
, &info
, sizeof(info
));
272 ret
= drmCommandWriteRead(sPriv
->fd
, DRM_RADEON_GETPARAM
, &gp
, sizeof(gp
));
277 static const __DRIconfig
**
278 radeonFillInModes( __DRIscreenPrivate
*psp
,
279 unsigned pixel_bits
, unsigned depth_bits
,
280 unsigned stencil_bits
, GLboolean have_back_buffer
)
282 __DRIconfig
**configs
;
284 unsigned depth_buffer_factor
;
285 unsigned back_buffer_factor
;
288 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
289 * enough to add support. Basically, if a context is created with an
290 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
291 * will never be used.
293 static const GLenum back_buffer_modes
[] = {
294 GLX_NONE
, GLX_SWAP_UNDEFINED_OML
/*, GLX_SWAP_COPY_OML */
297 uint8_t depth_bits_array
[2];
298 uint8_t stencil_bits_array
[2];
299 uint8_t msaa_samples_array
[1];
301 depth_bits_array
[0] = depth_bits
;
302 depth_bits_array
[1] = depth_bits
;
304 /* Just like with the accumulation buffer, always provide some modes
305 * with a stencil buffer. It will be a sw fallback, but some apps won't
308 stencil_bits_array
[0] = 0;
309 stencil_bits_array
[1] = (stencil_bits
== 0) ? 8 : stencil_bits
;
311 msaa_samples_array
[0] = 0;
313 depth_buffer_factor
= ((depth_bits
!= 0) || (stencil_bits
!= 0)) ? 2 : 1;
314 back_buffer_factor
= (have_back_buffer
) ? 2 : 1;
316 if (pixel_bits
== 16) {
317 __DRIconfig
**configs_a8r8g8b8
;
318 __DRIconfig
**configs_r5g6b5
;
320 configs_r5g6b5
= driCreateConfigs(GL_RGB
, GL_UNSIGNED_SHORT_5_6_5
,
321 depth_bits_array
, stencil_bits_array
,
322 depth_buffer_factor
, back_buffer_modes
,
323 back_buffer_factor
, msaa_samples_array
,
325 configs_a8r8g8b8
= driCreateConfigs(GL_BGRA
, GL_UNSIGNED_INT_8_8_8_8_REV
,
326 depth_bits_array
, stencil_bits_array
,
327 1, back_buffer_modes
, 1,
328 msaa_samples_array
, 1);
329 configs
= driConcatConfigs(configs_r5g6b5
, configs_a8r8g8b8
);
331 configs
= driCreateConfigs(GL_BGRA
, GL_UNSIGNED_INT_8_8_8_8_REV
,
332 depth_bits_array
, stencil_bits_array
,
334 back_buffer_modes
, back_buffer_factor
,
335 msaa_samples_array
, 1);
337 if (configs
== NULL
) {
338 fprintf( stderr
, "[%s:%u] Error creating FBConfig!\n",
339 __func__
, __LINE__
);
343 /* Mark the visual as slow if there are "fake" stencil bits.
345 for (i
= 0; configs
[i
]; i
++) {
346 m
= &configs
[i
]->modes
;
347 if ((m
->stencilBits
!= 0) && (m
->stencilBits
!= stencil_bits
)) {
348 m
->visualRating
= GLX_SLOW_CONFIG
;
352 return (const __DRIconfig
**) configs
;
356 static const __DRItexOffsetExtension radeonTexOffsetExtension
= {
357 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
361 static const __DRItexBufferExtension radeonTexBufferExtension
= {
362 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
368 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
369 static const __DRIallocateExtension r200AllocateExtension
= {
370 { __DRI_ALLOCATE
, __DRI_ALLOCATE_VERSION
},
371 r200AllocateMemoryMESA
,
373 r200GetMemoryOffsetMESA
376 static const __DRItexOffsetExtension r200texOffsetExtension
= {
377 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
381 static const __DRItexBufferExtension r200TexBufferExtension
= {
382 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
388 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
389 static const __DRItexOffsetExtension r300texOffsetExtension
= {
390 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
394 static const __DRItexBufferExtension r300TexBufferExtension
= {
395 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
401 static int radeon_set_screen_flags(radeonScreenPtr screen
, int device_id
)
403 screen
->chip_flags
= 0;
404 switch ( device_id
) {
405 case PCI_CHIP_RADEON_LY
:
406 case PCI_CHIP_RADEON_LZ
:
407 case PCI_CHIP_RADEON_QY
:
408 case PCI_CHIP_RADEON_QZ
:
409 case PCI_CHIP_RN50_515E
:
410 case PCI_CHIP_RN50_5969
:
411 screen
->chip_family
= CHIP_FAMILY_RV100
;
414 case PCI_CHIP_RS100_4136
:
415 case PCI_CHIP_RS100_4336
:
416 screen
->chip_family
= CHIP_FAMILY_RS100
;
419 case PCI_CHIP_RS200_4137
:
420 case PCI_CHIP_RS200_4337
:
421 case PCI_CHIP_RS250_4237
:
422 case PCI_CHIP_RS250_4437
:
423 screen
->chip_family
= CHIP_FAMILY_RS200
;
426 case PCI_CHIP_RADEON_QD
:
427 case PCI_CHIP_RADEON_QE
:
428 case PCI_CHIP_RADEON_QF
:
429 case PCI_CHIP_RADEON_QG
:
430 /* all original radeons (7200) presumably have a stencil op bug */
431 screen
->chip_family
= CHIP_FAMILY_R100
;
432 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_BROKEN_STENCIL
;
435 case PCI_CHIP_RV200_QW
:
436 case PCI_CHIP_RV200_QX
:
437 case PCI_CHIP_RADEON_LW
:
438 case PCI_CHIP_RADEON_LX
:
439 screen
->chip_family
= CHIP_FAMILY_RV200
;
440 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
443 case PCI_CHIP_R200_BB
:
444 case PCI_CHIP_R200_BC
:
445 case PCI_CHIP_R200_QH
:
446 case PCI_CHIP_R200_QL
:
447 case PCI_CHIP_R200_QM
:
448 screen
->chip_family
= CHIP_FAMILY_R200
;
449 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
452 case PCI_CHIP_RV250_If
:
453 case PCI_CHIP_RV250_Ig
:
454 case PCI_CHIP_RV250_Ld
:
455 case PCI_CHIP_RV250_Lf
:
456 case PCI_CHIP_RV250_Lg
:
457 screen
->chip_family
= CHIP_FAMILY_RV250
;
458 screen
->chip_flags
= R200_CHIPSET_YCBCR_BROKEN
| RADEON_CHIPSET_TCL
;
461 case PCI_CHIP_RV280_5960
:
462 case PCI_CHIP_RV280_5961
:
463 case PCI_CHIP_RV280_5962
:
464 case PCI_CHIP_RV280_5964
:
465 case PCI_CHIP_RV280_5965
:
466 case PCI_CHIP_RV280_5C61
:
467 case PCI_CHIP_RV280_5C63
:
468 screen
->chip_family
= CHIP_FAMILY_RV280
;
469 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
472 case PCI_CHIP_RS300_5834
:
473 case PCI_CHIP_RS300_5835
:
474 case PCI_CHIP_RS350_7834
:
475 case PCI_CHIP_RS350_7835
:
476 screen
->chip_family
= CHIP_FAMILY_RS300
;
479 case PCI_CHIP_R300_AD
:
480 case PCI_CHIP_R300_AE
:
481 case PCI_CHIP_R300_AF
:
482 case PCI_CHIP_R300_AG
:
483 case PCI_CHIP_R300_ND
:
484 case PCI_CHIP_R300_NE
:
485 case PCI_CHIP_R300_NF
:
486 case PCI_CHIP_R300_NG
:
487 screen
->chip_family
= CHIP_FAMILY_R300
;
488 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
491 case PCI_CHIP_RV350_AP
:
492 case PCI_CHIP_RV350_AQ
:
493 case PCI_CHIP_RV350_AR
:
494 case PCI_CHIP_RV350_AS
:
495 case PCI_CHIP_RV350_AT
:
496 case PCI_CHIP_RV350_AV
:
497 case PCI_CHIP_RV350_AU
:
498 case PCI_CHIP_RV350_NP
:
499 case PCI_CHIP_RV350_NQ
:
500 case PCI_CHIP_RV350_NR
:
501 case PCI_CHIP_RV350_NS
:
502 case PCI_CHIP_RV350_NT
:
503 case PCI_CHIP_RV350_NV
:
504 screen
->chip_family
= CHIP_FAMILY_RV350
;
505 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
508 case PCI_CHIP_R350_AH
:
509 case PCI_CHIP_R350_AI
:
510 case PCI_CHIP_R350_AJ
:
511 case PCI_CHIP_R350_AK
:
512 case PCI_CHIP_R350_NH
:
513 case PCI_CHIP_R350_NI
:
514 case PCI_CHIP_R360_NJ
:
515 case PCI_CHIP_R350_NK
:
516 screen
->chip_family
= CHIP_FAMILY_R350
;
517 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
520 case PCI_CHIP_RV370_5460
:
521 case PCI_CHIP_RV370_5462
:
522 case PCI_CHIP_RV370_5464
:
523 case PCI_CHIP_RV370_5B60
:
524 case PCI_CHIP_RV370_5B62
:
525 case PCI_CHIP_RV370_5B63
:
526 case PCI_CHIP_RV370_5B64
:
527 case PCI_CHIP_RV370_5B65
:
528 case PCI_CHIP_RV380_3150
:
529 case PCI_CHIP_RV380_3152
:
530 case PCI_CHIP_RV380_3154
:
531 case PCI_CHIP_RV380_3E50
:
532 case PCI_CHIP_RV380_3E54
:
533 screen
->chip_family
= CHIP_FAMILY_RV380
;
534 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
537 case PCI_CHIP_R420_JN
:
538 case PCI_CHIP_R420_JH
:
539 case PCI_CHIP_R420_JI
:
540 case PCI_CHIP_R420_JJ
:
541 case PCI_CHIP_R420_JK
:
542 case PCI_CHIP_R420_JL
:
543 case PCI_CHIP_R420_JM
:
544 case PCI_CHIP_R420_JO
:
545 case PCI_CHIP_R420_JP
:
546 case PCI_CHIP_R420_JT
:
547 case PCI_CHIP_R481_4B49
:
548 case PCI_CHIP_R481_4B4A
:
549 case PCI_CHIP_R481_4B4B
:
550 case PCI_CHIP_R481_4B4C
:
551 case PCI_CHIP_R423_UH
:
552 case PCI_CHIP_R423_UI
:
553 case PCI_CHIP_R423_UJ
:
554 case PCI_CHIP_R423_UK
:
555 case PCI_CHIP_R430_554C
:
556 case PCI_CHIP_R430_554D
:
557 case PCI_CHIP_R430_554E
:
558 case PCI_CHIP_R430_554F
:
559 case PCI_CHIP_R423_5550
:
560 case PCI_CHIP_R423_UQ
:
561 case PCI_CHIP_R423_UR
:
562 case PCI_CHIP_R423_UT
:
563 case PCI_CHIP_R430_5D48
:
564 case PCI_CHIP_R430_5D49
:
565 case PCI_CHIP_R430_5D4A
:
566 case PCI_CHIP_R480_5D4C
:
567 case PCI_CHIP_R480_5D4D
:
568 case PCI_CHIP_R480_5D4E
:
569 case PCI_CHIP_R480_5D4F
:
570 case PCI_CHIP_R480_5D50
:
571 case PCI_CHIP_R480_5D52
:
572 case PCI_CHIP_R423_5D57
:
573 screen
->chip_family
= CHIP_FAMILY_R420
;
574 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
577 case PCI_CHIP_RV410_5E4C
:
578 case PCI_CHIP_RV410_5E4F
:
579 case PCI_CHIP_RV410_564A
:
580 case PCI_CHIP_RV410_564B
:
581 case PCI_CHIP_RV410_564F
:
582 case PCI_CHIP_RV410_5652
:
583 case PCI_CHIP_RV410_5653
:
584 case PCI_CHIP_RV410_5657
:
585 case PCI_CHIP_RV410_5E48
:
586 case PCI_CHIP_RV410_5E4A
:
587 case PCI_CHIP_RV410_5E4B
:
588 case PCI_CHIP_RV410_5E4D
:
589 screen
->chip_family
= CHIP_FAMILY_RV410
;
590 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
593 case PCI_CHIP_RS480_5954
:
594 case PCI_CHIP_RS480_5955
:
595 case PCI_CHIP_RS482_5974
:
596 case PCI_CHIP_RS482_5975
:
597 case PCI_CHIP_RS400_5A41
:
598 case PCI_CHIP_RS400_5A42
:
599 case PCI_CHIP_RC410_5A61
:
600 case PCI_CHIP_RC410_5A62
:
601 screen
->chip_family
= CHIP_FAMILY_RS400
;
604 case PCI_CHIP_RS600_793F
:
605 case PCI_CHIP_RS600_7941
:
606 case PCI_CHIP_RS600_7942
:
607 screen
->chip_family
= CHIP_FAMILY_RS600
;
610 case PCI_CHIP_RS690_791E
:
611 case PCI_CHIP_RS690_791F
:
612 screen
->chip_family
= CHIP_FAMILY_RS690
;
614 case PCI_CHIP_RS740_796C
:
615 case PCI_CHIP_RS740_796D
:
616 case PCI_CHIP_RS740_796E
:
617 case PCI_CHIP_RS740_796F
:
618 screen
->chip_family
= CHIP_FAMILY_RS740
;
621 case PCI_CHIP_R520_7100
:
622 case PCI_CHIP_R520_7101
:
623 case PCI_CHIP_R520_7102
:
624 case PCI_CHIP_R520_7103
:
625 case PCI_CHIP_R520_7104
:
626 case PCI_CHIP_R520_7105
:
627 case PCI_CHIP_R520_7106
:
628 case PCI_CHIP_R520_7108
:
629 case PCI_CHIP_R520_7109
:
630 case PCI_CHIP_R520_710A
:
631 case PCI_CHIP_R520_710B
:
632 case PCI_CHIP_R520_710C
:
633 case PCI_CHIP_R520_710E
:
634 case PCI_CHIP_R520_710F
:
635 screen
->chip_family
= CHIP_FAMILY_R520
;
636 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
639 case PCI_CHIP_RV515_7140
:
640 case PCI_CHIP_RV515_7141
:
641 case PCI_CHIP_RV515_7142
:
642 case PCI_CHIP_RV515_7143
:
643 case PCI_CHIP_RV515_7144
:
644 case PCI_CHIP_RV515_7145
:
645 case PCI_CHIP_RV515_7146
:
646 case PCI_CHIP_RV515_7147
:
647 case PCI_CHIP_RV515_7149
:
648 case PCI_CHIP_RV515_714A
:
649 case PCI_CHIP_RV515_714B
:
650 case PCI_CHIP_RV515_714C
:
651 case PCI_CHIP_RV515_714D
:
652 case PCI_CHIP_RV515_714E
:
653 case PCI_CHIP_RV515_714F
:
654 case PCI_CHIP_RV515_7151
:
655 case PCI_CHIP_RV515_7152
:
656 case PCI_CHIP_RV515_7153
:
657 case PCI_CHIP_RV515_715E
:
658 case PCI_CHIP_RV515_715F
:
659 case PCI_CHIP_RV515_7180
:
660 case PCI_CHIP_RV515_7181
:
661 case PCI_CHIP_RV515_7183
:
662 case PCI_CHIP_RV515_7186
:
663 case PCI_CHIP_RV515_7187
:
664 case PCI_CHIP_RV515_7188
:
665 case PCI_CHIP_RV515_718A
:
666 case PCI_CHIP_RV515_718B
:
667 case PCI_CHIP_RV515_718C
:
668 case PCI_CHIP_RV515_718D
:
669 case PCI_CHIP_RV515_718F
:
670 case PCI_CHIP_RV515_7193
:
671 case PCI_CHIP_RV515_7196
:
672 case PCI_CHIP_RV515_719B
:
673 case PCI_CHIP_RV515_719F
:
674 case PCI_CHIP_RV515_7200
:
675 case PCI_CHIP_RV515_7210
:
676 case PCI_CHIP_RV515_7211
:
677 screen
->chip_family
= CHIP_FAMILY_RV515
;
678 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
681 case PCI_CHIP_RV530_71C0
:
682 case PCI_CHIP_RV530_71C1
:
683 case PCI_CHIP_RV530_71C2
:
684 case PCI_CHIP_RV530_71C3
:
685 case PCI_CHIP_RV530_71C4
:
686 case PCI_CHIP_RV530_71C5
:
687 case PCI_CHIP_RV530_71C6
:
688 case PCI_CHIP_RV530_71C7
:
689 case PCI_CHIP_RV530_71CD
:
690 case PCI_CHIP_RV530_71CE
:
691 case PCI_CHIP_RV530_71D2
:
692 case PCI_CHIP_RV530_71D4
:
693 case PCI_CHIP_RV530_71D5
:
694 case PCI_CHIP_RV530_71D6
:
695 case PCI_CHIP_RV530_71DA
:
696 case PCI_CHIP_RV530_71DE
:
697 screen
->chip_family
= CHIP_FAMILY_RV530
;
698 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
701 case PCI_CHIP_R580_7240
:
702 case PCI_CHIP_R580_7243
:
703 case PCI_CHIP_R580_7244
:
704 case PCI_CHIP_R580_7245
:
705 case PCI_CHIP_R580_7246
:
706 case PCI_CHIP_R580_7247
:
707 case PCI_CHIP_R580_7248
:
708 case PCI_CHIP_R580_7249
:
709 case PCI_CHIP_R580_724A
:
710 case PCI_CHIP_R580_724B
:
711 case PCI_CHIP_R580_724C
:
712 case PCI_CHIP_R580_724D
:
713 case PCI_CHIP_R580_724E
:
714 case PCI_CHIP_R580_724F
:
715 case PCI_CHIP_R580_7284
:
716 screen
->chip_family
= CHIP_FAMILY_R580
;
717 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
720 case PCI_CHIP_RV570_7280
:
721 case PCI_CHIP_RV560_7281
:
722 case PCI_CHIP_RV560_7283
:
723 case PCI_CHIP_RV560_7287
:
724 case PCI_CHIP_RV570_7288
:
725 case PCI_CHIP_RV570_7289
:
726 case PCI_CHIP_RV570_728B
:
727 case PCI_CHIP_RV570_728C
:
728 case PCI_CHIP_RV560_7290
:
729 case PCI_CHIP_RV560_7291
:
730 case PCI_CHIP_RV560_7293
:
731 case PCI_CHIP_RV560_7297
:
732 screen
->chip_family
= CHIP_FAMILY_RV560
;
733 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
737 fprintf(stderr
, "unknown chip id 0x%x, can't guess.\n",
746 /* Create the device specific screen private data struct.
748 static radeonScreenPtr
749 radeonCreateScreen( __DRIscreenPrivate
*sPriv
)
751 radeonScreenPtr screen
;
752 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
)sPriv
->pDevPriv
;
753 unsigned char *RADEONMMIO
= NULL
;
758 if (sPriv
->devPrivSize
!= sizeof(RADEONDRIRec
)) {
759 fprintf(stderr
,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
763 /* Allocate the private area */
764 screen
= (radeonScreenPtr
) CALLOC( sizeof(*screen
) );
766 __driUtilMessage("%s: Could not allocate memory for screen structure",
771 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
772 RADEON_DEBUG
= driParseDebugString(getenv("RADEON_DEBUG"), debug_control
);
775 /* parse information in __driConfigOptions */
776 driParseOptionInfo (&screen
->optionCache
,
777 __driConfigOptions
, __driNConfigOptions
);
779 /* This is first since which regions we map depends on whether or
780 * not we are using a PCI card.
782 screen
->card_type
= (dri_priv
->IsPCI
? RADEON_CARD_PCI
: RADEON_CARD_AGP
);
786 ret
= radeonGetParam(sPriv
, RADEON_PARAM_GART_BUFFER_OFFSET
,
787 &screen
->gart_buffer_offset
);
791 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret
);
795 ret
= radeonGetParam(sPriv
, RADEON_PARAM_GART_BASE
,
799 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret
);
803 ret
= radeonGetParam(sPriv
, RADEON_PARAM_IRQ_NR
,
807 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret
);
810 screen
->drmSupportsCubeMapsR200
= (sPriv
->drm_version
.minor
>= 7);
811 screen
->drmSupportsBlendColor
= (sPriv
->drm_version
.minor
>= 11);
812 screen
->drmSupportsTriPerf
= (sPriv
->drm_version
.minor
>= 16);
813 screen
->drmSupportsFragShader
= (sPriv
->drm_version
.minor
>= 18);
814 screen
->drmSupportsPointSprites
= (sPriv
->drm_version
.minor
>= 13);
815 screen
->drmSupportsCubeMapsR100
= (sPriv
->drm_version
.minor
>= 15);
816 screen
->drmSupportsVertexProgram
= (sPriv
->drm_version
.minor
>= 25);
819 screen
->mmio
.handle
= dri_priv
->registerHandle
;
820 screen
->mmio
.size
= dri_priv
->registerSize
;
821 if ( drmMap( sPriv
->fd
,
824 &screen
->mmio
.map
) ) {
826 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__
);
830 RADEONMMIO
= screen
->mmio
.map
;
832 screen
->status
.handle
= dri_priv
->statusHandle
;
833 screen
->status
.size
= dri_priv
->statusSize
;
834 if ( drmMap( sPriv
->fd
,
835 screen
->status
.handle
,
837 &screen
->status
.map
) ) {
838 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
840 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__
);
843 screen
->scratch
= (__volatile__
uint32_t *)
844 ((GLubyte
*)screen
->status
.map
+ RADEON_SCRATCH_REG_OFFSET
);
846 screen
->buffers
= drmMapBufs( sPriv
->fd
);
847 if ( !screen
->buffers
) {
848 drmUnmap( screen
->status
.map
, screen
->status
.size
);
849 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
851 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__
);
855 if ( dri_priv
->gartTexHandle
&& dri_priv
->gartTexMapSize
) {
856 screen
->gartTextures
.handle
= dri_priv
->gartTexHandle
;
857 screen
->gartTextures
.size
= dri_priv
->gartTexMapSize
;
858 if ( drmMap( sPriv
->fd
,
859 screen
->gartTextures
.handle
,
860 screen
->gartTextures
.size
,
861 (drmAddressPtr
)&screen
->gartTextures
.map
) ) {
862 drmUnmapBufs( screen
->buffers
);
863 drmUnmap( screen
->status
.map
, screen
->status
.size
);
864 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
866 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__
);
870 screen
->gart_texture_offset
= dri_priv
->gartTexOffset
+ screen
->gart_base
;
873 ret
= radeon_set_screen_flags(screen
, dri_priv
->deviceID
);
877 if ((screen
->chip_family
== CHIP_FAMILY_R350
|| screen
->chip_family
== CHIP_FAMILY_R300
) &&
878 sPriv
->ddx_version
.minor
< 2) {
879 fprintf(stderr
, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
883 if ((sPriv
->drm_version
.minor
< 29) && (screen
->chip_family
>= CHIP_FAMILY_RV515
)) {
884 fprintf(stderr
, "R500 support requires a newer drm.\n");
888 if (getenv("R300_NO_TCL"))
889 screen
->chip_flags
&= ~RADEON_CHIPSET_TCL
;
891 if (screen
->chip_family
<= CHIP_FAMILY_RS200
)
892 screen
->chip_flags
|= RADEON_CLASS_R100
;
893 else if (screen
->chip_family
<= CHIP_FAMILY_RV280
)
894 screen
->chip_flags
|= RADEON_CLASS_R200
;
896 screen
->chip_flags
|= RADEON_CLASS_R300
;
898 screen
->cpp
= dri_priv
->bpp
/ 8;
899 screen
->AGPMode
= dri_priv
->AGPMode
;
901 ret
= radeonGetParam(sPriv
, RADEON_PARAM_FB_LOCATION
, &temp
);
903 if (screen
->chip_family
< CHIP_FAMILY_RS600
)
904 screen
->fbLocation
= ( INREG( RADEON_MC_FB_LOCATION
) & 0xffff) << 16;
907 fprintf(stderr
, "Unable to get fb location need newer drm\n");
911 screen
->fbLocation
= (temp
& 0xffff) << 16;
914 if (screen
->chip_family
>= CHIP_FAMILY_R300
) {
915 ret
= radeonGetParam(sPriv
, RADEON_PARAM_NUM_GB_PIPES
, &temp
);
917 fprintf(stderr
, "Unable to get num_pipes, need newer drm\n");
918 switch (screen
->chip_family
) {
919 case CHIP_FAMILY_R300
:
920 case CHIP_FAMILY_R350
:
921 screen
->num_gb_pipes
= 2;
923 case CHIP_FAMILY_R420
:
924 case CHIP_FAMILY_R520
:
925 case CHIP_FAMILY_R580
:
926 case CHIP_FAMILY_RV560
:
927 case CHIP_FAMILY_RV570
:
928 screen
->num_gb_pipes
= 4;
930 case CHIP_FAMILY_RV350
:
931 case CHIP_FAMILY_RV515
:
932 case CHIP_FAMILY_RV530
:
933 case CHIP_FAMILY_RV410
:
935 screen
->num_gb_pipes
= 1;
939 screen
->num_gb_pipes
= temp
;
943 switch (dri_priv
->deviceID
) {
944 case PCI_CHIP_R300_AD
: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
945 case PCI_CHIP_RV410_5E4C
: /* RV410 SE only have 1 quadpipe */
946 case PCI_CHIP_RV410_5E4F
: /* RV410 SE only have 1 quadpipe */
947 screen
->num_gb_pipes
= 1;
954 if ( sPriv
->drm_version
.minor
>= 10 ) {
955 drm_radeon_setparam_t sp
;
957 sp
.param
= RADEON_SETPARAM_FB_LOCATION
;
958 sp
.value
= screen
->fbLocation
;
960 drmCommandWrite( sPriv
->fd
, DRM_RADEON_SETPARAM
,
964 screen
->frontOffset
= dri_priv
->frontOffset
;
965 screen
->frontPitch
= dri_priv
->frontPitch
;
966 screen
->backOffset
= dri_priv
->backOffset
;
967 screen
->backPitch
= dri_priv
->backPitch
;
968 screen
->depthOffset
= dri_priv
->depthOffset
;
969 screen
->depthPitch
= dri_priv
->depthPitch
;
971 /* Check if ddx has set up a surface reg to cover depth buffer */
972 screen
->depthHasSurface
= (sPriv
->ddx_version
.major
> 4) ||
973 /* these chips don't use tiled z without hyperz. So always pretend
974 we have set up a surface which will cause linear reads/writes */
975 (IS_R100_CLASS(screen
) &&
976 !(screen
->chip_flags
& RADEON_CHIPSET_TCL
));
978 if ( dri_priv
->textureSize
== 0 ) {
979 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = screen
->gart_texture_offset
;
980 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
981 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
982 dri_priv
->log2GARTTexGran
;
984 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureOffset
985 + screen
->fbLocation
;
986 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureSize
;
987 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
988 dri_priv
->log2TexGran
;
991 if ( !screen
->gartTextures
.map
|| dri_priv
->textureSize
== 0
992 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
993 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
- 1;
994 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = 0;
995 screen
->texSize
[RADEON_GART_TEX_HEAP
] = 0;
996 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] = 0;
998 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
;
999 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = screen
->gart_texture_offset
;
1000 screen
->texSize
[RADEON_GART_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
1001 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] =
1002 dri_priv
->log2GARTTexGran
;
1006 screen
->extensions
[i
++] = &driCopySubBufferExtension
.base
;
1007 screen
->extensions
[i
++] = &driFrameTrackingExtension
.base
;
1008 screen
->extensions
[i
++] = &driReadDrawableExtension
;
1010 if ( screen
->irq
!= 0 ) {
1011 screen
->extensions
[i
++] = &driSwapControlExtension
.base
;
1012 screen
->extensions
[i
++] = &driMediaStreamCounterExtension
.base
;
1016 screen
->extensions
[i
++] = &radeonTexOffsetExtension
.base
;
1019 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1020 if (IS_R200_CLASS(screen
))
1021 screen
->extensions
[i
++] = &r200AllocateExtension
.base
;
1023 screen
->extensions
[i
++] = &r200texOffsetExtension
.base
;
1026 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1027 screen
->extensions
[i
++] = &r300texOffsetExtension
.base
;
1030 screen
->extensions
[i
++] = NULL
;
1031 sPriv
->extensions
= screen
->extensions
;
1033 screen
->driScreen
= sPriv
;
1034 screen
->sarea_priv_offset
= dri_priv
->sarea_priv_offset
;
1035 screen
->sarea
= (drm_radeon_sarea_t
*) ((GLubyte
*) sPriv
->pSAREA
+
1036 screen
->sarea_priv_offset
);
1038 screen
->bom
= radeon_bo_manager_legacy_ctor(screen
);
1039 if (screen
->bom
== NULL
) {
1047 static radeonScreenPtr
1048 radeonCreateScreen2(__DRIscreenPrivate
*sPriv
)
1050 radeonScreenPtr screen
;
1053 uint32_t device_id
= 0;
1056 /* Allocate the private area */
1057 screen
= (radeonScreenPtr
) CALLOC( sizeof(*screen
) );
1059 __driUtilMessage("%s: Could not allocate memory for screen structure",
1061 fprintf(stderr
, "leaving here\n");
1065 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1066 RADEON_DEBUG
= driParseDebugString(getenv("RADEON_DEBUG"), debug_control
);
1069 /* parse information in __driConfigOptions */
1070 driParseOptionInfo (&screen
->optionCache
,
1071 __driConfigOptions
, __driNConfigOptions
);
1073 screen
->kernel_mm
= 1;
1074 screen
->chip_flags
= 0;
1076 /* if we have kms we can support all of these */
1077 screen
->drmSupportsCubeMapsR200
= 1;
1078 screen
->drmSupportsBlendColor
= 1;
1079 screen
->drmSupportsTriPerf
= 1;
1080 screen
->drmSupportsFragShader
= 1;
1081 screen
->drmSupportsPointSprites
= 1;
1082 screen
->drmSupportsCubeMapsR100
= 1;
1083 screen
->drmSupportsVertexProgram
= 1;
1086 ret
= radeonGetParam(sPriv
, RADEON_PARAM_DEVICE_ID
, &device_id
);
1089 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret
);
1093 ret
= radeon_set_screen_flags(screen
, device_id
);
1097 if (screen
->chip_family
>= CHIP_FAMILY_R300
) {
1098 ret
= radeonGetParam(sPriv
, RADEON_PARAM_NUM_GB_PIPES
, &temp
);
1100 fprintf(stderr
, "Unable to get num_pipes, need newer drm\n");
1101 switch (screen
->chip_family
) {
1102 case CHIP_FAMILY_R300
:
1103 case CHIP_FAMILY_R350
:
1104 screen
->num_gb_pipes
= 2;
1106 case CHIP_FAMILY_R420
:
1107 case CHIP_FAMILY_R520
:
1108 case CHIP_FAMILY_R580
:
1109 case CHIP_FAMILY_RV560
:
1110 case CHIP_FAMILY_RV570
:
1111 screen
->num_gb_pipes
= 4;
1113 case CHIP_FAMILY_RV350
:
1114 case CHIP_FAMILY_RV515
:
1115 case CHIP_FAMILY_RV530
:
1116 case CHIP_FAMILY_RV410
:
1118 screen
->num_gb_pipes
= 1;
1122 screen
->num_gb_pipes
= temp
;
1125 /* pipe overrides */
1126 switch (device_id
) {
1127 case PCI_CHIP_R300_AD
: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1128 case PCI_CHIP_RV410_5E4C
: /* RV410 SE only have 1 quadpipe */
1129 case PCI_CHIP_RV410_5E4F
: /* RV410 SE only have 1 quadpipe */
1130 screen
->num_gb_pipes
= 1;
1138 if (screen
->chip_family
<= CHIP_FAMILY_RS200
)
1139 screen
->chip_flags
|= RADEON_CLASS_R100
;
1140 else if (screen
->chip_family
<= CHIP_FAMILY_RV280
)
1141 screen
->chip_flags
|= RADEON_CLASS_R200
;
1143 screen
->chip_flags
|= RADEON_CLASS_R300
;
1145 if (getenv("R300_NO_TCL"))
1146 screen
->chip_flags
&= ~RADEON_CHIPSET_TCL
;
1149 screen
->extensions
[i
++] = &driCopySubBufferExtension
.base
;
1150 screen
->extensions
[i
++] = &driFrameTrackingExtension
.base
;
1151 screen
->extensions
[i
++] = &driReadDrawableExtension
;
1153 if ( screen
->irq
!= 0 ) {
1154 screen
->extensions
[i
++] = &driSwapControlExtension
.base
;
1155 screen
->extensions
[i
++] = &driMediaStreamCounterExtension
.base
;
1159 screen
->extensions
[i
++] = &radeonTexBufferExtension
.base
;
1162 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1163 if (IS_R200_CLASS(screen
))
1164 screen
->extensions
[i
++] = &r200AllocateExtension
.base
;
1166 screen
->extensions
[i
++] = &r200TexBufferExtension
.base
;
1169 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1170 screen
->extensions
[i
++] = &r300TexBufferExtension
.base
;
1173 screen
->extensions
[i
++] = NULL
;
1174 sPriv
->extensions
= screen
->extensions
;
1176 screen
->driScreen
= sPriv
;
1177 screen
->bom
= radeon_bo_manager_gem_ctor(sPriv
->fd
);
1178 if (screen
->bom
== NULL
) {
1185 /* Destroy the device specific screen private data struct.
1188 radeonDestroyScreen( __DRIscreenPrivate
*sPriv
)
1190 radeonScreenPtr screen
= (radeonScreenPtr
)sPriv
->private;
1195 if (screen
->kernel_mm
) {
1196 #ifdef RADEON_BO_TRACK
1197 radeon_tracker_print(&screen
->bom
->tracker
, stderr
);
1199 radeon_bo_manager_gem_dtor(screen
->bom
);
1201 radeon_bo_manager_legacy_dtor(screen
->bom
);
1203 if ( screen
->gartTextures
.map
) {
1204 drmUnmap( screen
->gartTextures
.map
, screen
->gartTextures
.size
);
1206 drmUnmapBufs( screen
->buffers
);
1207 drmUnmap( screen
->status
.map
, screen
->status
.size
);
1208 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
1211 /* free all option information */
1212 driDestroyOptionInfo (&screen
->optionCache
);
1215 sPriv
->private = NULL
;
1219 /* Initialize the driver specific screen private data.
1222 radeonInitDriver( __DRIscreenPrivate
*sPriv
)
1224 if (sPriv
->dri2
.enabled
) {
1225 sPriv
->private = (void *) radeonCreateScreen2( sPriv
);
1227 sPriv
->private = (void *) radeonCreateScreen( sPriv
);
1229 if ( !sPriv
->private ) {
1230 radeonDestroyScreen( sPriv
);
1240 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1242 * \todo This function (and its interface) will need to be updated to support
1246 radeonCreateBuffer( __DRIscreenPrivate
*driScrnPriv
,
1247 __DRIdrawablePrivate
*driDrawPriv
,
1248 const __GLcontextModes
*mesaVis
,
1249 GLboolean isPixmap
)
1251 radeonScreenPtr screen
= (radeonScreenPtr
) driScrnPriv
->private;
1253 const GLboolean swDepth
= GL_FALSE
;
1254 const GLboolean swAlpha
= GL_FALSE
;
1255 const GLboolean swAccum
= mesaVis
->accumRedBits
> 0;
1256 const GLboolean swStencil
= mesaVis
->stencilBits
> 0 &&
1257 mesaVis
->depthBits
!= 24;
1259 struct radeon_framebuffer
*rfb
;
1262 return GL_FALSE
; /* not implemented */
1264 rfb
= CALLOC_STRUCT(radeon_framebuffer
);
1268 _mesa_initialize_framebuffer(&rfb
->base
, mesaVis
);
1270 if (mesaVis
->redBits
== 5)
1271 rgbFormat
= GL_RGB5
;
1272 else if (mesaVis
->alphaBits
== 0)
1273 rgbFormat
= GL_RGB8
;
1275 rgbFormat
= GL_RGBA8
;
1277 /* front color renderbuffer */
1278 rfb
->color_rb
[0] = radeon_create_renderbuffer(rgbFormat
, driDrawPriv
);
1279 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_FRONT_LEFT
, &rfb
->color_rb
[0]->base
);
1280 rfb
->color_rb
[0]->has_surface
= 1;
1282 /* back color renderbuffer */
1283 if (mesaVis
->doubleBufferMode
) {
1284 rfb
->color_rb
[1] = radeon_create_renderbuffer(rgbFormat
, driDrawPriv
);
1285 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_BACK_LEFT
, &rfb
->color_rb
[1]->base
);
1286 rfb
->color_rb
[1]->has_surface
= 1;
1289 if (mesaVis
->depthBits
== 24) {
1290 if (mesaVis
->stencilBits
== 8) {
1291 struct radeon_renderbuffer
*depthStencilRb
= radeon_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT
, driDrawPriv
);
1292 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_DEPTH
, &depthStencilRb
->base
);
1293 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_STENCIL
, &depthStencilRb
->base
);
1294 depthStencilRb
->has_surface
= screen
->depthHasSurface
;
1296 /* depth renderbuffer */
1297 struct radeon_renderbuffer
*depth
= radeon_create_renderbuffer(GL_DEPTH_COMPONENT24
, driDrawPriv
);
1298 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_DEPTH
, &depth
->base
);
1299 depth
->has_surface
= screen
->depthHasSurface
;
1301 } else if (mesaVis
->depthBits
== 16) {
1302 /* just 16-bit depth buffer, no hw stencil */
1303 struct radeon_renderbuffer
*depth
= radeon_create_renderbuffer(GL_DEPTH_COMPONENT16
, driDrawPriv
);
1304 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_DEPTH
, &depth
->base
);
1305 depth
->has_surface
= screen
->depthHasSurface
;
1308 _mesa_add_soft_renderbuffers(&rfb
->base
,
1309 GL_FALSE
, /* color */
1314 GL_FALSE
/* aux */);
1315 driDrawPriv
->driverPrivate
= (void *) rfb
;
1317 return (driDrawPriv
->driverPrivate
!= NULL
);
1321 static void radeon_cleanup_renderbuffers(struct radeon_framebuffer
*rfb
)
1323 struct radeon_renderbuffer
*rb
;
1325 rb
= rfb
->color_rb
[0];
1327 radeon_bo_unref(rb
->bo
);
1330 rb
= rfb
->color_rb
[1];
1332 radeon_bo_unref(rb
->bo
);
1335 rb
= radeon_get_renderbuffer(&rfb
->base
, BUFFER_DEPTH
);
1337 radeon_bo_unref(rb
->bo
);
1343 radeonDestroyBuffer(__DRIdrawablePrivate
*driDrawPriv
)
1345 struct radeon_framebuffer
*rfb
;
1349 rfb
= (void*)driDrawPriv
->driverPrivate
;
1352 radeon_cleanup_renderbuffers(rfb
);
1353 _mesa_reference_framebuffer((GLframebuffer
**)(&(driDrawPriv
->driverPrivate
)), NULL
);
1357 * Choose the appropriate CreateContext function based on the chipset.
1358 * Eventually, all drivers will go through this process.
1360 static GLboolean
radeonCreateContext(const __GLcontextModes
* glVisual
,
1361 __DRIcontextPrivate
* driContextPriv
,
1362 void *sharedContextPriv
)
1364 __DRIscreenPrivate
*sPriv
= driContextPriv
->driScreenPriv
;
1365 radeonScreenPtr screen
= (radeonScreenPtr
) (sPriv
->private);
1366 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1367 if (IS_R300_CLASS(screen
))
1368 return r300CreateContext(glVisual
, driContextPriv
, sharedContextPriv
);
1371 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1372 if (IS_R200_CLASS(screen
))
1373 return r200CreateContext(glVisual
, driContextPriv
, sharedContextPriv
);
1378 return r100CreateContext(glVisual
, driContextPriv
, sharedContextPriv
);
1385 * This is the driver specific part of the createNewScreen entry point.
1387 * \todo maybe fold this into intelInitDriver
1389 * \return the __GLcontextModes supported by this driver
1391 static const __DRIconfig
**
1392 radeonInitScreen(__DRIscreenPrivate
*psp
)
1395 static const char *driver_name
= "Radeon";
1396 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1397 static const __DRIversion dri_expected
= { 4, 0, 0 };
1398 static const __DRIversion drm_expected
= { 1, 6, 0 };
1399 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1400 static const char *driver_name
= "R200";
1401 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1402 static const __DRIversion dri_expected
= { 4, 0, 0 };
1403 static const __DRIversion drm_expected
= { 1, 6, 0 };
1404 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1405 static const char *driver_name
= "R300";
1406 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1407 static const __DRIversion dri_expected
= { 4, 0, 0 };
1408 static const __DRIversion drm_expected
= { 1, 24, 0 };
1410 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
) psp
->pDevPriv
;
1412 if ( ! driCheckDriDdxDrmVersions3( driver_name
,
1413 &psp
->dri_version
, & dri_expected
,
1414 &psp
->ddx_version
, & ddx_expected
,
1415 &psp
->drm_version
, & drm_expected
) ) {
1419 /* Calling driInitExtensions here, with a NULL context pointer,
1420 * does not actually enable the extensions. It just makes sure
1421 * that all the dispatch offsets for all the extensions that
1422 * *might* be enables are known. This is needed because the
1423 * dispatch offsets need to be known when _mesa_context_create
1424 * is called, but we can't enable the extensions until we have a
1427 * Hello chicken. Hello egg. How are you two today?
1429 driInitExtensions( NULL
, card_extensions
, GL_FALSE
);
1430 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1431 driInitExtensions( NULL
, blend_extensions
, GL_FALSE
);
1432 driInitSingleExtension( NULL
, ARB_vp_extension
);
1433 driInitSingleExtension( NULL
, NV_vp_extension
);
1434 driInitSingleExtension( NULL
, ATI_fs_extension
);
1435 driInitExtensions( NULL
, point_extensions
, GL_FALSE
);
1436 #elif defined(RADEON_COMMON_FOR_R300)
1437 driInitSingleExtension( NULL
, gl_20_extension
);
1440 if (!radeonInitDriver(psp
))
1443 /* for now fill in all modes */
1444 return radeonFillInModes( psp
,
1446 (dri_priv
->bpp
== 16) ? 16 : 24,
1447 (dri_priv
->bpp
== 16) ? 0 : 8, 1);
1449 #define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
1452 * This is the driver specific part of the createNewScreen entry point.
1453 * Called when using DRI2.
1455 * \return the __GLcontextModes supported by this driver
1458 __DRIconfig
**radeonInitScreen2(__DRIscreenPrivate
*psp
)
1460 GLenum fb_format
[3];
1462 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
1463 * support pageflipping at all.
1465 static const GLenum back_buffer_modes
[] = {
1466 GLX_NONE
, GLX_SWAP_UNDEFINED_OML
, /*, GLX_SWAP_COPY_OML*/
1468 uint8_t depth_bits
[4], stencil_bits
[4], msaa_samples_array
[1];
1470 __DRIconfig
**configs
= NULL
;
1472 /* Calling driInitExtensions here, with a NULL context pointer,
1473 * does not actually enable the extensions. It just makes sure
1474 * that all the dispatch offsets for all the extensions that
1475 * *might* be enables are known. This is needed because the
1476 * dispatch offsets need to be known when _mesa_context_create
1477 * is called, but we can't enable the extensions until we have a
1480 * Hello chicken. Hello egg. How are you two today?
1482 driInitExtensions( NULL
, card_extensions
, GL_FALSE
);
1483 driInitExtensions( NULL
, mm_extensions
, GL_FALSE
);
1484 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1485 driInitExtensions( NULL
, blend_extensions
, GL_FALSE
);
1486 driInitSingleExtension( NULL
, ARB_vp_extension
);
1487 driInitSingleExtension( NULL
, NV_vp_extension
);
1488 driInitSingleExtension( NULL
, ATI_fs_extension
);
1489 driInitExtensions( NULL
, point_extensions
, GL_FALSE
);
1492 if (!radeonInitDriver(psp
)) {
1496 stencil_bits
[0] = 0;
1498 stencil_bits
[1] = 0;
1500 stencil_bits
[2] = 0;
1502 stencil_bits
[3] = 8;
1504 msaa_samples_array
[0] = 0;
1506 fb_format
[0] = GL_RGB
;
1507 fb_type
[0] = GL_UNSIGNED_SHORT_5_6_5
;
1509 fb_format
[1] = GL_BGR
;
1510 fb_type
[1] = GL_UNSIGNED_INT_8_8_8_8_REV
;
1512 fb_format
[2] = GL_BGRA
;
1513 fb_type
[2] = GL_UNSIGNED_INT_8_8_8_8_REV
;
1515 for (color
= 0; color
< ARRAY_SIZE(fb_format
); color
++) {
1516 __DRIconfig
**new_configs
;
1518 new_configs
= driCreateConfigs(fb_format
[color
], fb_type
[color
],
1521 ARRAY_SIZE(depth_bits
),
1523 ARRAY_SIZE(back_buffer_modes
),
1525 ARRAY_SIZE(msaa_samples_array
));
1526 if (configs
== NULL
)
1527 configs
= new_configs
;
1529 configs
= driConcatConfigs(configs
, new_configs
);
1532 if (configs
== NULL
) {
1533 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1538 return (const __DRIconfig
**)configs
;
1542 * Get information about previous buffer swaps.
1545 getSwapInfo( __DRIdrawablePrivate
*dPriv
, __DRIswapInfo
* sInfo
)
1547 struct radeon_framebuffer
*rfb
;
1549 if ( (dPriv
== NULL
) || (dPriv
->driContextPriv
== NULL
)
1550 || (dPriv
->driContextPriv
->driverPrivate
== NULL
)
1551 || (sInfo
== NULL
) ) {
1555 rfb
= dPriv
->driverPrivate
;
1556 sInfo
->swap_count
= rfb
->swap_count
;
1557 sInfo
->swap_ust
= rfb
->swap_ust
;
1558 sInfo
->swap_missed_count
= rfb
->swap_missed_count
;
1560 sInfo
->swap_missed_usage
= (sInfo
->swap_missed_count
!= 0)
1561 ? driCalculateSwapUsage( dPriv
, 0, rfb
->swap_missed_ust
)
1567 const struct __DriverAPIRec driDriverAPI
= {
1568 .InitScreen
= radeonInitScreen
,
1569 .DestroyScreen
= radeonDestroyScreen
,
1570 .CreateContext
= radeonCreateContext
,
1571 .DestroyContext
= radeonDestroyContext
,
1572 .CreateBuffer
= radeonCreateBuffer
,
1573 .DestroyBuffer
= radeonDestroyBuffer
,
1574 .SwapBuffers
= radeonSwapBuffers
,
1575 .MakeCurrent
= radeonMakeCurrent
,
1576 .UnbindContext
= radeonUnbindContext
,
1577 .GetSwapInfo
= getSwapInfo
,
1578 .GetDrawableMSC
= driDrawableGetMSC32
,
1579 .WaitForMSC
= driWaitForMSC32
,
1581 .SwapBuffersMSC
= NULL
,
1582 .CopySubBuffer
= radeonCopySubBuffer
,
1584 .InitScreen2
= radeonInitScreen2
,