1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
39 #include "main/glheader.h"
40 #include "main/mtypes.h"
41 #include "main/framebuffer.h"
42 #include "main/renderbuffer.h"
43 #include "main/fbobject.h"
44 #include "util/u_memory.h"
45 #include "swrast/s_renderbuffer.h"
47 #include "radeon_chipset.h"
48 #include "radeon_screen.h"
49 #include "radeon_common.h"
50 #include "radeon_common_context.h"
51 #if defined(RADEON_R100)
52 #include "radeon_context.h"
53 #include "radeon_tex.h"
54 #elif defined(RADEON_R200)
55 #include "r200_context.h"
61 #include "GL/internal/dri_interface.h"
63 /* Radeon configuration
65 #include "util/xmlpool.h"
67 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
68 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
69 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
70 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
73 #define DRI_CONF_MAX_TEXTURE_UNITS(def,min,max) \
74 DRI_CONF_OPT_BEGIN_V(texture_units,int,def, # min ":" # max ) \
75 DRI_CONF_DESC(en,"Number of texture units used") \
78 #define DRI_CONF_HYPERZ(def) \
79 DRI_CONF_OPT_BEGIN_B(hyperz, def) \
80 DRI_CONF_DESC(en,"Use HyperZ to boost performance") \
83 #define DRI_CONF_TCL_MODE(def) \
84 DRI_CONF_OPT_BEGIN_V(tcl_mode,enum,def,"0:3") \
85 DRI_CONF_DESC_BEGIN(en,"TCL mode (Transformation, Clipping, Lighting)") \
86 DRI_CONF_ENUM(0,"Use software TCL pipeline") \
87 DRI_CONF_ENUM(1,"Use hardware TCL as first TCL pipeline stage") \
88 DRI_CONF_ENUM(2,"Bypass the TCL pipeline") \
89 DRI_CONF_ENUM(3,"Bypass the TCL pipeline with state-based machine code generated on-the-fly") \
93 #define DRI_CONF_NO_NEG_LOD_BIAS(def) \
94 DRI_CONF_OPT_BEGIN_B(no_neg_lod_bias, def) \
95 DRI_CONF_DESC(en,"Forbid negative texture LOD bias") \
98 #define DRI_CONF_DEF_MAX_ANISOTROPY(def,range) \
99 DRI_CONF_OPT_BEGIN_V(def_max_anisotropy,float,def,range) \
100 DRI_CONF_DESC(en,"Initial maximum value for anisotropic texture filtering") \
103 #if defined(RADEON_R100) /* R100 */
104 static const __DRIconfigOptionsExtension radeon_config_options
= {
105 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
108 DRI_CONF_SECTION_PERFORMANCE
109 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
110 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
111 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
112 DRI_CONF_HYPERZ("false")
113 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
115 DRI_CONF_SECTION_QUALITY
116 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
117 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
118 DRI_CONF_NO_NEG_LOD_BIAS("false")
119 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
120 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
121 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
126 #elif defined(RADEON_R200)
128 #define DRI_CONF_TEXTURE_BLEND_QUALITY(def,range) \
129 DRI_CONF_OPT_BEGIN_V(texture_blend_quality,float,def,range) \
130 DRI_CONF_DESC(en,"Texture filtering quality vs. speed, AKA “brilinear” texture filtering") \
133 static const __DRIconfigOptionsExtension radeon_config_options
= {
134 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
137 DRI_CONF_SECTION_PERFORMANCE
138 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
139 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
140 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
141 DRI_CONF_HYPERZ("false")
142 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
144 DRI_CONF_SECTION_QUALITY
145 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
146 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
147 DRI_CONF_NO_NEG_LOD_BIAS("false")
148 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
149 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
150 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
151 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
158 radeonGetParam(__DRIscreen
*sPriv
, int param
, void *value
)
160 struct drm_radeon_info info
= { 0 };
162 info
.value
= (uint64_t)(uintptr_t)value
;
164 case RADEON_PARAM_DEVICE_ID
:
165 info
.request
= RADEON_INFO_DEVICE_ID
;
167 case RADEON_PARAM_NUM_GB_PIPES
:
168 info
.request
= RADEON_INFO_NUM_GB_PIPES
;
170 case RADEON_PARAM_NUM_Z_PIPES
:
171 info
.request
= RADEON_INFO_NUM_Z_PIPES
;
173 case RADEON_INFO_TILING_CONFIG
:
174 info
.request
= RADEON_INFO_TILING_CONFIG
;
179 return drmCommandWriteRead(sPriv
->fd
, DRM_RADEON_INFO
, &info
, sizeof(info
));
182 #if defined(RADEON_R100)
183 static const __DRItexBufferExtension radeonTexBufferExtension
= {
184 .base
= { __DRI_TEX_BUFFER
, 3 },
186 .setTexBuffer
= radeonSetTexBuffer
,
187 .setTexBuffer2
= radeonSetTexBuffer2
,
188 .releaseTexBuffer
= NULL
,
190 #elif defined(RADEON_R200)
191 static const __DRItexBufferExtension r200TexBufferExtension
= {
192 .base
= { __DRI_TEX_BUFFER
, 3 },
194 .setTexBuffer
= r200SetTexBuffer
,
195 .setTexBuffer2
= r200SetTexBuffer2
,
196 .releaseTexBuffer
= NULL
,
201 radeonDRI2Flush(__DRIdrawable
*drawable
)
203 radeonContextPtr rmesa
;
205 rmesa
= (radeonContextPtr
) drawable
->driContextPriv
->driverPrivate
;
206 radeonFlush(&rmesa
->glCtx
);
209 static const struct __DRI2flushExtensionRec radeonFlushExtension
= {
210 .base
= { __DRI2_FLUSH
, 3 },
212 .flush
= radeonDRI2Flush
,
213 .invalidate
= dri2InvalidateDrawable
,
217 radeon_create_image_from_name(__DRIscreen
*screen
,
218 int width
, int height
, int format
,
219 int name
, int pitch
, void *loaderPrivate
)
222 radeonScreenPtr radeonScreen
= screen
->driverPrivate
;
227 image
= calloc(1, sizeof *image
);
232 case __DRI_IMAGE_FORMAT_RGB565
:
233 image
->format
= MESA_FORMAT_B5G6R5_UNORM
;
234 image
->internal_format
= GL_RGB
;
235 image
->data_type
= GL_UNSIGNED_BYTE
;
237 case __DRI_IMAGE_FORMAT_XRGB8888
:
238 image
->format
= MESA_FORMAT_B8G8R8X8_UNORM
;
239 image
->internal_format
= GL_RGB
;
240 image
->data_type
= GL_UNSIGNED_BYTE
;
242 case __DRI_IMAGE_FORMAT_ARGB8888
:
243 image
->format
= MESA_FORMAT_B8G8R8A8_UNORM
;
244 image
->internal_format
= GL_RGBA
;
245 image
->data_type
= GL_UNSIGNED_BYTE
;
252 image
->data
= loaderPrivate
;
253 image
->cpp
= _mesa_get_format_bytes(image
->format
);
254 image
->width
= width
;
255 image
->pitch
= pitch
;
256 image
->height
= height
;
258 image
->bo
= radeon_bo_open(radeonScreen
->bom
,
260 image
->pitch
* image
->height
* image
->cpp
,
262 RADEON_GEM_DOMAIN_VRAM
,
265 if (image
->bo
== NULL
) {
274 radeon_create_image_from_renderbuffer(__DRIcontext
*context
,
275 int renderbuffer
, void *loaderPrivate
)
278 radeonContextPtr radeon
= context
->driverPrivate
;
279 struct gl_renderbuffer
*rb
;
280 struct radeon_renderbuffer
*rrb
;
282 rb
= _mesa_lookup_renderbuffer(&radeon
->glCtx
, renderbuffer
);
284 _mesa_error(&radeon
->glCtx
,
285 GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
289 rrb
= radeon_renderbuffer(rb
);
290 image
= calloc(1, sizeof *image
);
294 image
->internal_format
= rb
->InternalFormat
;
295 image
->format
= rb
->Format
;
296 image
->cpp
= rrb
->cpp
;
297 image
->data_type
= GL_UNSIGNED_BYTE
;
298 image
->data
= loaderPrivate
;
299 radeon_bo_ref(rrb
->bo
);
302 image
->width
= rb
->Width
;
303 image
->height
= rb
->Height
;
304 image
->pitch
= rrb
->pitch
/ image
->cpp
;
310 radeon_destroy_image(__DRIimage
*image
)
312 radeon_bo_unref(image
->bo
);
317 radeon_create_image(__DRIscreen
*screen
,
318 int width
, int height
, int format
,
323 radeonScreenPtr radeonScreen
= screen
->driverPrivate
;
325 image
= calloc(1, sizeof *image
);
329 image
->dri_format
= format
;
332 case __DRI_IMAGE_FORMAT_RGB565
:
333 image
->format
= MESA_FORMAT_B5G6R5_UNORM
;
334 image
->internal_format
= GL_RGB
;
335 image
->data_type
= GL_UNSIGNED_BYTE
;
337 case __DRI_IMAGE_FORMAT_XRGB8888
:
338 image
->format
= MESA_FORMAT_B8G8R8X8_UNORM
;
339 image
->internal_format
= GL_RGB
;
340 image
->data_type
= GL_UNSIGNED_BYTE
;
342 case __DRI_IMAGE_FORMAT_ARGB8888
:
343 image
->format
= MESA_FORMAT_B8G8R8A8_UNORM
;
344 image
->internal_format
= GL_RGBA
;
345 image
->data_type
= GL_UNSIGNED_BYTE
;
352 image
->data
= loaderPrivate
;
353 image
->cpp
= _mesa_get_format_bytes(image
->format
);
354 image
->width
= width
;
355 image
->height
= height
;
356 image
->pitch
= ((image
->cpp
* image
->width
+ 255) & ~255) / image
->cpp
;
358 image
->bo
= radeon_bo_open(radeonScreen
->bom
,
360 image
->pitch
* image
->height
* image
->cpp
,
362 RADEON_GEM_DOMAIN_VRAM
,
365 if (image
->bo
== NULL
) {
374 radeon_query_image(__DRIimage
*image
, int attrib
, int *value
)
377 case __DRI_IMAGE_ATTRIB_STRIDE
:
378 *value
= image
->pitch
* image
->cpp
;
380 case __DRI_IMAGE_ATTRIB_HANDLE
:
381 *value
= image
->bo
->handle
;
383 case __DRI_IMAGE_ATTRIB_NAME
:
384 radeon_gem_get_kernel_name(image
->bo
, (uint32_t *) value
);
391 static const __DRIimageExtension radeonImageExtension
= {
392 .base
= { __DRI_IMAGE
, 1 },
394 .createImageFromName
= radeon_create_image_from_name
,
395 .createImageFromRenderbuffer
= radeon_create_image_from_renderbuffer
,
396 .destroyImage
= radeon_destroy_image
,
397 .createImage
= radeon_create_image
,
398 .queryImage
= radeon_query_image
401 static int radeon_set_screen_flags(radeonScreenPtr screen
, int device_id
)
403 screen
->device_id
= device_id
;
404 screen
->chip_flags
= 0;
405 switch ( device_id
) {
406 #if defined(RADEON_R100)
407 case PCI_CHIP_RN50_515E
:
408 case PCI_CHIP_RN50_5969
:
411 case PCI_CHIP_RADEON_LY
:
412 case PCI_CHIP_RADEON_LZ
:
413 case PCI_CHIP_RADEON_QY
:
414 case PCI_CHIP_RADEON_QZ
:
415 screen
->chip_family
= CHIP_FAMILY_RV100
;
418 case PCI_CHIP_RS100_4136
:
419 case PCI_CHIP_RS100_4336
:
420 screen
->chip_family
= CHIP_FAMILY_RS100
;
423 case PCI_CHIP_RS200_4137
:
424 case PCI_CHIP_RS200_4337
:
425 case PCI_CHIP_RS250_4237
:
426 case PCI_CHIP_RS250_4437
:
427 screen
->chip_family
= CHIP_FAMILY_RS200
;
430 case PCI_CHIP_RADEON_QD
:
431 case PCI_CHIP_RADEON_QE
:
432 case PCI_CHIP_RADEON_QF
:
433 case PCI_CHIP_RADEON_QG
:
434 /* all original radeons (7200) presumably have a stencil op bug */
435 screen
->chip_family
= CHIP_FAMILY_R100
;
436 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_BROKEN_STENCIL
| RADEON_CHIPSET_DEPTH_ALWAYS_TILED
;
439 case PCI_CHIP_RV200_QW
:
440 case PCI_CHIP_RV200_QX
:
441 case PCI_CHIP_RADEON_LW
:
442 case PCI_CHIP_RADEON_LX
:
443 screen
->chip_family
= CHIP_FAMILY_RV200
;
444 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_DEPTH_ALWAYS_TILED
;
447 #elif defined(RADEON_R200)
448 case PCI_CHIP_R200_BB
:
449 case PCI_CHIP_R200_QH
:
450 case PCI_CHIP_R200_QL
:
451 case PCI_CHIP_R200_QM
:
452 screen
->chip_family
= CHIP_FAMILY_R200
;
453 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_DEPTH_ALWAYS_TILED
;
456 case PCI_CHIP_RV250_If
:
457 case PCI_CHIP_RV250_Ig
:
458 case PCI_CHIP_RV250_Ld
:
459 case PCI_CHIP_RV250_Lf
:
460 case PCI_CHIP_RV250_Lg
:
461 screen
->chip_family
= CHIP_FAMILY_RV250
;
462 screen
->chip_flags
= R200_CHIPSET_YCBCR_BROKEN
| RADEON_CHIPSET_TCL
| RADEON_CHIPSET_DEPTH_ALWAYS_TILED
;
465 case PCI_CHIP_RV280_4C6E
:
466 case PCI_CHIP_RV280_5960
:
467 case PCI_CHIP_RV280_5961
:
468 case PCI_CHIP_RV280_5962
:
469 case PCI_CHIP_RV280_5964
:
470 case PCI_CHIP_RV280_5965
:
471 case PCI_CHIP_RV280_5C61
:
472 case PCI_CHIP_RV280_5C63
:
473 screen
->chip_family
= CHIP_FAMILY_RV280
;
474 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_DEPTH_ALWAYS_TILED
;
477 case PCI_CHIP_RS300_5834
:
478 case PCI_CHIP_RS300_5835
:
479 case PCI_CHIP_RS350_7834
:
480 case PCI_CHIP_RS350_7835
:
481 screen
->chip_family
= CHIP_FAMILY_RS300
;
482 screen
->chip_flags
= RADEON_CHIPSET_DEPTH_ALWAYS_TILED
;
487 fprintf(stderr
, "unknown chip id 0x%x, can't guess.\n",
496 radeonQueryRendererInteger(__DRIscreen
*psp
, int param
,
499 radeonScreenPtr screen
= (radeonScreenPtr
)psp
->driverPrivate
;
502 case __DRI2_RENDERER_VENDOR_ID
:
505 case __DRI2_RENDERER_DEVICE_ID
:
506 value
[0] = screen
->device_id
;
508 case __DRI2_RENDERER_ACCELERATED
:
511 case __DRI2_RENDERER_VIDEO_MEMORY
: {
512 struct drm_radeon_gem_info gem_info
;
514 memset(&gem_info
, 0, sizeof(gem_info
));
517 retval
= drmCommandWriteRead(psp
->fd
, DRM_RADEON_GEM_INFO
, &gem_info
,
521 fprintf(stderr
, "radeon: Failed to get MM info, error number %d\n",
526 /* XXX: Do we want to return vram_size or vram_visible ? */
527 value
[0] = gem_info
.vram_size
>> 20;
530 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
534 return driQueryRendererIntegerCommon(psp
, param
, value
);
539 radeonQueryRendererString(__DRIscreen
*psp
, int param
, const char **value
)
541 radeonScreenPtr screen
= (radeonScreenPtr
)psp
->driverPrivate
;
544 case __DRI2_RENDERER_VENDOR_ID
:
545 value
[0] = radeonVendorString
;
547 case __DRI2_RENDERER_DEVICE_ID
:
548 value
[0] = radeonGetRendererString(screen
);
555 static const __DRI2rendererQueryExtension radeonRendererQueryExtension
= {
556 .base
= { __DRI2_RENDERER_QUERY
, 1 },
558 .queryInteger
= radeonQueryRendererInteger
,
559 .queryString
= radeonQueryRendererString
563 static const __DRIextension
*radeon_screen_extensions
[] = {
564 &dri2ConfigQueryExtension
.base
,
565 #if defined(RADEON_R100)
566 &radeonTexBufferExtension
.base
,
567 #elif defined(RADEON_R200)
568 &r200TexBufferExtension
.base
,
570 &radeonFlushExtension
.base
,
571 &radeonImageExtension
.base
,
572 &radeonRendererQueryExtension
.base
,
573 &dri2NoErrorExtension
.base
,
577 static radeonScreenPtr
578 radeonCreateScreen2(__DRIscreen
*sPriv
)
580 radeonScreenPtr screen
;
582 uint32_t device_id
= 0;
584 /* Allocate the private area */
585 screen
= calloc(1, sizeof(*screen
));
587 fprintf(stderr
, "%s: Could not allocate memory for screen structure", __func__
);
588 fprintf(stderr
, "leaving here\n");
594 /* parse information in __driConfigOptions */
595 driParseOptionInfo (&screen
->optionCache
, radeon_config_options
.xml
);
597 screen
->chip_flags
= 0;
601 ret
= radeonGetParam(sPriv
, RADEON_PARAM_DEVICE_ID
, &device_id
);
604 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret
);
608 ret
= radeon_set_screen_flags(screen
, device_id
);
614 if (getenv("RADEON_NO_TCL"))
615 screen
->chip_flags
&= ~RADEON_CHIPSET_TCL
;
617 sPriv
->extensions
= radeon_screen_extensions
;
619 screen
->driScreen
= sPriv
;
620 screen
->bom
= radeon_bo_manager_gem_ctor(sPriv
->fd
);
621 if (screen
->bom
== NULL
) {
628 /* Destroy the device specific screen private data struct.
631 radeonDestroyScreen( __DRIscreen
*sPriv
)
633 radeonScreenPtr screen
= (radeonScreenPtr
)sPriv
->driverPrivate
;
638 #ifdef RADEON_BO_TRACK
639 radeon_tracker_print(&screen
->bom
->tracker
, stderr
);
641 radeon_bo_manager_gem_dtor(screen
->bom
);
643 /* free all option information */
644 driDestroyOptionInfo (&screen
->optionCache
);
647 sPriv
->driverPrivate
= NULL
;
651 /* Initialize the driver specific screen private data.
654 radeonInitDriver( __DRIscreen
*sPriv
)
656 sPriv
->driverPrivate
= (void *) radeonCreateScreen2( sPriv
);
657 if ( !sPriv
->driverPrivate
) {
658 radeonDestroyScreen( sPriv
);
668 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
670 * \todo This function (and its interface) will need to be updated to support
674 radeonCreateBuffer( __DRIscreen
*driScrnPriv
,
675 __DRIdrawable
*driDrawPriv
,
676 const struct gl_config
*mesaVis
,
679 radeonScreenPtr screen
= (radeonScreenPtr
) driScrnPriv
->driverPrivate
;
681 const GLboolean swDepth
= GL_FALSE
;
682 const GLboolean swAlpha
= GL_FALSE
;
683 const GLboolean swAccum
= mesaVis
->accumRedBits
> 0;
684 const GLboolean swStencil
= mesaVis
->stencilBits
> 0 &&
685 mesaVis
->depthBits
!= 24;
686 mesa_format rgbFormat
;
687 struct radeon_framebuffer
*rfb
;
690 return GL_FALSE
; /* not implemented */
692 rfb
= CALLOC_STRUCT(radeon_framebuffer
);
696 _mesa_initialize_window_framebuffer(&rfb
->base
, mesaVis
);
698 if (mesaVis
->redBits
== 5)
700 #if UTIL_ARCH_LITTLE_ENDIAN
701 MESA_FORMAT_B5G6R5_UNORM
;
703 MESA_FORMAT_R5G6B5_UNORM
;
705 else if (mesaVis
->alphaBits
== 0)
707 #if UTIL_ARCH_LITTLE_ENDIAN
708 MESA_FORMAT_B8G8R8X8_UNORM
;
710 MESA_FORMAT_X8R8G8B8_UNORM
;
714 #if UTIL_ARCH_LITTLE_ENDIAN
715 MESA_FORMAT_B8G8R8A8_UNORM
;
717 MESA_FORMAT_A8R8G8B8_UNORM
;
720 /* front color renderbuffer */
721 rfb
->color_rb
[0] = radeon_create_renderbuffer(rgbFormat
, driDrawPriv
);
722 _mesa_attach_and_own_rb(&rfb
->base
, BUFFER_FRONT_LEFT
, &rfb
->color_rb
[0]->base
.Base
);
723 rfb
->color_rb
[0]->has_surface
= 1;
725 /* back color renderbuffer */
726 if (mesaVis
->doubleBufferMode
) {
727 rfb
->color_rb
[1] = radeon_create_renderbuffer(rgbFormat
, driDrawPriv
);
728 _mesa_attach_and_own_rb(&rfb
->base
, BUFFER_BACK_LEFT
, &rfb
->color_rb
[1]->base
.Base
);
729 rfb
->color_rb
[1]->has_surface
= 1;
732 if (mesaVis
->depthBits
== 24) {
733 if (mesaVis
->stencilBits
== 8) {
734 struct radeon_renderbuffer
*depthStencilRb
=
735 radeon_create_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
, driDrawPriv
);
736 _mesa_attach_and_own_rb(&rfb
->base
, BUFFER_DEPTH
, &depthStencilRb
->base
.Base
);
737 _mesa_attach_and_reference_rb(&rfb
->base
, BUFFER_STENCIL
, &depthStencilRb
->base
.Base
);
738 depthStencilRb
->has_surface
= screen
->depthHasSurface
;
740 /* depth renderbuffer */
741 struct radeon_renderbuffer
*depth
=
742 radeon_create_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
, driDrawPriv
);
743 _mesa_attach_and_own_rb(&rfb
->base
, BUFFER_DEPTH
, &depth
->base
.Base
);
744 depth
->has_surface
= screen
->depthHasSurface
;
746 } else if (mesaVis
->depthBits
== 16) {
747 /* just 16-bit depth buffer, no hw stencil */
748 struct radeon_renderbuffer
*depth
=
749 radeon_create_renderbuffer(MESA_FORMAT_Z_UNORM16
, driDrawPriv
);
750 _mesa_attach_and_own_rb(&rfb
->base
, BUFFER_DEPTH
, &depth
->base
.Base
);
751 depth
->has_surface
= screen
->depthHasSurface
;
754 _swrast_add_soft_renderbuffers(&rfb
->base
,
755 GL_FALSE
, /* color */
761 driDrawPriv
->driverPrivate
= (void *) rfb
;
763 return (driDrawPriv
->driverPrivate
!= NULL
);
767 static void radeon_cleanup_renderbuffers(struct radeon_framebuffer
*rfb
)
769 struct radeon_renderbuffer
*rb
;
771 rb
= rfb
->color_rb
[0];
773 radeon_bo_unref(rb
->bo
);
776 rb
= rfb
->color_rb
[1];
778 radeon_bo_unref(rb
->bo
);
781 rb
= radeon_get_renderbuffer(&rfb
->base
, BUFFER_DEPTH
);
783 radeon_bo_unref(rb
->bo
);
789 radeonDestroyBuffer(__DRIdrawable
*driDrawPriv
)
791 struct radeon_framebuffer
*rfb
;
795 rfb
= (void*)driDrawPriv
->driverPrivate
;
798 radeon_cleanup_renderbuffers(rfb
);
799 _mesa_reference_framebuffer((struct gl_framebuffer
**)(&(driDrawPriv
->driverPrivate
)), NULL
);
803 * This is the driver specific part of the createNewScreen entry point.
804 * Called when using DRI2.
806 * \return the struct gl_config supported by this driver
809 __DRIconfig
**radeonInitScreen2(__DRIscreen
*psp
)
811 static const mesa_format formats
[3] = {
812 MESA_FORMAT_B5G6R5_UNORM
,
813 MESA_FORMAT_B8G8R8X8_UNORM
,
814 MESA_FORMAT_B8G8R8A8_UNORM
817 static const GLenum back_buffer_modes
[] = {
818 __DRI_ATTRIB_SWAP_NONE
, __DRI_ATTRIB_SWAP_UNDEFINED
820 uint8_t depth_bits
[4], stencil_bits
[4], msaa_samples_array
[1];
822 __DRIconfig
**configs
= NULL
;
824 psp
->max_gl_compat_version
= 13;
825 psp
->max_gl_es1_version
= 11;
827 if (!radeonInitDriver(psp
)) {
839 msaa_samples_array
[0] = 0;
841 for (color
= 0; color
< ARRAY_SIZE(formats
); color
++) {
842 __DRIconfig
**new_configs
;
844 new_configs
= driCreateConfigs(formats
[color
],
847 ARRAY_SIZE(depth_bits
),
849 ARRAY_SIZE(back_buffer_modes
),
851 ARRAY_SIZE(msaa_samples_array
),
852 GL_TRUE
, GL_FALSE
, GL_FALSE
);
853 configs
= driConcatConfigs(configs
, new_configs
);
856 if (configs
== NULL
) {
857 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
862 return (const __DRIconfig
**)configs
;
865 static const struct __DriverAPIRec radeon_driver_api
= {
866 .InitScreen
= radeonInitScreen2
,
867 .DestroyScreen
= radeonDestroyScreen
,
868 #if defined(RADEON_R200)
869 .CreateContext
= r200CreateContext
,
870 .DestroyContext
= r200DestroyContext
,
872 .CreateContext
= r100CreateContext
,
873 .DestroyContext
= radeonDestroyContext
,
875 .CreateBuffer
= radeonCreateBuffer
,
876 .DestroyBuffer
= radeonDestroyBuffer
,
877 .MakeCurrent
= radeonMakeCurrent
,
878 .UnbindContext
= radeonUnbindContext
,
881 static const struct __DRIDriverVtableExtensionRec radeon_vtable
= {
882 .base
= { __DRI_DRIVER_VTABLE
, 1 },
883 .vtable
= &radeon_driver_api
,
886 /* This is the table of extensions that the loader will dlsym() for. */
887 static const __DRIextension
*radeon_driver_extensions
[] = {
888 &driCoreExtension
.base
,
889 &driDRI2Extension
.base
,
890 &radeon_config_options
.base
,
896 PUBLIC
const __DRIextension
**__driDriverGetExtensions_r200(void)
898 globalDriverAPI
= &radeon_driver_api
;
900 return radeon_driver_extensions
;
903 PUBLIC
const __DRIextension
**__driDriverGetExtensions_radeon(void)
905 globalDriverAPI
= &radeon_driver_api
;
907 return radeon_driver_extensions
;