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Merge remote branch 'vdpau/pipe-video' into pipe-video
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
36 */
37
38 #include <errno.h>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
44 #include "main/fbobject.h"
45
46 #define STANDALONE_MMIO
47 #include "radeon_chipset.h"
48 #include "radeon_macros.h"
49 #include "radeon_screen.h"
50 #include "radeon_common.h"
51 #include "radeon_common_context.h"
52 #if defined(RADEON_R100)
53 #include "radeon_context.h"
54 #include "radeon_tex.h"
55 #elif defined(RADEON_R200)
56 #include "r200_context.h"
57 #include "r200_tex.h"
58 #elif defined(RADEON_R300)
59 #include "r300_context.h"
60 #include "r300_tex.h"
61 #elif defined(RADEON_R600)
62 #include "r600_context.h"
63 #include "r700_driconf.h" /* +r6/r7 */
64 #include "r600_tex.h" /* +r6/r7 */
65 #endif
66
67 #include "utils.h"
68 #include "vblank.h"
69
70 #include "radeon_bocs_wrapper.h"
71
72 #include "GL/internal/dri_interface.h"
73
74 /* Radeon configuration
75 */
76 #include "xmlpool.h"
77
78 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
79 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
80 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
81 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
82 DRI_CONF_OPT_END
83
84 #if defined(RADEON_R100) /* R100 */
85 PUBLIC const char __driConfigOptions[] =
86 DRI_CONF_BEGIN
87 DRI_CONF_SECTION_PERFORMANCE
88 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
89 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
90 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
91 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
92 DRI_CONF_HYPERZ(false)
93 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
94 DRI_CONF_SECTION_END
95 DRI_CONF_SECTION_QUALITY
96 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
97 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
98 DRI_CONF_NO_NEG_LOD_BIAS(false)
99 DRI_CONF_FORCE_S3TC_ENABLE(false)
100 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
101 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
102 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
103 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
104 DRI_CONF_SECTION_END
105 DRI_CONF_SECTION_DEBUG
106 DRI_CONF_NO_RAST(false)
107 DRI_CONF_SECTION_END
108 DRI_CONF_END;
109 static const GLuint __driNConfigOptions = 15;
110
111 #elif defined(RADEON_R200)
112
113 PUBLIC const char __driConfigOptions[] =
114 DRI_CONF_BEGIN
115 DRI_CONF_SECTION_PERFORMANCE
116 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
117 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
118 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
119 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
120 DRI_CONF_HYPERZ(false)
121 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
122 DRI_CONF_SECTION_END
123 DRI_CONF_SECTION_QUALITY
124 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
125 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
126 DRI_CONF_NO_NEG_LOD_BIAS(false)
127 DRI_CONF_FORCE_S3TC_ENABLE(false)
128 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
129 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
130 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
131 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
132 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
133 DRI_CONF_SECTION_END
134 DRI_CONF_SECTION_DEBUG
135 DRI_CONF_NO_RAST(false)
136 DRI_CONF_SECTION_END
137 DRI_CONF_SECTION_SOFTWARE
138 DRI_CONF_NV_VERTEX_PROGRAM(false)
139 DRI_CONF_SECTION_END
140 DRI_CONF_END;
141 static const GLuint __driNConfigOptions = 17;
142
143 #elif defined(RADEON_R300) || defined(RADEON_R600)
144
145 #define DRI_CONF_FP_OPTIMIZATION_SPEED 0
146 #define DRI_CONF_FP_OPTIMIZATION_QUALITY 1
147
148 /* TODO: integrate these into xmlpool.h! */
149 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
150 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
151 DRI_CONF_DESC(en,"Number of texture image units") \
152 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
153 DRI_CONF_OPT_END
154
155 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
156 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
157 DRI_CONF_DESC(en,"Number of texture coordinate units") \
158 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
159 DRI_CONF_OPT_END
160
161
162
163 #define DRI_CONF_DISABLE_S3TC(def) \
164 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
165 DRI_CONF_DESC(en,"Disable S3TC compression") \
166 DRI_CONF_OPT_END
167
168 #define DRI_CONF_DISABLE_FALLBACK(def) \
169 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
170 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
171 DRI_CONF_OPT_END
172
173 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
174 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
175 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
176 DRI_CONF_OPT_END
177
178 #define DRI_CONF_FP_OPTIMIZATION(def) \
179 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
180 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
181 DRI_CONF_ENUM(0,"Optimize for Speed") \
182 DRI_CONF_ENUM(1,"Optimize for Quality") \
183 DRI_CONF_DESC_END \
184 DRI_CONF_OPT_END
185
186 PUBLIC const char __driConfigOptions[] =
187 DRI_CONF_BEGIN
188 DRI_CONF_SECTION_PERFORMANCE
189 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
190 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
191 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
192 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
193 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
194 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
195 DRI_CONF_DISABLE_FALLBACK(true)
196 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
197 DRI_CONF_SECTION_END
198 DRI_CONF_SECTION_QUALITY
199 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
200 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
201 DRI_CONF_FORCE_S3TC_ENABLE(false)
202 DRI_CONF_DISABLE_S3TC(false)
203 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
204 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
205 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
206 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
207 DRI_CONF_SECTION_END
208 DRI_CONF_SECTION_DEBUG
209 DRI_CONF_NO_RAST(false)
210 DRI_CONF_SECTION_END
211 DRI_CONF_END;
212 static const GLuint __driNConfigOptions = 17;
213
214 #endif
215
216 static int getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo );
217
218 #ifndef RADEON_INFO_TILE_CONFIG
219 #define RADEON_INFO_TILE_CONFIG 0x6
220 #endif
221
222 static int
223 radeonGetParam(__DRIscreen *sPriv, int param, void *value)
224 {
225 int ret;
226 drm_radeon_getparam_t gp = { 0 };
227 struct drm_radeon_info info = { 0 };
228
229 if (sPriv->drm_version.major >= 2) {
230 info.value = (uint64_t)(uintptr_t)value;
231 switch (param) {
232 case RADEON_PARAM_DEVICE_ID:
233 info.request = RADEON_INFO_DEVICE_ID;
234 break;
235 case RADEON_PARAM_NUM_GB_PIPES:
236 info.request = RADEON_INFO_NUM_GB_PIPES;
237 break;
238 case RADEON_PARAM_NUM_Z_PIPES:
239 info.request = RADEON_INFO_NUM_Z_PIPES;
240 break;
241 case RADEON_INFO_TILE_CONFIG:
242 info.request = RADEON_INFO_TILE_CONFIG;
243 break;
244 default:
245 return -EINVAL;
246 }
247 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info));
248 } else {
249 gp.param = param;
250 gp.value = value;
251
252 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
253 }
254 return ret;
255 }
256
257 static const __DRIconfig **
258 radeonFillInModes( __DRIscreen *psp,
259 unsigned pixel_bits, unsigned depth_bits,
260 unsigned stencil_bits, GLboolean have_back_buffer )
261 {
262 __DRIconfig **configs;
263 struct gl_config *m;
264 unsigned depth_buffer_factor;
265 unsigned back_buffer_factor;
266 int i;
267
268 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
269 * enough to add support. Basically, if a context is created with an
270 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
271 * will never be used.
272 */
273 static const GLenum back_buffer_modes[] = {
274 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
275 };
276
277 uint8_t depth_bits_array[2];
278 uint8_t stencil_bits_array[2];
279 uint8_t msaa_samples_array[1];
280
281 depth_bits_array[0] = depth_bits;
282 depth_bits_array[1] = depth_bits;
283
284 /* Just like with the accumulation buffer, always provide some modes
285 * with a stencil buffer. It will be a sw fallback, but some apps won't
286 * care about that.
287 */
288 stencil_bits_array[0] = stencil_bits;
289 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
290
291 msaa_samples_array[0] = 0;
292
293 depth_buffer_factor = (stencil_bits == 0) ? 2 : 1;
294 back_buffer_factor = (have_back_buffer) ? 2 : 1;
295
296 if (pixel_bits == 16) {
297 __DRIconfig **configs_a8r8g8b8;
298 __DRIconfig **configs_r5g6b5;
299
300 configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5,
301 depth_bits_array, stencil_bits_array,
302 depth_buffer_factor, back_buffer_modes,
303 back_buffer_factor, msaa_samples_array,
304 1, GL_TRUE);
305 configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
306 depth_bits_array, stencil_bits_array,
307 1, back_buffer_modes, 1,
308 msaa_samples_array, 1, GL_TRUE);
309 configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8);
310 } else
311 configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
312 depth_bits_array, stencil_bits_array,
313 depth_buffer_factor,
314 back_buffer_modes, back_buffer_factor,
315 msaa_samples_array, 1, GL_TRUE);
316
317 if (configs == NULL) {
318 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
319 __func__, __LINE__ );
320 return NULL;
321 }
322
323 /* Mark the visual as slow if there are "fake" stencil bits.
324 */
325 for (i = 0; configs[i]; i++) {
326 m = &configs[i]->modes;
327 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
328 m->visualRating = GLX_SLOW_CONFIG;
329 }
330 }
331
332 return (const __DRIconfig **) configs;
333 }
334
335 #if defined(RADEON_R100)
336 static const __DRItexOffsetExtension radeonTexOffsetExtension = {
337 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
338 radeonSetTexOffset,
339 };
340
341 static const __DRItexBufferExtension radeonTexBufferExtension = {
342 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
343 radeonSetTexBuffer,
344 radeonSetTexBuffer2,
345 };
346 #endif
347
348 #if defined(RADEON_R200)
349
350 static const __DRItexOffsetExtension r200texOffsetExtension = {
351 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
352 r200SetTexOffset,
353 };
354
355 static const __DRItexBufferExtension r200TexBufferExtension = {
356 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
357 r200SetTexBuffer,
358 r200SetTexBuffer2,
359 };
360 #endif
361
362 #if defined(RADEON_R300)
363 static const __DRItexOffsetExtension r300texOffsetExtension = {
364 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
365 r300SetTexOffset,
366 };
367
368 static const __DRItexBufferExtension r300TexBufferExtension = {
369 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
370 r300SetTexBuffer,
371 r300SetTexBuffer2,
372 };
373 #endif
374
375 #if defined(RADEON_R600)
376 static const __DRItexOffsetExtension r600texOffsetExtension = {
377 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
378 r600SetTexOffset, /* +r6/r7 */
379 };
380
381 static const __DRItexBufferExtension r600TexBufferExtension = {
382 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
383 r600SetTexBuffer, /* +r6/r7 */
384 r600SetTexBuffer2, /* +r6/r7 */
385 };
386 #endif
387
388 static void
389 radeonDRI2Flush(__DRIdrawable *drawable)
390 {
391 radeonContextPtr rmesa;
392
393 rmesa = (radeonContextPtr) drawable->driContextPriv->driverPrivate;
394 radeonFlush(rmesa->glCtx);
395 }
396
397 static const struct __DRI2flushExtensionRec radeonFlushExtension = {
398 { __DRI2_FLUSH, __DRI2_FLUSH_VERSION },
399 radeonDRI2Flush,
400 dri2InvalidateDrawable,
401 };
402
403 static __DRIimage *
404 radeon_create_image_from_name(__DRIcontext *context,
405 int width, int height, int format,
406 int name, int pitch, void *loaderPrivate)
407 {
408 __DRIimage *image;
409 radeonContextPtr radeon = context->driverPrivate;
410
411 if (name == 0)
412 return NULL;
413
414 image = CALLOC(sizeof *image);
415 if (image == NULL)
416 return NULL;
417
418 switch (format) {
419 case __DRI_IMAGE_FORMAT_RGB565:
420 image->format = MESA_FORMAT_RGB565;
421 image->internal_format = GL_RGB;
422 image->data_type = GL_UNSIGNED_BYTE;
423 break;
424 case __DRI_IMAGE_FORMAT_XRGB8888:
425 image->format = MESA_FORMAT_XRGB8888;
426 image->internal_format = GL_RGB;
427 image->data_type = GL_UNSIGNED_BYTE;
428 break;
429 case __DRI_IMAGE_FORMAT_ARGB8888:
430 image->format = MESA_FORMAT_ARGB8888;
431 image->internal_format = GL_RGBA;
432 image->data_type = GL_UNSIGNED_BYTE;
433 break;
434 default:
435 free(image);
436 return NULL;
437 }
438
439 image->data = loaderPrivate;
440 image->cpp = _mesa_get_format_bytes(image->format);
441 image->width = width;
442 image->pitch = pitch;
443 image->height = height;
444
445 image->bo = radeon_bo_open(radeon->radeonScreen->bom,
446 (uint32_t)name,
447 image->pitch * image->height * image->cpp,
448 0,
449 RADEON_GEM_DOMAIN_VRAM,
450 0);
451
452 if (image->bo == NULL) {
453 FREE(image);
454 return NULL;
455 }
456
457 return image;
458 }
459
460 static __DRIimage *
461 radeon_create_image_from_renderbuffer(__DRIcontext *context,
462 int renderbuffer, void *loaderPrivate)
463 {
464 __DRIimage *image;
465 radeonContextPtr radeon = context->driverPrivate;
466 struct gl_renderbuffer *rb;
467 struct radeon_renderbuffer *rrb;
468
469 rb = _mesa_lookup_renderbuffer(radeon->glCtx, renderbuffer);
470 if (!rb) {
471 _mesa_error(radeon->glCtx,
472 GL_INVALID_OPERATION, "glRenderbufferExternalMESA");
473 return NULL;
474 }
475
476 rrb = radeon_renderbuffer(rb);
477 image = CALLOC(sizeof *image);
478 if (image == NULL)
479 return NULL;
480
481 image->internal_format = rb->InternalFormat;
482 image->format = rb->Format;
483 image->cpp = rrb->cpp;
484 image->data_type = rb->DataType;
485 image->data = loaderPrivate;
486 radeon_bo_ref(rrb->bo);
487 image->bo = rrb->bo;
488
489 image->width = rb->Width;
490 image->height = rb->Height;
491 image->pitch = rrb->pitch / image->cpp;
492
493 return image;
494 }
495
496 static void
497 radeon_destroy_image(__DRIimage *image)
498 {
499 radeon_bo_unref(image->bo);
500 FREE(image);
501 }
502
503 static __DRIimage *
504 radeon_create_image(__DRIscreen *screen,
505 int width, int height, int format,
506 unsigned int use,
507 void *loaderPrivate)
508 {
509 __DRIimage *image;
510 radeonScreenPtr radeonScreen = screen->private;
511
512 image = CALLOC(sizeof *image);
513 if (image == NULL)
514 return NULL;
515
516 switch (format) {
517 case __DRI_IMAGE_FORMAT_RGB565:
518 image->format = MESA_FORMAT_RGB565;
519 image->internal_format = GL_RGB;
520 image->data_type = GL_UNSIGNED_BYTE;
521 break;
522 case __DRI_IMAGE_FORMAT_XRGB8888:
523 image->format = MESA_FORMAT_XRGB8888;
524 image->internal_format = GL_RGB;
525 image->data_type = GL_UNSIGNED_BYTE;
526 break;
527 case __DRI_IMAGE_FORMAT_ARGB8888:
528 image->format = MESA_FORMAT_ARGB8888;
529 image->internal_format = GL_RGBA;
530 image->data_type = GL_UNSIGNED_BYTE;
531 break;
532 default:
533 free(image);
534 return NULL;
535 }
536
537 image->data = loaderPrivate;
538 image->cpp = _mesa_get_format_bytes(image->format);
539 image->width = width;
540 image->height = height;
541 image->pitch = ((image->cpp * image->width + 255) & ~255) / image->cpp;
542
543 image->bo = radeon_bo_open(radeonScreen->bom,
544 0,
545 image->pitch * image->height * image->cpp,
546 0,
547 RADEON_GEM_DOMAIN_VRAM,
548 0);
549
550 if (image->bo == NULL) {
551 FREE(image);
552 return NULL;
553 }
554
555 return image;
556 }
557
558 static GLboolean
559 radeon_query_image(__DRIimage *image, int attrib, int *value)
560 {
561 switch (attrib) {
562 case __DRI_IMAGE_ATTRIB_STRIDE:
563 *value = image->pitch * image->cpp;
564 return GL_TRUE;
565 case __DRI_IMAGE_ATTRIB_HANDLE:
566 *value = image->bo->handle;
567 return GL_TRUE;
568 case __DRI_IMAGE_ATTRIB_NAME:
569 radeon_gem_get_kernel_name(image->bo, (uint32_t *) value);
570 return GL_TRUE;
571 default:
572 return GL_FALSE;
573 }
574 }
575
576 static struct __DRIimageExtensionRec radeonImageExtension = {
577 { __DRI_IMAGE, __DRI_IMAGE_VERSION },
578 radeon_create_image_from_name,
579 radeon_create_image_from_renderbuffer,
580 radeon_destroy_image,
581 radeon_create_image,
582 radeon_query_image
583 };
584
585 static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
586 {
587 screen->device_id = device_id;
588 screen->chip_flags = 0;
589 switch ( device_id ) {
590 case PCI_CHIP_RN50_515E:
591 case PCI_CHIP_RN50_5969:
592 return -1;
593
594 case PCI_CHIP_RADEON_LY:
595 case PCI_CHIP_RADEON_LZ:
596 case PCI_CHIP_RADEON_QY:
597 case PCI_CHIP_RADEON_QZ:
598 screen->chip_family = CHIP_FAMILY_RV100;
599 break;
600
601 case PCI_CHIP_RS100_4136:
602 case PCI_CHIP_RS100_4336:
603 screen->chip_family = CHIP_FAMILY_RS100;
604 break;
605
606 case PCI_CHIP_RS200_4137:
607 case PCI_CHIP_RS200_4337:
608 case PCI_CHIP_RS250_4237:
609 case PCI_CHIP_RS250_4437:
610 screen->chip_family = CHIP_FAMILY_RS200;
611 break;
612
613 case PCI_CHIP_RADEON_QD:
614 case PCI_CHIP_RADEON_QE:
615 case PCI_CHIP_RADEON_QF:
616 case PCI_CHIP_RADEON_QG:
617 /* all original radeons (7200) presumably have a stencil op bug */
618 screen->chip_family = CHIP_FAMILY_R100;
619 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
620 break;
621
622 case PCI_CHIP_RV200_QW:
623 case PCI_CHIP_RV200_QX:
624 case PCI_CHIP_RADEON_LW:
625 case PCI_CHIP_RADEON_LX:
626 screen->chip_family = CHIP_FAMILY_RV200;
627 screen->chip_flags = RADEON_CHIPSET_TCL;
628 break;
629
630 case PCI_CHIP_R200_BB:
631 case PCI_CHIP_R200_BC:
632 case PCI_CHIP_R200_QH:
633 case PCI_CHIP_R200_QL:
634 case PCI_CHIP_R200_QM:
635 screen->chip_family = CHIP_FAMILY_R200;
636 screen->chip_flags = RADEON_CHIPSET_TCL;
637 break;
638
639 case PCI_CHIP_RV250_If:
640 case PCI_CHIP_RV250_Ig:
641 case PCI_CHIP_RV250_Ld:
642 case PCI_CHIP_RV250_Lf:
643 case PCI_CHIP_RV250_Lg:
644 screen->chip_family = CHIP_FAMILY_RV250;
645 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
646 break;
647
648 case PCI_CHIP_RV280_5960:
649 case PCI_CHIP_RV280_5961:
650 case PCI_CHIP_RV280_5962:
651 case PCI_CHIP_RV280_5964:
652 case PCI_CHIP_RV280_5965:
653 case PCI_CHIP_RV280_5C61:
654 case PCI_CHIP_RV280_5C63:
655 screen->chip_family = CHIP_FAMILY_RV280;
656 screen->chip_flags = RADEON_CHIPSET_TCL;
657 break;
658
659 case PCI_CHIP_RS300_5834:
660 case PCI_CHIP_RS300_5835:
661 case PCI_CHIP_RS350_7834:
662 case PCI_CHIP_RS350_7835:
663 screen->chip_family = CHIP_FAMILY_RS300;
664 break;
665
666 case PCI_CHIP_R300_AD:
667 case PCI_CHIP_R300_AE:
668 case PCI_CHIP_R300_AF:
669 case PCI_CHIP_R300_AG:
670 case PCI_CHIP_R300_ND:
671 case PCI_CHIP_R300_NE:
672 case PCI_CHIP_R300_NF:
673 case PCI_CHIP_R300_NG:
674 screen->chip_family = CHIP_FAMILY_R300;
675 screen->chip_flags = RADEON_CHIPSET_TCL;
676 break;
677
678 case PCI_CHIP_RV350_AP:
679 case PCI_CHIP_RV350_AQ:
680 case PCI_CHIP_RV350_AR:
681 case PCI_CHIP_RV350_AS:
682 case PCI_CHIP_RV350_AT:
683 case PCI_CHIP_RV350_AV:
684 case PCI_CHIP_RV350_AU:
685 case PCI_CHIP_RV350_NP:
686 case PCI_CHIP_RV350_NQ:
687 case PCI_CHIP_RV350_NR:
688 case PCI_CHIP_RV350_NS:
689 case PCI_CHIP_RV350_NT:
690 case PCI_CHIP_RV350_NV:
691 screen->chip_family = CHIP_FAMILY_RV350;
692 screen->chip_flags = RADEON_CHIPSET_TCL;
693 break;
694
695 case PCI_CHIP_R350_AH:
696 case PCI_CHIP_R350_AI:
697 case PCI_CHIP_R350_AJ:
698 case PCI_CHIP_R350_AK:
699 case PCI_CHIP_R350_NH:
700 case PCI_CHIP_R350_NI:
701 case PCI_CHIP_R360_NJ:
702 case PCI_CHIP_R350_NK:
703 screen->chip_family = CHIP_FAMILY_R350;
704 screen->chip_flags = RADEON_CHIPSET_TCL;
705 break;
706
707 case PCI_CHIP_RV370_5460:
708 case PCI_CHIP_RV370_5462:
709 case PCI_CHIP_RV370_5464:
710 case PCI_CHIP_RV370_5B60:
711 case PCI_CHIP_RV370_5B62:
712 case PCI_CHIP_RV370_5B63:
713 case PCI_CHIP_RV370_5B64:
714 case PCI_CHIP_RV370_5B65:
715 case PCI_CHIP_RV380_3150:
716 case PCI_CHIP_RV380_3152:
717 case PCI_CHIP_RV380_3154:
718 case PCI_CHIP_RV380_3155:
719 case PCI_CHIP_RV380_3E50:
720 case PCI_CHIP_RV380_3E54:
721 screen->chip_family = CHIP_FAMILY_RV380;
722 screen->chip_flags = RADEON_CHIPSET_TCL;
723 break;
724
725 case PCI_CHIP_R420_JN:
726 case PCI_CHIP_R420_JH:
727 case PCI_CHIP_R420_JI:
728 case PCI_CHIP_R420_JJ:
729 case PCI_CHIP_R420_JK:
730 case PCI_CHIP_R420_JL:
731 case PCI_CHIP_R420_JM:
732 case PCI_CHIP_R420_JO:
733 case PCI_CHIP_R420_JP:
734 case PCI_CHIP_R420_JT:
735 case PCI_CHIP_R481_4B49:
736 case PCI_CHIP_R481_4B4A:
737 case PCI_CHIP_R481_4B4B:
738 case PCI_CHIP_R481_4B4C:
739 case PCI_CHIP_R423_UH:
740 case PCI_CHIP_R423_UI:
741 case PCI_CHIP_R423_UJ:
742 case PCI_CHIP_R423_UK:
743 case PCI_CHIP_R430_554C:
744 case PCI_CHIP_R430_554D:
745 case PCI_CHIP_R430_554E:
746 case PCI_CHIP_R430_554F:
747 case PCI_CHIP_R423_5550:
748 case PCI_CHIP_R423_UQ:
749 case PCI_CHIP_R423_UR:
750 case PCI_CHIP_R423_UT:
751 case PCI_CHIP_R430_5D48:
752 case PCI_CHIP_R430_5D49:
753 case PCI_CHIP_R430_5D4A:
754 case PCI_CHIP_R480_5D4C:
755 case PCI_CHIP_R480_5D4D:
756 case PCI_CHIP_R480_5D4E:
757 case PCI_CHIP_R480_5D4F:
758 case PCI_CHIP_R480_5D50:
759 case PCI_CHIP_R480_5D52:
760 case PCI_CHIP_R423_5D57:
761 screen->chip_family = CHIP_FAMILY_R420;
762 screen->chip_flags = RADEON_CHIPSET_TCL;
763 break;
764
765 case PCI_CHIP_RV410_5E4C:
766 case PCI_CHIP_RV410_5E4F:
767 case PCI_CHIP_RV410_564A:
768 case PCI_CHIP_RV410_564B:
769 case PCI_CHIP_RV410_564F:
770 case PCI_CHIP_RV410_5652:
771 case PCI_CHIP_RV410_5653:
772 case PCI_CHIP_RV410_5657:
773 case PCI_CHIP_RV410_5E48:
774 case PCI_CHIP_RV410_5E4A:
775 case PCI_CHIP_RV410_5E4B:
776 case PCI_CHIP_RV410_5E4D:
777 screen->chip_family = CHIP_FAMILY_RV410;
778 screen->chip_flags = RADEON_CHIPSET_TCL;
779 break;
780
781 case PCI_CHIP_RS480_5954:
782 case PCI_CHIP_RS480_5955:
783 case PCI_CHIP_RS482_5974:
784 case PCI_CHIP_RS482_5975:
785 case PCI_CHIP_RS400_5A41:
786 case PCI_CHIP_RS400_5A42:
787 case PCI_CHIP_RC410_5A61:
788 case PCI_CHIP_RC410_5A62:
789 screen->chip_family = CHIP_FAMILY_RS400;
790 break;
791
792 case PCI_CHIP_RS600_793F:
793 case PCI_CHIP_RS600_7941:
794 case PCI_CHIP_RS600_7942:
795 screen->chip_family = CHIP_FAMILY_RS600;
796 break;
797
798 case PCI_CHIP_RS690_791E:
799 case PCI_CHIP_RS690_791F:
800 screen->chip_family = CHIP_FAMILY_RS690;
801 break;
802 case PCI_CHIP_RS740_796C:
803 case PCI_CHIP_RS740_796D:
804 case PCI_CHIP_RS740_796E:
805 case PCI_CHIP_RS740_796F:
806 screen->chip_family = CHIP_FAMILY_RS740;
807 break;
808
809 case PCI_CHIP_R520_7100:
810 case PCI_CHIP_R520_7101:
811 case PCI_CHIP_R520_7102:
812 case PCI_CHIP_R520_7103:
813 case PCI_CHIP_R520_7104:
814 case PCI_CHIP_R520_7105:
815 case PCI_CHIP_R520_7106:
816 case PCI_CHIP_R520_7108:
817 case PCI_CHIP_R520_7109:
818 case PCI_CHIP_R520_710A:
819 case PCI_CHIP_R520_710B:
820 case PCI_CHIP_R520_710C:
821 case PCI_CHIP_R520_710E:
822 case PCI_CHIP_R520_710F:
823 screen->chip_family = CHIP_FAMILY_R520;
824 screen->chip_flags = RADEON_CHIPSET_TCL;
825 break;
826
827 case PCI_CHIP_RV515_7140:
828 case PCI_CHIP_RV515_7141:
829 case PCI_CHIP_RV515_7142:
830 case PCI_CHIP_RV515_7143:
831 case PCI_CHIP_RV515_7144:
832 case PCI_CHIP_RV515_7145:
833 case PCI_CHIP_RV515_7146:
834 case PCI_CHIP_RV515_7147:
835 case PCI_CHIP_RV515_7149:
836 case PCI_CHIP_RV515_714A:
837 case PCI_CHIP_RV515_714B:
838 case PCI_CHIP_RV515_714C:
839 case PCI_CHIP_RV515_714D:
840 case PCI_CHIP_RV515_714E:
841 case PCI_CHIP_RV515_714F:
842 case PCI_CHIP_RV515_7151:
843 case PCI_CHIP_RV515_7152:
844 case PCI_CHIP_RV515_7153:
845 case PCI_CHIP_RV515_715E:
846 case PCI_CHIP_RV515_715F:
847 case PCI_CHIP_RV515_7180:
848 case PCI_CHIP_RV515_7181:
849 case PCI_CHIP_RV515_7183:
850 case PCI_CHIP_RV515_7186:
851 case PCI_CHIP_RV515_7187:
852 case PCI_CHIP_RV515_7188:
853 case PCI_CHIP_RV515_718A:
854 case PCI_CHIP_RV515_718B:
855 case PCI_CHIP_RV515_718C:
856 case PCI_CHIP_RV515_718D:
857 case PCI_CHIP_RV515_718F:
858 case PCI_CHIP_RV515_7193:
859 case PCI_CHIP_RV515_7196:
860 case PCI_CHIP_RV515_719B:
861 case PCI_CHIP_RV515_719F:
862 case PCI_CHIP_RV515_7200:
863 case PCI_CHIP_RV515_7210:
864 case PCI_CHIP_RV515_7211:
865 screen->chip_family = CHIP_FAMILY_RV515;
866 screen->chip_flags = RADEON_CHIPSET_TCL;
867 break;
868
869 case PCI_CHIP_RV530_71C0:
870 case PCI_CHIP_RV530_71C1:
871 case PCI_CHIP_RV530_71C2:
872 case PCI_CHIP_RV530_71C3:
873 case PCI_CHIP_RV530_71C4:
874 case PCI_CHIP_RV530_71C5:
875 case PCI_CHIP_RV530_71C6:
876 case PCI_CHIP_RV530_71C7:
877 case PCI_CHIP_RV530_71CD:
878 case PCI_CHIP_RV530_71CE:
879 case PCI_CHIP_RV530_71D2:
880 case PCI_CHIP_RV530_71D4:
881 case PCI_CHIP_RV530_71D5:
882 case PCI_CHIP_RV530_71D6:
883 case PCI_CHIP_RV530_71DA:
884 case PCI_CHIP_RV530_71DE:
885 screen->chip_family = CHIP_FAMILY_RV530;
886 screen->chip_flags = RADEON_CHIPSET_TCL;
887 break;
888
889 case PCI_CHIP_R580_7240:
890 case PCI_CHIP_R580_7243:
891 case PCI_CHIP_R580_7244:
892 case PCI_CHIP_R580_7245:
893 case PCI_CHIP_R580_7246:
894 case PCI_CHIP_R580_7247:
895 case PCI_CHIP_R580_7248:
896 case PCI_CHIP_R580_7249:
897 case PCI_CHIP_R580_724A:
898 case PCI_CHIP_R580_724B:
899 case PCI_CHIP_R580_724C:
900 case PCI_CHIP_R580_724D:
901 case PCI_CHIP_R580_724E:
902 case PCI_CHIP_R580_724F:
903 case PCI_CHIP_R580_7284:
904 screen->chip_family = CHIP_FAMILY_R580;
905 screen->chip_flags = RADEON_CHIPSET_TCL;
906 break;
907
908 case PCI_CHIP_RV570_7280:
909 case PCI_CHIP_RV560_7281:
910 case PCI_CHIP_RV560_7283:
911 case PCI_CHIP_RV560_7287:
912 case PCI_CHIP_RV570_7288:
913 case PCI_CHIP_RV570_7289:
914 case PCI_CHIP_RV570_728B:
915 case PCI_CHIP_RV570_728C:
916 case PCI_CHIP_RV560_7290:
917 case PCI_CHIP_RV560_7291:
918 case PCI_CHIP_RV560_7293:
919 case PCI_CHIP_RV560_7297:
920 screen->chip_family = CHIP_FAMILY_RV560;
921 screen->chip_flags = RADEON_CHIPSET_TCL;
922 break;
923
924 case PCI_CHIP_R600_9400:
925 case PCI_CHIP_R600_9401:
926 case PCI_CHIP_R600_9402:
927 case PCI_CHIP_R600_9403:
928 case PCI_CHIP_R600_9405:
929 case PCI_CHIP_R600_940A:
930 case PCI_CHIP_R600_940B:
931 case PCI_CHIP_R600_940F:
932 screen->chip_family = CHIP_FAMILY_R600;
933 screen->chip_flags = RADEON_CHIPSET_TCL;
934 break;
935
936 case PCI_CHIP_RV610_94C0:
937 case PCI_CHIP_RV610_94C1:
938 case PCI_CHIP_RV610_94C3:
939 case PCI_CHIP_RV610_94C4:
940 case PCI_CHIP_RV610_94C5:
941 case PCI_CHIP_RV610_94C6:
942 case PCI_CHIP_RV610_94C7:
943 case PCI_CHIP_RV610_94C8:
944 case PCI_CHIP_RV610_94C9:
945 case PCI_CHIP_RV610_94CB:
946 case PCI_CHIP_RV610_94CC:
947 case PCI_CHIP_RV610_94CD:
948 screen->chip_family = CHIP_FAMILY_RV610;
949 screen->chip_flags = RADEON_CHIPSET_TCL;
950 break;
951
952 case PCI_CHIP_RV630_9580:
953 case PCI_CHIP_RV630_9581:
954 case PCI_CHIP_RV630_9583:
955 case PCI_CHIP_RV630_9586:
956 case PCI_CHIP_RV630_9587:
957 case PCI_CHIP_RV630_9588:
958 case PCI_CHIP_RV630_9589:
959 case PCI_CHIP_RV630_958A:
960 case PCI_CHIP_RV630_958B:
961 case PCI_CHIP_RV630_958C:
962 case PCI_CHIP_RV630_958D:
963 case PCI_CHIP_RV630_958E:
964 case PCI_CHIP_RV630_958F:
965 screen->chip_family = CHIP_FAMILY_RV630;
966 screen->chip_flags = RADEON_CHIPSET_TCL;
967 break;
968
969 case PCI_CHIP_RV670_9500:
970 case PCI_CHIP_RV670_9501:
971 case PCI_CHIP_RV670_9504:
972 case PCI_CHIP_RV670_9505:
973 case PCI_CHIP_RV670_9506:
974 case PCI_CHIP_RV670_9507:
975 case PCI_CHIP_RV670_9508:
976 case PCI_CHIP_RV670_9509:
977 case PCI_CHIP_RV670_950F:
978 case PCI_CHIP_RV670_9511:
979 case PCI_CHIP_RV670_9515:
980 case PCI_CHIP_RV670_9517:
981 case PCI_CHIP_RV670_9519:
982 screen->chip_family = CHIP_FAMILY_RV670;
983 screen->chip_flags = RADEON_CHIPSET_TCL;
984 break;
985
986 case PCI_CHIP_RV620_95C0:
987 case PCI_CHIP_RV620_95C2:
988 case PCI_CHIP_RV620_95C4:
989 case PCI_CHIP_RV620_95C5:
990 case PCI_CHIP_RV620_95C6:
991 case PCI_CHIP_RV620_95C7:
992 case PCI_CHIP_RV620_95C9:
993 case PCI_CHIP_RV620_95CC:
994 case PCI_CHIP_RV620_95CD:
995 case PCI_CHIP_RV620_95CE:
996 case PCI_CHIP_RV620_95CF:
997 screen->chip_family = CHIP_FAMILY_RV620;
998 screen->chip_flags = RADEON_CHIPSET_TCL;
999 break;
1000
1001 case PCI_CHIP_RV635_9590:
1002 case PCI_CHIP_RV635_9591:
1003 case PCI_CHIP_RV635_9593:
1004 case PCI_CHIP_RV635_9595:
1005 case PCI_CHIP_RV635_9596:
1006 case PCI_CHIP_RV635_9597:
1007 case PCI_CHIP_RV635_9598:
1008 case PCI_CHIP_RV635_9599:
1009 case PCI_CHIP_RV635_959B:
1010 screen->chip_family = CHIP_FAMILY_RV635;
1011 screen->chip_flags = RADEON_CHIPSET_TCL;
1012 break;
1013
1014 case PCI_CHIP_RS780_9610:
1015 case PCI_CHIP_RS780_9611:
1016 case PCI_CHIP_RS780_9612:
1017 case PCI_CHIP_RS780_9613:
1018 case PCI_CHIP_RS780_9614:
1019 case PCI_CHIP_RS780_9615:
1020 case PCI_CHIP_RS780_9616:
1021 screen->chip_family = CHIP_FAMILY_RS780;
1022 screen->chip_flags = RADEON_CHIPSET_TCL;
1023 break;
1024 case PCI_CHIP_RS880_9710:
1025 case PCI_CHIP_RS880_9711:
1026 case PCI_CHIP_RS880_9712:
1027 case PCI_CHIP_RS880_9713:
1028 case PCI_CHIP_RS880_9714:
1029 case PCI_CHIP_RS880_9715:
1030 screen->chip_family = CHIP_FAMILY_RS880;
1031 screen->chip_flags = RADEON_CHIPSET_TCL;
1032 break;
1033
1034 case PCI_CHIP_RV770_9440:
1035 case PCI_CHIP_RV770_9441:
1036 case PCI_CHIP_RV770_9442:
1037 case PCI_CHIP_RV770_9443:
1038 case PCI_CHIP_RV770_9444:
1039 case PCI_CHIP_RV770_9446:
1040 case PCI_CHIP_RV770_944A:
1041 case PCI_CHIP_RV770_944B:
1042 case PCI_CHIP_RV770_944C:
1043 case PCI_CHIP_RV770_944E:
1044 case PCI_CHIP_RV770_9450:
1045 case PCI_CHIP_RV770_9452:
1046 case PCI_CHIP_RV770_9456:
1047 case PCI_CHIP_RV770_945A:
1048 case PCI_CHIP_RV770_945B:
1049 case PCI_CHIP_RV770_945E:
1050 case PCI_CHIP_RV790_9460:
1051 case PCI_CHIP_RV790_9462:
1052 case PCI_CHIP_RV770_946A:
1053 case PCI_CHIP_RV770_946B:
1054 case PCI_CHIP_RV770_947A:
1055 case PCI_CHIP_RV770_947B:
1056 screen->chip_family = CHIP_FAMILY_RV770;
1057 screen->chip_flags = RADEON_CHIPSET_TCL;
1058 break;
1059
1060 case PCI_CHIP_RV730_9480:
1061 case PCI_CHIP_RV730_9487:
1062 case PCI_CHIP_RV730_9488:
1063 case PCI_CHIP_RV730_9489:
1064 case PCI_CHIP_RV730_948A:
1065 case PCI_CHIP_RV730_948F:
1066 case PCI_CHIP_RV730_9490:
1067 case PCI_CHIP_RV730_9491:
1068 case PCI_CHIP_RV730_9495:
1069 case PCI_CHIP_RV730_9498:
1070 case PCI_CHIP_RV730_949C:
1071 case PCI_CHIP_RV730_949E:
1072 case PCI_CHIP_RV730_949F:
1073 screen->chip_family = CHIP_FAMILY_RV730;
1074 screen->chip_flags = RADEON_CHIPSET_TCL;
1075 break;
1076
1077 case PCI_CHIP_RV710_9540:
1078 case PCI_CHIP_RV710_9541:
1079 case PCI_CHIP_RV710_9542:
1080 case PCI_CHIP_RV710_954E:
1081 case PCI_CHIP_RV710_954F:
1082 case PCI_CHIP_RV710_9552:
1083 case PCI_CHIP_RV710_9553:
1084 case PCI_CHIP_RV710_9555:
1085 case PCI_CHIP_RV710_9557:
1086 case PCI_CHIP_RV710_955F:
1087 screen->chip_family = CHIP_FAMILY_RV710;
1088 screen->chip_flags = RADEON_CHIPSET_TCL;
1089 break;
1090
1091 case PCI_CHIP_RV740_94A0:
1092 case PCI_CHIP_RV740_94A1:
1093 case PCI_CHIP_RV740_94A3:
1094 case PCI_CHIP_RV740_94B1:
1095 case PCI_CHIP_RV740_94B3:
1096 case PCI_CHIP_RV740_94B4:
1097 case PCI_CHIP_RV740_94B5:
1098 case PCI_CHIP_RV740_94B9:
1099 screen->chip_family = CHIP_FAMILY_RV740;
1100 screen->chip_flags = RADEON_CHIPSET_TCL;
1101 break;
1102
1103 case PCI_CHIP_CEDAR_68E0:
1104 case PCI_CHIP_CEDAR_68E1:
1105 case PCI_CHIP_CEDAR_68E4:
1106 case PCI_CHIP_CEDAR_68E5:
1107 case PCI_CHIP_CEDAR_68E8:
1108 case PCI_CHIP_CEDAR_68E9:
1109 case PCI_CHIP_CEDAR_68F1:
1110 case PCI_CHIP_CEDAR_68F8:
1111 case PCI_CHIP_CEDAR_68F9:
1112 case PCI_CHIP_CEDAR_68FE:
1113 screen->chip_family = CHIP_FAMILY_CEDAR;
1114 screen->chip_flags = RADEON_CHIPSET_TCL;
1115 break;
1116
1117 case PCI_CHIP_REDWOOD_68C0:
1118 case PCI_CHIP_REDWOOD_68C1:
1119 case PCI_CHIP_REDWOOD_68C8:
1120 case PCI_CHIP_REDWOOD_68C9:
1121 case PCI_CHIP_REDWOOD_68D8:
1122 case PCI_CHIP_REDWOOD_68D9:
1123 case PCI_CHIP_REDWOOD_68DA:
1124 case PCI_CHIP_REDWOOD_68DE:
1125 screen->chip_family = CHIP_FAMILY_REDWOOD;
1126 screen->chip_flags = RADEON_CHIPSET_TCL;
1127 break;
1128
1129 case PCI_CHIP_JUNIPER_68A0:
1130 case PCI_CHIP_JUNIPER_68A1:
1131 case PCI_CHIP_JUNIPER_68A8:
1132 case PCI_CHIP_JUNIPER_68A9:
1133 case PCI_CHIP_JUNIPER_68B0:
1134 case PCI_CHIP_JUNIPER_68B8:
1135 case PCI_CHIP_JUNIPER_68B9:
1136 case PCI_CHIP_JUNIPER_68BE:
1137 screen->chip_family = CHIP_FAMILY_JUNIPER;
1138 screen->chip_flags = RADEON_CHIPSET_TCL;
1139 break;
1140
1141 case PCI_CHIP_CYPRESS_6880:
1142 case PCI_CHIP_CYPRESS_6888:
1143 case PCI_CHIP_CYPRESS_6889:
1144 case PCI_CHIP_CYPRESS_688A:
1145 case PCI_CHIP_CYPRESS_6898:
1146 case PCI_CHIP_CYPRESS_6899:
1147 case PCI_CHIP_CYPRESS_689E:
1148 screen->chip_family = CHIP_FAMILY_CYPRESS;
1149 screen->chip_flags = RADEON_CHIPSET_TCL;
1150 break;
1151
1152 case PCI_CHIP_HEMLOCK_689C:
1153 case PCI_CHIP_HEMLOCK_689D:
1154 screen->chip_family = CHIP_FAMILY_HEMLOCK;
1155 screen->chip_flags = RADEON_CHIPSET_TCL;
1156 break;
1157
1158 case PCI_CHIP_PALM_9802:
1159 case PCI_CHIP_PALM_9803:
1160 case PCI_CHIP_PALM_9804:
1161 case PCI_CHIP_PALM_9805:
1162 screen->chip_family = CHIP_FAMILY_PALM;
1163 screen->chip_flags = RADEON_CHIPSET_TCL;
1164 break;
1165
1166 case PCI_CHIP_BARTS_6720:
1167 case PCI_CHIP_BARTS_6721:
1168 case PCI_CHIP_BARTS_6722:
1169 case PCI_CHIP_BARTS_6723:
1170 case PCI_CHIP_BARTS_6724:
1171 case PCI_CHIP_BARTS_6725:
1172 case PCI_CHIP_BARTS_6726:
1173 case PCI_CHIP_BARTS_6727:
1174 case PCI_CHIP_BARTS_6728:
1175 case PCI_CHIP_BARTS_6729:
1176 case PCI_CHIP_BARTS_6738:
1177 case PCI_CHIP_BARTS_6739:
1178 screen->chip_family = CHIP_FAMILY_BARTS;
1179 screen->chip_flags = RADEON_CHIPSET_TCL;
1180 break;
1181
1182 case PCI_CHIP_TURKS_6740:
1183 case PCI_CHIP_TURKS_6741:
1184 case PCI_CHIP_TURKS_6742:
1185 case PCI_CHIP_TURKS_6743:
1186 case PCI_CHIP_TURKS_6744:
1187 case PCI_CHIP_TURKS_6745:
1188 case PCI_CHIP_TURKS_6746:
1189 case PCI_CHIP_TURKS_6747:
1190 case PCI_CHIP_TURKS_6748:
1191 case PCI_CHIP_TURKS_6749:
1192 case PCI_CHIP_TURKS_6750:
1193 case PCI_CHIP_TURKS_6758:
1194 case PCI_CHIP_TURKS_6759:
1195 screen->chip_family = CHIP_FAMILY_TURKS;
1196 screen->chip_flags = RADEON_CHIPSET_TCL;
1197 break;
1198
1199 case PCI_CHIP_CAICOS_6760:
1200 case PCI_CHIP_CAICOS_6761:
1201 case PCI_CHIP_CAICOS_6762:
1202 case PCI_CHIP_CAICOS_6763:
1203 case PCI_CHIP_CAICOS_6764:
1204 case PCI_CHIP_CAICOS_6765:
1205 case PCI_CHIP_CAICOS_6766:
1206 case PCI_CHIP_CAICOS_6767:
1207 case PCI_CHIP_CAICOS_6768:
1208 case PCI_CHIP_CAICOS_6770:
1209 case PCI_CHIP_CAICOS_6779:
1210 screen->chip_family = CHIP_FAMILY_CAICOS;
1211 screen->chip_flags = RADEON_CHIPSET_TCL;
1212 break;
1213
1214 default:
1215 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
1216 device_id);
1217 return -1;
1218 }
1219
1220 return 0;
1221 }
1222
1223
1224 /* Create the device specific screen private data struct.
1225 */
1226 static radeonScreenPtr
1227 radeonCreateScreen( __DRIscreen *sPriv )
1228 {
1229 radeonScreenPtr screen;
1230 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
1231 unsigned char *RADEONMMIO = NULL;
1232 int i;
1233 int ret;
1234 uint32_t temp = 0;
1235
1236 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
1237 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
1238 return GL_FALSE;
1239 }
1240
1241 /* Allocate the private area */
1242 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1243 if ( !screen ) {
1244 __driUtilMessage("%s: Could not allocate memory for screen structure",
1245 __FUNCTION__);
1246 return NULL;
1247 }
1248
1249 radeon_init_debug();
1250
1251 /* parse information in __driConfigOptions */
1252 driParseOptionInfo (&screen->optionCache,
1253 __driConfigOptions, __driNConfigOptions);
1254
1255 /* This is first since which regions we map depends on whether or
1256 * not we are using a PCI card.
1257 */
1258 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
1259 {
1260 int ret;
1261
1262 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET,
1263 &screen->gart_buffer_offset);
1264
1265 if (ret) {
1266 FREE( screen );
1267 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
1268 return NULL;
1269 }
1270
1271 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE,
1272 &screen->gart_base);
1273 if (ret) {
1274 FREE( screen );
1275 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
1276 return NULL;
1277 }
1278
1279 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR,
1280 &screen->irq);
1281 if (ret) {
1282 FREE( screen );
1283 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
1284 return NULL;
1285 }
1286 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
1287 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
1288 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
1289 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
1290 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
1291 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
1292 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
1293 screen->drmSupportsOcclusionQueries = (sPriv->drm_version.minor >= 30);
1294 }
1295
1296 ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
1297 if (ret == -1)
1298 return NULL;
1299
1300 screen->mmio.handle = dri_priv->registerHandle;
1301 screen->mmio.size = dri_priv->registerSize;
1302 if ( drmMap( sPriv->fd,
1303 screen->mmio.handle,
1304 screen->mmio.size,
1305 &screen->mmio.map ) ) {
1306 FREE( screen );
1307 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
1308 return NULL;
1309 }
1310
1311 RADEONMMIO = screen->mmio.map;
1312
1313 screen->status.handle = dri_priv->statusHandle;
1314 screen->status.size = dri_priv->statusSize;
1315 if ( drmMap( sPriv->fd,
1316 screen->status.handle,
1317 screen->status.size,
1318 &screen->status.map ) ) {
1319 drmUnmap( screen->mmio.map, screen->mmio.size );
1320 FREE( screen );
1321 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
1322 return NULL;
1323 }
1324 if (screen->chip_family < CHIP_FAMILY_R600)
1325 screen->scratch = (__volatile__ uint32_t *)
1326 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
1327 else
1328 screen->scratch = (__volatile__ uint32_t *)
1329 ((GLubyte *)screen->status.map + R600_SCRATCH_REG_OFFSET);
1330
1331 screen->buffers = drmMapBufs( sPriv->fd );
1332 if ( !screen->buffers ) {
1333 drmUnmap( screen->status.map, screen->status.size );
1334 drmUnmap( screen->mmio.map, screen->mmio.size );
1335 FREE( screen );
1336 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
1337 return NULL;
1338 }
1339
1340 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
1341 screen->gartTextures.handle = dri_priv->gartTexHandle;
1342 screen->gartTextures.size = dri_priv->gartTexMapSize;
1343 if ( drmMap( sPriv->fd,
1344 screen->gartTextures.handle,
1345 screen->gartTextures.size,
1346 (drmAddressPtr)&screen->gartTextures.map ) ) {
1347 drmUnmapBufs( screen->buffers );
1348 drmUnmap( screen->status.map, screen->status.size );
1349 drmUnmap( screen->mmio.map, screen->mmio.size );
1350 FREE( screen );
1351 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
1352 return NULL;
1353 }
1354
1355 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
1356 }
1357
1358 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
1359 sPriv->ddx_version.minor < 2) {
1360 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
1361 return NULL;
1362 }
1363
1364 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
1365 fprintf(stderr, "R500 support requires a newer drm.\n");
1366 return NULL;
1367 }
1368
1369 if (getenv("R300_NO_TCL"))
1370 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1371
1372 if (screen->chip_family <= CHIP_FAMILY_RS200)
1373 screen->chip_flags |= RADEON_CLASS_R100;
1374 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1375 screen->chip_flags |= RADEON_CLASS_R200;
1376 else if (screen->chip_family <= CHIP_FAMILY_RV570)
1377 screen->chip_flags |= RADEON_CLASS_R300;
1378 else
1379 screen->chip_flags |= RADEON_CLASS_R600;
1380
1381 /* set group bytes for r6xx+ */
1382 if (screen->chip_family >= CHIP_FAMILY_CEDAR)
1383 screen->group_bytes = 512;
1384 else
1385 screen->group_bytes = 256;
1386
1387 screen->cpp = dri_priv->bpp / 8;
1388 screen->AGPMode = dri_priv->AGPMode;
1389
1390 ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp);
1391
1392 /* +r6/r7 */
1393 if(screen->chip_family >= CHIP_FAMILY_R600)
1394 {
1395 if (ret)
1396 {
1397 FREE( screen );
1398 fprintf(stderr, "Unable to get fb location need newer drm\n");
1399 return NULL;
1400 }
1401 else
1402 {
1403 screen->fbLocation = (temp & 0xffff) << 24;
1404 }
1405 }
1406 else
1407 {
1408 if (ret)
1409 {
1410 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm)
1411 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
1412 else
1413 {
1414 FREE( screen );
1415 fprintf(stderr, "Unable to get fb location need newer drm\n");
1416 return NULL;
1417 }
1418 }
1419 else
1420 {
1421 screen->fbLocation = (temp & 0xffff) << 16;
1422 }
1423 }
1424
1425 if (IS_R300_CLASS(screen)) {
1426 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1427 if (ret) {
1428 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1429 switch (screen->chip_family) {
1430 case CHIP_FAMILY_R300:
1431 case CHIP_FAMILY_R350:
1432 screen->num_gb_pipes = 2;
1433 break;
1434 case CHIP_FAMILY_R420:
1435 case CHIP_FAMILY_R520:
1436 case CHIP_FAMILY_R580:
1437 case CHIP_FAMILY_RV560:
1438 case CHIP_FAMILY_RV570:
1439 screen->num_gb_pipes = 4;
1440 break;
1441 case CHIP_FAMILY_RV350:
1442 case CHIP_FAMILY_RV515:
1443 case CHIP_FAMILY_RV530:
1444 case CHIP_FAMILY_RV410:
1445 default:
1446 screen->num_gb_pipes = 1;
1447 break;
1448 }
1449 } else {
1450 screen->num_gb_pipes = temp;
1451 }
1452
1453 /* pipe overrides */
1454 switch (dri_priv->deviceID) {
1455 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1456 case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */
1457 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
1458 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
1459 screen->num_gb_pipes = 1;
1460 break;
1461 default:
1462 break;
1463 }
1464
1465 if ( sPriv->drm_version.minor >= 31 ) {
1466 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp);
1467 if (ret)
1468 screen->num_z_pipes = 2;
1469 else
1470 screen->num_z_pipes = temp;
1471 } else
1472 screen->num_z_pipes = 2;
1473 }
1474
1475 if ( sPriv->drm_version.minor >= 10 ) {
1476 drm_radeon_setparam_t sp;
1477
1478 sp.param = RADEON_SETPARAM_FB_LOCATION;
1479 sp.value = screen->fbLocation;
1480
1481 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
1482 &sp, sizeof( sp ) );
1483 }
1484
1485 screen->frontOffset = dri_priv->frontOffset;
1486 screen->frontPitch = dri_priv->frontPitch;
1487 screen->backOffset = dri_priv->backOffset;
1488 screen->backPitch = dri_priv->backPitch;
1489 screen->depthOffset = dri_priv->depthOffset;
1490 screen->depthPitch = dri_priv->depthPitch;
1491
1492 /* Check if ddx has set up a surface reg to cover depth buffer */
1493 screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
1494 /* these chips don't use tiled z without hyperz. So always pretend
1495 we have set up a surface which will cause linear reads/writes */
1496 (IS_R100_CLASS(screen) &&
1497 !(screen->chip_flags & RADEON_CHIPSET_TCL));
1498
1499 if ( dri_priv->textureSize == 0 ) {
1500 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
1501 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
1502 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
1503 dri_priv->log2GARTTexGran;
1504 } else {
1505 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
1506 + screen->fbLocation;
1507 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
1508 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
1509 dri_priv->log2TexGran;
1510 }
1511
1512 if ( !screen->gartTextures.map || dri_priv->textureSize == 0
1513 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
1514 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
1515 screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
1516 screen->texSize[RADEON_GART_TEX_HEAP] = 0;
1517 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
1518 } else {
1519 screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
1520 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
1521 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
1522 screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
1523 dri_priv->log2GARTTexGran;
1524 }
1525
1526 i = 0;
1527 screen->extensions[i++] = &driCopySubBufferExtension.base;
1528 screen->extensions[i++] = &driReadDrawableExtension;
1529
1530 if ( screen->irq != 0 ) {
1531 screen->extensions[i++] = &driSwapControlExtension.base;
1532 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1533 }
1534
1535 #if defined(RADEON_R100)
1536 screen->extensions[i++] = &radeonTexOffsetExtension.base;
1537 #endif
1538
1539 #if defined(RADEON_R200)
1540 screen->extensions[i++] = &r200texOffsetExtension.base;
1541 #endif
1542
1543 #if defined(RADEON_R300)
1544 screen->extensions[i++] = &r300texOffsetExtension.base;
1545 #endif
1546
1547 #if defined(RADEON_R600)
1548 screen->extensions[i++] = &r600texOffsetExtension.base;
1549 #endif
1550
1551 screen->extensions[i++] = &dri2ConfigQueryExtension.base;
1552
1553 screen->extensions[i++] = NULL;
1554 sPriv->extensions = screen->extensions;
1555
1556 screen->driScreen = sPriv;
1557 screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
1558 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
1559 screen->sarea_priv_offset);
1560
1561 screen->bom = radeon_bo_manager_legacy_ctor(screen);
1562 if (screen->bom == NULL) {
1563 free(screen);
1564 return NULL;
1565 }
1566
1567 return screen;
1568 }
1569
1570 static radeonScreenPtr
1571 radeonCreateScreen2(__DRIscreen *sPriv)
1572 {
1573 radeonScreenPtr screen;
1574 int i;
1575 int ret;
1576 uint32_t device_id = 0;
1577 uint32_t temp = 0;
1578
1579 /* Allocate the private area */
1580 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1581 if ( !screen ) {
1582 __driUtilMessage("%s: Could not allocate memory for screen structure",
1583 __FUNCTION__);
1584 fprintf(stderr, "leaving here\n");
1585 return NULL;
1586 }
1587
1588 radeon_init_debug();
1589
1590 /* parse information in __driConfigOptions */
1591 driParseOptionInfo (&screen->optionCache,
1592 __driConfigOptions, __driNConfigOptions);
1593
1594 screen->kernel_mm = 1;
1595 screen->chip_flags = 0;
1596
1597 /* if we have kms we can support all of these */
1598 screen->drmSupportsCubeMapsR200 = 1;
1599 screen->drmSupportsBlendColor = 1;
1600 screen->drmSupportsTriPerf = 1;
1601 screen->drmSupportsFragShader = 1;
1602 screen->drmSupportsPointSprites = 1;
1603 screen->drmSupportsCubeMapsR100 = 1;
1604 screen->drmSupportsVertexProgram = 1;
1605 screen->drmSupportsOcclusionQueries = 1;
1606 screen->irq = 1;
1607
1608 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id);
1609 if (ret) {
1610 FREE( screen );
1611 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret);
1612 return NULL;
1613 }
1614
1615 ret = radeon_set_screen_flags(screen, device_id);
1616 if (ret == -1)
1617 return NULL;
1618
1619 if (getenv("R300_NO_TCL"))
1620 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1621
1622 if (screen->chip_family <= CHIP_FAMILY_RS200)
1623 screen->chip_flags |= RADEON_CLASS_R100;
1624 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1625 screen->chip_flags |= RADEON_CLASS_R200;
1626 else if (screen->chip_family <= CHIP_FAMILY_RV570)
1627 screen->chip_flags |= RADEON_CLASS_R300;
1628 else
1629 screen->chip_flags |= RADEON_CLASS_R600;
1630
1631 /* r6xx+ tiling, default group bytes */
1632 if (screen->chip_family >= CHIP_FAMILY_CEDAR)
1633 screen->group_bytes = 512;
1634 else
1635 screen->group_bytes = 256;
1636 if (IS_R600_CLASS(screen) && (sPriv->drm_version.minor >= 6) &&
1637 (screen->chip_family < CHIP_FAMILY_CEDAR)) {
1638 ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
1639 if (ret)
1640 fprintf(stderr, "failed to get tiling info\n");
1641 else {
1642 screen->tile_config = temp;
1643 screen->r7xx_bank_op = 0;
1644 switch((screen->tile_config & 0xe) >> 1) {
1645 case 0:
1646 screen->num_channels = 1;
1647 break;
1648 case 1:
1649 screen->num_channels = 2;
1650 break;
1651 case 2:
1652 screen->num_channels = 4;
1653 break;
1654 case 3:
1655 screen->num_channels = 8;
1656 break;
1657 default:
1658 fprintf(stderr, "bad channels\n");
1659 break;
1660 }
1661 switch((screen->tile_config & 0x30) >> 4) {
1662 case 0:
1663 screen->num_banks = 4;
1664 break;
1665 case 1:
1666 screen->num_banks = 8;
1667 break;
1668 default:
1669 fprintf(stderr, "bad banks\n");
1670 break;
1671 }
1672 switch((screen->tile_config & 0xc0) >> 6) {
1673 case 0:
1674 screen->group_bytes = 256;
1675 break;
1676 case 1:
1677 screen->group_bytes = 512;
1678 break;
1679 default:
1680 fprintf(stderr, "bad group_bytes\n");
1681 break;
1682 }
1683 }
1684 }
1685
1686 if (IS_R300_CLASS(screen)) {
1687 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1688 if (ret) {
1689 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1690 switch (screen->chip_family) {
1691 case CHIP_FAMILY_R300:
1692 case CHIP_FAMILY_R350:
1693 screen->num_gb_pipes = 2;
1694 break;
1695 case CHIP_FAMILY_R420:
1696 case CHIP_FAMILY_R520:
1697 case CHIP_FAMILY_R580:
1698 case CHIP_FAMILY_RV560:
1699 case CHIP_FAMILY_RV570:
1700 screen->num_gb_pipes = 4;
1701 break;
1702 case CHIP_FAMILY_RV350:
1703 case CHIP_FAMILY_RV515:
1704 case CHIP_FAMILY_RV530:
1705 case CHIP_FAMILY_RV410:
1706 default:
1707 screen->num_gb_pipes = 1;
1708 break;
1709 }
1710 } else {
1711 screen->num_gb_pipes = temp;
1712 }
1713
1714 /* pipe overrides */
1715 switch (device_id) {
1716 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1717 case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */
1718 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
1719 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
1720 screen->num_gb_pipes = 1;
1721 break;
1722 default:
1723 break;
1724 }
1725
1726 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp);
1727 if (ret)
1728 screen->num_z_pipes = 2;
1729 else
1730 screen->num_z_pipes = temp;
1731
1732 }
1733
1734 i = 0;
1735 screen->extensions[i++] = &driCopySubBufferExtension.base;
1736 screen->extensions[i++] = &driReadDrawableExtension;
1737 screen->extensions[i++] = &dri2ConfigQueryExtension.base;
1738
1739 if ( screen->irq != 0 ) {
1740 screen->extensions[i++] = &driSwapControlExtension.base;
1741 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1742 }
1743
1744 #if defined(RADEON_R100)
1745 screen->extensions[i++] = &radeonTexBufferExtension.base;
1746 #endif
1747
1748 #if defined(RADEON_R200)
1749 screen->extensions[i++] = &r200TexBufferExtension.base;
1750 #endif
1751
1752 #if defined(RADEON_R300)
1753 screen->extensions[i++] = &r300TexBufferExtension.base;
1754 #endif
1755
1756 #if defined(RADEON_R600)
1757 screen->extensions[i++] = &r600TexBufferExtension.base;
1758 #endif
1759
1760 screen->extensions[i++] = &radeonFlushExtension.base;
1761 screen->extensions[i++] = &radeonImageExtension.base;
1762
1763 screen->extensions[i++] = NULL;
1764 sPriv->extensions = screen->extensions;
1765
1766 screen->driScreen = sPriv;
1767 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1768 if (screen->bom == NULL) {
1769 free(screen);
1770 return NULL;
1771 }
1772 return screen;
1773 }
1774
1775 /* Destroy the device specific screen private data struct.
1776 */
1777 static void
1778 radeonDestroyScreen( __DRIscreen *sPriv )
1779 {
1780 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1781
1782 if (!screen)
1783 return;
1784
1785 if (screen->kernel_mm) {
1786 #ifdef RADEON_BO_TRACK
1787 radeon_tracker_print(&screen->bom->tracker, stderr);
1788 #endif
1789 radeon_bo_manager_gem_dtor(screen->bom);
1790 } else {
1791 radeon_bo_manager_legacy_dtor(screen->bom);
1792
1793 if ( screen->gartTextures.map ) {
1794 drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
1795 }
1796 drmUnmapBufs( screen->buffers );
1797 drmUnmap( screen->status.map, screen->status.size );
1798 drmUnmap( screen->mmio.map, screen->mmio.size );
1799 }
1800
1801 /* free all option information */
1802 driDestroyOptionInfo (&screen->optionCache);
1803
1804 FREE( screen );
1805 sPriv->private = NULL;
1806 }
1807
1808
1809 /* Initialize the driver specific screen private data.
1810 */
1811 static GLboolean
1812 radeonInitDriver( __DRIscreen *sPriv )
1813 {
1814 if (sPriv->dri2.enabled) {
1815 sPriv->private = (void *) radeonCreateScreen2( sPriv );
1816 } else {
1817 sPriv->private = (void *) radeonCreateScreen( sPriv );
1818 }
1819 if ( !sPriv->private ) {
1820 radeonDestroyScreen( sPriv );
1821 return GL_FALSE;
1822 }
1823
1824 return GL_TRUE;
1825 }
1826
1827
1828
1829 /**
1830 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1831 *
1832 * \todo This function (and its interface) will need to be updated to support
1833 * pbuffers.
1834 */
1835 static GLboolean
1836 radeonCreateBuffer( __DRIscreen *driScrnPriv,
1837 __DRIdrawable *driDrawPriv,
1838 const struct gl_config *mesaVis,
1839 GLboolean isPixmap )
1840 {
1841 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1842
1843 const GLboolean swDepth = GL_FALSE;
1844 const GLboolean swAlpha = GL_FALSE;
1845 const GLboolean swAccum = mesaVis->accumRedBits > 0;
1846 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1847 mesaVis->depthBits != 24;
1848 gl_format rgbFormat;
1849 struct radeon_framebuffer *rfb;
1850
1851 if (isPixmap)
1852 return GL_FALSE; /* not implemented */
1853
1854 rfb = CALLOC_STRUCT(radeon_framebuffer);
1855 if (!rfb)
1856 return GL_FALSE;
1857
1858 _mesa_initialize_window_framebuffer(&rfb->base, mesaVis);
1859
1860 if (mesaVis->redBits == 5)
1861 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_RGB565 : MESA_FORMAT_RGB565_REV;
1862 else if (mesaVis->alphaBits == 0)
1863 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_XRGB8888 : MESA_FORMAT_XRGB8888_REV;
1864 else
1865 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB8888_REV;
1866
1867 /* front color renderbuffer */
1868 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1869 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base);
1870 rfb->color_rb[0]->has_surface = 1;
1871
1872 /* back color renderbuffer */
1873 if (mesaVis->doubleBufferMode) {
1874 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1875 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base);
1876 rfb->color_rb[1]->has_surface = 1;
1877 }
1878
1879 if (mesaVis->depthBits == 24) {
1880 if (mesaVis->stencilBits == 8) {
1881 struct radeon_renderbuffer *depthStencilRb =
1882 radeon_create_renderbuffer(MESA_FORMAT_S8_Z24, driDrawPriv);
1883 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base);
1884 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base);
1885 depthStencilRb->has_surface = screen->depthHasSurface;
1886 } else {
1887 /* depth renderbuffer */
1888 struct radeon_renderbuffer *depth =
1889 radeon_create_renderbuffer(MESA_FORMAT_X8_Z24, driDrawPriv);
1890 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1891 depth->has_surface = screen->depthHasSurface;
1892 }
1893 } else if (mesaVis->depthBits == 16) {
1894 /* just 16-bit depth buffer, no hw stencil */
1895 struct radeon_renderbuffer *depth =
1896 radeon_create_renderbuffer(MESA_FORMAT_Z16, driDrawPriv);
1897 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1898 depth->has_surface = screen->depthHasSurface;
1899 }
1900
1901 _mesa_add_soft_renderbuffers(&rfb->base,
1902 GL_FALSE, /* color */
1903 swDepth,
1904 swStencil,
1905 swAccum,
1906 swAlpha,
1907 GL_FALSE /* aux */);
1908 driDrawPriv->driverPrivate = (void *) rfb;
1909
1910 return (driDrawPriv->driverPrivate != NULL);
1911 }
1912
1913
1914 static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb)
1915 {
1916 struct radeon_renderbuffer *rb;
1917
1918 rb = rfb->color_rb[0];
1919 if (rb && rb->bo) {
1920 radeon_bo_unref(rb->bo);
1921 rb->bo = NULL;
1922 }
1923 rb = rfb->color_rb[1];
1924 if (rb && rb->bo) {
1925 radeon_bo_unref(rb->bo);
1926 rb->bo = NULL;
1927 }
1928 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
1929 if (rb && rb->bo) {
1930 radeon_bo_unref(rb->bo);
1931 rb->bo = NULL;
1932 }
1933 }
1934
1935 void
1936 radeonDestroyBuffer(__DRIdrawable *driDrawPriv)
1937 {
1938 struct radeon_framebuffer *rfb;
1939 if (!driDrawPriv)
1940 return;
1941
1942 rfb = (void*)driDrawPriv->driverPrivate;
1943 if (!rfb)
1944 return;
1945 radeon_cleanup_renderbuffers(rfb);
1946 _mesa_reference_framebuffer((struct gl_framebuffer **)(&(driDrawPriv->driverPrivate)), NULL);
1947 }
1948
1949
1950 /**
1951 * This is the driver specific part of the createNewScreen entry point.
1952 *
1953 * \todo maybe fold this into intelInitDriver
1954 *
1955 * \return the struct gl_config supported by this driver
1956 */
1957 static const __DRIconfig **
1958 radeonInitScreen(__DRIscreen *psp)
1959 {
1960 #if defined(RADEON_R100)
1961 static const char *driver_name = "Radeon";
1962 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1963 static const __DRIversion dri_expected = { 4, 0, 0 };
1964 static const __DRIversion drm_expected = { 1, 6, 0 };
1965 #elif defined(RADEON_R200)
1966 static const char *driver_name = "R200";
1967 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1968 static const __DRIversion dri_expected = { 4, 0, 0 };
1969 static const __DRIversion drm_expected = { 1, 6, 0 };
1970 #elif defined(RADEON_R300)
1971 static const char *driver_name = "R300";
1972 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1973 static const __DRIversion dri_expected = { 4, 0, 0 };
1974 static const __DRIversion drm_expected = { 1, 24, 0 };
1975 #elif defined(RADEON_R600)
1976 static const char *driver_name = "R600";
1977 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1978 static const __DRIversion dri_expected = { 4, 0, 0 };
1979 static const __DRIversion drm_expected = { 1, 24, 0 };
1980 #endif
1981 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1982
1983 if ( ! driCheckDriDdxDrmVersions3( driver_name,
1984 &psp->dri_version, & dri_expected,
1985 &psp->ddx_version, & ddx_expected,
1986 &psp->drm_version, & drm_expected ) ) {
1987 return NULL;
1988 }
1989
1990 if (!radeonInitDriver(psp))
1991 return NULL;
1992
1993 /* for now fill in all modes */
1994 return radeonFillInModes( psp,
1995 dri_priv->bpp,
1996 (dri_priv->bpp == 16) ? 16 : 24,
1997 (dri_priv->bpp == 16) ? 0 : 8, 1);
1998 }
1999 #define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
2000
2001 /**
2002 * This is the driver specific part of the createNewScreen entry point.
2003 * Called when using DRI2.
2004 *
2005 * \return the struct gl_config supported by this driver
2006 */
2007 static const
2008 __DRIconfig **radeonInitScreen2(__DRIscreen *psp)
2009 {
2010 GLenum fb_format[3];
2011 GLenum fb_type[3];
2012 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
2013 * support pageflipping at all.
2014 */
2015 static const GLenum back_buffer_modes[] = {
2016 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/
2017 };
2018 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
2019 int color;
2020 __DRIconfig **configs = NULL;
2021
2022 if (!radeonInitDriver(psp)) {
2023 return NULL;
2024 }
2025 depth_bits[0] = 0;
2026 stencil_bits[0] = 0;
2027 depth_bits[1] = 16;
2028 stencil_bits[1] = 0;
2029 depth_bits[2] = 24;
2030 stencil_bits[2] = 0;
2031 depth_bits[3] = 24;
2032 stencil_bits[3] = 8;
2033
2034 msaa_samples_array[0] = 0;
2035
2036 fb_format[0] = GL_RGB;
2037 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5;
2038
2039 fb_format[1] = GL_BGR;
2040 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV;
2041
2042 fb_format[2] = GL_BGRA;
2043 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
2044
2045 for (color = 0; color < ARRAY_SIZE(fb_format); color++) {
2046 __DRIconfig **new_configs;
2047
2048 new_configs = driCreateConfigs(fb_format[color], fb_type[color],
2049 depth_bits,
2050 stencil_bits,
2051 ARRAY_SIZE(depth_bits),
2052 back_buffer_modes,
2053 ARRAY_SIZE(back_buffer_modes),
2054 msaa_samples_array,
2055 ARRAY_SIZE(msaa_samples_array),
2056 GL_TRUE);
2057 if (configs == NULL)
2058 configs = new_configs;
2059 else
2060 configs = driConcatConfigs(configs, new_configs);
2061 }
2062
2063 if (configs == NULL) {
2064 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
2065 __LINE__);
2066 return NULL;
2067 }
2068
2069 return (const __DRIconfig **)configs;
2070 }
2071
2072 /**
2073 * Get information about previous buffer swaps.
2074 */
2075 static int
2076 getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo )
2077 {
2078 struct radeon_framebuffer *rfb;
2079
2080 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
2081 || (dPriv->driContextPriv->driverPrivate == NULL)
2082 || (sInfo == NULL) ) {
2083 return -1;
2084 }
2085
2086 rfb = dPriv->driverPrivate;
2087 sInfo->swap_count = rfb->swap_count;
2088 sInfo->swap_ust = rfb->swap_ust;
2089 sInfo->swap_missed_count = rfb->swap_missed_count;
2090
2091 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
2092 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust )
2093 : 0.0;
2094
2095 return 0;
2096 }
2097
2098 const struct __DriverAPIRec driDriverAPI = {
2099 .InitScreen = radeonInitScreen,
2100 .DestroyScreen = radeonDestroyScreen,
2101 #if defined(RADEON_R200)
2102 .CreateContext = r200CreateContext,
2103 .DestroyContext = r200DestroyContext,
2104 #elif defined(RADEON_R600)
2105 .CreateContext = r600CreateContext,
2106 .DestroyContext = radeonDestroyContext,
2107 #elif defined(RADEON_R300)
2108 .CreateContext = r300CreateContext,
2109 .DestroyContext = radeonDestroyContext,
2110 #else
2111 .CreateContext = r100CreateContext,
2112 .DestroyContext = radeonDestroyContext,
2113 #endif
2114 .CreateBuffer = radeonCreateBuffer,
2115 .DestroyBuffer = radeonDestroyBuffer,
2116 .SwapBuffers = radeonSwapBuffers,
2117 .MakeCurrent = radeonMakeCurrent,
2118 .UnbindContext = radeonUnbindContext,
2119 .GetSwapInfo = getSwapInfo,
2120 .GetDrawableMSC = driDrawableGetMSC32,
2121 .WaitForMSC = driWaitForMSC32,
2122 .WaitForSBC = NULL,
2123 .SwapBuffersMSC = NULL,
2124 .CopySubBuffer = radeonCopySubBuffer,
2125 /* DRI2 */
2126 .InitScreen2 = radeonInitScreen2,
2127 };
2128
2129 /* This is the table of extensions that the loader will dlsym() for. */
2130 PUBLIC const __DRIextension *__driDriverExtensions[] = {
2131 &driCoreExtension.base,
2132 &driLegacyExtension.base,
2133 &driDRI2Extension.base,
2134 NULL
2135 };