projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeon: settexbuffer support
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
36 */
37
38 #include <errno.h>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
44
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #include "radeon_common.h"
50 #include "radeon_span.h"
51 #if !RADEON_COMMON
52 #include "radeon_context.h"
53 #include "radeon_tex.h"
54 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
55 #include "r200_context.h"
56 #include "r200_ioctl.h"
57 #include "r200_tex.h"
58 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
59 #include "r300_context.h"
60 #include "r300_fragprog.h"
61 #include "r300_tex.h"
62 #endif
63
64 #include "utils.h"
65 #include "vblank.h"
66 #include "drirenderbuffer.h"
67
68 #include "radeon_bocs_wrapper.h"
69
70 #include "GL/internal/dri_interface.h"
71
72 /* Radeon configuration
73 */
74 #include "xmlpool.h"
75
76 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
77 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
78 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
79 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
80 DRI_CONF_OPT_END
81
82 #if !RADEON_COMMON /* R100 */
83 PUBLIC const char __driConfigOptions[] =
84 DRI_CONF_BEGIN
85 DRI_CONF_SECTION_PERFORMANCE
86 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
87 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
88 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
89 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
90 DRI_CONF_HYPERZ(false)
91 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
92 DRI_CONF_SECTION_END
93 DRI_CONF_SECTION_QUALITY
94 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
95 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
96 DRI_CONF_NO_NEG_LOD_BIAS(false)
97 DRI_CONF_FORCE_S3TC_ENABLE(false)
98 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
99 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
100 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
101 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
102 DRI_CONF_SECTION_END
103 DRI_CONF_SECTION_DEBUG
104 DRI_CONF_NO_RAST(false)
105 DRI_CONF_SECTION_END
106 DRI_CONF_END;
107 static const GLuint __driNConfigOptions = 15;
108
109 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
110
111 PUBLIC const char __driConfigOptions[] =
112 DRI_CONF_BEGIN
113 DRI_CONF_SECTION_PERFORMANCE
114 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
115 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
116 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
117 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
118 DRI_CONF_HYPERZ(false)
119 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
120 DRI_CONF_SECTION_END
121 DRI_CONF_SECTION_QUALITY
122 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
123 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
124 DRI_CONF_NO_NEG_LOD_BIAS(false)
125 DRI_CONF_FORCE_S3TC_ENABLE(false)
126 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
127 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
128 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
129 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
130 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
131 DRI_CONF_SECTION_END
132 DRI_CONF_SECTION_DEBUG
133 DRI_CONF_NO_RAST(false)
134 DRI_CONF_SECTION_END
135 DRI_CONF_SECTION_SOFTWARE
136 DRI_CONF_NV_VERTEX_PROGRAM(false)
137 DRI_CONF_SECTION_END
138 DRI_CONF_END;
139 static const GLuint __driNConfigOptions = 17;
140
141 extern const struct dri_extension blend_extensions[];
142 extern const struct dri_extension ARB_vp_extension[];
143 extern const struct dri_extension NV_vp_extension[];
144 extern const struct dri_extension ATI_fs_extension[];
145 extern const struct dri_extension point_extensions[];
146
147 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
148
149 /* TODO: integrate these into xmlpool.h! */
150 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
151 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
152 DRI_CONF_DESC(en,"Number of texture image units") \
153 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
154 DRI_CONF_OPT_END
155
156 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
157 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
158 DRI_CONF_DESC(en,"Number of texture coordinate units") \
159 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
160 DRI_CONF_OPT_END
161
162
163
164 #define DRI_CONF_DISABLE_S3TC(def) \
165 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
166 DRI_CONF_DESC(en,"Disable S3TC compression") \
167 DRI_CONF_OPT_END
168
169 #define DRI_CONF_DISABLE_FALLBACK(def) \
170 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
171 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
172 DRI_CONF_OPT_END
173
174 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
175 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
176 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
177 DRI_CONF_OPT_END
178
179 #define DRI_CONF_FP_OPTIMIZATION(def) \
180 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
181 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
182 DRI_CONF_ENUM(0,"Optimize for Speed") \
183 DRI_CONF_ENUM(1,"Optimize for Quality") \
184 DRI_CONF_DESC_END \
185 DRI_CONF_OPT_END
186
187 PUBLIC const char __driConfigOptions[] =
188 DRI_CONF_BEGIN
189 DRI_CONF_SECTION_PERFORMANCE
190 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
191 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
192 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
193 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
194 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
195 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
196 DRI_CONF_DISABLE_FALLBACK(true)
197 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
198 DRI_CONF_SECTION_END
199 DRI_CONF_SECTION_QUALITY
200 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
201 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
202 DRI_CONF_FORCE_S3TC_ENABLE(false)
203 DRI_CONF_DISABLE_S3TC(false)
204 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
205 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
206 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
207 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
208 DRI_CONF_SECTION_END
209 DRI_CONF_SECTION_DEBUG
210 DRI_CONF_NO_RAST(false)
211 DRI_CONF_SECTION_END
212 DRI_CONF_END;
213 static const GLuint __driNConfigOptions = 17;
214
215 extern const struct dri_extension gl_20_extension[];
216
217 #ifndef RADEON_DEBUG
218
219 static const struct dri_debug_control debug_control[] = {
220 {"fall", DEBUG_FALLBACKS},
221 {"tex", DEBUG_TEXTURE},
222 {"ioctl", DEBUG_IOCTL},
223 {"prim", DEBUG_PRIMS},
224 {"vert", DEBUG_VERTS},
225 {"state", DEBUG_STATE},
226 {"code", DEBUG_CODEGEN},
227 {"vfmt", DEBUG_VFMT},
228 {"vtxf", DEBUG_VFMT},
229 {"verb", DEBUG_VERBOSE},
230 {"dri", DEBUG_DRI},
231 {"dma", DEBUG_DMA},
232 {"san", DEBUG_SANITY},
233 {"sync", DEBUG_SYNC},
234 {"pix", DEBUG_PIXEL},
235 {"mem", DEBUG_MEMORY},
236 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
237 {NULL, 0}
238 };
239 #endif /* RADEON_DEBUG */
240
241 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
242
243 extern const struct dri_extension card_extensions[];
244
245 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
246
247 static int
248 radeonGetParam(int fd, int param, void *value)
249 {
250 int ret;
251 drm_radeon_getparam_t gp;
252
253 gp.param = param;
254 gp.value = value;
255
256 ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
257 return ret;
258 }
259
260 static const __DRIconfig **
261 radeonFillInModes( __DRIscreenPrivate *psp,
262 unsigned pixel_bits, unsigned depth_bits,
263 unsigned stencil_bits, GLboolean have_back_buffer )
264 {
265 __DRIconfig **configs;
266 __GLcontextModes *m;
267 unsigned depth_buffer_factor;
268 unsigned back_buffer_factor;
269 GLenum fb_format;
270 GLenum fb_type;
271 int i;
272
273 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
274 * enough to add support. Basically, if a context is created with an
275 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
276 * will never be used.
277 */
278 static const GLenum back_buffer_modes[] = {
279 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
280 };
281
282 uint8_t depth_bits_array[2];
283 uint8_t stencil_bits_array[2];
284 uint8_t msaa_samples_array[1];
285
286 depth_bits_array[0] = depth_bits;
287 depth_bits_array[1] = depth_bits;
288
289 /* Just like with the accumulation buffer, always provide some modes
290 * with a stencil buffer. It will be a sw fallback, but some apps won't
291 * care about that.
292 */
293 stencil_bits_array[0] = 0;
294 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
295
296 msaa_samples_array[0] = 0;
297
298 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
299 back_buffer_factor = (have_back_buffer) ? 2 : 1;
300
301 if ( pixel_bits == 16 ) {
302 fb_format = GL_RGB;
303 fb_type = GL_UNSIGNED_SHORT_5_6_5;
304 }
305 else {
306 fb_format = GL_BGRA;
307 fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
308 }
309
310 configs = driCreateConfigs(fb_format, fb_type,
311 depth_bits_array, stencil_bits_array,
312 depth_buffer_factor,
313 back_buffer_modes, back_buffer_factor,
314 msaa_samples_array, 1);
315 if (configs == NULL) {
316 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
317 __func__, __LINE__ );
318 return NULL;
319 }
320
321 /* Mark the visual as slow if there are "fake" stencil bits.
322 */
323 for (i = 0; configs[i]; i++) {
324 m = &configs[i]->modes;
325 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
326 m->visualRating = GLX_SLOW_CONFIG;
327 }
328 }
329
330 return (const __DRIconfig **) configs;
331 }
332
333 #if !RADEON_COMMON
334 static const __DRItexOffsetExtension radeonTexOffsetExtension = {
335 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
336 radeonSetTexOffset,
337 };
338
339 static const __DRItexBufferExtension radeonTexBufferExtension = {
340 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
341 radeonSetTexBuffer,
342 };
343 #endif
344
345 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
346 static const __DRIallocateExtension r200AllocateExtension = {
347 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
348 r200AllocateMemoryMESA,
349 r200FreeMemoryMESA,
350 r200GetMemoryOffsetMESA
351 };
352
353 static const __DRItexOffsetExtension r200texOffsetExtension = {
354 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
355 r200SetTexOffset,
356 };
357 #endif
358
359 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
360 static const __DRItexOffsetExtension r300texOffsetExtension = {
361 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
362 r300SetTexOffset,
363 };
364
365 static const __DRItexBufferExtension r300TexBufferExtension = {
366 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
367 r300SetTexBuffer,
368 };
369 #endif
370
371 static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
372 {
373 screen->chip_flags = 0;
374 switch ( device_id ) {
375 case PCI_CHIP_RADEON_LY:
376 case PCI_CHIP_RADEON_LZ:
377 case PCI_CHIP_RADEON_QY:
378 case PCI_CHIP_RADEON_QZ:
379 case PCI_CHIP_RN50_515E:
380 case PCI_CHIP_RN50_5969:
381 screen->chip_family = CHIP_FAMILY_RV100;
382 break;
383
384 case PCI_CHIP_RS100_4136:
385 case PCI_CHIP_RS100_4336:
386 screen->chip_family = CHIP_FAMILY_RS100;
387 break;
388
389 case PCI_CHIP_RS200_4137:
390 case PCI_CHIP_RS200_4337:
391 case PCI_CHIP_RS250_4237:
392 case PCI_CHIP_RS250_4437:
393 screen->chip_family = CHIP_FAMILY_RS200;
394 break;
395
396 case PCI_CHIP_RADEON_QD:
397 case PCI_CHIP_RADEON_QE:
398 case PCI_CHIP_RADEON_QF:
399 case PCI_CHIP_RADEON_QG:
400 /* all original radeons (7200) presumably have a stencil op bug */
401 screen->chip_family = CHIP_FAMILY_R100;
402 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
403 break;
404
405 case PCI_CHIP_RV200_QW:
406 case PCI_CHIP_RV200_QX:
407 case PCI_CHIP_RADEON_LW:
408 case PCI_CHIP_RADEON_LX:
409 screen->chip_family = CHIP_FAMILY_RV200;
410 screen->chip_flags = RADEON_CHIPSET_TCL;
411 break;
412
413 case PCI_CHIP_R200_BB:
414 case PCI_CHIP_R200_BC:
415 case PCI_CHIP_R200_QH:
416 case PCI_CHIP_R200_QL:
417 case PCI_CHIP_R200_QM:
418 screen->chip_family = CHIP_FAMILY_R200;
419 screen->chip_flags = RADEON_CHIPSET_TCL;
420 break;
421
422 case PCI_CHIP_RV250_If:
423 case PCI_CHIP_RV250_Ig:
424 case PCI_CHIP_RV250_Ld:
425 case PCI_CHIP_RV250_Lf:
426 case PCI_CHIP_RV250_Lg:
427 screen->chip_family = CHIP_FAMILY_RV250;
428 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
429 break;
430
431 case PCI_CHIP_RV280_5960:
432 case PCI_CHIP_RV280_5961:
433 case PCI_CHIP_RV280_5962:
434 case PCI_CHIP_RV280_5964:
435 case PCI_CHIP_RV280_5965:
436 case PCI_CHIP_RV280_5C61:
437 case PCI_CHIP_RV280_5C63:
438 screen->chip_family = CHIP_FAMILY_RV280;
439 screen->chip_flags = RADEON_CHIPSET_TCL;
440 break;
441
442 case PCI_CHIP_RS300_5834:
443 case PCI_CHIP_RS300_5835:
444 case PCI_CHIP_RS350_7834:
445 case PCI_CHIP_RS350_7835:
446 screen->chip_family = CHIP_FAMILY_RS300;
447 break;
448
449 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
450 case PCI_CHIP_R300_AD:
451 screen->chip_family = CHIP_FAMILY_RV350;
452 screen->chip_flags = RADEON_CHIPSET_TCL;
453 break;
454 case PCI_CHIP_R300_AE:
455 case PCI_CHIP_R300_AF:
456 case PCI_CHIP_R300_AG:
457 case PCI_CHIP_R300_ND:
458 case PCI_CHIP_R300_NE:
459 case PCI_CHIP_R300_NF:
460 case PCI_CHIP_R300_NG:
461 screen->chip_family = CHIP_FAMILY_R300;
462 screen->chip_flags = RADEON_CHIPSET_TCL;
463 break;
464
465 case PCI_CHIP_RV350_AP:
466 case PCI_CHIP_RV350_AQ:
467 case PCI_CHIP_RV350_AR:
468 case PCI_CHIP_RV350_AS:
469 case PCI_CHIP_RV350_AT:
470 case PCI_CHIP_RV350_AV:
471 case PCI_CHIP_RV350_AU:
472 case PCI_CHIP_RV350_NP:
473 case PCI_CHIP_RV350_NQ:
474 case PCI_CHIP_RV350_NR:
475 case PCI_CHIP_RV350_NS:
476 case PCI_CHIP_RV350_NT:
477 case PCI_CHIP_RV350_NV:
478 screen->chip_family = CHIP_FAMILY_RV350;
479 screen->chip_flags = RADEON_CHIPSET_TCL;
480 break;
481
482 case PCI_CHIP_R350_AH:
483 case PCI_CHIP_R350_AI:
484 case PCI_CHIP_R350_AJ:
485 case PCI_CHIP_R350_AK:
486 case PCI_CHIP_R350_NH:
487 case PCI_CHIP_R350_NI:
488 case PCI_CHIP_R360_NJ:
489 case PCI_CHIP_R350_NK:
490 screen->chip_family = CHIP_FAMILY_R350;
491 screen->chip_flags = RADEON_CHIPSET_TCL;
492 break;
493
494 case PCI_CHIP_RV370_5460:
495 case PCI_CHIP_RV370_5462:
496 case PCI_CHIP_RV370_5464:
497 case PCI_CHIP_RV370_5B60:
498 case PCI_CHIP_RV370_5B62:
499 case PCI_CHIP_RV370_5B63:
500 case PCI_CHIP_RV370_5B64:
501 case PCI_CHIP_RV370_5B65:
502 case PCI_CHIP_RV380_3150:
503 case PCI_CHIP_RV380_3152:
504 case PCI_CHIP_RV380_3154:
505 case PCI_CHIP_RV380_3E50:
506 case PCI_CHIP_RV380_3E54:
507 screen->chip_family = CHIP_FAMILY_RV380;
508 screen->chip_flags = RADEON_CHIPSET_TCL;
509 break;
510
511 case PCI_CHIP_R420_JN:
512 case PCI_CHIP_R420_JH:
513 case PCI_CHIP_R420_JI:
514 case PCI_CHIP_R420_JJ:
515 case PCI_CHIP_R420_JK:
516 case PCI_CHIP_R420_JL:
517 case PCI_CHIP_R420_JM:
518 case PCI_CHIP_R420_JO:
519 case PCI_CHIP_R420_JP:
520 case PCI_CHIP_R420_JT:
521 case PCI_CHIP_R481_4B49:
522 case PCI_CHIP_R481_4B4A:
523 case PCI_CHIP_R481_4B4B:
524 case PCI_CHIP_R481_4B4C:
525 case PCI_CHIP_R423_UH:
526 case PCI_CHIP_R423_UI:
527 case PCI_CHIP_R423_UJ:
528 case PCI_CHIP_R423_UK:
529 case PCI_CHIP_R430_554C:
530 case PCI_CHIP_R430_554D:
531 case PCI_CHIP_R430_554E:
532 case PCI_CHIP_R430_554F:
533 case PCI_CHIP_R423_5550:
534 case PCI_CHIP_R423_UQ:
535 case PCI_CHIP_R423_UR:
536 case PCI_CHIP_R423_UT:
537 case PCI_CHIP_R430_5D48:
538 case PCI_CHIP_R430_5D49:
539 case PCI_CHIP_R430_5D4A:
540 case PCI_CHIP_R480_5D4C:
541 case PCI_CHIP_R480_5D4D:
542 case PCI_CHIP_R480_5D4E:
543 case PCI_CHIP_R480_5D4F:
544 case PCI_CHIP_R480_5D50:
545 case PCI_CHIP_R480_5D52:
546 case PCI_CHIP_R423_5D57:
547 screen->chip_family = CHIP_FAMILY_R420;
548 screen->chip_flags = RADEON_CHIPSET_TCL;
549 break;
550
551 case PCI_CHIP_RV410_5E4C:
552 case PCI_CHIP_RV410_5E4F:
553 case PCI_CHIP_RV410_564A:
554 case PCI_CHIP_RV410_564B:
555 case PCI_CHIP_RV410_564F:
556 case PCI_CHIP_RV410_5652:
557 case PCI_CHIP_RV410_5653:
558 case PCI_CHIP_RV410_5657:
559 case PCI_CHIP_RV410_5E48:
560 case PCI_CHIP_RV410_5E4A:
561 case PCI_CHIP_RV410_5E4B:
562 case PCI_CHIP_RV410_5E4D:
563 screen->chip_family = CHIP_FAMILY_RV410;
564 screen->chip_flags = RADEON_CHIPSET_TCL;
565 break;
566
567 case PCI_CHIP_RS480_5954:
568 case PCI_CHIP_RS480_5955:
569 case PCI_CHIP_RS482_5974:
570 case PCI_CHIP_RS482_5975:
571 case PCI_CHIP_RS400_5A41:
572 case PCI_CHIP_RS400_5A42:
573 case PCI_CHIP_RC410_5A61:
574 case PCI_CHIP_RC410_5A62:
575 screen->chip_family = CHIP_FAMILY_RS400;
576 break;
577
578 case PCI_CHIP_RS600_793F:
579 case PCI_CHIP_RS600_7941:
580 case PCI_CHIP_RS600_7942:
581 screen->chip_family = CHIP_FAMILY_RS600;
582 break;
583
584 case PCI_CHIP_RS690_791E:
585 case PCI_CHIP_RS690_791F:
586 screen->chip_family = CHIP_FAMILY_RS690;
587 break;
588 case PCI_CHIP_RS740_796C:
589 case PCI_CHIP_RS740_796D:
590 case PCI_CHIP_RS740_796E:
591 case PCI_CHIP_RS740_796F:
592 screen->chip_family = CHIP_FAMILY_RS740;
593 break;
594
595 case PCI_CHIP_R520_7100:
596 case PCI_CHIP_R520_7101:
597 case PCI_CHIP_R520_7102:
598 case PCI_CHIP_R520_7103:
599 case PCI_CHIP_R520_7104:
600 case PCI_CHIP_R520_7105:
601 case PCI_CHIP_R520_7106:
602 case PCI_CHIP_R520_7108:
603 case PCI_CHIP_R520_7109:
604 case PCI_CHIP_R520_710A:
605 case PCI_CHIP_R520_710B:
606 case PCI_CHIP_R520_710C:
607 case PCI_CHIP_R520_710E:
608 case PCI_CHIP_R520_710F:
609 screen->chip_family = CHIP_FAMILY_R520;
610 screen->chip_flags = RADEON_CHIPSET_TCL;
611 break;
612
613 case PCI_CHIP_RV515_7140:
614 case PCI_CHIP_RV515_7141:
615 case PCI_CHIP_RV515_7142:
616 case PCI_CHIP_RV515_7143:
617 case PCI_CHIP_RV515_7144:
618 case PCI_CHIP_RV515_7145:
619 case PCI_CHIP_RV515_7146:
620 case PCI_CHIP_RV515_7147:
621 case PCI_CHIP_RV515_7149:
622 case PCI_CHIP_RV515_714A:
623 case PCI_CHIP_RV515_714B:
624 case PCI_CHIP_RV515_714C:
625 case PCI_CHIP_RV515_714D:
626 case PCI_CHIP_RV515_714E:
627 case PCI_CHIP_RV515_714F:
628 case PCI_CHIP_RV515_7151:
629 case PCI_CHIP_RV515_7152:
630 case PCI_CHIP_RV515_7153:
631 case PCI_CHIP_RV515_715E:
632 case PCI_CHIP_RV515_715F:
633 case PCI_CHIP_RV515_7180:
634 case PCI_CHIP_RV515_7181:
635 case PCI_CHIP_RV515_7183:
636 case PCI_CHIP_RV515_7186:
637 case PCI_CHIP_RV515_7187:
638 case PCI_CHIP_RV515_7188:
639 case PCI_CHIP_RV515_718A:
640 case PCI_CHIP_RV515_718B:
641 case PCI_CHIP_RV515_718C:
642 case PCI_CHIP_RV515_718D:
643 case PCI_CHIP_RV515_718F:
644 case PCI_CHIP_RV515_7193:
645 case PCI_CHIP_RV515_7196:
646 case PCI_CHIP_RV515_719B:
647 case PCI_CHIP_RV515_719F:
648 case PCI_CHIP_RV515_7200:
649 case PCI_CHIP_RV515_7210:
650 case PCI_CHIP_RV515_7211:
651 screen->chip_family = CHIP_FAMILY_RV515;
652 screen->chip_flags = RADEON_CHIPSET_TCL;
653 break;
654
655 case PCI_CHIP_RV530_71C0:
656 case PCI_CHIP_RV530_71C1:
657 case PCI_CHIP_RV530_71C2:
658 case PCI_CHIP_RV530_71C3:
659 case PCI_CHIP_RV530_71C4:
660 case PCI_CHIP_RV530_71C5:
661 case PCI_CHIP_RV530_71C6:
662 case PCI_CHIP_RV530_71C7:
663 case PCI_CHIP_RV530_71CD:
664 case PCI_CHIP_RV530_71CE:
665 case PCI_CHIP_RV530_71D2:
666 case PCI_CHIP_RV530_71D4:
667 case PCI_CHIP_RV530_71D5:
668 case PCI_CHIP_RV530_71D6:
669 case PCI_CHIP_RV530_71DA:
670 case PCI_CHIP_RV530_71DE:
671 screen->chip_family = CHIP_FAMILY_RV530;
672 screen->chip_flags = RADEON_CHIPSET_TCL;
673 break;
674
675 case PCI_CHIP_R580_7240:
676 case PCI_CHIP_R580_7243:
677 case PCI_CHIP_R580_7244:
678 case PCI_CHIP_R580_7245:
679 case PCI_CHIP_R580_7246:
680 case PCI_CHIP_R580_7247:
681 case PCI_CHIP_R580_7248:
682 case PCI_CHIP_R580_7249:
683 case PCI_CHIP_R580_724A:
684 case PCI_CHIP_R580_724B:
685 case PCI_CHIP_R580_724C:
686 case PCI_CHIP_R580_724D:
687 case PCI_CHIP_R580_724E:
688 case PCI_CHIP_R580_724F:
689 case PCI_CHIP_R580_7284:
690 screen->chip_family = CHIP_FAMILY_R580;
691 screen->chip_flags = RADEON_CHIPSET_TCL;
692 break;
693
694 case PCI_CHIP_RV570_7280:
695 case PCI_CHIP_RV560_7281:
696 case PCI_CHIP_RV560_7283:
697 case PCI_CHIP_RV560_7287:
698 case PCI_CHIP_RV570_7288:
699 case PCI_CHIP_RV570_7289:
700 case PCI_CHIP_RV570_728B:
701 case PCI_CHIP_RV570_728C:
702 case PCI_CHIP_RV560_7290:
703 case PCI_CHIP_RV560_7291:
704 case PCI_CHIP_RV560_7293:
705 case PCI_CHIP_RV560_7297:
706 screen->chip_family = CHIP_FAMILY_RV560;
707 screen->chip_flags = RADEON_CHIPSET_TCL;
708 break;
709
710 default:
711 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
712 device_id);
713 return -1;
714 }
715
716 return 0;
717 }
718
719
720 /* Create the device specific screen private data struct.
721 */
722 static radeonScreenPtr
723 radeonCreateScreen( __DRIscreenPrivate *sPriv )
724 {
725 radeonScreenPtr screen;
726 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
727 unsigned char *RADEONMMIO = NULL;
728 int i;
729 int ret;
730 uint32_t temp;
731
732 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
733 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
734 return GL_FALSE;
735 }
736
737 /* Allocate the private area */
738 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
739 if ( !screen ) {
740 __driUtilMessage("%s: Could not allocate memory for screen structure",
741 __FUNCTION__);
742 return NULL;
743 }
744
745 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
746 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
747 #endif
748
749 /* parse information in __driConfigOptions */
750 driParseOptionInfo (&screen->optionCache,
751 __driConfigOptions, __driNConfigOptions);
752
753 /* This is first since which regions we map depends on whether or
754 * not we are using a PCI card.
755 */
756 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
757 {
758 int ret;
759
760 #ifdef RADEON_PARAM_KERNEL_MM
761 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_KERNEL_MM,
762 &screen->kernel_mm);
763
764 if (ret && ret != -EINVAL) {
765 FREE( screen );
766 fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret);
767 return NULL;
768 }
769
770 if (ret == -EINVAL)
771 screen->kernel_mm = 0;
772 #endif
773
774 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET,
775 &screen->gart_buffer_offset);
776
777 if (ret) {
778 FREE( screen );
779 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
780 return NULL;
781 }
782
783 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE,
784 &screen->gart_base);
785 if (ret) {
786 FREE( screen );
787 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
788 return NULL;
789 }
790
791 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
792 &screen->irq);
793 if (ret) {
794 FREE( screen );
795 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
796 return NULL;
797 }
798 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
799 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
800 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
801 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
802 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
803 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
804 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
805 }
806
807 if (!screen->kernel_mm) {
808 screen->mmio.handle = dri_priv->registerHandle;
809 screen->mmio.size = dri_priv->registerSize;
810 if ( drmMap( sPriv->fd,
811 screen->mmio.handle,
812 screen->mmio.size,
813 &screen->mmio.map ) ) {
814 FREE( screen );
815 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
816 return NULL;
817 }
818
819 RADEONMMIO = screen->mmio.map;
820
821 screen->status.handle = dri_priv->statusHandle;
822 screen->status.size = dri_priv->statusSize;
823 if ( drmMap( sPriv->fd,
824 screen->status.handle,
825 screen->status.size,
826 &screen->status.map ) ) {
827 drmUnmap( screen->mmio.map, screen->mmio.size );
828 FREE( screen );
829 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
830 return NULL;
831 }
832 screen->scratch = (__volatile__ uint32_t *)
833 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
834
835 screen->buffers = drmMapBufs( sPriv->fd );
836 if ( !screen->buffers ) {
837 drmUnmap( screen->status.map, screen->status.size );
838 drmUnmap( screen->mmio.map, screen->mmio.size );
839 FREE( screen );
840 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
841 return NULL;
842 }
843
844 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
845 screen->gartTextures.handle = dri_priv->gartTexHandle;
846 screen->gartTextures.size = dri_priv->gartTexMapSize;
847 if ( drmMap( sPriv->fd,
848 screen->gartTextures.handle,
849 screen->gartTextures.size,
850 (drmAddressPtr)&screen->gartTextures.map ) ) {
851 drmUnmapBufs( screen->buffers );
852 drmUnmap( screen->status.map, screen->status.size );
853 drmUnmap( screen->mmio.map, screen->mmio.size );
854 FREE( screen );
855 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
856 return NULL;
857 }
858
859 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
860 }
861 }
862
863
864 ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
865 if (ret == -1)
866 return NULL;
867
868 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
869 sPriv->ddx_version.minor < 2) {
870 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
871 return NULL;
872 }
873
874 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
875 fprintf(stderr, "R500 support requires a newer drm.\n");
876 return NULL;
877 }
878
879 if (getenv("R300_NO_TCL"))
880 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
881
882 if (screen->chip_family <= CHIP_FAMILY_RS200)
883 screen->chip_flags |= RADEON_CLASS_R100;
884 else if (screen->chip_family <= CHIP_FAMILY_RV280)
885 screen->chip_flags |= RADEON_CLASS_R200;
886 else
887 screen->chip_flags |= RADEON_CLASS_R300;
888
889 screen->cpp = dri_priv->bpp / 8;
890 screen->AGPMode = dri_priv->AGPMode;
891
892 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION,
893 &temp);
894 if (ret) {
895 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm)
896 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
897 else {
898 FREE( screen );
899 fprintf(stderr, "Unable to get fb location need newer drm\n");
900 return NULL;
901 }
902 } else {
903 screen->fbLocation = (temp & 0xffff) << 16;
904 }
905
906 if (screen->chip_family >= CHIP_FAMILY_R300) {
907 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES,
908 &temp);
909 if (ret) {
910 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
911 switch (screen->chip_family) {
912 case CHIP_FAMILY_R300:
913 case CHIP_FAMILY_R350:
914 screen->num_gb_pipes = 2;
915 break;
916 case CHIP_FAMILY_R420:
917 case CHIP_FAMILY_R520:
918 case CHIP_FAMILY_R580:
919 case CHIP_FAMILY_RV560:
920 case CHIP_FAMILY_RV570:
921 screen->num_gb_pipes = 4;
922 break;
923 case CHIP_FAMILY_RV350:
924 case CHIP_FAMILY_RV515:
925 case CHIP_FAMILY_RV530:
926 case CHIP_FAMILY_RV410:
927 default:
928 screen->num_gb_pipes = 1;
929 break;
930 }
931 } else {
932 screen->num_gb_pipes = temp;
933 }
934 }
935
936 if ( sPriv->drm_version.minor >= 10 ) {
937 drm_radeon_setparam_t sp;
938
939 sp.param = RADEON_SETPARAM_FB_LOCATION;
940 sp.value = screen->fbLocation;
941
942 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
943 &sp, sizeof( sp ) );
944 }
945
946 screen->frontOffset = dri_priv->frontOffset;
947 screen->frontPitch = dri_priv->frontPitch;
948 screen->backOffset = dri_priv->backOffset;
949 screen->backPitch = dri_priv->backPitch;
950 screen->depthOffset = dri_priv->depthOffset;
951 screen->depthPitch = dri_priv->depthPitch;
952
953 /* Check if ddx has set up a surface reg to cover depth buffer */
954 screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
955 /* these chips don't use tiled z without hyperz. So always pretend
956 we have set up a surface which will cause linear reads/writes */
957 (IS_R100_CLASS(screen) &&
958 !(screen->chip_flags & RADEON_CHIPSET_TCL));
959
960 if ( dri_priv->textureSize == 0 ) {
961 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
962 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
963 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
964 dri_priv->log2GARTTexGran;
965 } else {
966 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
967 + screen->fbLocation;
968 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
969 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
970 dri_priv->log2TexGran;
971 }
972
973 if ( !screen->gartTextures.map || dri_priv->textureSize == 0
974 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
975 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
976 screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
977 screen->texSize[RADEON_GART_TEX_HEAP] = 0;
978 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
979 } else {
980 screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
981 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
982 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
983 screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
984 dri_priv->log2GARTTexGran;
985 }
986
987 i = 0;
988 screen->extensions[i++] = &driCopySubBufferExtension.base;
989 screen->extensions[i++] = &driFrameTrackingExtension.base;
990 screen->extensions[i++] = &driReadDrawableExtension;
991
992 if ( screen->irq != 0 ) {
993 screen->extensions[i++] = &driSwapControlExtension.base;
994 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
995 }
996
997 if (!screen->kernel_mm) {
998 #if !RADEON_COMMON
999 screen->extensions[i++] = &radeonTexOffsetExtension.base;
1000 #endif
1001
1002 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1003 if (IS_R200_CLASS(screen))
1004 screen->extensions[i++] = &r200AllocateExtension.base;
1005
1006 screen->extensions[i++] = &r200texOffsetExtension.base;
1007 #endif
1008
1009 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1010 screen->extensions[i++] = &r300texOffsetExtension.base;
1011 #endif
1012 }
1013
1014 screen->extensions[i++] = NULL;
1015 sPriv->extensions = screen->extensions;
1016
1017 screen->driScreen = sPriv;
1018 screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
1019 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
1020 screen->sarea_priv_offset);
1021
1022 if (screen->kernel_mm)
1023 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1024 else
1025 screen->bom = radeon_bo_manager_legacy_ctor(screen);
1026 if (screen->bom == NULL) {
1027 free(screen);
1028 return NULL;
1029 }
1030
1031 return screen;
1032 }
1033
1034 static radeonScreenPtr
1035 radeonCreateScreen2(__DRIscreenPrivate *sPriv)
1036 {
1037 radeonScreenPtr screen;
1038 int i;
1039 int ret;
1040 uint32_t device_id;
1041
1042 /* Allocate the private area */
1043 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1044 if ( !screen ) {
1045 __driUtilMessage("%s: Could not allocate memory for screen structure",
1046 __FUNCTION__);
1047 fprintf(stderr, "leaving here\n");
1048 return NULL;
1049 }
1050
1051 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1052 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
1053 #endif
1054
1055 /* parse information in __driConfigOptions */
1056 driParseOptionInfo (&screen->optionCache,
1057 __driConfigOptions, __driNConfigOptions);
1058
1059 screen->kernel_mm = 1;
1060 screen->chip_flags = 0;
1061
1062 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
1063 &screen->irq);
1064
1065 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_DEVICE_ID,
1066 &device_id);
1067 if (ret) {
1068 FREE( screen );
1069 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret);
1070 return NULL;
1071 }
1072
1073 ret = radeon_set_screen_flags(screen, device_id);
1074 if (ret == -1)
1075 return NULL;
1076
1077 if (screen->chip_family <= CHIP_FAMILY_RS200)
1078 screen->chip_flags |= RADEON_CLASS_R100;
1079 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1080 screen->chip_flags |= RADEON_CLASS_R200;
1081 else
1082 screen->chip_flags |= RADEON_CLASS_R300;
1083
1084 i = 0;
1085 screen->extensions[i++] = &driCopySubBufferExtension.base;
1086 screen->extensions[i++] = &driFrameTrackingExtension.base;
1087 screen->extensions[i++] = &driReadDrawableExtension;
1088
1089 if ( screen->irq != 0 ) {
1090 screen->extensions[i++] = &driSwapControlExtension.base;
1091 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1092 }
1093
1094 #if !RADEON_COMMON
1095 screen->extensions[i++] = &radeonTexOffsetExtension.base;
1096 screen->extensions[i++] = &radeonTexBufferExtension.base;
1097 #endif
1098
1099 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1100 if (IS_R200_CLASS(screen))
1101 screen->extensions[i++] = &r200AllocateExtension.base;
1102
1103 screen->extensions[i++] = &r200texOffsetExtension.base;
1104 #endif
1105
1106 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1107 //screen->extensions[i++] = &r300texOffsetExtension.base;
1108 screen->extensions[i++] = &r300TexBufferExtension.base;
1109 #endif
1110
1111 screen->extensions[i++] = NULL;
1112 sPriv->extensions = screen->extensions;
1113
1114 screen->driScreen = sPriv;
1115 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1116 if (screen->bom == NULL) {
1117 free(screen);
1118 return NULL;
1119 }
1120 return screen;
1121 }
1122
1123 /* Destroy the device specific screen private data struct.
1124 */
1125 static void
1126 radeonDestroyScreen( __DRIscreenPrivate *sPriv )
1127 {
1128 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1129
1130 if (!screen)
1131 return;
1132
1133 if (screen->kernel_mm) {
1134 #ifdef RADEON_BO_TRACK
1135 radeon_tracker_print(&screen->bom->tracker, stderr);
1136 #endif
1137 radeon_bo_manager_gem_dtor(screen->bom);
1138 } else {
1139 radeon_bo_manager_legacy_dtor(screen->bom);
1140
1141 if ( screen->gartTextures.map ) {
1142 drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
1143 }
1144 drmUnmapBufs( screen->buffers );
1145 drmUnmap( screen->status.map, screen->status.size );
1146 drmUnmap( screen->mmio.map, screen->mmio.size );
1147 }
1148
1149 /* free all option information */
1150 driDestroyOptionInfo (&screen->optionCache);
1151
1152 FREE( screen );
1153 sPriv->private = NULL;
1154 }
1155
1156
1157 /* Initialize the driver specific screen private data.
1158 */
1159 static GLboolean
1160 radeonInitDriver( __DRIscreenPrivate *sPriv )
1161 {
1162 if (sPriv->dri2.enabled) {
1163 sPriv->private = (void *) radeonCreateScreen2( sPriv );
1164 } else {
1165 sPriv->private = (void *) radeonCreateScreen( sPriv );
1166 }
1167 if ( !sPriv->private ) {
1168 radeonDestroyScreen( sPriv );
1169 return GL_FALSE;
1170 }
1171
1172 return GL_TRUE;
1173 }
1174
1175 static GLboolean
1176 radeon_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb,
1177 GLenum intFormat, GLuint w, GLuint h)
1178 {
1179 rb->Width = w;
1180 rb->Height = h;
1181 rb->_ActualFormat = intFormat;
1182
1183 return GL_TRUE;
1184 }
1185
1186
1187 static struct radeon_renderbuffer *
1188 radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv)
1189 {
1190 struct radeon_renderbuffer *ret;
1191
1192 ret = CALLOC_STRUCT(radeon_renderbuffer);
1193 if (!ret)
1194 return NULL;
1195
1196 _mesa_init_renderbuffer(&ret->base, 0);
1197
1198 /* XXX format junk */
1199 switch (format) {
1200 case GL_RGB5:
1201 ret->base._ActualFormat = GL_RGB5;
1202 ret->base._BaseFormat = GL_RGBA;
1203 ret->base.RedBits = 5;
1204 ret->base.GreenBits = 6;
1205 ret->base.BlueBits = 5;
1206 ret->base.DataType = GL_UNSIGNED_BYTE;
1207 break;
1208 case GL_RGBA8:
1209 ret->base._ActualFormat = GL_RGBA8;
1210 ret->base._BaseFormat = GL_RGBA;
1211 ret->base.RedBits = 8;
1212 ret->base.GreenBits = 8;
1213 ret->base.BlueBits = 8;
1214 ret->base.AlphaBits = 8;
1215 ret->base.DataType = GL_UNSIGNED_BYTE;
1216 break;
1217 case GL_STENCIL_INDEX8_EXT:
1218 ret->base._ActualFormat = GL_STENCIL_INDEX8_EXT;
1219 ret->base._BaseFormat = GL_STENCIL_INDEX;
1220 ret->base.StencilBits = 8;
1221 ret->base.DataType = GL_UNSIGNED_BYTE;
1222 break;
1223 case GL_DEPTH_COMPONENT16:
1224 ret->base._ActualFormat = GL_DEPTH_COMPONENT16;
1225 ret->base._BaseFormat = GL_DEPTH_COMPONENT;
1226 ret->base.DepthBits = 16;
1227 ret->base.DataType = GL_UNSIGNED_SHORT;
1228 break;
1229 case GL_DEPTH_COMPONENT24:
1230 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT;
1231 ret->base._BaseFormat = GL_DEPTH_COMPONENT;
1232 ret->base.DepthBits = 24;
1233 ret->base.DataType = GL_UNSIGNED_INT;
1234 break;
1235 case GL_DEPTH24_STENCIL8_EXT:
1236 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT;
1237 ret->base._BaseFormat = GL_DEPTH_STENCIL_EXT;
1238 ret->base.DepthBits = 24;
1239 ret->base.StencilBits = 8;
1240 ret->base.DataType = GL_UNSIGNED_INT_24_8_EXT;
1241 break;
1242 default:
1243 fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format);
1244 _mesa_delete_renderbuffer(&ret->base);
1245 return NULL;
1246 }
1247
1248 ret->dPriv = driDrawPriv;
1249 ret->base.InternalFormat = format;
1250
1251 ret->base.AllocStorage = radeon_alloc_window_storage;
1252
1253 radeonSetSpanFunctions(ret);
1254
1255 ret->bo = NULL;
1256 return ret;
1257 }
1258
1259 /**
1260 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1261 *
1262 * \todo This function (and its interface) will need to be updated to support
1263 * pbuffers.
1264 */
1265 static GLboolean
1266 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
1267 __DRIdrawablePrivate *driDrawPriv,
1268 const __GLcontextModes *mesaVis,
1269 GLboolean isPixmap )
1270 {
1271 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1272
1273 const GLboolean swDepth = GL_FALSE;
1274 const GLboolean swAlpha = GL_FALSE;
1275 const GLboolean swAccum = mesaVis->accumRedBits > 0;
1276 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1277 mesaVis->depthBits != 24;
1278 GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8);
1279 GLenum depthFormat = GL_NONE;
1280 struct radeon_framebuffer *rfb;
1281
1282 if (isPixmap)
1283 return GL_FALSE; /* not implemented */
1284
1285 rfb = CALLOC_STRUCT(radeon_framebuffer);
1286 if (!rfb)
1287 return GL_FALSE;
1288
1289 _mesa_initialize_framebuffer(&rfb->base, mesaVis);
1290
1291 if (mesaVis->depthBits == 16)
1292 depthFormat = GL_DEPTH_COMPONENT16;
1293 else if (mesaVis->depthBits == 24)
1294 depthFormat = GL_DEPTH_COMPONENT24;
1295
1296 /* front color renderbuffer */
1297 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1298 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base);
1299 rfb->color_rb[0]->has_surface = 1;
1300
1301 /* back color renderbuffer */
1302 if (mesaVis->doubleBufferMode) {
1303 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1304 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base);
1305 rfb->color_rb[1]->has_surface = 1;
1306 }
1307
1308 /* depth renderbuffer */
1309 if (depthFormat != GL_NONE) {
1310 struct radeon_renderbuffer *depth =
1311 radeon_create_renderbuffer(depthFormat, driDrawPriv);
1312 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1313 depth->has_surface = screen->depthHasSurface;
1314 }
1315
1316 /* stencil renderbuffer */
1317 if (mesaVis->stencilBits > 0 && !swStencil) {
1318 struct radeon_renderbuffer *stencil =
1319 radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv);
1320 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &stencil->base);
1321 stencil->has_surface = screen->depthHasSurface;
1322 }
1323
1324 _mesa_add_soft_renderbuffers(&rfb->base,
1325 GL_FALSE, /* color */
1326 swDepth,
1327 swStencil,
1328 swAccum,
1329 swAlpha,
1330 GL_FALSE /* aux */);
1331 driDrawPriv->driverPrivate = (void *) rfb;
1332
1333 return (driDrawPriv->driverPrivate != NULL);
1334 }
1335
1336 static void
1337 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
1338 {
1339 struct radeon_renderbuffer *rb;
1340 struct radeon_framebuffer *rfb;
1341
1342 rfb = (void*)driDrawPriv->driverPrivate;
1343 rb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
1344 if (rb && rb->bo) {
1345 radeon_bo_unref(rb->bo);
1346 rb->bo = NULL;
1347 }
1348 rb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
1349 if (rb && rb->bo) {
1350 radeon_bo_unref(rb->bo);
1351 rb->bo = NULL;
1352 }
1353 rb = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer;
1354 if (rb && rb->bo) {
1355 radeon_bo_unref(rb->bo);
1356 rb->bo = NULL;
1357 }
1358 _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)));
1359 }
1360
1361 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1362 /**
1363 * Choose the appropriate CreateContext function based on the chipset.
1364 * Eventually, all drivers will go through this process.
1365 */
1366 static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
1367 __DRIcontextPrivate * driContextPriv,
1368 void *sharedContextPriv)
1369 {
1370 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
1371 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
1372
1373 if (IS_R300_CLASS(screen))
1374 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
1375 return GL_FALSE;
1376 }
1377
1378 /**
1379 * Choose the appropriate DestroyContext function based on the chipset.
1380 */
1381 static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
1382 {
1383 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
1384
1385 if (IS_R300_CLASS(radeon->radeonScreen))
1386 return r300DestroyContext(driContextPriv);
1387 }
1388
1389
1390 #endif
1391
1392
1393 /**
1394 * This is the driver specific part of the createNewScreen entry point.
1395 *
1396 * \todo maybe fold this into intelInitDriver
1397 *
1398 * \return the __GLcontextModes supported by this driver
1399 */
1400 static const __DRIconfig **
1401 radeonInitScreen(__DRIscreenPrivate *psp)
1402 {
1403 #if !RADEON_COMMON
1404 static const char *driver_name = "Radeon";
1405 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1406 static const __DRIversion dri_expected = { 4, 0, 0 };
1407 static const __DRIversion drm_expected = { 1, 6, 0 };
1408 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1409 static const char *driver_name = "R200";
1410 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1411 static const __DRIversion dri_expected = { 4, 0, 0 };
1412 static const __DRIversion drm_expected = { 1, 6, 0 };
1413 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1414 static const char *driver_name = "R300";
1415 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1416 static const __DRIversion dri_expected = { 4, 0, 0 };
1417 static const __DRIversion drm_expected = { 1, 24, 0 };
1418 #endif
1419 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1420
1421 if ( ! driCheckDriDdxDrmVersions3( driver_name,
1422 &psp->dri_version, & dri_expected,
1423 &psp->ddx_version, & ddx_expected,
1424 &psp->drm_version, & drm_expected ) ) {
1425 return NULL;
1426 }
1427
1428 /* Calling driInitExtensions here, with a NULL context pointer,
1429 * does not actually enable the extensions. It just makes sure
1430 * that all the dispatch offsets for all the extensions that
1431 * *might* be enables are known. This is needed because the
1432 * dispatch offsets need to be known when _mesa_context_create
1433 * is called, but we can't enable the extensions until we have a
1434 * context pointer.
1435 *
1436 * Hello chicken. Hello egg. How are you two today?
1437 */
1438 driInitExtensions( NULL, card_extensions, GL_FALSE );
1439 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1440 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1441 driInitSingleExtension( NULL, ARB_vp_extension );
1442 driInitSingleExtension( NULL, NV_vp_extension );
1443 driInitSingleExtension( NULL, ATI_fs_extension );
1444 driInitExtensions( NULL, point_extensions, GL_FALSE );
1445 #elif defined(RADEON_COMMON_FOR_R300)
1446 driInitSingleExtension( NULL, gl_20_extension );
1447 #endif
1448
1449 if (!radeonInitDriver(psp))
1450 return NULL;
1451
1452 /* for now fill in all modes */
1453 return radeonFillInModes( psp,
1454 dri_priv->bpp,
1455 (dri_priv->bpp == 16) ? 16 : 24,
1456 (dri_priv->bpp == 16) ? 0 : 8, 1);
1457 }
1458 #define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
1459
1460 /**
1461 * This is the driver specific part of the createNewScreen entry point.
1462 * Called when using DRI2.
1463 *
1464 * \return the __GLcontextModes supported by this driver
1465 */
1466 static const
1467 __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp)
1468 {
1469 GLenum fb_format[3];
1470 GLenum fb_type[3];
1471 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
1472 * support pageflipping at all.
1473 */
1474 static const GLenum back_buffer_modes[] = {
1475 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/
1476 };
1477 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
1478 int color;
1479 __DRIconfig **configs = NULL;
1480
1481 /* Calling driInitExtensions here, with a NULL context pointer,
1482 * does not actually enable the extensions. It just makes sure
1483 * that all the dispatch offsets for all the extensions that
1484 * *might* be enables are known. This is needed because the
1485 * dispatch offsets need to be known when _mesa_context_create
1486 * is called, but we can't enable the extensions until we have a
1487 * context pointer.
1488 *
1489 * Hello chicken. Hello egg. How are you two today?
1490 */
1491 driInitExtensions( NULL, card_extensions, GL_FALSE );
1492 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1493 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1494 driInitSingleExtension( NULL, ARB_vp_extension );
1495 driInitSingleExtension( NULL, NV_vp_extension );
1496 driInitSingleExtension( NULL, ATI_fs_extension );
1497 driInitExtensions( NULL, point_extensions, GL_FALSE );
1498 #endif
1499
1500 if (!radeonInitDriver(psp)) {
1501 return NULL;
1502 }
1503 depth_bits[0] = 0;
1504 stencil_bits[0] = 0;
1505 depth_bits[1] = 16;
1506 stencil_bits[1] = 0;
1507 depth_bits[2] = 24;
1508 stencil_bits[2] = 0;
1509 depth_bits[3] = 24;
1510 stencil_bits[3] = 8;
1511
1512 msaa_samples_array[0] = 0;
1513
1514 fb_format[0] = GL_RGB;
1515 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5;
1516
1517 fb_format[1] = GL_BGR;
1518 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV;
1519
1520 fb_format[2] = GL_BGRA;
1521 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
1522
1523 for (color = 0; color < ARRAY_SIZE(fb_format); color++) {
1524 __DRIconfig **new_configs;
1525
1526 new_configs = driCreateConfigs(fb_format[color], fb_type[color],
1527 depth_bits,
1528 stencil_bits,
1529 ARRAY_SIZE(depth_bits),
1530 back_buffer_modes,
1531 ARRAY_SIZE(back_buffer_modes),
1532 msaa_samples_array,
1533 ARRAY_SIZE(msaa_samples_array));
1534 if (configs == NULL)
1535 configs = new_configs;
1536 else
1537 configs = driConcatConfigs(configs, new_configs);
1538 }
1539
1540 if (configs == NULL) {
1541 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
1542 __LINE__);
1543 return NULL;
1544 }
1545
1546 return (const __DRIconfig **)configs;
1547 }
1548
1549 /**
1550 * Get information about previous buffer swaps.
1551 */
1552 static int
1553 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1554 {
1555 struct radeon_framebuffer *rfb;
1556
1557 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1558 || (dPriv->driContextPriv->driverPrivate == NULL)
1559 || (sInfo == NULL) ) {
1560 return -1;
1561 }
1562
1563 rfb = dPriv->driverPrivate;
1564 sInfo->swap_count = rfb->swap_count;
1565 sInfo->swap_ust = rfb->swap_ust;
1566 sInfo->swap_missed_count = rfb->swap_missed_count;
1567
1568 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1569 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust )
1570 : 0.0;
1571
1572 return 0;
1573 }
1574
1575 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1576 const struct __DriverAPIRec driDriverAPI = {
1577 .InitScreen = radeonInitScreen,
1578 .DestroyScreen = radeonDestroyScreen,
1579 .CreateContext = radeonCreateContext,
1580 .DestroyContext = radeonDestroyContext,
1581 .CreateBuffer = radeonCreateBuffer,
1582 .DestroyBuffer = radeonDestroyBuffer,
1583 .SwapBuffers = radeonSwapBuffers,
1584 .MakeCurrent = radeonMakeCurrent,
1585 .UnbindContext = radeonUnbindContext,
1586 .GetSwapInfo = getSwapInfo,
1587 .GetDrawableMSC = driDrawableGetMSC32,
1588 .WaitForMSC = driWaitForMSC32,
1589 .WaitForSBC = NULL,
1590 .SwapBuffersMSC = NULL,
1591 .CopySubBuffer = radeonCopySubBuffer,
1592 /* DRI2 */
1593 .InitScreen2 = radeonInitScreen2,
1594 };
1595 #else
1596 const struct __DriverAPIRec driDriverAPI = {
1597 .InitScreen = radeonInitScreen,
1598 .DestroyScreen = radeonDestroyScreen,
1599 .CreateContext = r200CreateContext,
1600 .DestroyContext = r200DestroyContext,
1601 .CreateBuffer = radeonCreateBuffer,
1602 .DestroyBuffer = radeonDestroyBuffer,
1603 .SwapBuffers = radeonSwapBuffers,
1604 .MakeCurrent = radeonMakeCurrent,
1605 .UnbindContext = radeonUnbindContext,
1606 .GetSwapInfo = getSwapInfo,
1607 .GetDrawableMSC = driDrawableGetMSC32,
1608 .WaitForMSC = driWaitForMSC32,
1609 .WaitForSBC = NULL,
1610 .SwapBuffersMSC = NULL,
1611 .CopySubBuffer = radeonCopySubBuffer,
1612 .InitScreen2 = radeonInitScreen2,
1613 };
1614 #endif
1615