src/mesa/drivers/dri/radeon/radeon_screen.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
   2 /**************************************************************************
   3
   4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   5                      VA Linux Systems Inc., Fremont, California.
   6
   7 All Rights Reserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining
  10 a copy of this software and associated documentation files (the
  11 "Software"), to deal in the Software without restriction, including
  12 without limitation the rights to use, copy, modify, merge, publish,
  13 distribute, sublicense, and/or sell copies of the Software, and to
  14 permit persons to whom the Software is furnished to do so, subject to
  15 the following conditions:
  16
  17 The above copyright notice and this permission notice (including the
  18 next paragraph) shall be included in all copies or substantial
  19 portions of the Software.
  20
  21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28
  29 **************************************************************************/
  30
  31 /**
  32  * \file radeon_screen.c
  33  * Screen initialization functions for the Radeon driver.
  34  *
  35  * \author Kevin E. Martin <martin@valinux.com>
  36  * \author  Gareth Hughes <gareth@valinux.com>
  37  */
  38
  39 #include "glheader.h"
  40 #include "imports.h"
  41
  42 #define STANDALONE_MMIO
  43 #include "radeon_context.h"
  44 #include "radeon_screen.h"
  45 #include "radeon_macros.h"
  46
  47 #include "utils.h"
  48 #include "context.h"
  49 #include "vblank.h"
  50
  51 #include "GL/internal/dri_interface.h"
  52
  53 /* Radeon configuration
  54  */
  55 #include "xmlpool.h"
  56
  57 PUBLIC const char __driConfigOptions[] =
  58 DRI_CONF_BEGIN
  59     DRI_CONF_SECTION_PERFORMANCE
  60         DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
  61         DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
  62         DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
  63         DRI_CONF_HYPERZ(false)
  64     DRI_CONF_SECTION_END
  65     DRI_CONF_SECTION_QUALITY
  66         DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
  67         DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
  68         DRI_CONF_NO_NEG_LOD_BIAS(false)
  69         DRI_CONF_FORCE_S3TC_ENABLE(false)
  70         DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
  71         DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
  72         DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
  73     DRI_CONF_SECTION_END
  74     DRI_CONF_SECTION_DEBUG
  75         DRI_CONF_NO_RAST(false)
  76     DRI_CONF_SECTION_END
  77 DRI_CONF_END;
  78 static const GLuint __driNConfigOptions = 12;
  79
  80 #if 1
  81 /* Including xf86PciInfo.h introduces a bunch of errors...
  82  */
  83 #define PCI_CHIP_RADEON_QD      0x5144
  84 #define PCI_CHIP_RADEON_QE      0x5145
  85 #define PCI_CHIP_RADEON_QF      0x5146
  86 #define PCI_CHIP_RADEON_QG      0x5147
  87
  88 #define PCI_CHIP_RADEON_QY      0x5159
  89 #define PCI_CHIP_RADEON_QZ      0x515A
  90
  91 #define PCI_CHIP_RN50_5969      0x5969
  92
  93 #define PCI_CHIP_RADEON_LW      0x4C57 /* mobility 7 - has tcl */
  94 #define PCI_CHIP_RADEON_LX      0x4C58 /* mobility FireGL 7800 m7 */
  95
  96 #define PCI_CHIP_RADEON_LY      0x4C59
  97 #define PCI_CHIP_RADEON_LZ      0x4C5A
  98
  99 #define PCI_CHIP_RV200_QW       0x5157 /* Radeon 7500 - not an R200 at all */
 100 #define PCI_CHIP_RV200_QX       0x5158
 101
 102 /* IGP Chipsets */
 103 #define PCI_CHIP_RS100_4136     0x4136
 104 #define PCI_CHIP_RS200_4137     0x4137
 105 #define PCI_CHIP_RS250_4237     0x4237
 106 #define PCI_CHIP_RS100_4336     0x4336
 107 #define PCI_CHIP_RS200_4337     0x4337
 108 #define PCI_CHIP_RS250_4437     0x4437
 109 #endif
 110
 111 #ifdef USE_NEW_INTERFACE
 112 static PFNGLXCREATECONTEXTMODES create_context_modes = NULL;
 113 #endif /* USE_NEW_INTERFACE */
 114
 115 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
 116
 117 #ifdef USE_NEW_INTERFACE
 118 static __GLcontextModes *
 119 radeonFillInModes( unsigned pixel_bits, unsigned depth_bits,
 120                  unsigned stencil_bits, GLboolean have_back_buffer )
 121 {
 122     __GLcontextModes * modes;
 123     __GLcontextModes * m;
 124     unsigned num_modes;
 125     unsigned depth_buffer_factor;
 126     unsigned back_buffer_factor;
 127     GLenum fb_format;
 128     GLenum fb_type;
 129
 130     /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
 131      * enough to add support.  Basically, if a context is created with an
 132      * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
 133      * will never be used.
 134      */
 135     static const GLenum back_buffer_modes[] = {
 136         GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
 137     };
 138
 139     u_int8_t depth_bits_array[2];
 140     u_int8_t stencil_bits_array[2];
 141
 142
 143     depth_bits_array[0] = depth_bits;
 144     depth_bits_array[1] = depth_bits;
 145
 146     /* Just like with the accumulation buffer, always provide some modes
 147      * with a stencil buffer.  It will be a sw fallback, but some apps won't
 148      * care about that.
 149      */
 150     stencil_bits_array[0] = 0;
 151     stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
 152
 153     depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
 154     back_buffer_factor  = (have_back_buffer) ? 2 : 1;
 155
 156     num_modes = depth_buffer_factor * back_buffer_factor * 4;
 157
 158     if ( pixel_bits == 16 ) {
 159         fb_format = GL_RGB;
 160         fb_type = GL_UNSIGNED_SHORT_5_6_5;
 161     }
 162     else {
 163         fb_format = GL_BGRA;
 164         fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
 165     }
 166
 167     modes = (*create_context_modes)( num_modes, sizeof( __GLcontextModes ) );
 168     m = modes;
 169     if ( ! driFillInModes( & m, fb_format, fb_type,
 170                            depth_bits_array, stencil_bits_array, depth_buffer_factor,
 171                            back_buffer_modes, back_buffer_factor,
 172                            GLX_TRUE_COLOR ) ) {
 173         fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
 174                  __func__, __LINE__ );
 175         return NULL;
 176     }
 177
 178     if ( ! driFillInModes( & m, fb_format, fb_type,
 179                            depth_bits_array, stencil_bits_array, depth_buffer_factor,
 180                            back_buffer_modes, back_buffer_factor,
 181                            GLX_DIRECT_COLOR ) ) {
 182         fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
 183                  __func__, __LINE__ );
 184         return NULL;
 185     }
 186
 187     /* Mark the visual as slow if there are "fake" stencil bits.
 188      */
 189     for ( m = modes ; m != NULL ; m = m->next ) {
 190         if ( (m->stencilBits != 0) && (m->stencilBits != stencil_bits) ) {
 191             m->visualRating = GLX_SLOW_CONFIG;
 192         }
 193     }
 194
 195     return modes;
 196 }
 197 #endif /* USE_NEW_INTERFACE */
 198
 199 /* Create the device specific screen private data struct.
 200  */
 201 radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv )
 202 {
 203    radeonScreenPtr screen;
 204    RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
 205    unsigned char *RADEONMMIO;
 206
 207
 208    /* Allocate the private area */
 209    screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
 210    if ( !screen ) {
 211       __driUtilMessage("%s: Could not allocate memory for screen structure",
 212                        __FUNCTION__);
 213       return NULL;
 214    }
 215
 216    /* parse information in __driConfigOptions */
 217    driParseOptionInfo (&screen->optionCache,
 218                        __driConfigOptions, __driNConfigOptions);
 219
 220    /* This is first since which regions we map depends on whether or
 221     * not we are using a PCI card.
 222     */
 223    screen->IsPCI = dri_priv->IsPCI;
 224
 225    {
 226       int ret;
 227       drm_radeon_getparam_t gp;
 228
 229       gp.param = RADEON_PARAM_GART_BUFFER_OFFSET;
 230       gp.value = &screen->gart_buffer_offset;
 231
 232       ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
 233                                  &gp, sizeof(gp));
 234       if (ret) {
 235          FREE( screen );
 236          fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
 237          return NULL;
 238       }
 239
 240       if (sPriv->drmMinor >= 6) {
 241          gp.param = RADEON_PARAM_IRQ_NR;
 242          gp.value = &screen->irq;
 243
 244          ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
 245                                     &gp, sizeof(gp));
 246          if (ret) {
 247             FREE( screen );
 248             fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
 249             return NULL;
 250          }
 251       }
 252    }
 253
 254    screen->mmio.handle = dri_priv->registerHandle;
 255    screen->mmio.size   = dri_priv->registerSize;
 256    if ( drmMap( sPriv->fd,
 257                 screen->mmio.handle,
 258                 screen->mmio.size,
 259                 &screen->mmio.map ) ) {
 260       FREE( screen );
 261       __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
 262       return NULL;
 263    }
 264
 265    RADEONMMIO = screen->mmio.map;
 266
 267    screen->status.handle = dri_priv->statusHandle;
 268    screen->status.size   = dri_priv->statusSize;
 269    if ( drmMap( sPriv->fd,
 270                 screen->status.handle,
 271                 screen->status.size,
 272                 &screen->status.map ) ) {
 273       drmUnmap( screen->mmio.map, screen->mmio.size );
 274       FREE( screen );
 275       __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
 276       return NULL;
 277    }
 278    screen->scratch = (__volatile__ u_int32_t *)
 279       ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
 280
 281    screen->buffers = drmMapBufs( sPriv->fd );
 282    if ( !screen->buffers ) {
 283       drmUnmap( screen->status.map, screen->status.size );
 284       drmUnmap( screen->mmio.map, screen->mmio.size );
 285       FREE( screen );
 286       __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
 287       return NULL;
 288    }
 289
 290    if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
 291       screen->gartTextures.handle = dri_priv->gartTexHandle;
 292       screen->gartTextures.size   = dri_priv->gartTexMapSize;
 293       if ( drmMap( sPriv->fd,
 294                    screen->gartTextures.handle,
 295                    screen->gartTextures.size,
 296                    (drmAddressPtr)&screen->gartTextures.map ) ) {
 297          drmUnmapBufs( screen->buffers );
 298          drmUnmap( screen->status.map, screen->status.size );
 299          drmUnmap( screen->mmio.map, screen->mmio.size );
 300          FREE( screen );
 301          __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
 302          return NULL;
 303       }
 304
 305       screen->gart_texture_offset = dri_priv->gartTexOffset + ( screen->IsPCI
 306                 ? INREG( RADEON_AIC_LO_ADDR )
 307                 : ( ( INREG( RADEON_MC_AGP_LOCATION ) & 0x0ffffU ) << 16 ) );
 308    }
 309
 310    screen->chipset = 0;
 311    switch ( dri_priv->deviceID ) {
 312    default:
 313       fprintf(stderr, "unknown chip id, assuming full radeon support\n");
 314    case PCI_CHIP_RADEON_QD:
 315    case PCI_CHIP_RADEON_QE:
 316    case PCI_CHIP_RADEON_QF:
 317    case PCI_CHIP_RADEON_QG:
 318       /* all original radeons (7200) presumably have a stencil op bug */
 319       screen->chipset |= RADEON_CHIPSET_BROKEN_STENCIL;
 320    case PCI_CHIP_RV200_QW:
 321    case PCI_CHIP_RV200_QX:
 322    case PCI_CHIP_RADEON_LW:
 323    case PCI_CHIP_RADEON_LX:
 324       screen->chipset |= RADEON_CHIPSET_TCL;
 325    case PCI_CHIP_RADEON_QY:
 326    case PCI_CHIP_RADEON_QZ:
 327    case PCI_CHIP_RN50_5969:
 328    case PCI_CHIP_RADEON_LY:
 329    case PCI_CHIP_RADEON_LZ:
 330    case PCI_CHIP_RS100_4136: /* IGPs don't have TCL */
 331    case PCI_CHIP_RS200_4137:
 332    case PCI_CHIP_RS250_4237:
 333    case PCI_CHIP_RS100_4336:
 334    case PCI_CHIP_RS200_4337:
 335    case PCI_CHIP_RS250_4437:
 336       break;
 337    }
 338
 339    screen->cpp = dri_priv->bpp / 8;
 340    screen->AGPMode = dri_priv->AGPMode;
 341
 342    screen->fbLocation   = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff ) << 16;
 343
 344    if ( sPriv->drmMinor >= 10 ) {
 345       drm_radeon_setparam_t sp;
 346
 347       sp.param = RADEON_SETPARAM_FB_LOCATION;
 348       sp.value = screen->fbLocation;
 349
 350       drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
 351                        &sp, sizeof( sp ) );
 352    }
 353
 354    screen->frontOffset  = dri_priv->frontOffset;
 355    screen->frontPitch   = dri_priv->frontPitch;
 356    screen->backOffset   = dri_priv->backOffset;
 357    screen->backPitch    = dri_priv->backPitch;
 358    screen->depthOffset  = dri_priv->depthOffset;
 359    screen->depthPitch   = dri_priv->depthPitch;
 360
 361    /* Check if ddx has set up a surface reg to cover depth buffer */
 362    screen->depthHasSurface = ((sPriv->ddxMajor > 4) &&
 363       (screen->chipset & RADEON_CHIPSET_TCL));
 364
 365    screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
 366                                        + screen->fbLocation;
 367    screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
 368    screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
 369       dri_priv->log2TexGran;
 370
 371    if ( !screen->gartTextures.map
 372         || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
 373       screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
 374       screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
 375       screen->texSize[RADEON_GART_TEX_HEAP] = 0;
 376       screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
 377    } else {
 378       screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
 379       screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
 380       screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
 381       screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
 382          dri_priv->log2GARTTexGran;
 383    }
 384
 385    if ( driCompareGLXAPIVersion( 20030813 ) >= 0 ) {
 386       PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension =
 387           (PFNGLXSCRENABLEEXTENSIONPROC) glXGetProcAddress( (const GLubyte *) "__glXScrEnableExtension" );
 388       void * const psc = sPriv->psc->screenConfigs;
 389
 390       if ( glx_enable_extension != NULL ) {
 391          if ( screen->irq != 0 ) {
 392             (*glx_enable_extension)( psc, "GLX_SGI_swap_control" );
 393             (*glx_enable_extension)( psc, "GLX_SGI_video_sync" );
 394             (*glx_enable_extension)( psc, "GLX_MESA_swap_control" );
 395          }
 396
 397          (*glx_enable_extension)( psc, "GLX_MESA_swap_frame_usage" );
 398
 399          if ( driCompareGLXAPIVersion( 20030915 ) >= 0 ) {
 400             (*glx_enable_extension)( psc, "GLX_SGIX_fbconfig" );
 401             (*glx_enable_extension)( psc, "GLX_OML_swap_method" );
 402          }
 403
 404       }
 405    }
 406
 407    screen->driScreen = sPriv;
 408    screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
 409    return screen;
 410 }
 411
 412 /* Destroy the device specific screen private data struct.
 413  */
 414 void radeonDestroyScreen( __DRIscreenPrivate *sPriv )
 415 {
 416    radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
 417
 418    if (!screen)
 419       return;
 420
 421    if ( screen->gartTextures.map ) {
 422       drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
 423    }
 424    drmUnmapBufs( screen->buffers );
 425    drmUnmap( screen->status.map, screen->status.size );
 426    drmUnmap( screen->mmio.map, screen->mmio.size );
 427
 428    /* free all option information */
 429    driDestroyOptionInfo (&screen->optionCache);
 430
 431    FREE( screen );
 432    sPriv->private = NULL;
 433 }
 434
 435
 436 /* Initialize the driver specific screen private data.
 437  */
 438 static GLboolean
 439 radeonInitDriver( __DRIscreenPrivate *sPriv )
 440 {
 441    sPriv->private = (void *) radeonCreateScreen( sPriv );
 442    if ( !sPriv->private ) {
 443       radeonDestroyScreen( sPriv );
 444       return GL_FALSE;
 445    }
 446
 447    return GL_TRUE;
 448 }
 449
 450
 451
 452 /**
 453  * Create and initialize the Mesa and driver specific pixmap buffer
 454  * data.
 455  *
 456  * \todo This function (and its interface) will need to be updated to support
 457  * pbuffers.
 458  */
 459 static GLboolean
 460 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
 461                     __DRIdrawablePrivate *driDrawPriv,
 462                     const __GLcontextModes *mesaVis,
 463                     GLboolean isPixmap )
 464 {
 465    if (isPixmap) {
 466       return GL_FALSE; /* not implemented */
 467    }
 468    else {
 469       const GLboolean swDepth = GL_FALSE;
 470       const GLboolean swAlpha = GL_FALSE;
 471       const GLboolean swAccum = mesaVis->accumRedBits > 0;
 472       const GLboolean swStencil = mesaVis->stencilBits > 0 &&
 473          mesaVis->depthBits != 24;
 474       driDrawPriv->driverPrivate = (void *)
 475          _mesa_create_framebuffer( mesaVis,
 476                                    swDepth,
 477                                    swStencil,
 478                                    swAccum,
 479                                    swAlpha );
 480       return (driDrawPriv->driverPrivate != NULL);
 481    }
 482 }
 483
 484
 485 static void
 486 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
 487 {
 488    _mesa_destroy_framebuffer((GLframebuffer *) (driDrawPriv->driverPrivate));
 489 }
 490
 491 static struct __DriverAPIRec radeonAPI = {
 492    .InitDriver      = radeonInitDriver,
 493    .DestroyScreen   = radeonDestroyScreen,
 494    .CreateContext   = radeonCreateContext,
 495    .DestroyContext  = radeonDestroyContext,
 496    .CreateBuffer    = radeonCreateBuffer,
 497    .DestroyBuffer   = radeonDestroyBuffer,
 498    .SwapBuffers     = radeonSwapBuffers,
 499    .MakeCurrent     = radeonMakeCurrent,
 500    .UnbindContext   = radeonUnbindContext,
 501    .GetSwapInfo     = getSwapInfo,
 502    .GetMSC          = driGetMSC32,
 503    .WaitForMSC      = driWaitForMSC32,
 504    .WaitForSBC      = NULL,
 505    .SwapBuffersMSC  = NULL
 506 };
 507
 508
 509 /*
 510  * This is the bootstrap function for the driver.
 511  * The __driCreateScreen name is the symbol that libGL.so fetches.
 512  * Return:  pointer to a __DRIscreenPrivate.
 513  */
 514 #if !defined(DRI_NEW_INTERFACE_ONLY)
 515 void *__driCreateScreen(Display *dpy, int scrn, __DRIscreen *psc,
 516                         int numConfigs, __GLXvisualConfig *config)
 517 {
 518    __DRIscreenPrivate *psp;
 519    psp = __driUtilCreateScreen(dpy, scrn, psc, numConfigs, config, &radeonAPI);
 520    return (void *) psp;
 521 }
 522 #endif /* !defined(DRI_NEW_INTERFACE_ONLY) */
 523
 524 /**
 525  * This is the bootstrap function for the driver.  libGL supplies all of the
 526  * requisite information about the system, and the driver initializes itself.
 527  * This routine also fills in the linked list pointed to by \c driver_modes
 528  * with the \c __GLcontextModes that the driver can support for windows or
 529  * pbuffers.
 530  *
 531  * \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on
 532  *         failure.
 533  */
 534 #ifdef USE_NEW_INTERFACE
 535 PUBLIC
 536 void * __driCreateNewScreen( __DRInativeDisplay *dpy, int scrn, __DRIscreen *psc,
 537                              const __GLcontextModes * modes,
 538                              const __DRIversion * ddx_version,
 539                              const __DRIversion * dri_version,
 540                              const __DRIversion * drm_version,
 541                              const __DRIframebuffer * frame_buffer,
 542                              drmAddress pSAREA, int fd,
 543                              int internal_api_version,
 544                              __GLcontextModes ** driver_modes )
 545
 546 {
 547    __DRIscreenPrivate *psp;
 548    static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
 549    static const __DRIversion dri_expected = { 4, 0, 0 };
 550    static const __DRIversion drm_expected = { 1, 3, 0 };
 551
 552    if ( ! driCheckDriDdxDrmVersions3( "Radeon",
 553                                       dri_version, & dri_expected,
 554                                       ddx_version, & ddx_expected,
 555                                       drm_version, & drm_expected ) ) {
 556       return NULL;
 557    }
 558
 559    psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
 560                                   ddx_version, dri_version, drm_version,
 561                                   frame_buffer, pSAREA, fd,
 562                                   internal_api_version, &radeonAPI);
 563    if ( psp != NULL ) {
 564       create_context_modes = (PFNGLXCREATECONTEXTMODES)
 565           glXGetProcAddress( (const GLubyte *) "__glXCreateContextModes" );
 566       if ( create_context_modes != NULL ) {
 567          RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
 568          *driver_modes = radeonFillInModes( dri_priv->bpp,
 569                                             (dri_priv->bpp == 16) ? 16 : 24,
 570                                             (dri_priv->bpp == 16) ? 0  : 8,
 571                                             (dri_priv->backOffset != dri_priv->depthOffset) );
 572       }
 573    }
 574
 575    return (void *) psp;
 576 }
 577 #endif /* USE_NEW_INTERFACE */
 578
 579 /**
 580  * Get information about previous buffer swaps.
 581  */
 582 static int
 583 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
 584 {
 585    radeonContextPtr  rmesa;
 586
 587    if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
 588         || (dPriv->driContextPriv->driverPrivate == NULL)
 589         || (sInfo == NULL) ) {
 590       return -1;
 591    }
 592
 593    rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
 594    sInfo->swap_count = rmesa->swap_count;
 595    sInfo->swap_ust = rmesa->swap_ust;
 596    sInfo->swap_missed_count = rmesa->swap_missed_count;
 597
 598    sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
 599        ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
 600        : 0.0;
 601
 602    return 0;
 603 }