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Merge commit 'origin/openvg-1.0'
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
36 */
37
38 #include <errno.h>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
44
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #include "radeon_common.h"
50 #include "radeon_span.h"
51 #if !RADEON_COMMON
52 #include "radeon_context.h"
53 #include "radeon_tex.h"
54 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
55 #include "r200_context.h"
56 #include "r200_ioctl.h"
57 #include "r200_tex.h"
58 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
59 #include "r300_context.h"
60 #include "r300_fragprog.h"
61 #include "r300_tex.h"
62 #endif
63
64 #include "utils.h"
65 #include "vblank.h"
66 #include "drirenderbuffer.h"
67
68 #include "radeon_bocs_wrapper.h"
69
70 #include "GL/internal/dri_interface.h"
71
72 /* Radeon configuration
73 */
74 #include "xmlpool.h"
75
76 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
77 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
78 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
79 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
80 DRI_CONF_OPT_END
81
82 #if !RADEON_COMMON /* R100 */
83 PUBLIC const char __driConfigOptions[] =
84 DRI_CONF_BEGIN
85 DRI_CONF_SECTION_PERFORMANCE
86 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
87 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
88 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
89 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
90 DRI_CONF_HYPERZ(false)
91 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
92 DRI_CONF_SECTION_END
93 DRI_CONF_SECTION_QUALITY
94 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
95 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
96 DRI_CONF_NO_NEG_LOD_BIAS(false)
97 DRI_CONF_FORCE_S3TC_ENABLE(false)
98 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
99 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
100 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
101 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
102 DRI_CONF_SECTION_END
103 DRI_CONF_SECTION_DEBUG
104 DRI_CONF_NO_RAST(false)
105 DRI_CONF_SECTION_END
106 DRI_CONF_END;
107 static const GLuint __driNConfigOptions = 15;
108
109 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
110
111 PUBLIC const char __driConfigOptions[] =
112 DRI_CONF_BEGIN
113 DRI_CONF_SECTION_PERFORMANCE
114 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
115 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
116 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
117 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
118 DRI_CONF_HYPERZ(false)
119 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
120 DRI_CONF_SECTION_END
121 DRI_CONF_SECTION_QUALITY
122 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
123 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
124 DRI_CONF_NO_NEG_LOD_BIAS(false)
125 DRI_CONF_FORCE_S3TC_ENABLE(false)
126 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
127 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
128 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
129 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
130 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
131 DRI_CONF_SECTION_END
132 DRI_CONF_SECTION_DEBUG
133 DRI_CONF_NO_RAST(false)
134 DRI_CONF_SECTION_END
135 DRI_CONF_SECTION_SOFTWARE
136 DRI_CONF_NV_VERTEX_PROGRAM(false)
137 DRI_CONF_SECTION_END
138 DRI_CONF_END;
139 static const GLuint __driNConfigOptions = 17;
140
141 extern const struct dri_extension blend_extensions[];
142 extern const struct dri_extension ARB_vp_extension[];
143 extern const struct dri_extension NV_vp_extension[];
144 extern const struct dri_extension ATI_fs_extension[];
145 extern const struct dri_extension point_extensions[];
146
147 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
148
149 /* TODO: integrate these into xmlpool.h! */
150 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
151 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
152 DRI_CONF_DESC(en,"Number of texture image units") \
153 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
154 DRI_CONF_OPT_END
155
156 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
157 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
158 DRI_CONF_DESC(en,"Number of texture coordinate units") \
159 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
160 DRI_CONF_OPT_END
161
162
163
164 #define DRI_CONF_DISABLE_S3TC(def) \
165 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
166 DRI_CONF_DESC(en,"Disable S3TC compression") \
167 DRI_CONF_OPT_END
168
169 #define DRI_CONF_DISABLE_FALLBACK(def) \
170 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
171 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
172 DRI_CONF_OPT_END
173
174 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
175 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
176 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
177 DRI_CONF_OPT_END
178
179 #define DRI_CONF_FP_OPTIMIZATION(def) \
180 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
181 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
182 DRI_CONF_ENUM(0,"Optimize for Speed") \
183 DRI_CONF_ENUM(1,"Optimize for Quality") \
184 DRI_CONF_DESC_END \
185 DRI_CONF_OPT_END
186
187 PUBLIC const char __driConfigOptions[] =
188 DRI_CONF_BEGIN
189 DRI_CONF_SECTION_PERFORMANCE
190 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
191 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
192 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
193 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
194 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
195 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
196 DRI_CONF_DISABLE_FALLBACK(true)
197 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
198 DRI_CONF_SECTION_END
199 DRI_CONF_SECTION_QUALITY
200 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
201 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
202 DRI_CONF_FORCE_S3TC_ENABLE(false)
203 DRI_CONF_DISABLE_S3TC(false)
204 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
205 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
206 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
207 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
208 DRI_CONF_SECTION_END
209 DRI_CONF_SECTION_DEBUG
210 DRI_CONF_NO_RAST(false)
211 DRI_CONF_SECTION_END
212 DRI_CONF_END;
213 static const GLuint __driNConfigOptions = 17;
214
215 extern const struct dri_extension gl_20_extension[];
216
217 #ifndef RADEON_DEBUG
218
219 static const struct dri_debug_control debug_control[] = {
220 {"fall", DEBUG_FALLBACKS},
221 {"tex", DEBUG_TEXTURE},
222 {"ioctl", DEBUG_IOCTL},
223 {"prim", DEBUG_PRIMS},
224 {"vert", DEBUG_VERTS},
225 {"state", DEBUG_STATE},
226 {"code", DEBUG_CODEGEN},
227 {"vfmt", DEBUG_VFMT},
228 {"vtxf", DEBUG_VFMT},
229 {"verb", DEBUG_VERBOSE},
230 {"dri", DEBUG_DRI},
231 {"dma", DEBUG_DMA},
232 {"san", DEBUG_SANITY},
233 {"sync", DEBUG_SYNC},
234 {"pix", DEBUG_PIXEL},
235 {"mem", DEBUG_MEMORY},
236 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
237 {NULL, 0}
238 };
239 #endif /* RADEON_DEBUG */
240
241 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
242
243 extern const struct dri_extension card_extensions[];
244 extern const struct dri_extension mm_extensions[];
245
246 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
247
248 static int
249 radeonGetParam(__DRIscreenPrivate *sPriv, int param, void *value)
250 {
251 int ret;
252 drm_radeon_getparam_t gp = { 0 };
253 struct drm_radeon_info info = { 0 };
254
255 if (sPriv->drm_version.major >= 2) {
256 info.value = (uint64_t)value;
257 switch (param) {
258 case RADEON_PARAM_DEVICE_ID:
259 info.request = RADEON_INFO_DEVICE_ID;
260 break;
261 case RADEON_PARAM_NUM_GB_PIPES:
262 info.request = RADEON_INFO_NUM_GB_PIPES;
263 break;
264 default:
265 return -EINVAL;
266 }
267 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info));
268 } else {
269 gp.param = param;
270 gp.value = value;
271
272 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
273 }
274 return ret;
275 }
276
277 static const __DRIconfig **
278 radeonFillInModes( __DRIscreenPrivate *psp,
279 unsigned pixel_bits, unsigned depth_bits,
280 unsigned stencil_bits, GLboolean have_back_buffer )
281 {
282 __DRIconfig **configs;
283 __GLcontextModes *m;
284 unsigned depth_buffer_factor;
285 unsigned back_buffer_factor;
286 int i;
287
288 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
289 * enough to add support. Basically, if a context is created with an
290 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
291 * will never be used.
292 */
293 static const GLenum back_buffer_modes[] = {
294 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
295 };
296
297 uint8_t depth_bits_array[2];
298 uint8_t stencil_bits_array[2];
299 uint8_t msaa_samples_array[1];
300
301 depth_bits_array[0] = depth_bits;
302 depth_bits_array[1] = depth_bits;
303
304 /* Just like with the accumulation buffer, always provide some modes
305 * with a stencil buffer. It will be a sw fallback, but some apps won't
306 * care about that.
307 */
308 stencil_bits_array[0] = 0;
309 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
310
311 msaa_samples_array[0] = 0;
312
313 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
314 back_buffer_factor = (have_back_buffer) ? 2 : 1;
315
316 if (pixel_bits == 16) {
317 __DRIconfig **configs_a8r8g8b8;
318 __DRIconfig **configs_r5g6b5;
319
320 configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5,
321 depth_bits_array, stencil_bits_array,
322 depth_buffer_factor, back_buffer_modes,
323 back_buffer_factor, msaa_samples_array,
324 1);
325 configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
326 depth_bits_array, stencil_bits_array,
327 1, back_buffer_modes, 1,
328 msaa_samples_array, 1);
329 configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8);
330 } else
331 configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
332 depth_bits_array, stencil_bits_array,
333 depth_buffer_factor,
334 back_buffer_modes, back_buffer_factor,
335 msaa_samples_array, 1);
336
337 if (configs == NULL) {
338 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
339 __func__, __LINE__ );
340 return NULL;
341 }
342
343 /* Mark the visual as slow if there are "fake" stencil bits.
344 */
345 for (i = 0; configs[i]; i++) {
346 m = &configs[i]->modes;
347 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
348 m->visualRating = GLX_SLOW_CONFIG;
349 }
350 }
351
352 return (const __DRIconfig **) configs;
353 }
354
355 #if !RADEON_COMMON
356 static const __DRItexOffsetExtension radeonTexOffsetExtension = {
357 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
358 radeonSetTexOffset,
359 };
360
361 static const __DRItexBufferExtension radeonTexBufferExtension = {
362 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
363 radeonSetTexBuffer,
364 radeonSetTexBuffer2,
365 };
366 #endif
367
368 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
369 static const __DRIallocateExtension r200AllocateExtension = {
370 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
371 r200AllocateMemoryMESA,
372 r200FreeMemoryMESA,
373 r200GetMemoryOffsetMESA
374 };
375
376 static const __DRItexOffsetExtension r200texOffsetExtension = {
377 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
378 r200SetTexOffset,
379 };
380
381 static const __DRItexBufferExtension r200TexBufferExtension = {
382 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
383 r200SetTexBuffer,
384 r200SetTexBuffer2,
385 };
386 #endif
387
388 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
389 static const __DRItexOffsetExtension r300texOffsetExtension = {
390 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
391 r300SetTexOffset,
392 };
393
394 static const __DRItexBufferExtension r300TexBufferExtension = {
395 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
396 r300SetTexBuffer,
397 r300SetTexBuffer2,
398 };
399 #endif
400
401 static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
402 {
403 screen->device_id = device_id;
404 screen->chip_flags = 0;
405 switch ( device_id ) {
406 case PCI_CHIP_RADEON_LY:
407 case PCI_CHIP_RADEON_LZ:
408 case PCI_CHIP_RADEON_QY:
409 case PCI_CHIP_RADEON_QZ:
410 case PCI_CHIP_RN50_515E:
411 case PCI_CHIP_RN50_5969:
412 screen->chip_family = CHIP_FAMILY_RV100;
413 break;
414
415 case PCI_CHIP_RS100_4136:
416 case PCI_CHIP_RS100_4336:
417 screen->chip_family = CHIP_FAMILY_RS100;
418 break;
419
420 case PCI_CHIP_RS200_4137:
421 case PCI_CHIP_RS200_4337:
422 case PCI_CHIP_RS250_4237:
423 case PCI_CHIP_RS250_4437:
424 screen->chip_family = CHIP_FAMILY_RS200;
425 break;
426
427 case PCI_CHIP_RADEON_QD:
428 case PCI_CHIP_RADEON_QE:
429 case PCI_CHIP_RADEON_QF:
430 case PCI_CHIP_RADEON_QG:
431 /* all original radeons (7200) presumably have a stencil op bug */
432 screen->chip_family = CHIP_FAMILY_R100;
433 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
434 break;
435
436 case PCI_CHIP_RV200_QW:
437 case PCI_CHIP_RV200_QX:
438 case PCI_CHIP_RADEON_LW:
439 case PCI_CHIP_RADEON_LX:
440 screen->chip_family = CHIP_FAMILY_RV200;
441 screen->chip_flags = RADEON_CHIPSET_TCL;
442 break;
443
444 case PCI_CHIP_R200_BB:
445 case PCI_CHIP_R200_BC:
446 case PCI_CHIP_R200_QH:
447 case PCI_CHIP_R200_QL:
448 case PCI_CHIP_R200_QM:
449 screen->chip_family = CHIP_FAMILY_R200;
450 screen->chip_flags = RADEON_CHIPSET_TCL;
451 break;
452
453 case PCI_CHIP_RV250_If:
454 case PCI_CHIP_RV250_Ig:
455 case PCI_CHIP_RV250_Ld:
456 case PCI_CHIP_RV250_Lf:
457 case PCI_CHIP_RV250_Lg:
458 screen->chip_family = CHIP_FAMILY_RV250;
459 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
460 break;
461
462 case PCI_CHIP_RV280_5960:
463 case PCI_CHIP_RV280_5961:
464 case PCI_CHIP_RV280_5962:
465 case PCI_CHIP_RV280_5964:
466 case PCI_CHIP_RV280_5965:
467 case PCI_CHIP_RV280_5C61:
468 case PCI_CHIP_RV280_5C63:
469 screen->chip_family = CHIP_FAMILY_RV280;
470 screen->chip_flags = RADEON_CHIPSET_TCL;
471 break;
472
473 case PCI_CHIP_RS300_5834:
474 case PCI_CHIP_RS300_5835:
475 case PCI_CHIP_RS350_7834:
476 case PCI_CHIP_RS350_7835:
477 screen->chip_family = CHIP_FAMILY_RS300;
478 break;
479
480 case PCI_CHIP_R300_AD:
481 case PCI_CHIP_R300_AE:
482 case PCI_CHIP_R300_AF:
483 case PCI_CHIP_R300_AG:
484 case PCI_CHIP_R300_ND:
485 case PCI_CHIP_R300_NE:
486 case PCI_CHIP_R300_NF:
487 case PCI_CHIP_R300_NG:
488 screen->chip_family = CHIP_FAMILY_R300;
489 screen->chip_flags = RADEON_CHIPSET_TCL;
490 break;
491
492 case PCI_CHIP_RV350_AP:
493 case PCI_CHIP_RV350_AQ:
494 case PCI_CHIP_RV350_AR:
495 case PCI_CHIP_RV350_AS:
496 case PCI_CHIP_RV350_AT:
497 case PCI_CHIP_RV350_AV:
498 case PCI_CHIP_RV350_AU:
499 case PCI_CHIP_RV350_NP:
500 case PCI_CHIP_RV350_NQ:
501 case PCI_CHIP_RV350_NR:
502 case PCI_CHIP_RV350_NS:
503 case PCI_CHIP_RV350_NT:
504 case PCI_CHIP_RV350_NV:
505 screen->chip_family = CHIP_FAMILY_RV350;
506 screen->chip_flags = RADEON_CHIPSET_TCL;
507 break;
508
509 case PCI_CHIP_R350_AH:
510 case PCI_CHIP_R350_AI:
511 case PCI_CHIP_R350_AJ:
512 case PCI_CHIP_R350_AK:
513 case PCI_CHIP_R350_NH:
514 case PCI_CHIP_R350_NI:
515 case PCI_CHIP_R360_NJ:
516 case PCI_CHIP_R350_NK:
517 screen->chip_family = CHIP_FAMILY_R350;
518 screen->chip_flags = RADEON_CHIPSET_TCL;
519 break;
520
521 case PCI_CHIP_RV370_5460:
522 case PCI_CHIP_RV370_5462:
523 case PCI_CHIP_RV370_5464:
524 case PCI_CHIP_RV370_5B60:
525 case PCI_CHIP_RV370_5B62:
526 case PCI_CHIP_RV370_5B63:
527 case PCI_CHIP_RV370_5B64:
528 case PCI_CHIP_RV370_5B65:
529 case PCI_CHIP_RV380_3150:
530 case PCI_CHIP_RV380_3152:
531 case PCI_CHIP_RV380_3154:
532 case PCI_CHIP_RV380_3E50:
533 case PCI_CHIP_RV380_3E54:
534 screen->chip_family = CHIP_FAMILY_RV380;
535 screen->chip_flags = RADEON_CHIPSET_TCL;
536 break;
537
538 case PCI_CHIP_R420_JN:
539 case PCI_CHIP_R420_JH:
540 case PCI_CHIP_R420_JI:
541 case PCI_CHIP_R420_JJ:
542 case PCI_CHIP_R420_JK:
543 case PCI_CHIP_R420_JL:
544 case PCI_CHIP_R420_JM:
545 case PCI_CHIP_R420_JO:
546 case PCI_CHIP_R420_JP:
547 case PCI_CHIP_R420_JT:
548 case PCI_CHIP_R481_4B49:
549 case PCI_CHIP_R481_4B4A:
550 case PCI_CHIP_R481_4B4B:
551 case PCI_CHIP_R481_4B4C:
552 case PCI_CHIP_R423_UH:
553 case PCI_CHIP_R423_UI:
554 case PCI_CHIP_R423_UJ:
555 case PCI_CHIP_R423_UK:
556 case PCI_CHIP_R430_554C:
557 case PCI_CHIP_R430_554D:
558 case PCI_CHIP_R430_554E:
559 case PCI_CHIP_R430_554F:
560 case PCI_CHIP_R423_5550:
561 case PCI_CHIP_R423_UQ:
562 case PCI_CHIP_R423_UR:
563 case PCI_CHIP_R423_UT:
564 case PCI_CHIP_R430_5D48:
565 case PCI_CHIP_R430_5D49:
566 case PCI_CHIP_R430_5D4A:
567 case PCI_CHIP_R480_5D4C:
568 case PCI_CHIP_R480_5D4D:
569 case PCI_CHIP_R480_5D4E:
570 case PCI_CHIP_R480_5D4F:
571 case PCI_CHIP_R480_5D50:
572 case PCI_CHIP_R480_5D52:
573 case PCI_CHIP_R423_5D57:
574 screen->chip_family = CHIP_FAMILY_R420;
575 screen->chip_flags = RADEON_CHIPSET_TCL;
576 break;
577
578 case PCI_CHIP_RV410_5E4C:
579 case PCI_CHIP_RV410_5E4F:
580 case PCI_CHIP_RV410_564A:
581 case PCI_CHIP_RV410_564B:
582 case PCI_CHIP_RV410_564F:
583 case PCI_CHIP_RV410_5652:
584 case PCI_CHIP_RV410_5653:
585 case PCI_CHIP_RV410_5657:
586 case PCI_CHIP_RV410_5E48:
587 case PCI_CHIP_RV410_5E4A:
588 case PCI_CHIP_RV410_5E4B:
589 case PCI_CHIP_RV410_5E4D:
590 screen->chip_family = CHIP_FAMILY_RV410;
591 screen->chip_flags = RADEON_CHIPSET_TCL;
592 break;
593
594 case PCI_CHIP_RS480_5954:
595 case PCI_CHIP_RS480_5955:
596 case PCI_CHIP_RS482_5974:
597 case PCI_CHIP_RS482_5975:
598 case PCI_CHIP_RS400_5A41:
599 case PCI_CHIP_RS400_5A42:
600 case PCI_CHIP_RC410_5A61:
601 case PCI_CHIP_RC410_5A62:
602 screen->chip_family = CHIP_FAMILY_RS400;
603 break;
604
605 case PCI_CHIP_RS600_793F:
606 case PCI_CHIP_RS600_7941:
607 case PCI_CHIP_RS600_7942:
608 screen->chip_family = CHIP_FAMILY_RS600;
609 break;
610
611 case PCI_CHIP_RS690_791E:
612 case PCI_CHIP_RS690_791F:
613 screen->chip_family = CHIP_FAMILY_RS690;
614 break;
615 case PCI_CHIP_RS740_796C:
616 case PCI_CHIP_RS740_796D:
617 case PCI_CHIP_RS740_796E:
618 case PCI_CHIP_RS740_796F:
619 screen->chip_family = CHIP_FAMILY_RS740;
620 break;
621
622 case PCI_CHIP_R520_7100:
623 case PCI_CHIP_R520_7101:
624 case PCI_CHIP_R520_7102:
625 case PCI_CHIP_R520_7103:
626 case PCI_CHIP_R520_7104:
627 case PCI_CHIP_R520_7105:
628 case PCI_CHIP_R520_7106:
629 case PCI_CHIP_R520_7108:
630 case PCI_CHIP_R520_7109:
631 case PCI_CHIP_R520_710A:
632 case PCI_CHIP_R520_710B:
633 case PCI_CHIP_R520_710C:
634 case PCI_CHIP_R520_710E:
635 case PCI_CHIP_R520_710F:
636 screen->chip_family = CHIP_FAMILY_R520;
637 screen->chip_flags = RADEON_CHIPSET_TCL;
638 break;
639
640 case PCI_CHIP_RV515_7140:
641 case PCI_CHIP_RV515_7141:
642 case PCI_CHIP_RV515_7142:
643 case PCI_CHIP_RV515_7143:
644 case PCI_CHIP_RV515_7144:
645 case PCI_CHIP_RV515_7145:
646 case PCI_CHIP_RV515_7146:
647 case PCI_CHIP_RV515_7147:
648 case PCI_CHIP_RV515_7149:
649 case PCI_CHIP_RV515_714A:
650 case PCI_CHIP_RV515_714B:
651 case PCI_CHIP_RV515_714C:
652 case PCI_CHIP_RV515_714D:
653 case PCI_CHIP_RV515_714E:
654 case PCI_CHIP_RV515_714F:
655 case PCI_CHIP_RV515_7151:
656 case PCI_CHIP_RV515_7152:
657 case PCI_CHIP_RV515_7153:
658 case PCI_CHIP_RV515_715E:
659 case PCI_CHIP_RV515_715F:
660 case PCI_CHIP_RV515_7180:
661 case PCI_CHIP_RV515_7181:
662 case PCI_CHIP_RV515_7183:
663 case PCI_CHIP_RV515_7186:
664 case PCI_CHIP_RV515_7187:
665 case PCI_CHIP_RV515_7188:
666 case PCI_CHIP_RV515_718A:
667 case PCI_CHIP_RV515_718B:
668 case PCI_CHIP_RV515_718C:
669 case PCI_CHIP_RV515_718D:
670 case PCI_CHIP_RV515_718F:
671 case PCI_CHIP_RV515_7193:
672 case PCI_CHIP_RV515_7196:
673 case PCI_CHIP_RV515_719B:
674 case PCI_CHIP_RV515_719F:
675 case PCI_CHIP_RV515_7200:
676 case PCI_CHIP_RV515_7210:
677 case PCI_CHIP_RV515_7211:
678 screen->chip_family = CHIP_FAMILY_RV515;
679 screen->chip_flags = RADEON_CHIPSET_TCL;
680 break;
681
682 case PCI_CHIP_RV530_71C0:
683 case PCI_CHIP_RV530_71C1:
684 case PCI_CHIP_RV530_71C2:
685 case PCI_CHIP_RV530_71C3:
686 case PCI_CHIP_RV530_71C4:
687 case PCI_CHIP_RV530_71C5:
688 case PCI_CHIP_RV530_71C6:
689 case PCI_CHIP_RV530_71C7:
690 case PCI_CHIP_RV530_71CD:
691 case PCI_CHIP_RV530_71CE:
692 case PCI_CHIP_RV530_71D2:
693 case PCI_CHIP_RV530_71D4:
694 case PCI_CHIP_RV530_71D5:
695 case PCI_CHIP_RV530_71D6:
696 case PCI_CHIP_RV530_71DA:
697 case PCI_CHIP_RV530_71DE:
698 screen->chip_family = CHIP_FAMILY_RV530;
699 screen->chip_flags = RADEON_CHIPSET_TCL;
700 break;
701
702 case PCI_CHIP_R580_7240:
703 case PCI_CHIP_R580_7243:
704 case PCI_CHIP_R580_7244:
705 case PCI_CHIP_R580_7245:
706 case PCI_CHIP_R580_7246:
707 case PCI_CHIP_R580_7247:
708 case PCI_CHIP_R580_7248:
709 case PCI_CHIP_R580_7249:
710 case PCI_CHIP_R580_724A:
711 case PCI_CHIP_R580_724B:
712 case PCI_CHIP_R580_724C:
713 case PCI_CHIP_R580_724D:
714 case PCI_CHIP_R580_724E:
715 case PCI_CHIP_R580_724F:
716 case PCI_CHIP_R580_7284:
717 screen->chip_family = CHIP_FAMILY_R580;
718 screen->chip_flags = RADEON_CHIPSET_TCL;
719 break;
720
721 case PCI_CHIP_RV570_7280:
722 case PCI_CHIP_RV560_7281:
723 case PCI_CHIP_RV560_7283:
724 case PCI_CHIP_RV560_7287:
725 case PCI_CHIP_RV570_7288:
726 case PCI_CHIP_RV570_7289:
727 case PCI_CHIP_RV570_728B:
728 case PCI_CHIP_RV570_728C:
729 case PCI_CHIP_RV560_7290:
730 case PCI_CHIP_RV560_7291:
731 case PCI_CHIP_RV560_7293:
732 case PCI_CHIP_RV560_7297:
733 screen->chip_family = CHIP_FAMILY_RV560;
734 screen->chip_flags = RADEON_CHIPSET_TCL;
735 break;
736
737 default:
738 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
739 device_id);
740 return -1;
741 }
742
743 return 0;
744 }
745
746
747 /* Create the device specific screen private data struct.
748 */
749 static radeonScreenPtr
750 radeonCreateScreen( __DRIscreenPrivate *sPriv )
751 {
752 radeonScreenPtr screen;
753 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
754 unsigned char *RADEONMMIO = NULL;
755 int i;
756 int ret;
757 uint32_t temp = 0;
758
759 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
760 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
761 return GL_FALSE;
762 }
763
764 /* Allocate the private area */
765 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
766 if ( !screen ) {
767 __driUtilMessage("%s: Could not allocate memory for screen structure",
768 __FUNCTION__);
769 return NULL;
770 }
771
772 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
773 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
774 #endif
775
776 /* parse information in __driConfigOptions */
777 driParseOptionInfo (&screen->optionCache,
778 __driConfigOptions, __driNConfigOptions);
779
780 /* This is first since which regions we map depends on whether or
781 * not we are using a PCI card.
782 */
783 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
784 {
785 int ret;
786
787 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET,
788 &screen->gart_buffer_offset);
789
790 if (ret) {
791 FREE( screen );
792 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
793 return NULL;
794 }
795
796 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE,
797 &screen->gart_base);
798 if (ret) {
799 FREE( screen );
800 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
801 return NULL;
802 }
803
804 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR,
805 &screen->irq);
806 if (ret) {
807 FREE( screen );
808 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
809 return NULL;
810 }
811 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
812 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
813 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
814 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
815 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
816 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
817 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
818 }
819
820 screen->mmio.handle = dri_priv->registerHandle;
821 screen->mmio.size = dri_priv->registerSize;
822 if ( drmMap( sPriv->fd,
823 screen->mmio.handle,
824 screen->mmio.size,
825 &screen->mmio.map ) ) {
826 FREE( screen );
827 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
828 return NULL;
829 }
830
831 RADEONMMIO = screen->mmio.map;
832
833 screen->status.handle = dri_priv->statusHandle;
834 screen->status.size = dri_priv->statusSize;
835 if ( drmMap( sPriv->fd,
836 screen->status.handle,
837 screen->status.size,
838 &screen->status.map ) ) {
839 drmUnmap( screen->mmio.map, screen->mmio.size );
840 FREE( screen );
841 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
842 return NULL;
843 }
844 screen->scratch = (__volatile__ uint32_t *)
845 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
846
847 screen->buffers = drmMapBufs( sPriv->fd );
848 if ( !screen->buffers ) {
849 drmUnmap( screen->status.map, screen->status.size );
850 drmUnmap( screen->mmio.map, screen->mmio.size );
851 FREE( screen );
852 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
853 return NULL;
854 }
855
856 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
857 screen->gartTextures.handle = dri_priv->gartTexHandle;
858 screen->gartTextures.size = dri_priv->gartTexMapSize;
859 if ( drmMap( sPriv->fd,
860 screen->gartTextures.handle,
861 screen->gartTextures.size,
862 (drmAddressPtr)&screen->gartTextures.map ) ) {
863 drmUnmapBufs( screen->buffers );
864 drmUnmap( screen->status.map, screen->status.size );
865 drmUnmap( screen->mmio.map, screen->mmio.size );
866 FREE( screen );
867 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
868 return NULL;
869 }
870
871 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
872 }
873
874 ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
875 if (ret == -1)
876 return NULL;
877
878 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
879 sPriv->ddx_version.minor < 2) {
880 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
881 return NULL;
882 }
883
884 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
885 fprintf(stderr, "R500 support requires a newer drm.\n");
886 return NULL;
887 }
888
889 if (getenv("R300_NO_TCL"))
890 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
891
892 if (screen->chip_family <= CHIP_FAMILY_RS200)
893 screen->chip_flags |= RADEON_CLASS_R100;
894 else if (screen->chip_family <= CHIP_FAMILY_RV280)
895 screen->chip_flags |= RADEON_CLASS_R200;
896 else
897 screen->chip_flags |= RADEON_CLASS_R300;
898
899 screen->cpp = dri_priv->bpp / 8;
900 screen->AGPMode = dri_priv->AGPMode;
901
902 ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp);
903 if (ret) {
904 if (screen->chip_family < CHIP_FAMILY_RS600)
905 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
906 else {
907 FREE( screen );
908 fprintf(stderr, "Unable to get fb location need newer drm\n");
909 return NULL;
910 }
911 } else {
912 screen->fbLocation = (temp & 0xffff) << 16;
913 }
914
915 if (screen->chip_family >= CHIP_FAMILY_R300) {
916 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
917 if (ret) {
918 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
919 switch (screen->chip_family) {
920 case CHIP_FAMILY_R300:
921 case CHIP_FAMILY_R350:
922 screen->num_gb_pipes = 2;
923 break;
924 case CHIP_FAMILY_R420:
925 case CHIP_FAMILY_R520:
926 case CHIP_FAMILY_R580:
927 case CHIP_FAMILY_RV560:
928 case CHIP_FAMILY_RV570:
929 screen->num_gb_pipes = 4;
930 break;
931 case CHIP_FAMILY_RV350:
932 case CHIP_FAMILY_RV515:
933 case CHIP_FAMILY_RV530:
934 case CHIP_FAMILY_RV410:
935 default:
936 screen->num_gb_pipes = 1;
937 break;
938 }
939 } else {
940 screen->num_gb_pipes = temp;
941 }
942
943 /* pipe overrides */
944 switch (dri_priv->deviceID) {
945 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
946 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
947 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
948 screen->num_gb_pipes = 1;
949 break;
950 default:
951 break;
952 }
953 }
954
955 if ( sPriv->drm_version.minor >= 10 ) {
956 drm_radeon_setparam_t sp;
957
958 sp.param = RADEON_SETPARAM_FB_LOCATION;
959 sp.value = screen->fbLocation;
960
961 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
962 &sp, sizeof( sp ) );
963 }
964
965 screen->frontOffset = dri_priv->frontOffset;
966 screen->frontPitch = dri_priv->frontPitch;
967 screen->backOffset = dri_priv->backOffset;
968 screen->backPitch = dri_priv->backPitch;
969 screen->depthOffset = dri_priv->depthOffset;
970 screen->depthPitch = dri_priv->depthPitch;
971
972 /* Check if ddx has set up a surface reg to cover depth buffer */
973 screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
974 /* these chips don't use tiled z without hyperz. So always pretend
975 we have set up a surface which will cause linear reads/writes */
976 (IS_R100_CLASS(screen) &&
977 !(screen->chip_flags & RADEON_CHIPSET_TCL));
978
979 if ( dri_priv->textureSize == 0 ) {
980 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
981 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
982 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
983 dri_priv->log2GARTTexGran;
984 } else {
985 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
986 + screen->fbLocation;
987 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
988 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
989 dri_priv->log2TexGran;
990 }
991
992 if ( !screen->gartTextures.map || dri_priv->textureSize == 0
993 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
994 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
995 screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
996 screen->texSize[RADEON_GART_TEX_HEAP] = 0;
997 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
998 } else {
999 screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
1000 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
1001 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
1002 screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
1003 dri_priv->log2GARTTexGran;
1004 }
1005
1006 i = 0;
1007 screen->extensions[i++] = &driCopySubBufferExtension.base;
1008 screen->extensions[i++] = &driFrameTrackingExtension.base;
1009 screen->extensions[i++] = &driReadDrawableExtension;
1010
1011 if ( screen->irq != 0 ) {
1012 screen->extensions[i++] = &driSwapControlExtension.base;
1013 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1014 }
1015
1016 #if !RADEON_COMMON
1017 screen->extensions[i++] = &radeonTexOffsetExtension.base;
1018 #endif
1019
1020 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1021 if (IS_R200_CLASS(screen))
1022 screen->extensions[i++] = &r200AllocateExtension.base;
1023
1024 screen->extensions[i++] = &r200texOffsetExtension.base;
1025 #endif
1026
1027 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1028 screen->extensions[i++] = &r300texOffsetExtension.base;
1029 #endif
1030
1031 screen->extensions[i++] = NULL;
1032 sPriv->extensions = screen->extensions;
1033
1034 screen->driScreen = sPriv;
1035 screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
1036 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
1037 screen->sarea_priv_offset);
1038
1039 screen->bom = radeon_bo_manager_legacy_ctor(screen);
1040 if (screen->bom == NULL) {
1041 free(screen);
1042 return NULL;
1043 }
1044
1045 return screen;
1046 }
1047
1048 static radeonScreenPtr
1049 radeonCreateScreen2(__DRIscreenPrivate *sPriv)
1050 {
1051 radeonScreenPtr screen;
1052 int i;
1053 int ret;
1054 uint32_t device_id = 0;
1055 uint32_t temp = 0;
1056
1057 /* Allocate the private area */
1058 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1059 if ( !screen ) {
1060 __driUtilMessage("%s: Could not allocate memory for screen structure",
1061 __FUNCTION__);
1062 fprintf(stderr, "leaving here\n");
1063 return NULL;
1064 }
1065
1066 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1067 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
1068 #endif
1069
1070 /* parse information in __driConfigOptions */
1071 driParseOptionInfo (&screen->optionCache,
1072 __driConfigOptions, __driNConfigOptions);
1073
1074 screen->kernel_mm = 1;
1075 screen->chip_flags = 0;
1076
1077 /* if we have kms we can support all of these */
1078 screen->drmSupportsCubeMapsR200 = 1;
1079 screen->drmSupportsBlendColor = 1;
1080 screen->drmSupportsTriPerf = 1;
1081 screen->drmSupportsFragShader = 1;
1082 screen->drmSupportsPointSprites = 1;
1083 screen->drmSupportsCubeMapsR100 = 1;
1084 screen->drmSupportsVertexProgram = 1;
1085 screen->irq = 1;
1086
1087 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id);
1088 if (ret) {
1089 FREE( screen );
1090 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret);
1091 return NULL;
1092 }
1093
1094 ret = radeon_set_screen_flags(screen, device_id);
1095 if (ret == -1)
1096 return NULL;
1097
1098 if (screen->chip_family >= CHIP_FAMILY_R300) {
1099 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1100 if (ret) {
1101 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1102 switch (screen->chip_family) {
1103 case CHIP_FAMILY_R300:
1104 case CHIP_FAMILY_R350:
1105 screen->num_gb_pipes = 2;
1106 break;
1107 case CHIP_FAMILY_R420:
1108 case CHIP_FAMILY_R520:
1109 case CHIP_FAMILY_R580:
1110 case CHIP_FAMILY_RV560:
1111 case CHIP_FAMILY_RV570:
1112 screen->num_gb_pipes = 4;
1113 break;
1114 case CHIP_FAMILY_RV350:
1115 case CHIP_FAMILY_RV515:
1116 case CHIP_FAMILY_RV530:
1117 case CHIP_FAMILY_RV410:
1118 default:
1119 screen->num_gb_pipes = 1;
1120 break;
1121 }
1122 } else {
1123 screen->num_gb_pipes = temp;
1124 }
1125
1126 /* pipe overrides */
1127 switch (device_id) {
1128 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1129 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
1130 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
1131 screen->num_gb_pipes = 1;
1132 break;
1133 default:
1134 break;
1135 }
1136
1137 }
1138
1139 if (screen->chip_family <= CHIP_FAMILY_RS200)
1140 screen->chip_flags |= RADEON_CLASS_R100;
1141 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1142 screen->chip_flags |= RADEON_CLASS_R200;
1143 else
1144 screen->chip_flags |= RADEON_CLASS_R300;
1145
1146 if (getenv("R300_NO_TCL"))
1147 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1148
1149 i = 0;
1150 screen->extensions[i++] = &driCopySubBufferExtension.base;
1151 screen->extensions[i++] = &driFrameTrackingExtension.base;
1152 screen->extensions[i++] = &driReadDrawableExtension;
1153
1154 if ( screen->irq != 0 ) {
1155 screen->extensions[i++] = &driSwapControlExtension.base;
1156 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1157 }
1158
1159 #if !RADEON_COMMON
1160 screen->extensions[i++] = &radeonTexBufferExtension.base;
1161 #endif
1162
1163 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1164 if (IS_R200_CLASS(screen))
1165 screen->extensions[i++] = &r200AllocateExtension.base;
1166
1167 screen->extensions[i++] = &r200TexBufferExtension.base;
1168 #endif
1169
1170 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1171 screen->extensions[i++] = &r300TexBufferExtension.base;
1172 #endif
1173
1174 screen->extensions[i++] = NULL;
1175 sPriv->extensions = screen->extensions;
1176
1177 screen->driScreen = sPriv;
1178 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1179 if (screen->bom == NULL) {
1180 free(screen);
1181 return NULL;
1182 }
1183 return screen;
1184 }
1185
1186 /* Destroy the device specific screen private data struct.
1187 */
1188 static void
1189 radeonDestroyScreen( __DRIscreenPrivate *sPriv )
1190 {
1191 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1192
1193 if (!screen)
1194 return;
1195
1196 if (screen->kernel_mm) {
1197 #ifdef RADEON_BO_TRACK
1198 radeon_tracker_print(&screen->bom->tracker, stderr);
1199 #endif
1200 radeon_bo_manager_gem_dtor(screen->bom);
1201 } else {
1202 radeon_bo_manager_legacy_dtor(screen->bom);
1203
1204 if ( screen->gartTextures.map ) {
1205 drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
1206 }
1207 drmUnmapBufs( screen->buffers );
1208 drmUnmap( screen->status.map, screen->status.size );
1209 drmUnmap( screen->mmio.map, screen->mmio.size );
1210 }
1211
1212 /* free all option information */
1213 driDestroyOptionInfo (&screen->optionCache);
1214
1215 FREE( screen );
1216 sPriv->private = NULL;
1217 }
1218
1219
1220 /* Initialize the driver specific screen private data.
1221 */
1222 static GLboolean
1223 radeonInitDriver( __DRIscreenPrivate *sPriv )
1224 {
1225 if (sPriv->dri2.enabled) {
1226 sPriv->private = (void *) radeonCreateScreen2( sPriv );
1227 } else {
1228 sPriv->private = (void *) radeonCreateScreen( sPriv );
1229 }
1230 if ( !sPriv->private ) {
1231 radeonDestroyScreen( sPriv );
1232 return GL_FALSE;
1233 }
1234
1235 return GL_TRUE;
1236 }
1237
1238
1239
1240 /**
1241 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1242 *
1243 * \todo This function (and its interface) will need to be updated to support
1244 * pbuffers.
1245 */
1246 static GLboolean
1247 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
1248 __DRIdrawablePrivate *driDrawPriv,
1249 const __GLcontextModes *mesaVis,
1250 GLboolean isPixmap )
1251 {
1252 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1253
1254 const GLboolean swDepth = GL_FALSE;
1255 const GLboolean swAlpha = GL_FALSE;
1256 const GLboolean swAccum = mesaVis->accumRedBits > 0;
1257 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1258 mesaVis->depthBits != 24;
1259 GLenum rgbFormat;
1260 struct radeon_framebuffer *rfb;
1261
1262 if (isPixmap)
1263 return GL_FALSE; /* not implemented */
1264
1265 rfb = CALLOC_STRUCT(radeon_framebuffer);
1266 if (!rfb)
1267 return GL_FALSE;
1268
1269 _mesa_initialize_framebuffer(&rfb->base, mesaVis);
1270
1271 if (mesaVis->redBits == 5)
1272 rgbFormat = GL_RGB5;
1273 else if (mesaVis->alphaBits == 0)
1274 rgbFormat = GL_RGB8;
1275 else
1276 rgbFormat = GL_RGBA8;
1277
1278 /* front color renderbuffer */
1279 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1280 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base);
1281 rfb->color_rb[0]->has_surface = 1;
1282
1283 /* back color renderbuffer */
1284 if (mesaVis->doubleBufferMode) {
1285 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1286 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base);
1287 rfb->color_rb[1]->has_surface = 1;
1288 }
1289
1290 if (mesaVis->depthBits == 24) {
1291 if (mesaVis->stencilBits == 8) {
1292 struct radeon_renderbuffer *depthStencilRb = radeon_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT, driDrawPriv);
1293 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base);
1294 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base);
1295 depthStencilRb->has_surface = screen->depthHasSurface;
1296 } else {
1297 /* depth renderbuffer */
1298 struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT24, driDrawPriv);
1299 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1300 depth->has_surface = screen->depthHasSurface;
1301 }
1302 } else if (mesaVis->depthBits == 16) {
1303 /* just 16-bit depth buffer, no hw stencil */
1304 struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT16, driDrawPriv);
1305 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1306 depth->has_surface = screen->depthHasSurface;
1307 }
1308
1309 _mesa_add_soft_renderbuffers(&rfb->base,
1310 GL_FALSE, /* color */
1311 swDepth,
1312 swStencil,
1313 swAccum,
1314 swAlpha,
1315 GL_FALSE /* aux */);
1316 driDrawPriv->driverPrivate = (void *) rfb;
1317
1318 return (driDrawPriv->driverPrivate != NULL);
1319 }
1320
1321
1322 static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb)
1323 {
1324 struct radeon_renderbuffer *rb;
1325
1326 rb = rfb->color_rb[0];
1327 if (rb && rb->bo) {
1328 radeon_bo_unref(rb->bo);
1329 rb->bo = NULL;
1330 }
1331 rb = rfb->color_rb[1];
1332 if (rb && rb->bo) {
1333 radeon_bo_unref(rb->bo);
1334 rb->bo = NULL;
1335 }
1336 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
1337 if (rb && rb->bo) {
1338 radeon_bo_unref(rb->bo);
1339 rb->bo = NULL;
1340 }
1341 }
1342
1343 void
1344 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
1345 {
1346 struct radeon_framebuffer *rfb;
1347 if (!driDrawPriv)
1348 return;
1349
1350 rfb = (void*)driDrawPriv->driverPrivate;
1351 if (!rfb)
1352 return;
1353 radeon_cleanup_renderbuffers(rfb);
1354 _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL);
1355 }
1356
1357 /**
1358 * Choose the appropriate CreateContext function based on the chipset.
1359 * Eventually, all drivers will go through this process.
1360 */
1361 static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
1362 __DRIcontextPrivate * driContextPriv,
1363 void *sharedContextPriv)
1364 {
1365 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
1366 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
1367 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1368 if (IS_R300_CLASS(screen))
1369 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
1370 #endif
1371
1372 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1373 if (IS_R200_CLASS(screen))
1374 return r200CreateContext(glVisual, driContextPriv, sharedContextPriv);
1375 #endif
1376
1377 #if !RADEON_COMMON
1378 (void)screen;
1379 return r100CreateContext(glVisual, driContextPriv, sharedContextPriv);
1380 #endif
1381 return GL_FALSE;
1382 }
1383
1384
1385 /**
1386 * This is the driver specific part of the createNewScreen entry point.
1387 *
1388 * \todo maybe fold this into intelInitDriver
1389 *
1390 * \return the __GLcontextModes supported by this driver
1391 */
1392 static const __DRIconfig **
1393 radeonInitScreen(__DRIscreenPrivate *psp)
1394 {
1395 #if !RADEON_COMMON
1396 static const char *driver_name = "Radeon";
1397 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1398 static const __DRIversion dri_expected = { 4, 0, 0 };
1399 static const __DRIversion drm_expected = { 1, 6, 0 };
1400 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1401 static const char *driver_name = "R200";
1402 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1403 static const __DRIversion dri_expected = { 4, 0, 0 };
1404 static const __DRIversion drm_expected = { 1, 6, 0 };
1405 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1406 static const char *driver_name = "R300";
1407 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1408 static const __DRIversion dri_expected = { 4, 0, 0 };
1409 static const __DRIversion drm_expected = { 1, 24, 0 };
1410 #endif
1411 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1412
1413 if ( ! driCheckDriDdxDrmVersions3( driver_name,
1414 &psp->dri_version, & dri_expected,
1415 &psp->ddx_version, & ddx_expected,
1416 &psp->drm_version, & drm_expected ) ) {
1417 return NULL;
1418 }
1419
1420 /* Calling driInitExtensions here, with a NULL context pointer,
1421 * does not actually enable the extensions. It just makes sure
1422 * that all the dispatch offsets for all the extensions that
1423 * *might* be enables are known. This is needed because the
1424 * dispatch offsets need to be known when _mesa_context_create
1425 * is called, but we can't enable the extensions until we have a
1426 * context pointer.
1427 *
1428 * Hello chicken. Hello egg. How are you two today?
1429 */
1430 driInitExtensions( NULL, card_extensions, GL_FALSE );
1431 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1432 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1433 driInitSingleExtension( NULL, ARB_vp_extension );
1434 driInitSingleExtension( NULL, NV_vp_extension );
1435 driInitSingleExtension( NULL, ATI_fs_extension );
1436 driInitExtensions( NULL, point_extensions, GL_FALSE );
1437 #elif defined(RADEON_COMMON_FOR_R300)
1438 driInitSingleExtension( NULL, gl_20_extension );
1439 #endif
1440
1441 if (!radeonInitDriver(psp))
1442 return NULL;
1443
1444 /* for now fill in all modes */
1445 return radeonFillInModes( psp,
1446 dri_priv->bpp,
1447 (dri_priv->bpp == 16) ? 16 : 24,
1448 (dri_priv->bpp == 16) ? 0 : 8, 1);
1449 }
1450 #define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
1451
1452 /**
1453 * This is the driver specific part of the createNewScreen entry point.
1454 * Called when using DRI2.
1455 *
1456 * \return the __GLcontextModes supported by this driver
1457 */
1458 static const
1459 __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp)
1460 {
1461 GLenum fb_format[3];
1462 GLenum fb_type[3];
1463 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
1464 * support pageflipping at all.
1465 */
1466 static const GLenum back_buffer_modes[] = {
1467 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/
1468 };
1469 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
1470 int color;
1471 __DRIconfig **configs = NULL;
1472
1473 /* Calling driInitExtensions here, with a NULL context pointer,
1474 * does not actually enable the extensions. It just makes sure
1475 * that all the dispatch offsets for all the extensions that
1476 * *might* be enables are known. This is needed because the
1477 * dispatch offsets need to be known when _mesa_context_create
1478 * is called, but we can't enable the extensions until we have a
1479 * context pointer.
1480 *
1481 * Hello chicken. Hello egg. How are you two today?
1482 */
1483 driInitExtensions( NULL, card_extensions, GL_FALSE );
1484 driInitExtensions( NULL, mm_extensions, GL_FALSE );
1485 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1486 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1487 driInitSingleExtension( NULL, ARB_vp_extension );
1488 driInitSingleExtension( NULL, NV_vp_extension );
1489 driInitSingleExtension( NULL, ATI_fs_extension );
1490 driInitExtensions( NULL, point_extensions, GL_FALSE );
1491 #endif
1492
1493 if (!radeonInitDriver(psp)) {
1494 return NULL;
1495 }
1496 depth_bits[0] = 0;
1497 stencil_bits[0] = 0;
1498 depth_bits[1] = 16;
1499 stencil_bits[1] = 0;
1500 depth_bits[2] = 24;
1501 stencil_bits[2] = 0;
1502 depth_bits[3] = 24;
1503 stencil_bits[3] = 8;
1504
1505 msaa_samples_array[0] = 0;
1506
1507 fb_format[0] = GL_RGB;
1508 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5;
1509
1510 fb_format[1] = GL_BGR;
1511 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV;
1512
1513 fb_format[2] = GL_BGRA;
1514 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
1515
1516 for (color = 0; color < ARRAY_SIZE(fb_format); color++) {
1517 __DRIconfig **new_configs;
1518
1519 new_configs = driCreateConfigs(fb_format[color], fb_type[color],
1520 depth_bits,
1521 stencil_bits,
1522 ARRAY_SIZE(depth_bits),
1523 back_buffer_modes,
1524 ARRAY_SIZE(back_buffer_modes),
1525 msaa_samples_array,
1526 ARRAY_SIZE(msaa_samples_array));
1527 if (configs == NULL)
1528 configs = new_configs;
1529 else
1530 configs = driConcatConfigs(configs, new_configs);
1531 }
1532
1533 if (configs == NULL) {
1534 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
1535 __LINE__);
1536 return NULL;
1537 }
1538
1539 return (const __DRIconfig **)configs;
1540 }
1541
1542 /**
1543 * Get information about previous buffer swaps.
1544 */
1545 static int
1546 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1547 {
1548 struct radeon_framebuffer *rfb;
1549
1550 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1551 || (dPriv->driContextPriv->driverPrivate == NULL)
1552 || (sInfo == NULL) ) {
1553 return -1;
1554 }
1555
1556 rfb = dPriv->driverPrivate;
1557 sInfo->swap_count = rfb->swap_count;
1558 sInfo->swap_ust = rfb->swap_ust;
1559 sInfo->swap_missed_count = rfb->swap_missed_count;
1560
1561 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1562 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust )
1563 : 0.0;
1564
1565 return 0;
1566 }
1567
1568 const struct __DriverAPIRec driDriverAPI = {
1569 .InitScreen = radeonInitScreen,
1570 .DestroyScreen = radeonDestroyScreen,
1571 .CreateContext = radeonCreateContext,
1572 .DestroyContext = radeonDestroyContext,
1573 .CreateBuffer = radeonCreateBuffer,
1574 .DestroyBuffer = radeonDestroyBuffer,
1575 .SwapBuffers = radeonSwapBuffers,
1576 .MakeCurrent = radeonMakeCurrent,
1577 .UnbindContext = radeonUnbindContext,
1578 .GetSwapInfo = getSwapInfo,
1579 .GetDrawableMSC = driDrawableGetMSC32,
1580 .WaitForMSC = driWaitForMSC32,
1581 .WaitForSBC = NULL,
1582 .SwapBuffersMSC = NULL,
1583 .CopySubBuffer = radeonCopySubBuffer,
1584 /* DRI2 */
1585 .InitScreen2 = radeonInitScreen2,
1586 };
1587