1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
32 * \file radeon_screen.c
33 * Screen initialization functions for the Radeon driver.
35 * \author Kevin E. Martin <martin@valinux.com>
36 * \author Gareth Hughes <gareth@valinux.com>
42 #include "framebuffer.h"
43 #include "renderbuffer.h"
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
50 #include "radeon_context.h"
51 #include "radeon_span.h"
52 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
53 #include "r200_context.h"
54 #include "r200_ioctl.h"
55 #include "r200_span.h"
56 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
57 #include "r300_context.h"
58 #include "radeon_span.h"
64 #include "drirenderbuffer.h"
66 #include "GL/internal/dri_interface.h"
68 /* Radeon configuration
72 #if !RADEON_COMMON /* R100 */
73 PUBLIC
const char __driConfigOptions
[] =
75 DRI_CONF_SECTION_PERFORMANCE
76 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
77 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
78 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
79 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
80 DRI_CONF_HYPERZ(false)
82 DRI_CONF_SECTION_QUALITY
83 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
84 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
85 DRI_CONF_NO_NEG_LOD_BIAS(false)
86 DRI_CONF_FORCE_S3TC_ENABLE(false)
87 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
88 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
89 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
90 DRI_CONF_ALLOW_LARGE_TEXTURES(1)
92 DRI_CONF_SECTION_DEBUG
93 DRI_CONF_NO_RAST(false)
96 static const GLuint __driNConfigOptions
= 14;
98 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
100 PUBLIC
const char __driConfigOptions
[] =
102 DRI_CONF_SECTION_PERFORMANCE
103 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
104 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
105 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
106 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
107 DRI_CONF_HYPERZ(false)
109 DRI_CONF_SECTION_QUALITY
110 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
111 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
112 DRI_CONF_NO_NEG_LOD_BIAS(false)
113 DRI_CONF_FORCE_S3TC_ENABLE(false)
114 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
115 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
116 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
117 DRI_CONF_ALLOW_LARGE_TEXTURES(1)
118 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
120 DRI_CONF_SECTION_DEBUG
121 DRI_CONF_NO_RAST(false)
123 DRI_CONF_SECTION_SOFTWARE
124 DRI_CONF_ARB_VERTEX_PROGRAM(false)
125 DRI_CONF_NV_VERTEX_PROGRAM(false)
128 static const GLuint __driNConfigOptions
= 17;
130 extern const struct dri_extension blend_extensions
[];
131 extern const struct dri_extension ARB_vp_extension
[];
132 extern const struct dri_extension NV_vp_extension
[];
133 extern const struct dri_extension ATI_fs_extension
[];
135 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
137 /* TODO: integrate these into xmlpool.h! */
138 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
139 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
140 DRI_CONF_DESC(en,"Number of texture image units") \
141 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
144 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
145 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
146 DRI_CONF_DESC(en,"Number of texture coordinate units") \
147 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
150 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
151 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
152 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
153 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
156 const char __driConfigOptions
[] =
158 DRI_CONF_SECTION_PERFORMANCE
159 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
160 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
161 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
162 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(16, 2, 16)
163 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
164 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
166 DRI_CONF_SECTION_QUALITY
167 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
168 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
169 DRI_CONF_NO_NEG_LOD_BIAS(false)
170 DRI_CONF_FORCE_S3TC_ENABLE(false)
171 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
172 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
173 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
175 DRI_CONF_SECTION_DEBUG
176 DRI_CONF_NO_RAST(false)
179 static const GLuint __driNConfigOptions
= 14;
182 int RADEON_DEBUG
= 0;
184 static const struct dri_debug_control debug_control
[] = {
185 {"fall", DEBUG_FALLBACKS
},
186 {"tex", DEBUG_TEXTURE
},
187 {"ioctl", DEBUG_IOCTL
},
188 {"prim", DEBUG_PRIMS
},
189 {"vert", DEBUG_VERTS
},
190 {"state", DEBUG_STATE
},
191 {"code", DEBUG_CODEGEN
},
192 {"vfmt", DEBUG_VFMT
},
193 {"vtxf", DEBUG_VFMT
},
194 {"verb", DEBUG_VERBOSE
},
197 {"san", DEBUG_SANITY
},
198 {"sync", DEBUG_SYNC
},
199 {"pix", DEBUG_PIXEL
},
200 {"mem", DEBUG_MEMORY
},
201 {"allmsg", ~DEBUG_SYNC
}, /* avoid the term "sync" because the parser uses strstr */
204 #endif /* RADEON_DEBUG */
206 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
208 extern const struct dri_extension card_extensions
[];
210 static int getSwapInfo( __DRIdrawablePrivate
*dPriv
, __DRIswapInfo
* sInfo
);
212 static __GLcontextModes
*
213 radeonFillInModes( unsigned pixel_bits
, unsigned depth_bits
,
214 unsigned stencil_bits
, GLboolean have_back_buffer
)
216 __GLcontextModes
* modes
;
217 __GLcontextModes
* m
;
219 unsigned depth_buffer_factor
;
220 unsigned back_buffer_factor
;
224 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
225 * enough to add support. Basically, if a context is created with an
226 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
227 * will never be used.
229 static const GLenum back_buffer_modes
[] = {
230 GLX_NONE
, GLX_SWAP_UNDEFINED_OML
/*, GLX_SWAP_COPY_OML */
233 u_int8_t depth_bits_array
[2];
234 u_int8_t stencil_bits_array
[2];
237 depth_bits_array
[0] = depth_bits
;
238 depth_bits_array
[1] = depth_bits
;
240 /* Just like with the accumulation buffer, always provide some modes
241 * with a stencil buffer. It will be a sw fallback, but some apps won't
244 stencil_bits_array
[0] = 0;
245 stencil_bits_array
[1] = (stencil_bits
== 0) ? 8 : stencil_bits
;
247 depth_buffer_factor
= ((depth_bits
!= 0) || (stencil_bits
!= 0)) ? 2 : 1;
248 back_buffer_factor
= (have_back_buffer
) ? 2 : 1;
250 num_modes
= depth_buffer_factor
* back_buffer_factor
* 4;
252 if ( pixel_bits
== 16 ) {
254 fb_type
= GL_UNSIGNED_SHORT_5_6_5
;
258 fb_type
= GL_UNSIGNED_INT_8_8_8_8_REV
;
261 modes
= (*dri_interface
->createContextModes
)( num_modes
, sizeof( __GLcontextModes
) );
263 if ( ! driFillInModes( & m
, fb_format
, fb_type
,
264 depth_bits_array
, stencil_bits_array
, depth_buffer_factor
,
265 back_buffer_modes
, back_buffer_factor
,
267 fprintf( stderr
, "[%s:%u] Error creating FBConfig!\n",
268 __func__
, __LINE__
);
272 if ( ! driFillInModes( & m
, fb_format
, fb_type
,
273 depth_bits_array
, stencil_bits_array
, depth_buffer_factor
,
274 back_buffer_modes
, back_buffer_factor
,
275 GLX_DIRECT_COLOR
) ) {
276 fprintf( stderr
, "[%s:%u] Error creating FBConfig!\n",
277 __func__
, __LINE__
);
281 /* Mark the visual as slow if there are "fake" stencil bits.
283 for ( m
= modes
; m
!= NULL
; m
= m
->next
) {
284 if ( (m
->stencilBits
!= 0) && (m
->stencilBits
!= stencil_bits
) ) {
285 m
->visualRating
= GLX_SLOW_CONFIG
;
293 /* Create the device specific screen private data struct.
295 static radeonScreenPtr
296 radeonCreateScreen( __DRIscreenPrivate
*sPriv
)
298 radeonScreenPtr screen
;
299 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
)sPriv
->pDevPriv
;
300 unsigned char *RADEONMMIO
;
301 PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension
=
302 (PFNGLXSCRENABLEEXTENSIONPROC
) (*dri_interface
->getProcAddress("glxEnableExtension"));
303 void * const psc
= sPriv
->psc
->screenConfigs
;
305 if (sPriv
->devPrivSize
!= sizeof(RADEONDRIRec
)) {
306 fprintf(stderr
,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
310 /* Allocate the private area */
311 screen
= (radeonScreenPtr
) CALLOC( sizeof(*screen
) );
313 __driUtilMessage("%s: Could not allocate memory for screen structure",
318 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
319 RADEON_DEBUG
= driParseDebugString(getenv("RADEON_DEBUG"), debug_control
);
322 /* parse information in __driConfigOptions */
323 driParseOptionInfo (&screen
->optionCache
,
324 __driConfigOptions
, __driNConfigOptions
);
326 /* This is first since which regions we map depends on whether or
327 * not we are using a PCI card.
329 screen
->IsPCI
= dri_priv
->IsPCI
;
333 drm_radeon_getparam_t gp
;
335 gp
.param
= RADEON_PARAM_GART_BUFFER_OFFSET
;
336 gp
.value
= &screen
->gart_buffer_offset
;
338 ret
= drmCommandWriteRead( sPriv
->fd
, DRM_RADEON_GETPARAM
,
342 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret
);
346 if (sPriv
->drmMinor
>= 6) {
347 gp
.param
= RADEON_PARAM_GART_BASE
;
348 gp
.value
= &screen
->gart_base
;
350 ret
= drmCommandWriteRead( sPriv
->fd
, DRM_RADEON_GETPARAM
,
354 fprintf(stderr
, "drmR200GetParam (RADEON_PARAM_GART_BASE): %d\n", ret
);
358 gp
.param
= RADEON_PARAM_IRQ_NR
;
359 gp
.value
= &screen
->irq
;
361 ret
= drmCommandWriteRead( sPriv
->fd
, DRM_RADEON_GETPARAM
,
365 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret
);
368 screen
->drmSupportsCubeMapsR200
= (sPriv
->drmMinor
>= 7);
369 screen
->drmSupportsBlendColor
= (sPriv
->drmMinor
>= 11);
370 screen
->drmSupportsTriPerf
= (sPriv
->drmMinor
>= 16);
371 screen
->drmSupportsFragShader
= (sPriv
->drmMinor
>= 18);
372 screen
->drmSupportsPointSprites
= (sPriv
->drmMinor
>= 13);
373 screen
->drmSupportsCubeMapsR100
= (sPriv
->drmMinor
>= 15);
377 screen
->mmio
.handle
= dri_priv
->registerHandle
;
378 screen
->mmio
.size
= dri_priv
->registerSize
;
379 if ( drmMap( sPriv
->fd
,
382 &screen
->mmio
.map
) ) {
384 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__
);
388 RADEONMMIO
= screen
->mmio
.map
;
390 screen
->status
.handle
= dri_priv
->statusHandle
;
391 screen
->status
.size
= dri_priv
->statusSize
;
392 if ( drmMap( sPriv
->fd
,
393 screen
->status
.handle
,
395 &screen
->status
.map
) ) {
396 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
398 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__
);
401 screen
->scratch
= (__volatile__ u_int32_t
*)
402 ((GLubyte
*)screen
->status
.map
+ RADEON_SCRATCH_REG_OFFSET
);
404 screen
->buffers
= drmMapBufs( sPriv
->fd
);
405 if ( !screen
->buffers
) {
406 drmUnmap( screen
->status
.map
, screen
->status
.size
);
407 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
409 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__
);
413 if ( dri_priv
->gartTexHandle
&& dri_priv
->gartTexMapSize
) {
414 screen
->gartTextures
.handle
= dri_priv
->gartTexHandle
;
415 screen
->gartTextures
.size
= dri_priv
->gartTexMapSize
;
416 if ( drmMap( sPriv
->fd
,
417 screen
->gartTextures
.handle
,
418 screen
->gartTextures
.size
,
419 (drmAddressPtr
)&screen
->gartTextures
.map
) ) {
420 drmUnmapBufs( screen
->buffers
);
421 drmUnmap( screen
->status
.map
, screen
->status
.size
);
422 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
424 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__
);
428 screen
->gart_texture_offset
= dri_priv
->gartTexOffset
+ ( screen
->IsPCI
429 ? INREG( RADEON_AIC_LO_ADDR
)
430 : ( ( INREG( RADEON_MC_AGP_LOCATION
) & 0x0ffffU
) << 16 ) );
433 screen
->chip_flags
= 0;
434 /* XXX: add more chipsets */
435 switch ( dri_priv
->deviceID
) {
436 case PCI_CHIP_RADEON_LY
:
437 case PCI_CHIP_RADEON_LZ
:
438 case PCI_CHIP_RADEON_QY
:
439 case PCI_CHIP_RADEON_QZ
:
440 case PCI_CHIP_RN50_515E
:
441 case PCI_CHIP_RN50_5969
:
442 screen
->chip_family
= CHIP_FAMILY_RV100
;
445 case PCI_CHIP_RS100_4136
:
446 case PCI_CHIP_RS100_4336
:
447 screen
->chip_family
= CHIP_FAMILY_RS100
;
450 case PCI_CHIP_RS200_4137
:
451 case PCI_CHIP_RS200_4337
:
452 case PCI_CHIP_RS250_4237
:
453 case PCI_CHIP_RS250_4437
:
454 screen
->chip_family
= CHIP_FAMILY_RS200
;
457 case PCI_CHIP_RADEON_QD
:
458 case PCI_CHIP_RADEON_QE
:
459 case PCI_CHIP_RADEON_QF
:
460 case PCI_CHIP_RADEON_QG
:
461 /* all original radeons (7200) presumably have a stencil op bug */
462 screen
->chip_family
= CHIP_FAMILY_R100
;
463 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_BROKEN_STENCIL
;
466 case PCI_CHIP_RV200_QW
:
467 case PCI_CHIP_RV200_QX
:
468 case PCI_CHIP_RADEON_LW
:
469 case PCI_CHIP_RADEON_LX
:
470 screen
->chip_family
= CHIP_FAMILY_RV200
;
471 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
474 case PCI_CHIP_R200_BB
:
475 case PCI_CHIP_R200_BC
:
476 case PCI_CHIP_R200_QH
:
477 case PCI_CHIP_R200_QL
:
478 case PCI_CHIP_R200_QM
:
479 screen
->chip_family
= CHIP_FAMILY_R200
;
480 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
483 case PCI_CHIP_RV250_If
:
484 case PCI_CHIP_RV250_Ig
:
485 case PCI_CHIP_RV250_Ld
:
486 case PCI_CHIP_RV250_Lf
:
487 case PCI_CHIP_RV250_Lg
:
488 screen
->chip_family
= CHIP_FAMILY_RV250
;
489 screen
->chip_flags
= R200_CHIPSET_YCBCR_BROKEN
| RADEON_CHIPSET_TCL
;
492 case PCI_CHIP_RV280_5960
:
493 case PCI_CHIP_RV280_5961
:
494 case PCI_CHIP_RV280_5962
:
495 case PCI_CHIP_RV280_5964
:
496 case PCI_CHIP_RV280_5965
:
497 case PCI_CHIP_RV280_5C61
:
498 case PCI_CHIP_RV280_5C63
:
499 screen
->chip_family
= CHIP_FAMILY_RV280
;
500 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
503 case PCI_CHIP_RS300_5834
:
504 case PCI_CHIP_RS300_5835
:
505 case PCI_CHIP_RS350_7834
:
506 case PCI_CHIP_RS350_7835
:
507 screen
->chip_family
= CHIP_FAMILY_RS300
;
510 case PCI_CHIP_R300_AD
:
511 case PCI_CHIP_R300_AE
:
512 case PCI_CHIP_R300_AF
:
513 case PCI_CHIP_R300_AG
:
514 case PCI_CHIP_R300_ND
:
515 case PCI_CHIP_R300_NE
:
516 case PCI_CHIP_R300_NF
:
517 case PCI_CHIP_R300_NG
:
518 screen
->chip_family
= CHIP_FAMILY_R300
;
519 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
522 case PCI_CHIP_RV350_AP
:
523 case PCI_CHIP_RV350_AQ
:
524 case PCI_CHIP_RV350_AR
:
525 case PCI_CHIP_RV350_AS
:
526 case PCI_CHIP_RV350_AT
:
527 case PCI_CHIP_RV350_AV
:
528 case PCI_CHIP_RV350_AU
:
529 case PCI_CHIP_RV350_NP
:
530 case PCI_CHIP_RV350_NQ
:
531 case PCI_CHIP_RV350_NR
:
532 case PCI_CHIP_RV350_NS
:
533 case PCI_CHIP_RV350_NT
:
534 case PCI_CHIP_RV350_NV
:
535 screen
->chip_family
= CHIP_FAMILY_RV350
;
536 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
539 case PCI_CHIP_R350_AH
:
540 case PCI_CHIP_R350_AI
:
541 case PCI_CHIP_R350_AJ
:
542 case PCI_CHIP_R350_AK
:
543 case PCI_CHIP_R350_NH
:
544 case PCI_CHIP_R350_NI
:
545 case PCI_CHIP_R360_NJ
:
546 case PCI_CHIP_R350_NK
:
547 screen
->chip_family
= CHIP_FAMILY_R350
;
548 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
551 case PCI_CHIP_RV370_5460
:
552 case PCI_CHIP_RV370_5462
:
553 case PCI_CHIP_RV370_5464
:
554 case PCI_CHIP_RV370_5B60
:
555 case PCI_CHIP_RV370_5B62
:
556 case PCI_CHIP_RV370_5B63
:
557 case PCI_CHIP_RV370_5B64
:
558 case PCI_CHIP_RV370_5B65
:
559 case PCI_CHIP_RV380_3150
:
560 case PCI_CHIP_RV380_3152
:
561 case PCI_CHIP_RV380_3154
:
562 case PCI_CHIP_RV380_3E50
:
563 case PCI_CHIP_RV380_3E54
:
564 screen
->chip_family
= CHIP_FAMILY_RV380
;
565 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
568 case PCI_CHIP_R420_JN
:
569 case PCI_CHIP_R420_JH
:
570 case PCI_CHIP_R420_JI
:
571 case PCI_CHIP_R420_JJ
:
572 case PCI_CHIP_R420_JK
:
573 case PCI_CHIP_R420_JL
:
574 case PCI_CHIP_R420_JM
:
575 case PCI_CHIP_R420_JO
:
576 case PCI_CHIP_R420_JP
:
577 case PCI_CHIP_R420_JT
:
578 case PCI_CHIP_R481_4B49
:
579 case PCI_CHIP_R481_4B4A
:
580 case PCI_CHIP_R481_4B4B
:
581 case PCI_CHIP_R481_4B4C
:
582 case PCI_CHIP_R423_UH
:
583 case PCI_CHIP_R423_UI
:
584 case PCI_CHIP_R423_UJ
:
585 case PCI_CHIP_R423_UK
:
586 case PCI_CHIP_R430_554C
:
587 case PCI_CHIP_R430_554D
:
588 case PCI_CHIP_R430_554E
:
589 case PCI_CHIP_R430_554F
:
590 case PCI_CHIP_R423_5550
:
591 case PCI_CHIP_R423_UQ
:
592 case PCI_CHIP_R423_UR
:
593 case PCI_CHIP_R423_UT
:
594 case PCI_CHIP_R430_5D48
:
595 case PCI_CHIP_R430_5D49
:
596 case PCI_CHIP_R430_5D4A
:
597 case PCI_CHIP_R480_5D4C
:
598 case PCI_CHIP_R480_5D4D
:
599 case PCI_CHIP_R480_5D4E
:
600 case PCI_CHIP_R480_5D4F
:
601 case PCI_CHIP_R480_5D50
:
602 case PCI_CHIP_R480_5D52
:
603 case PCI_CHIP_R423_5D57
:
604 screen
->chip_family
= CHIP_FAMILY_R420
;
605 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
608 case PCI_CHIP_RV410_564A
:
609 case PCI_CHIP_RV410_564B
:
610 case PCI_CHIP_RV410_564F
:
611 case PCI_CHIP_RV410_5652
:
612 case PCI_CHIP_RV410_5653
:
613 case PCI_CHIP_RV410_5E48
:
614 case PCI_CHIP_RV410_5E4A
:
615 case PCI_CHIP_RV410_5E4B
:
616 case PCI_CHIP_RV410_5E4C
:
617 case PCI_CHIP_RV410_5E4D
:
618 case PCI_CHIP_RV410_5E4F
:
619 screen
->chip_family
= CHIP_FAMILY_RV410
;
620 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
623 case PCI_CHIP_RS480_5954
:
624 case PCI_CHIP_RS480_5955
:
625 case PCI_CHIP_RS482_5974
:
626 case PCI_CHIP_RS482_5975
:
627 case PCI_CHIP_RS400_5A41
:
628 case PCI_CHIP_RS400_5A42
:
629 case PCI_CHIP_RC410_5A61
:
630 case PCI_CHIP_RC410_5A62
:
631 screen
->chip_family
= CHIP_FAMILY_RS400
;
632 fprintf(stderr
, "Warning, xpress200 detected. Probably won't work.\n");
636 fprintf(stderr
, "unknown chip id 0x%x, can't guess.\n",
641 if (screen
->chip_family
<= CHIP_FAMILY_RS200
)
642 screen
->chip_flags
|= RADEON_CLASS_R100
;
643 else if (screen
->chip_family
<= CHIP_FAMILY_RV280
)
644 screen
->chip_flags
|= RADEON_CLASS_R200
;
646 screen
->chip_flags
|= RADEON_CLASS_R300
;
648 screen
->cpp
= dri_priv
->bpp
/ 8;
649 screen
->AGPMode
= dri_priv
->AGPMode
;
651 screen
->fbLocation
= ( INREG( RADEON_MC_FB_LOCATION
) & 0xffff ) << 16;
653 if ( sPriv
->drmMinor
>= 10 ) {
654 drm_radeon_setparam_t sp
;
656 sp
.param
= RADEON_SETPARAM_FB_LOCATION
;
657 sp
.value
= screen
->fbLocation
;
659 drmCommandWrite( sPriv
->fd
, DRM_RADEON_SETPARAM
,
663 screen
->frontOffset
= dri_priv
->frontOffset
;
664 screen
->frontPitch
= dri_priv
->frontPitch
;
665 screen
->backOffset
= dri_priv
->backOffset
;
666 screen
->backPitch
= dri_priv
->backPitch
;
667 screen
->depthOffset
= dri_priv
->depthOffset
;
668 screen
->depthPitch
= dri_priv
->depthPitch
;
670 /* Check if ddx has set up a surface reg to cover depth buffer */
671 screen
->depthHasSurface
= ((sPriv
->ddxMajor
> 4) &&
672 (screen
->chip_flags
& RADEON_CHIPSET_TCL
));
674 if ( dri_priv
->textureSize
== 0 ) {
675 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = screen
->gart_texture_offset
;
676 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
677 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
678 dri_priv
->log2GARTTexGran
;
680 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureOffset
681 + screen
->fbLocation
;
682 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureSize
;
683 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
684 dri_priv
->log2TexGran
;
687 if ( !screen
->gartTextures
.map
|| dri_priv
->textureSize
== 0
688 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
689 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
- 1;
690 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = 0;
691 screen
->texSize
[RADEON_GART_TEX_HEAP
] = 0;
692 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] = 0;
694 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
;
695 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = screen
->gart_texture_offset
;
696 screen
->texSize
[RADEON_GART_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
697 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] =
698 dri_priv
->log2GARTTexGran
;
701 if ( glx_enable_extension
!= NULL
) {
702 if ( screen
->irq
!= 0 ) {
703 (*glx_enable_extension
)( psc
, "GLX_SGI_swap_control" );
704 (*glx_enable_extension
)( psc
, "GLX_SGI_video_sync" );
705 (*glx_enable_extension
)( psc
, "GLX_MESA_swap_control" );
708 (*glx_enable_extension
)( psc
, "GLX_MESA_swap_frame_usage" );
709 if (IS_R200_CLASS(screen
))
710 (*glx_enable_extension
)( psc
, "GLX_MESA_allocate_memory" );
713 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
714 if (IS_R200_CLASS(screen
)) {
715 sPriv
->psc
->allocateMemory
= (void *) r200AllocateMemoryMESA
;
716 sPriv
->psc
->freeMemory
= (void *) r200FreeMemoryMESA
;
717 sPriv
->psc
->memoryOffset
= (void *) r200GetMemoryOffsetMESA
;
721 screen
->driScreen
= sPriv
;
722 screen
->sarea_priv_offset
= dri_priv
->sarea_priv_offset
;
726 /* Destroy the device specific screen private data struct.
729 radeonDestroyScreen( __DRIscreenPrivate
*sPriv
)
731 radeonScreenPtr screen
= (radeonScreenPtr
)sPriv
->private;
736 if ( screen
->gartTextures
.map
) {
737 drmUnmap( screen
->gartTextures
.map
, screen
->gartTextures
.size
);
739 drmUnmapBufs( screen
->buffers
);
740 drmUnmap( screen
->status
.map
, screen
->status
.size
);
741 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
743 /* free all option information */
744 driDestroyOptionInfo (&screen
->optionCache
);
747 sPriv
->private = NULL
;
751 /* Initialize the driver specific screen private data.
754 radeonInitDriver( __DRIscreenPrivate
*sPriv
)
756 sPriv
->private = (void *) radeonCreateScreen( sPriv
);
757 if ( !sPriv
->private ) {
758 radeonDestroyScreen( sPriv
);
767 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
769 * \todo This function (and its interface) will need to be updated to support
773 radeonCreateBuffer( __DRIscreenPrivate
*driScrnPriv
,
774 __DRIdrawablePrivate
*driDrawPriv
,
775 const __GLcontextModes
*mesaVis
,
778 radeonScreenPtr screen
= (radeonScreenPtr
) driScrnPriv
->private;
781 return GL_FALSE
; /* not implemented */
784 const GLboolean swDepth
= GL_FALSE
;
785 const GLboolean swAlpha
= GL_FALSE
;
786 const GLboolean swAccum
= mesaVis
->accumRedBits
> 0;
787 const GLboolean swStencil
= mesaVis
->stencilBits
> 0 &&
788 mesaVis
->depthBits
!= 24;
789 struct gl_framebuffer
*fb
= _mesa_create_framebuffer(mesaVis
);
791 /* front color renderbuffer */
793 driRenderbuffer
*frontRb
794 = driNewRenderbuffer(GL_RGBA
,
795 driScrnPriv
->pFB
+ screen
->frontOffset
,
797 screen
->frontOffset
, screen
->frontPitch
,
799 radeonSetSpanFunctions(frontRb
, mesaVis
);
800 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &frontRb
->Base
);
803 /* back color renderbuffer */
804 if (mesaVis
->doubleBufferMode
) {
805 driRenderbuffer
*backRb
806 = driNewRenderbuffer(GL_RGBA
,
807 driScrnPriv
->pFB
+ screen
->backOffset
,
809 screen
->backOffset
, screen
->backPitch
,
811 radeonSetSpanFunctions(backRb
, mesaVis
);
812 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &backRb
->Base
);
815 /* depth renderbuffer */
816 if (mesaVis
->depthBits
== 16) {
817 driRenderbuffer
*depthRb
818 = driNewRenderbuffer(GL_DEPTH_COMPONENT16
,
819 driScrnPriv
->pFB
+ screen
->depthOffset
,
821 screen
->depthOffset
, screen
->depthPitch
,
823 radeonSetSpanFunctions(depthRb
, mesaVis
);
824 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &depthRb
->Base
);
825 depthRb
->depthHasSurface
= screen
->depthHasSurface
;
827 else if (mesaVis
->depthBits
== 24) {
828 driRenderbuffer
*depthRb
829 = driNewRenderbuffer(GL_DEPTH_COMPONENT24
,
830 driScrnPriv
->pFB
+ screen
->depthOffset
,
832 screen
->depthOffset
, screen
->depthPitch
,
834 radeonSetSpanFunctions(depthRb
, mesaVis
);
835 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &depthRb
->Base
);
836 depthRb
->depthHasSurface
= screen
->depthHasSurface
;
839 /* stencil renderbuffer */
840 if (mesaVis
->stencilBits
> 0 && !swStencil
) {
841 driRenderbuffer
*stencilRb
842 = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT
,
843 driScrnPriv
->pFB
+ screen
->depthOffset
,
845 screen
->depthOffset
, screen
->depthPitch
,
847 radeonSetSpanFunctions(stencilRb
, mesaVis
);
848 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &stencilRb
->Base
);
849 stencilRb
->depthHasSurface
= screen
->depthHasSurface
;
852 _mesa_add_soft_renderbuffers(fb
,
853 GL_FALSE
, /* color */
859 driDrawPriv
->driverPrivate
= (void *) fb
;
861 return (driDrawPriv
->driverPrivate
!= NULL
);
867 radeonDestroyBuffer(__DRIdrawablePrivate
*driDrawPriv
)
869 _mesa_destroy_framebuffer((GLframebuffer
*) (driDrawPriv
->driverPrivate
));
872 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
874 * Choose the appropriate CreateContext function based on the chipset.
875 * Eventually, all drivers will go through this process.
877 static GLboolean
radeonCreateContext(const __GLcontextModes
* glVisual
,
878 __DRIcontextPrivate
* driContextPriv
,
879 void *sharedContextPriv
)
881 __DRIscreenPrivate
*sPriv
= driContextPriv
->driScreenPriv
;
882 radeonScreenPtr screen
= (radeonScreenPtr
) (sPriv
->private);
884 if (IS_R300_CLASS(screen
))
885 return r300CreateContext(glVisual
, driContextPriv
, sharedContextPriv
);
890 * Choose the appropriate DestroyContext function based on the chipset.
892 static void radeonDestroyContext(__DRIcontextPrivate
* driContextPriv
)
894 radeonContextPtr radeon
= (radeonContextPtr
) driContextPriv
->driverPrivate
;
896 if (IS_R300_CLASS(radeon
->radeonScreen
))
897 return r300DestroyContext(driContextPriv
);
903 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
904 static struct __DriverAPIRec radeonAPI
= {
905 .InitDriver
= radeonInitDriver
,
906 .DestroyScreen
= radeonDestroyScreen
,
907 .CreateContext
= radeonCreateContext
,
908 .DestroyContext
= radeonDestroyContext
,
909 .CreateBuffer
= radeonCreateBuffer
,
910 .DestroyBuffer
= radeonDestroyBuffer
,
911 .SwapBuffers
= radeonSwapBuffers
,
912 .MakeCurrent
= radeonMakeCurrent
,
913 .UnbindContext
= radeonUnbindContext
,
914 .GetSwapInfo
= getSwapInfo
,
915 .GetMSC
= driGetMSC32
,
916 .WaitForMSC
= driWaitForMSC32
,
918 .SwapBuffersMSC
= NULL
921 static const struct __DriverAPIRec r200API
= {
922 .InitDriver
= radeonInitDriver
,
923 .DestroyScreen
= radeonDestroyScreen
,
924 .CreateContext
= r200CreateContext
,
925 .DestroyContext
= r200DestroyContext
,
926 .CreateBuffer
= radeonCreateBuffer
,
927 .DestroyBuffer
= radeonDestroyBuffer
,
928 .SwapBuffers
= r200SwapBuffers
,
929 .MakeCurrent
= r200MakeCurrent
,
930 .UnbindContext
= r200UnbindContext
,
931 .GetSwapInfo
= getSwapInfo
,
932 .GetMSC
= driGetMSC32
,
933 .WaitForMSC
= driWaitForMSC32
,
935 .SwapBuffersMSC
= NULL
940 * This is the bootstrap function for the driver. libGL supplies all of the
941 * requisite information about the system, and the driver initializes itself.
942 * This routine also fills in the linked list pointed to by \c driver_modes
943 * with the \c __GLcontextModes that the driver can support for windows or
946 * \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on
950 __driCreateNewScreen_20050727( __DRInativeDisplay
*dpy
,
951 int scrn
, __DRIscreen
*psc
,
952 const __GLcontextModes
* modes
,
953 const __DRIversion
* ddx_version
,
954 const __DRIversion
* dri_version
,
955 const __DRIversion
* drm_version
,
956 const __DRIframebuffer
* frame_buffer
,
957 drmAddress pSAREA
, int fd
,
958 int internal_api_version
,
959 const __DRIinterfaceMethods
* interface
,
960 __GLcontextModes
** driver_modes
)
962 __DRIscreenPrivate
*psp
;
964 static const char *driver_name
= "Radeon";
965 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
966 static const __DRIversion dri_expected
= { 4, 0, 0 };
967 static const __DRIversion drm_expected
= { 1, 3, 0 };
968 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
969 static const char *driver_name
= "R200";
970 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
971 static const __DRIversion dri_expected
= { 4, 0, 0 };
972 static const __DRIversion drm_expected
= { 1, 5, 0 };
973 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
974 static const char *driver_name
= "R300";
975 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
976 static const __DRIversion dri_expected
= { 4, 0, 0 };
977 static const __DRIversion drm_expected
= { 1, 24, 0 };
980 dri_interface
= interface
;
982 if ( ! driCheckDriDdxDrmVersions3( driver_name
,
983 dri_version
, & dri_expected
,
984 ddx_version
, & ddx_expected
,
985 drm_version
, & drm_expected
) ) {
988 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
989 psp
= __driUtilCreateNewScreen(dpy
, scrn
, psc
, NULL
,
990 ddx_version
, dri_version
, drm_version
,
991 frame_buffer
, pSAREA
, fd
,
992 internal_api_version
, &radeonAPI
);
993 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
994 psp
= __driUtilCreateNewScreen(dpy
, scrn
, psc
, NULL
,
995 ddx_version
, dri_version
, drm_version
,
996 frame_buffer
, pSAREA
, fd
,
997 internal_api_version
, &r200API
);
1000 if ( psp
!= NULL
) {
1001 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
) psp
->pDevPriv
;
1003 *driver_modes
= radeonFillInModes( dri_priv
->bpp
,
1004 (dri_priv
->bpp
== 16) ? 16 : 24,
1005 (dri_priv
->bpp
== 16) ? 0 : 8,
1006 (dri_priv
->backOffset
!= dri_priv
->depthOffset
) );
1009 /* Calling driInitExtensions here, with a NULL context pointer,
1010 * does not actually enable the extensions. It just makes sure
1011 * that all the dispatch offsets for all the extensions that
1012 * *might* be enables are known. This is needed because the
1013 * dispatch offsets need to be known when _mesa_context_create
1014 * is called, but we can't enable the extensions until we have a
1017 * Hello chicken. Hello egg. How are you two today?
1019 driInitExtensions( NULL
, card_extensions
, GL_FALSE
);
1020 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1021 driInitExtensions( NULL
, blend_extensions
, GL_FALSE
);
1022 driInitSingleExtension( NULL
, ARB_vp_extension
);
1023 driInitSingleExtension( NULL
, NV_vp_extension
);
1024 driInitSingleExtension( NULL
, ATI_fs_extension
);
1028 return (void *) psp
;
1033 * Get information about previous buffer swaps.
1036 getSwapInfo( __DRIdrawablePrivate
*dPriv
, __DRIswapInfo
* sInfo
)
1038 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1039 radeonContextPtr rmesa
;
1040 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1041 r200ContextPtr rmesa
;
1044 if ( (dPriv
== NULL
) || (dPriv
->driContextPriv
== NULL
)
1045 || (dPriv
->driContextPriv
->driverPrivate
== NULL
)
1046 || (sInfo
== NULL
) ) {
1050 rmesa
= dPriv
->driContextPriv
->driverPrivate
;
1051 sInfo
->swap_count
= rmesa
->swap_count
;
1052 sInfo
->swap_ust
= rmesa
->swap_ust
;
1053 sInfo
->swap_missed_count
= rmesa
->swap_missed_count
;
1055 sInfo
->swap_missed_usage
= (sInfo
->swap_missed_count
!= 0)
1056 ? driCalculateSwapUsage( dPriv
, 0, rmesa
->swap_missed_ust
)