1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_span.c,v 1.6 2002/10/30 12:51:56 alanh Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
33 * Kevin E. Martin <martin@valinux.com>
34 * Gareth Hughes <gareth@valinux.com>
35 * Keith Whitwell <keith@tungstengraphics.com>
40 #include "swrast/swrast.h"
42 #include "radeon_context.h"
43 #include "radeon_ioctl.h"
44 #include "radeon_state.h"
45 #include "radeon_span.h"
46 #include "radeon_tex.h"
48 #include "drirenderbuffer.h"
55 * Eventually, try to remove all references to ctx/rmesa here.
56 * The renderbuffer parameter to the span functions should provide all
57 * the info needed to read/write the pixels.
58 * We'll be a step closer to supporting Pbuffer and framebuffer objects then.
61 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
62 __DRIscreenPrivate *sPriv = rmesa->dri.screen; \
63 __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; \
64 driRenderbuffer *drb = (driRenderbuffer *) rb; \
65 GLuint height = dPriv->h; \
69 #define LOCAL_DEPTH_VARS \
70 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
71 __DRIscreenPrivate *sPriv = rmesa->dri.screen; \
72 __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; \
73 driRenderbuffer *drb = (driRenderbuffer *) rb; \
74 GLuint height = dPriv->h; \
75 GLuint xo = dPriv->x; \
76 GLuint yo = dPriv->y; \
77 char *buf = (char *)(sPriv->pFB + drb->offset);
80 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
82 #define Y_FLIP( _y ) (height - _y - 1)
90 /* ================================================================
94 /* 16 bit, RGB565 color spanline and pixel functions
96 #define SPANTMP_PIXEL_FMT GL_RGB
97 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
99 #define TAG(x) radeon##x##_RGB565
100 #define TAG2(x,y) radeon##x##_RGB565##y
101 #define GET_PTR(X,Y) (sPriv->pFB + drb->flippedOffset \
102 + ((dPriv->y + (Y)) * drb->flippedPitch + (dPriv->x + (X))) * drb->cpp)
103 #include "spantmp2.h"
106 /* 32 bit, ARGB8888 color spanline and pixel functions
108 #define SPANTMP_PIXEL_FMT GL_BGRA
109 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
111 #define TAG(x) radeon##x##_ARGB8888
112 #define TAG2(x,y) radeon##x##_ARGB8888##y
113 #define GET_PTR(X,Y) (sPriv->pFB + drb->flippedOffset \
114 + ((dPriv->y + (Y)) * drb->flippedPitch + (dPriv->x + (X))) * drb->cpp)
115 #include "spantmp2.h"
118 /* ================================================================
122 /* The Radeon family has depth tiling on all the time, so we have to convert
123 * the x,y coordinates into the memory bus address (mba) in the same
124 * manner as the engine. In each case, the linear block address (ba)
125 * is calculated, and then wired with x and y to produce the final
127 * The chip will do address translation on its own if the surface registers
128 * are set up correctly. It is not quite enough to get it working with hyperz
133 radeon_mba_z32( const driRenderbuffer
*drb
, GLint x
, GLint y
)
135 GLuint pitch
= drb
->pitch
;
136 if (drb
->depthHasSurface
) {
137 return 4 * (x
+ y
* pitch
);
140 GLuint ba
, address
= 0; /* a[0..1] = 0 */
142 ba
= (y
/ 16) * (pitch
/ 16) + (x
/ 16);
144 address
|= (x
& 0x7) << 2; /* a[2..4] = x[0..2] */
145 address
|= (y
& 0x3) << 5; /* a[5..6] = y[0..1] */
147 (((x
& 0x10) >> 2) ^ (y
& 0x4)) << 5; /* a[7] = x[4] ^ y[2] */
148 address
|= (ba
& 0x3) << 8; /* a[8..9] = ba[0..1] */
150 address
|= (y
& 0x8) << 7; /* a[10] = y[3] */
152 (((x
& 0x8) << 1) ^ (y
& 0x10)) << 7; /* a[11] = x[3] ^ y[4] */
153 address
|= (ba
& ~0x3) << 10; /* a[12..] = ba[2..] */
161 radeon_mba_z16( const driRenderbuffer
*drb
, GLint x
, GLint y
)
163 GLuint pitch
= drb
->pitch
;
164 if (drb
->depthHasSurface
) {
165 return 2 * (x
+ y
* pitch
);
168 GLuint ba
, address
= 0; /* a[0] = 0 */
170 ba
= (y
/ 16) * (pitch
/ 32) + (x
/ 32);
172 address
|= (x
& 0x7) << 1; /* a[1..3] = x[0..2] */
173 address
|= (y
& 0x7) << 4; /* a[4..6] = y[0..2] */
174 address
|= (x
& 0x8) << 4; /* a[7] = x[3] */
175 address
|= (ba
& 0x3) << 8; /* a[8..9] = ba[0..1] */
176 address
|= (y
& 0x8) << 7; /* a[10] = y[3] */
177 address
|= ((x
& 0x10) ^ (y
& 0x10)) << 7;/* a[11] = x[4] ^ y[4] */
178 address
|= (ba
& ~0x3) << 10; /* a[12..] = ba[2..] */
185 /* 16-bit depth buffer functions
187 #define WRITE_DEPTH( _x, _y, d ) \
188 *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )) = d;
190 #define READ_DEPTH( d, _x, _y ) \
191 d = *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo ));
193 #define TAG(x) radeon##x##_z16
194 #include "depthtmp.h"
197 /* 24 bit depth, 8 bit stencil depthbuffer functions
199 #define WRITE_DEPTH( _x, _y, d ) \
201 GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
202 GLuint tmp = *(GLuint *)(buf + offset); \
204 tmp |= ((d) & 0x00ffffff); \
205 *(GLuint *)(buf + offset) = tmp; \
208 #define READ_DEPTH( d, _x, _y ) \
209 d = *(GLuint *)(buf + radeon_mba_z32( drb, _x + xo, \
210 _y + yo )) & 0x00ffffff;
212 #define TAG(x) radeon##x##_z24_s8
213 #include "depthtmp.h"
216 /* ================================================================
220 /* 24 bit depth, 8 bit stencil depthbuffer functions
222 #define WRITE_STENCIL( _x, _y, d ) \
224 GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
225 GLuint tmp = *(GLuint *)(buf + offset); \
227 tmp |= (((d) & 0xff) << 24); \
228 *(GLuint *)(buf + offset) = tmp; \
231 #define READ_STENCIL( d, _x, _y ) \
233 GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
234 GLuint tmp = *(GLuint *)(buf + offset); \
239 #define TAG(x) radeon##x##_z24_s8
240 #include "stenciltmp.h"
244 /* Move locking out to get reasonable span performance (10x better
245 * than doing this in HW_LOCK above). WaitForIdle() is the main
249 static void radeonSpanRenderStart( GLcontext
*ctx
)
251 radeonContextPtr rmesa
= RADEON_CONTEXT( ctx
);
252 RADEON_FIREVERTICES( rmesa
);
253 LOCK_HARDWARE( rmesa
);
254 radeonWaitForIdleLocked( rmesa
);
257 static void radeonSpanRenderFinish( GLcontext
*ctx
)
259 radeonContextPtr rmesa
= RADEON_CONTEXT( ctx
);
260 _swrast_flush( ctx
);
261 UNLOCK_HARDWARE( rmesa
);
264 void radeonInitSpanFuncs( GLcontext
*ctx
)
266 struct swrast_device_driver
*swdd
= _swrast_GetDeviceDriverReference(ctx
);
267 swdd
->SpanRenderStart
= radeonSpanRenderStart
;
268 swdd
->SpanRenderFinish
= radeonSpanRenderFinish
;
273 * Plug in the Get/Put routines for the given driRenderbuffer.
276 radeonSetSpanFunctions(driRenderbuffer
*drb
, const GLvisual
*vis
)
278 if (drb
->Base
.InternalFormat
== GL_RGBA
) {
279 if (vis
->redBits
== 5 && vis
->greenBits
== 6 && vis
->blueBits
== 5) {
280 radeonInitPointers_RGB565(&drb
->Base
);
283 radeonInitPointers_ARGB8888(&drb
->Base
);
286 else if (drb
->Base
.InternalFormat
== GL_DEPTH_COMPONENT16
) {
287 radeonInitDepthPointers_z16(&drb
->Base
);
289 else if (drb
->Base
.InternalFormat
== GL_DEPTH_COMPONENT24
) {
290 radeonInitDepthPointers_z24_s8(&drb
->Base
);
292 else if (drb
->Base
.InternalFormat
== GL_STENCIL_INDEX8_EXT
) {
293 radeonInitStencilPointers_z24_s8(&drb
->Base
);