1 /**************************************************************************
3 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
7 The Weather Channel (TM) funded Tungsten Graphics to develop the
8 initial release of the Radeon 8500 driver under the XFree86 license.
9 This notice must be preserved.
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
21 The above copyright notice and this permission notice (including the
22 next paragraph) shall be included in all copies or substantial
23 portions of the Software.
25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 **************************************************************************/
37 * Kevin E. Martin <martin@valinux.com>
38 * Gareth Hughes <gareth@valinux.com>
39 * Keith Whitwell <keith@tungstengraphics.com>
43 #include "main/glheader.h"
44 #include "swrast/swrast.h"
46 #include "radeon_common.h"
47 #include "radeon_lock.h"
48 #include "radeon_span.h"
52 static void radeonSetSpanFunctions(struct radeon_renderbuffer
*rrb
);
55 /* r200 depth buffer is always tiled - this is the formula
56 according to the docs unless I typo'ed in it
58 #if defined(RADEON_R200)
59 static GLubyte
*r200_depth_2byte(const struct radeon_renderbuffer
* rrb
,
62 GLubyte
*ptr
= rrb
->bo
->ptr
;
64 if (rrb
->has_surface
) {
65 offset
= x
* rrb
->cpp
+ y
* rrb
->pitch
;
69 b
= (((y
>> 4) * (rrb
->pitch
>> 8) + (x
>> 6)));
70 offset
+= (b
>> 1) << 12;
71 offset
+= (((rrb
->pitch
>> 8) & 0x1) ? (b
& 0x1) : ((b
& 0x1) ^ ((y
>> 4) & 0x1))) << 11;
72 offset
+= ((y
>> 2) & 0x3) << 9;
73 offset
+= ((x
>> 3) & 0x1) << 8;
74 offset
+= ((x
>> 4) & 0x3) << 6;
75 offset
+= ((x
>> 2) & 0x1) << 5;
76 offset
+= ((y
>> 1) & 0x1) << 4;
77 offset
+= ((x
>> 1) & 0x1) << 3;
78 offset
+= (y
& 0x1) << 2;
79 offset
+= (x
& 0x1) << 1;
84 static GLubyte
*r200_depth_4byte(const struct radeon_renderbuffer
* rrb
,
87 GLubyte
*ptr
= rrb
->bo
->ptr
;
89 if (rrb
->has_surface
) {
90 offset
= x
* rrb
->cpp
+ y
* rrb
->pitch
;
94 b
= (((y
& 0x7ff) >> 4) * (rrb
->pitch
>> 7) + (x
>> 5));
95 offset
+= (b
>> 1) << 12;
96 offset
+= (((rrb
->pitch
>> 7) & 0x1) ? (b
& 0x1) : ((b
& 0x1) ^ ((y
>> 4) & 0x1))) << 11;
97 offset
+= ((y
>> 2) & 0x3) << 9;
98 offset
+= ((x
>> 2) & 0x1) << 8;
99 offset
+= ((x
>> 3) & 0x3) << 6;
100 offset
+= ((y
>> 1) & 0x1) << 5;
101 offset
+= ((x
>> 1) & 0x1) << 4;
102 offset
+= (y
& 0x1) << 3;
103 offset
+= (x
& 0x1) << 2;
111 * - 1D (akin to macro-linear/micro-tiled on older asics)
112 * - 2D (akin to macro-tiled/micro-tiled on older asics)
113 * only 1D tiling is implemented below
115 #if defined(RADEON_R600)
116 static inline GLint
r600_1d_tile_helper(const struct radeon_renderbuffer
* rrb
,
117 GLint x
, GLint y
, GLint is_depth
, GLint is_stencil
)
119 GLint element_bytes
= rrb
->cpp
;
120 GLint num_samples
= 1;
121 GLint tile_width
= 8;
122 GLint tile_height
= 8;
123 GLint tile_thickness
= 1;
124 GLint pitch_elements
= rrb
->pitch
/ element_bytes
;
125 GLint height
= rrb
->base
.Height
;
127 GLint sample_number
= 0;
131 GLint tiles_per_slice
;
133 GLint tile_row_index
;
134 GLint tile_column_index
;
136 GLint pixel_number
= 0;
137 GLint element_offset
;
140 tile_bytes
= tile_width
* tile_height
* tile_thickness
* element_bytes
* num_samples
;
141 tiles_per_row
= pitch_elements
/ tile_width
;
142 tiles_per_slice
= tiles_per_row
* (height
/ tile_height
);
143 slice_offset
= (z
/ tile_thickness
) * tiles_per_slice
* tile_bytes
;
144 tile_row_index
= y
/ tile_height
;
145 tile_column_index
= x
/ tile_width
;
146 tile_offset
= ((tile_row_index
* tiles_per_row
) + tile_column_index
) * tile_bytes
;
149 GLint pixel_offset
= 0;
151 pixel_number
|= ((x
>> 0) & 1) << 0; // pn[0] = x[0]
152 pixel_number
|= ((y
>> 0) & 1) << 1; // pn[1] = y[0]
153 pixel_number
|= ((x
>> 1) & 1) << 2; // pn[2] = x[1]
154 pixel_number
|= ((y
>> 1) & 1) << 3; // pn[3] = y[1]
155 pixel_number
|= ((x
>> 2) & 1) << 4; // pn[4] = x[2]
156 pixel_number
|= ((y
>> 2) & 1) << 5; // pn[5] = y[2]
157 switch (element_bytes
) {
159 pixel_offset
= pixel_number
* element_bytes
* num_samples
;
162 /* stencil and depth data are stored separately within a tile.
163 * stencil is stored in a contiguous tile before the depth tile.
164 * stencil element is 1 byte, depth element is 3 bytes.
165 * stencil tile is 64 bytes.
168 pixel_offset
= pixel_number
* 1 * num_samples
;
170 pixel_offset
= (pixel_number
* 3 * num_samples
) + 64;
173 element_offset
= pixel_offset
+ (sample_number
* element_bytes
);
177 switch (element_bytes
) {
179 pixel_number
|= ((x
>> 0) & 1) << 0; // pn[0] = x[0]
180 pixel_number
|= ((x
>> 1) & 1) << 1; // pn[1] = x[1]
181 pixel_number
|= ((x
>> 2) & 1) << 2; // pn[2] = x[2]
182 pixel_number
|= ((y
>> 1) & 1) << 3; // pn[3] = y[1]
183 pixel_number
|= ((y
>> 0) & 1) << 4; // pn[4] = y[0]
184 pixel_number
|= ((y
>> 2) & 1) << 5; // pn[5] = y[2]
187 pixel_number
|= ((x
>> 0) & 1) << 0; // pn[0] = x[0]
188 pixel_number
|= ((x
>> 1) & 1) << 1; // pn[1] = x[1]
189 pixel_number
|= ((x
>> 2) & 1) << 2; // pn[2] = x[2]
190 pixel_number
|= ((y
>> 0) & 1) << 3; // pn[3] = y[0]
191 pixel_number
|= ((y
>> 1) & 1) << 4; // pn[4] = y[1]
192 pixel_number
|= ((y
>> 2) & 1) << 5; // pn[5] = y[2]
195 pixel_number
|= ((x
>> 0) & 1) << 0; // pn[0] = x[0]
196 pixel_number
|= ((x
>> 1) & 1) << 1; // pn[1] = x[1]
197 pixel_number
|= ((y
>> 0) & 1) << 2; // pn[2] = y[0]
198 pixel_number
|= ((x
>> 2) & 1) << 3; // pn[3] = x[2]
199 pixel_number
|= ((y
>> 1) & 1) << 4; // pn[4] = y[1]
200 pixel_number
|= ((y
>> 2) & 1) << 5; // pn[5] = y[2]
203 sample_offset
= sample_number
* (tile_bytes
/ num_samples
);
204 element_offset
= sample_offset
+ (pixel_number
* element_bytes
);
206 offset
= slice_offset
+ tile_offset
+ element_offset
;
211 static GLubyte
*r600_ptr_depth(const struct radeon_renderbuffer
* rrb
,
214 GLubyte
*ptr
= rrb
->bo
->ptr
;
215 GLint offset
= r600_1d_tile_helper(rrb
, x
, y
, 1, 0);
219 static GLubyte
*r600_ptr_stencil(const struct radeon_renderbuffer
* rrb
,
222 GLubyte
*ptr
= rrb
->bo
->ptr
;
223 GLint offset
= r600_1d_tile_helper(rrb
, x
, y
, 1, 1);
227 static GLubyte
*r600_ptr_color(const struct radeon_renderbuffer
* rrb
,
230 GLubyte
*ptr
= rrb
->bo
->ptr
;
231 uint32_t mask
= RADEON_BO_FLAGS_MACRO_TILE
| RADEON_BO_FLAGS_MICRO_TILE
;
234 if (rrb
->has_surface
|| !(rrb
->bo
->flags
& mask
)) {
235 offset
= x
* rrb
->cpp
+ y
* rrb
->pitch
;
237 offset
= r600_1d_tile_helper(rrb
, x
, y
, 0, 0);
244 /* radeon tiling on r300-r500 has 4 states,
245 macro-linear/micro-linear
246 macro-linear/micro-tiled
247 macro-tiled /micro-linear
248 macro-tiled /micro-tiled
250 2 byte surface - two types - we only provide 8x2 microtiling
254 static GLubyte
*radeon_ptr_4byte(const struct radeon_renderbuffer
* rrb
,
257 GLubyte
*ptr
= rrb
->bo
->ptr
;
258 uint32_t mask
= RADEON_BO_FLAGS_MACRO_TILE
| RADEON_BO_FLAGS_MICRO_TILE
;
261 if (rrb
->has_surface
|| !(rrb
->bo
->flags
& mask
)) {
262 offset
= x
* rrb
->cpp
+ y
* rrb
->pitch
;
265 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
) {
266 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MICRO_TILE
) {
267 offset
= ((y
>> 4) * (rrb
->pitch
>> 7) + (x
>> 5)) << 11;
268 offset
+= (((y
>> 3) ^ (x
>> 5)) & 0x1) << 10;
269 offset
+= (((y
>> 4) ^ (x
>> 4)) & 0x1) << 9;
270 offset
+= (((y
>> 2) ^ (x
>> 4)) & 0x1) << 8;
271 offset
+= (((y
>> 3) ^ (x
>> 3)) & 0x1) << 7;
272 offset
+= ((y
>> 1) & 0x1) << 6;
273 offset
+= ((x
>> 2) & 0x1) << 5;
274 offset
+= (y
& 1) << 4;
275 offset
+= (x
& 3) << 2;
277 offset
= ((y
>> 3) * (rrb
->pitch
>> 8) + (x
>> 6)) << 11;
278 offset
+= (((y
>> 2) ^ (x
>> 6)) & 0x1) << 10;
279 offset
+= (((y
>> 3) ^ (x
>> 5)) & 0x1) << 9;
280 offset
+= (((y
>> 1) ^ (x
>> 5)) & 0x1) << 8;
281 offset
+= (((y
>> 2) ^ (x
>> 4)) & 0x1) << 7;
282 offset
+= (y
& 1) << 6;
283 offset
+= (x
& 15) << 2;
286 offset
= ((y
>> 1) * (rrb
->pitch
>> 4) + (x
>> 2)) << 5;
287 offset
+= (y
& 1) << 4;
288 offset
+= (x
& 3) << 2;
294 static GLubyte
*radeon_ptr_2byte_8x2(const struct radeon_renderbuffer
* rrb
,
297 GLubyte
*ptr
= rrb
->bo
->ptr
;
298 uint32_t mask
= RADEON_BO_FLAGS_MACRO_TILE
| RADEON_BO_FLAGS_MICRO_TILE
;
301 if (rrb
->has_surface
|| !(rrb
->bo
->flags
& mask
)) {
302 offset
= x
* rrb
->cpp
+ y
* rrb
->pitch
;
305 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
) {
306 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MICRO_TILE
) {
307 offset
= ((y
>> 4) * (rrb
->pitch
>> 7) + (x
>> 6)) << 11;
308 offset
+= (((y
>> 3) ^ (x
>> 6)) & 0x1) << 10;
309 offset
+= (((y
>> 4) ^ (x
>> 5)) & 0x1) << 9;
310 offset
+= (((y
>> 2) ^ (x
>> 5)) & 0x1) << 8;
311 offset
+= (((y
>> 3) ^ (x
>> 4)) & 0x1) << 7;
312 offset
+= ((y
>> 1) & 0x1) << 6;
313 offset
+= ((x
>> 3) & 0x1) << 5;
314 offset
+= (y
& 1) << 4;
315 offset
+= (x
& 3) << 2;
317 offset
= ((y
>> 3) * (rrb
->pitch
>> 8) + (x
>> 7)) << 11;
318 offset
+= (((y
>> 2) ^ (x
>> 7)) & 0x1) << 10;
319 offset
+= (((y
>> 3) ^ (x
>> 6)) & 0x1) << 9;
320 offset
+= (((y
>> 1) ^ (x
>> 6)) & 0x1) << 8;
321 offset
+= (((y
>> 2) ^ (x
>> 5)) & 0x1) << 7;
322 offset
+= (y
& 1) << 6;
323 offset
+= ((x
>> 4) & 0x1) << 5;
324 offset
+= (x
& 15) << 2;
327 offset
= ((y
>> 1) * (rrb
->pitch
>> 4) + (x
>> 3)) << 5;
328 offset
+= (y
& 0x1) << 4;
329 offset
+= (x
& 0x7) << 1;
340 z24s8_to_s8z24(uint32_t val
)
342 return (val
<< 24) | (val
>> 8);
346 s8z24_to_z24s8(uint32_t val
)
348 return (val
>> 24) | (val
<< 8);
354 * Note that all information needed to access pixels in a renderbuffer
355 * should be obtained through the gl_renderbuffer parameter, not per-context
359 struct radeon_context *radeon = RADEON_CONTEXT(ctx); \
360 struct radeon_renderbuffer *rrb = (void *) rb; \
361 const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1; \
362 const GLint yBias = ctx->DrawBuffer->Name ? 0 : rrb->base.Height - 1;\
363 unsigned int num_cliprects; \
364 struct drm_clip_rect *cliprects; \
368 radeon_get_cliprects(radeon, &cliprects, &num_cliprects, &x_off, &y_off);
370 #define LOCAL_DEPTH_VARS \
371 struct radeon_context *radeon = RADEON_CONTEXT(ctx); \
372 struct radeon_renderbuffer *rrb = (void *) rb; \
373 const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1; \
374 const GLint yBias = ctx->DrawBuffer->Name ? 0 : rrb->base.Height - 1;\
375 unsigned int num_cliprects; \
376 struct drm_clip_rect *cliprects; \
378 radeon_get_cliprects(radeon, &cliprects, &num_cliprects, &x_off, &y_off);
380 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
382 #define Y_FLIP(_y) ((_y) * yScale + yBias)
388 /* XXX FBO: this is identical to the macro in spantmp2.h except we get
389 * the cliprect info from the context, not the driDrawable.
390 * Move this into spantmp2.h someday.
392 #define HW_CLIPLOOP() \
394 int _nc = num_cliprects; \
396 int minx = cliprects[_nc].x1 - x_off; \
397 int miny = cliprects[_nc].y1 - y_off; \
398 int maxx = cliprects[_nc].x2 - x_off; \
399 int maxy = cliprects[_nc].y2 - y_off;
401 /* ================================================================
405 /* 16 bit, RGB565 color spanline and pixel functions
407 #define SPANTMP_PIXEL_FMT GL_RGB
408 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
410 #define TAG(x) radeon##x##_RGB565
411 #define TAG2(x,y) radeon##x##_RGB565##y
412 #if defined(RADEON_R600)
413 #define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
415 #define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
417 #include "spantmp2.h"
419 /* 16 bit, ARGB1555 color spanline and pixel functions
421 #define SPANTMP_PIXEL_FMT GL_BGRA
422 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
424 #define TAG(x) radeon##x##_ARGB1555
425 #define TAG2(x,y) radeon##x##_ARGB1555##y
426 #if defined(RADEON_R600)
427 #define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
429 #define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
431 #include "spantmp2.h"
433 /* 16 bit, RGBA4 color spanline and pixel functions
435 #define SPANTMP_PIXEL_FMT GL_BGRA
436 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
438 #define TAG(x) radeon##x##_ARGB4444
439 #define TAG2(x,y) radeon##x##_ARGB4444##y
440 #if defined(RADEON_R600)
441 #define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
443 #define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
445 #include "spantmp2.h"
447 /* 32 bit, xRGB8888 color spanline and pixel functions
449 #define SPANTMP_PIXEL_FMT GL_BGRA
450 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
452 #define TAG(x) radeon##x##_xRGB8888
453 #define TAG2(x,y) radeon##x##_xRGB8888##y
454 #if defined(RADEON_R600)
455 #define GET_VALUE(_x, _y) ((*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off)) | 0xff000000))
456 #define PUT_VALUE(_x, _y, d) { \
457 GLuint *_ptr = (GLuint*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
461 #define GET_VALUE(_x, _y) ((*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)) | 0xff000000))
462 #define PUT_VALUE(_x, _y, d) { \
463 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \
467 #include "spantmp2.h"
469 /* 32 bit, ARGB8888 color spanline and pixel functions
471 #define SPANTMP_PIXEL_FMT GL_BGRA
472 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
474 #define TAG(x) radeon##x##_ARGB8888
475 #define TAG2(x,y) radeon##x##_ARGB8888##y
476 #if defined(RADEON_R600)
477 #define GET_VALUE(_x, _y) (*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off)))
478 #define PUT_VALUE(_x, _y, d) { \
479 GLuint *_ptr = (GLuint*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
483 #define GET_VALUE(_x, _y) (*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)))
484 #define PUT_VALUE(_x, _y, d) { \
485 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \
489 #include "spantmp2.h"
491 /* ================================================================
495 /* The Radeon family has depth tiling on all the time, so we have to convert
496 * the x,y coordinates into the memory bus address (mba) in the same
497 * manner as the engine. In each case, the linear block address (ba)
498 * is calculated, and then wired with x and y to produce the final
500 * The chip will do address translation on its own if the surface registers
501 * are set up correctly. It is not quite enough to get it working with hyperz
505 /* 16-bit depth buffer functions
507 #define VALUE_TYPE GLushort
509 #if defined(RADEON_R200)
510 #define WRITE_DEPTH( _x, _y, d ) \
511 *(GLushort *)r200_depth_2byte(rrb, _x + x_off, _y + y_off) = d
512 #elif defined(RADEON_R600)
513 #define WRITE_DEPTH( _x, _y, d ) \
514 *(GLushort *)r600_ptr_depth(rrb, _x + x_off, _y + y_off) = d
516 #define WRITE_DEPTH( _x, _y, d ) \
517 *(GLushort *)radeon_ptr_2byte_8x2(rrb, _x + x_off, _y + y_off) = d
520 #if defined(RADEON_R200)
521 #define READ_DEPTH( d, _x, _y ) \
522 d = *(GLushort *)r200_depth_2byte(rrb, _x + x_off, _y + y_off)
523 #elif defined(RADEON_R600)
524 #define READ_DEPTH( d, _x, _y ) \
525 d = *(GLushort *)r600_ptr_depth(rrb, _x + x_off, _y + y_off)
527 #define READ_DEPTH( d, _x, _y ) \
528 d = *(GLushort *)radeon_ptr_2byte_8x2(rrb, _x + x_off, _y + y_off)
531 #define TAG(x) radeon##x##_z16
532 #include "depthtmp.h"
536 * Careful: It looks like the R300 uses ZZZS byte order while the R200
537 * uses SZZZ for 24 bit depth, 8 bit stencil mode.
539 #define VALUE_TYPE GLuint
541 #if defined(RADEON_R300)
542 #define WRITE_DEPTH( _x, _y, d ) \
544 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \
545 GLuint tmp = *_ptr; \
547 tmp |= ((d << 8) & 0xffffff00); \
550 #elif defined(RADEON_R600)
551 #define WRITE_DEPTH( _x, _y, d ) \
553 GLuint *_ptr = (GLuint*)r600_ptr_depth( rrb, _x + x_off, _y + y_off ); \
554 GLuint tmp = *_ptr; \
556 tmp |= ((d) & 0x00ffffff); \
559 #elif defined(RADEON_R200)
560 #define WRITE_DEPTH( _x, _y, d ) \
562 GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x + x_off, _y + y_off ); \
563 GLuint tmp = *_ptr; \
565 tmp |= ((d) & 0x00ffffff); \
569 #define WRITE_DEPTH( _x, _y, d ) \
571 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \
572 GLuint tmp = *_ptr; \
574 tmp |= ((d) & 0x00ffffff); \
579 #if defined(RADEON_R300)
580 #define READ_DEPTH( d, _x, _y ) \
582 d = (*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)) & 0xffffff00) >> 8; \
584 #elif defined(RADEON_R600)
585 #define READ_DEPTH( d, _x, _y ) \
587 d = (*(GLuint*)(r600_ptr_depth(rrb, _x + x_off, _y + y_off)) & 0x00ffffff); \
589 #elif defined(RADEON_R200)
590 #define READ_DEPTH( d, _x, _y ) \
592 d = *(GLuint*)(r200_depth_4byte(rrb, _x + x_off, _y + y_off)) & 0x00ffffff; \
595 #define READ_DEPTH( d, _x, _y ) \
596 d = *(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)) & 0x00ffffff;
599 #define TAG(x) radeon##x##_z24
600 #include "depthtmp.h"
602 /* 24 bit depth, 8 bit stencil depthbuffer functions
605 * Careful: It looks like the R300 uses ZZZS byte order while the R200
606 * uses SZZZ for 24 bit depth, 8 bit stencil mode.
608 #define VALUE_TYPE GLuint
610 #if defined(RADEON_R300)
611 #define WRITE_DEPTH( _x, _y, d ) \
613 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \
616 #elif defined(RADEON_R600)
617 #define WRITE_DEPTH( _x, _y, d ) \
619 GLuint *_ptr = (GLuint*)r600_ptr_depth( rrb, _x + x_off, _y + y_off ); \
620 GLuint tmp = *_ptr; \
622 tmp |= (((d) >> 8) & 0x00ffffff); \
624 _ptr = (GLuint*)r600_ptr_stencil(rrb, _x + x_off, _y + y_off); \
630 #elif defined(RADEON_R200)
631 #define WRITE_DEPTH( _x, _y, d ) \
633 GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x + x_off, _y + y_off ); \
634 GLuint tmp = z24s8_to_s8z24(d); \
638 #define WRITE_DEPTH( _x, _y, d ) \
640 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \
641 GLuint tmp = z24s8_to_s8z24(d); \
646 #if defined(RADEON_R300)
647 #define READ_DEPTH( d, _x, _y ) \
649 d = (*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off))); \
651 #elif defined(RADEON_R600)
652 #define READ_DEPTH( d, _x, _y ) \
654 d = ((*(GLuint*)(r600_ptr_depth(rrb, _x + x_off, _y + y_off))) << 8) & 0xffffff00; \
655 d |= (*(GLuint*)(r600_ptr_stencil(rrb, _x + x_off, _y + y_off))) & 0x000000ff; \
657 #elif defined(RADEON_R200)
658 #define READ_DEPTH( d, _x, _y ) \
660 d = s8z24_to_z24s8(*(GLuint*)(r200_depth_4byte(rrb, _x + x_off, _y + y_off))); \
663 #define READ_DEPTH( d, _x, _y ) do { \
664 d = s8z24_to_z24s8(*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off ))); \
668 #define TAG(x) radeon##x##_z24_s8
669 #include "depthtmp.h"
671 /* ================================================================
675 /* 24 bit depth, 8 bit stencil depthbuffer functions
678 #define WRITE_STENCIL( _x, _y, d ) \
680 GLuint *_ptr = (GLuint*)radeon_ptr_4byte(rrb, _x + x_off, _y + y_off); \
681 GLuint tmp = *_ptr; \
686 #elif defined(RADEON_R600)
687 #define WRITE_STENCIL( _x, _y, d ) \
689 GLuint *_ptr = (GLuint*)r600_ptr_stencil(rrb, _x + x_off, _y + y_off); \
690 GLuint tmp = *_ptr; \
695 #elif defined(RADEON_R200)
696 #define WRITE_STENCIL( _x, _y, d ) \
698 GLuint *_ptr = (GLuint*)r200_depth_4byte(rrb, _x + x_off, _y + y_off); \
699 GLuint tmp = *_ptr; \
701 tmp |= (((d) & 0xff) << 24); \
705 #define WRITE_STENCIL( _x, _y, d ) \
707 GLuint *_ptr = (GLuint*)radeon_ptr_4byte(rrb, _x + x_off, _y + y_off); \
708 GLuint tmp = *_ptr; \
710 tmp |= (((d) & 0xff) << 24); \
716 #define READ_STENCIL( d, _x, _y ) \
718 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \
719 GLuint tmp = *_ptr; \
720 d = tmp & 0x000000ff; \
722 #elif defined(RADEON_R600)
723 #define READ_STENCIL( d, _x, _y ) \
725 GLuint *_ptr = (GLuint*)r600_ptr_stencil( rrb, _x + x_off, _y + y_off ); \
726 GLuint tmp = *_ptr; \
727 d = tmp & 0x000000ff; \
729 #elif defined(RADEON_R200)
730 #define READ_STENCIL( d, _x, _y ) \
732 GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x + x_off, _y + y_off ); \
733 GLuint tmp = *_ptr; \
734 d = (tmp & 0xff000000) >> 24; \
737 #define READ_STENCIL( d, _x, _y ) \
739 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \
740 GLuint tmp = *_ptr; \
741 d = (tmp & 0xff000000) >> 24; \
745 #define TAG(x) radeon##x##_z24_s8
746 #include "stenciltmp.h"
749 static void map_unmap_rb(struct gl_renderbuffer
*rb
, int flag
)
751 struct radeon_renderbuffer
*rrb
= radeon_renderbuffer(rb
);
754 if (rrb
== NULL
|| !rrb
->bo
)
758 if (rrb
->bo
->bom
->funcs
->bo_wait
)
759 radeon_bo_wait(rrb
->bo
);
760 r
= radeon_bo_map(rrb
->bo
, 1);
762 fprintf(stderr
, "(%s) error(%d) mapping buffer.\n",
766 radeonSetSpanFunctions(rrb
);
768 radeon_bo_unmap(rrb
->bo
);
775 radeon_map_unmap_buffers(GLcontext
*ctx
, GLboolean map
)
779 /* color draw buffers */
780 for (j
= 0; j
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; j
++)
781 map_unmap_rb(ctx
->DrawBuffer
->_ColorDrawBuffers
[j
], map
);
783 /* check for render to textures */
784 for (i
= 0; i
< BUFFER_COUNT
; i
++) {
785 struct gl_renderbuffer_attachment
*att
=
786 ctx
->DrawBuffer
->Attachment
+ i
;
787 struct gl_texture_object
*tex
= att
->Texture
;
789 /* Render to texture. Note that a mipmapped texture need not
790 * be complete for render to texture, so we must restrict to
791 * mapping only the attached image.
793 radeon_texture_image
*image
= get_radeon_texture_image(tex
->Image
[att
->CubeMapFace
][att
->TextureLevel
]);
794 ASSERT(att
->Renderbuffer
);
797 radeon_teximage_map(image
, GL_TRUE
);
799 radeon_teximage_unmap(image
);
803 map_unmap_rb(ctx
->ReadBuffer
->_ColorReadBuffer
, map
);
805 /* depth buffer (Note wrapper!) */
806 if (ctx
->DrawBuffer
->_DepthBuffer
)
807 map_unmap_rb(ctx
->DrawBuffer
->_DepthBuffer
->Wrapped
, map
);
809 if (ctx
->DrawBuffer
->_StencilBuffer
)
810 map_unmap_rb(ctx
->DrawBuffer
->_StencilBuffer
->Wrapped
, map
);
813 static void radeonSpanRenderStart(GLcontext
* ctx
)
815 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
818 radeon_firevertices(rmesa
);
820 /* The locking and wait for idle should really only be needed in classic mode.
821 * In a future memory manager based implementation, this should become
822 * unnecessary due to the fact that mapping our buffers, textures, etc.
823 * should implicitly wait for any previous rendering commands that must
825 if (!rmesa
->radeonScreen
->driScreen
->dri2
.enabled
) {
826 LOCK_HARDWARE(rmesa
);
827 radeonWaitForIdleLocked(rmesa
);
830 for (i
= 0; i
< ctx
->Const
.MaxTextureImageUnits
; i
++) {
831 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
)
832 ctx
->Driver
.MapTexture(ctx
, ctx
->Texture
.Unit
[i
]._Current
);
835 radeon_map_unmap_buffers(ctx
, 1);
838 static void radeonSpanRenderFinish(GLcontext
* ctx
)
840 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
843 if (!rmesa
->radeonScreen
->driScreen
->dri2
.enabled
) {
844 UNLOCK_HARDWARE(rmesa
);
846 for (i
= 0; i
< ctx
->Const
.MaxTextureImageUnits
; i
++) {
847 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
)
848 ctx
->Driver
.UnmapTexture(ctx
, ctx
->Texture
.Unit
[i
]._Current
);
851 radeon_map_unmap_buffers(ctx
, 0);
854 void radeonInitSpanFuncs(GLcontext
* ctx
)
856 struct swrast_device_driver
*swdd
=
857 _swrast_GetDeviceDriverReference(ctx
);
858 swdd
->SpanRenderStart
= radeonSpanRenderStart
;
859 swdd
->SpanRenderFinish
= radeonSpanRenderFinish
;
863 * Plug in the Get/Put routines for the given driRenderbuffer.
865 static void radeonSetSpanFunctions(struct radeon_renderbuffer
*rrb
)
867 if (rrb
->base
._ActualFormat
== GL_RGB5
) {
868 radeonInitPointers_RGB565(&rrb
->base
);
869 } else if (rrb
->base
._ActualFormat
== GL_RGB8
) {
870 radeonInitPointers_xRGB8888(&rrb
->base
);
871 } else if (rrb
->base
._ActualFormat
== GL_RGBA8
) {
872 radeonInitPointers_ARGB8888(&rrb
->base
);
873 } else if (rrb
->base
._ActualFormat
== GL_RGBA4
) {
874 radeonInitPointers_ARGB4444(&rrb
->base
);
875 } else if (rrb
->base
._ActualFormat
== GL_RGB5_A1
) {
876 radeonInitPointers_ARGB1555(&rrb
->base
);
877 } else if (rrb
->base
._ActualFormat
== GL_DEPTH_COMPONENT16
) {
878 radeonInitDepthPointers_z16(&rrb
->base
);
879 } else if (rrb
->base
._ActualFormat
== GL_DEPTH_COMPONENT24
) {
880 radeonInitDepthPointers_z24(&rrb
->base
);
881 } else if (rrb
->base
._ActualFormat
== GL_DEPTH24_STENCIL8_EXT
) {
882 radeonInitDepthPointers_z24_s8(&rrb
->base
);
883 } else if (rrb
->base
._ActualFormat
== GL_STENCIL_INDEX8_EXT
) {
884 radeonInitStencilPointers_z24_s8(&rrb
->base
);
886 fprintf(stderr
, "radeonSetSpanFunctions: bad actual format: 0x%04X\n", rrb
->base
._ActualFormat
);