1 /**************************************************************************
3 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
7 The Weather Channel (TM) funded Tungsten Graphics to develop the
8 initial release of the Radeon 8500 driver under the XFree86 license.
9 This notice must be preserved.
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
21 The above copyright notice and this permission notice (including the
22 next paragraph) shall be included in all copies or substantial
23 portions of the Software.
25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 **************************************************************************/
37 * Kevin E. Martin <martin@valinux.com>
38 * Gareth Hughes <gareth@valinux.com>
39 * Keith Whitwell <keith@tungstengraphics.com>
43 #include "main/glheader.h"
44 #include "main/texformat.h"
45 #include "swrast/swrast.h"
47 #include "radeon_common.h"
48 #include "radeon_lock.h"
49 #include "radeon_span.h"
53 static void radeonSetSpanFunctions(struct radeon_renderbuffer
*rrb
);
56 /* r200 depth buffer is always tiled - this is the formula
57 according to the docs unless I typo'ed in it
59 #if defined(RADEON_R200)
60 static GLubyte
*r200_depth_2byte(const struct radeon_renderbuffer
* rrb
,
63 GLubyte
*ptr
= rrb
->bo
->ptr
;
65 if (rrb
->has_surface
) {
66 offset
= x
* rrb
->cpp
+ y
* rrb
->pitch
;
70 b
= (((y
>> 4) * (rrb
->pitch
>> 8) + (x
>> 6)));
71 offset
+= (b
>> 1) << 12;
72 offset
+= (((rrb
->pitch
>> 8) & 0x1) ? (b
& 0x1) : ((b
& 0x1) ^ ((y
>> 4) & 0x1))) << 11;
73 offset
+= ((y
>> 2) & 0x3) << 9;
74 offset
+= ((x
>> 3) & 0x1) << 8;
75 offset
+= ((x
>> 4) & 0x3) << 6;
76 offset
+= ((x
>> 2) & 0x1) << 5;
77 offset
+= ((y
>> 1) & 0x1) << 4;
78 offset
+= ((x
>> 1) & 0x1) << 3;
79 offset
+= (y
& 0x1) << 2;
80 offset
+= (x
& 0x1) << 1;
85 static GLubyte
*r200_depth_4byte(const struct radeon_renderbuffer
* rrb
,
88 GLubyte
*ptr
= rrb
->bo
->ptr
;
90 if (rrb
->has_surface
) {
91 offset
= x
* rrb
->cpp
+ y
* rrb
->pitch
;
95 b
= (((y
& 0x7ff) >> 4) * (rrb
->pitch
>> 7) + (x
>> 5));
96 offset
+= (b
>> 1) << 12;
97 offset
+= (((rrb
->pitch
>> 7) & 0x1) ? (b
& 0x1) : ((b
& 0x1) ^ ((y
>> 4) & 0x1))) << 11;
98 offset
+= ((y
>> 2) & 0x3) << 9;
99 offset
+= ((x
>> 2) & 0x1) << 8;
100 offset
+= ((x
>> 3) & 0x3) << 6;
101 offset
+= ((y
>> 1) & 0x1) << 5;
102 offset
+= ((x
>> 1) & 0x1) << 4;
103 offset
+= (y
& 0x1) << 3;
104 offset
+= (x
& 0x1) << 2;
112 * - 1D (akin to macro-linear/micro-tiled on older asics)
113 * - 2D (akin to macro-tiled/micro-tiled on older asics)
115 #if defined(RADEON_R600)
116 static inline GLint
r600_1d_tile_helper(const struct radeon_renderbuffer
* rrb
,
117 GLint x
, GLint y
, GLint is_depth
, GLint is_stencil
)
119 GLint element_bytes
= rrb
->cpp
;
120 GLint num_samples
= 1;
121 GLint tile_width
= 8;
122 GLint tile_height
= 8;
123 GLint tile_thickness
= 1;
124 GLint pitch_elements
= rrb
->pitch
/ element_bytes
;
125 GLint height
= rrb
->base
.Height
;
127 GLint sample_number
= 0;
131 GLint tiles_per_slice
;
133 GLint tile_row_index
;
134 GLint tile_column_index
;
136 GLint pixel_number
= 0;
137 GLint element_offset
;
140 tile_bytes
= tile_width
* tile_height
* tile_thickness
* element_bytes
* num_samples
;
141 tiles_per_row
= pitch_elements
/ tile_width
;
142 tiles_per_slice
= tiles_per_row
* (height
/ tile_height
);
143 slice_offset
= (z
/ tile_thickness
) * tiles_per_slice
* tile_bytes
;
144 tile_row_index
= y
/ tile_height
;
145 tile_column_index
= x
/ tile_width
;
146 tile_offset
= ((tile_row_index
* tiles_per_row
) + tile_column_index
) * tile_bytes
;
149 GLint pixel_offset
= 0;
151 pixel_number
|= ((x
>> 0) & 1) << 0; // pn[0] = x[0]
152 pixel_number
|= ((y
>> 0) & 1) << 1; // pn[1] = y[0]
153 pixel_number
|= ((x
>> 1) & 1) << 2; // pn[2] = x[1]
154 pixel_number
|= ((y
>> 1) & 1) << 3; // pn[3] = y[1]
155 pixel_number
|= ((x
>> 2) & 1) << 4; // pn[4] = x[2]
156 pixel_number
|= ((y
>> 2) & 1) << 5; // pn[5] = y[2]
157 switch (element_bytes
) {
159 pixel_offset
= pixel_number
* element_bytes
* num_samples
;
162 /* stencil and depth data are stored separately within a tile.
163 * stencil is stored in a contiguous tile before the depth tile.
164 * stencil element is 1 byte, depth element is 3 bytes.
165 * stencil tile is 64 bytes.
168 pixel_offset
= pixel_number
* 1 * num_samples
;
170 pixel_offset
= (pixel_number
* 3 * num_samples
) + 64;
173 element_offset
= pixel_offset
+ (sample_number
* element_bytes
);
177 switch (element_bytes
) {
179 pixel_number
|= ((x
>> 0) & 1) << 0; // pn[0] = x[0]
180 pixel_number
|= ((x
>> 1) & 1) << 1; // pn[1] = x[1]
181 pixel_number
|= ((x
>> 2) & 1) << 2; // pn[2] = x[2]
182 pixel_number
|= ((y
>> 1) & 1) << 3; // pn[3] = y[1]
183 pixel_number
|= ((y
>> 0) & 1) << 4; // pn[4] = y[0]
184 pixel_number
|= ((y
>> 2) & 1) << 5; // pn[5] = y[2]
187 pixel_number
|= ((x
>> 0) & 1) << 0; // pn[0] = x[0]
188 pixel_number
|= ((x
>> 1) & 1) << 1; // pn[1] = x[1]
189 pixel_number
|= ((x
>> 2) & 1) << 2; // pn[2] = x[2]
190 pixel_number
|= ((y
>> 0) & 1) << 3; // pn[3] = y[0]
191 pixel_number
|= ((y
>> 1) & 1) << 4; // pn[4] = y[1]
192 pixel_number
|= ((y
>> 2) & 1) << 5; // pn[5] = y[2]
195 pixel_number
|= ((x
>> 0) & 1) << 0; // pn[0] = x[0]
196 pixel_number
|= ((x
>> 1) & 1) << 1; // pn[1] = x[1]
197 pixel_number
|= ((y
>> 0) & 1) << 2; // pn[2] = y[0]
198 pixel_number
|= ((x
>> 2) & 1) << 3; // pn[3] = x[2]
199 pixel_number
|= ((y
>> 1) & 1) << 4; // pn[4] = y[1]
200 pixel_number
|= ((y
>> 2) & 1) << 5; // pn[5] = y[2]
203 sample_offset
= sample_number
* (tile_bytes
/ num_samples
);
204 element_offset
= sample_offset
+ (pixel_number
* element_bytes
);
206 offset
= slice_offset
+ tile_offset
+ element_offset
;
210 static inline GLint
r600_log2(GLint n
)
219 static inline GLint
r600_2d_tile_helper(const struct radeon_renderbuffer
* rrb
,
220 GLint x
, GLint y
, GLint is_depth
, GLint is_stencil
)
222 GLint group_bytes
= rrb
->group_bytes
;
223 GLint num_channels
= rrb
->num_channels
;
224 GLint num_banks
= rrb
->num_banks
;
225 GLint r7xx_bank_op
= rrb
->r7xx_bank_op
;
227 GLint group_bits
= r600_log2(group_bytes
);
228 GLint channel_bits
= r600_log2(num_channels
);
229 GLint bank_bits
= r600_log2(num_banks
);
230 GLint element_bytes
= rrb
->cpp
;
231 GLint num_samples
= 1;
232 GLint tile_width
= 8;
233 GLint tile_height
= 8;
234 GLint tile_thickness
= 1;
235 GLint macro_tile_width
= num_banks
;
236 GLint macro_tile_height
= num_channels
;
237 GLint pitch_elements
= (rrb
->pitch
/ element_bytes
) / tile_width
;
238 GLint height
= rrb
->base
.Height
/ tile_height
;
240 GLint sample_number
= 0;
243 GLint macro_tile_bytes
;
244 GLint macro_tiles_per_row
;
245 GLint macro_tiles_per_slice
;
247 GLint macro_tile_row_index
;
248 GLint macro_tile_column_index
;
249 GLint macro_tile_offset
;
250 GLint pixel_number
= 0;
251 GLint element_offset
;
255 GLint group_mask
= (1 << group_bits
) - 1;
260 switch (num_channels
) {
263 // channel[0] = x[3] ^ y[3]
264 channel
|= (((x
>> 3) ^ (y
>> 3)) & 1) << 0;
267 // channel[0] = x[4] ^ y[3]
268 channel
|= (((x
>> 4) ^ (y
>> 3)) & 1) << 0;
269 // channel[1] = x[3] ^ y[4]
270 channel
|= (((x
>> 3) ^ (y
>> 4)) & 1) << 1;
273 // channel[0] = x[5] ^ y[3]
274 channel
|= (((x
>> 5) ^ (y
>> 3)) & 1) << 0;
275 // channel[0] = x[4] ^ x[5] ^ y[4]
276 channel
|= (((x
>> 4) ^ (x
>> 5) ^ (y
>> 4)) & 1) << 1;
277 // channel[0] = x[3] ^ y[5]
278 channel
|= (((x
>> 3) ^ (y
>> 5)) & 1) << 2;
284 // bank[0] = x[3] ^ y[4 + log2(num_channels)]
285 bank
|= (((x
>> 3) ^ (y
>> (4 + channel_bits
))) & 1) << 0;
287 // bank[1] = x[3] ^ y[4 + log2(num_channels)] ^ x[5]
288 bank
|= (((x
>> 4) ^ (y
>> (3 + channel_bits
)) ^ (x
>> 5)) & 1) << 1;
290 // bank[1] = x[4] ^ y[3 + log2(num_channels)]
291 bank
|= (((x
>> 4) ^ (y
>> (3 + channel_bits
))) & 1) << 1;
294 // bank[0] = x[3] ^ y[5 + log2(num_channels)]
295 bank
|= (((x
>> 3) ^ (y
>> (5 + channel_bits
))) & 1) << 0;
296 // bank[1] = x[4] ^ y[4 + log2(num_channels)] ^ y[5 + log2(num_channels)]
297 bank
|= (((x
>> 4) ^ (y
>> (4 + channel_bits
)) ^ (y
>> (5 + channel_bits
))) & 1) << 1;
299 // bank[2] = x[5] ^ y[3 + log2(num_channels)] ^ x[6]
300 bank
|= (((x
>> 5) ^ (y
>> (3 + channel_bits
)) ^ (x
>> 6)) & 1) << 2;
302 // bank[2] = x[5] ^ y[3 + log2(num_channels)]
303 bank
|= (((x
>> 5) ^ (y
>> (3 + channel_bits
))) & 1) << 2;
307 tile_bytes
= tile_width
* tile_height
* tile_thickness
* element_bytes
* num_samples
;
308 macro_tile_bytes
= macro_tile_width
* macro_tile_height
* tile_bytes
;
309 macro_tiles_per_row
= pitch_elements
/ macro_tile_width
;
310 macro_tiles_per_slice
= macro_tiles_per_row
* (height
/ macro_tile_height
);
311 slice_offset
= (z
/ tile_thickness
) * macro_tiles_per_slice
* macro_tile_bytes
;
312 macro_tile_row_index
= (y
/ tile_height
) / macro_tile_height
;
313 macro_tile_column_index
= (x
/ tile_width
) / macro_tile_width
;
314 macro_tile_offset
= ((macro_tile_row_index
* macro_tiles_per_row
) + macro_tile_column_index
) * macro_tile_bytes
;
317 GLint pixel_offset
= 0;
319 pixel_number
|= ((x
>> 0) & 1) << 0; // pn[0] = x[0]
320 pixel_number
|= ((y
>> 0) & 1) << 1; // pn[1] = y[0]
321 pixel_number
|= ((x
>> 1) & 1) << 2; // pn[2] = x[1]
322 pixel_number
|= ((y
>> 1) & 1) << 3; // pn[3] = y[1]
323 pixel_number
|= ((x
>> 2) & 1) << 4; // pn[4] = x[2]
324 pixel_number
|= ((y
>> 2) & 1) << 5; // pn[5] = y[2]
325 switch (element_bytes
) {
327 pixel_offset
= pixel_number
* element_bytes
* num_samples
;
330 /* stencil and depth data are stored separately within a tile.
331 * stencil is stored in a contiguous tile before the depth tile.
332 * stencil element is 1 byte, depth element is 3 bytes.
333 * stencil tile is 64 bytes.
336 pixel_offset
= pixel_number
* 1 * num_samples
;
338 pixel_offset
= (pixel_number
* 3 * num_samples
) + 64;
341 element_offset
= pixel_offset
+ (sample_number
* element_bytes
);
345 switch (element_bytes
) {
347 pixel_number
|= ((x
>> 0) & 1) << 0; // pn[0] = x[0]
348 pixel_number
|= ((x
>> 1) & 1) << 1; // pn[1] = x[1]
349 pixel_number
|= ((x
>> 2) & 1) << 2; // pn[2] = x[2]
350 pixel_number
|= ((y
>> 1) & 1) << 3; // pn[3] = y[1]
351 pixel_number
|= ((y
>> 0) & 1) << 4; // pn[4] = y[0]
352 pixel_number
|= ((y
>> 2) & 1) << 5; // pn[5] = y[2]
355 pixel_number
|= ((x
>> 0) & 1) << 0; // pn[0] = x[0]
356 pixel_number
|= ((x
>> 1) & 1) << 1; // pn[1] = x[1]
357 pixel_number
|= ((x
>> 2) & 1) << 2; // pn[2] = x[2]
358 pixel_number
|= ((y
>> 0) & 1) << 3; // pn[3] = y[0]
359 pixel_number
|= ((y
>> 1) & 1) << 4; // pn[4] = y[1]
360 pixel_number
|= ((y
>> 2) & 1) << 5; // pn[5] = y[2]
363 pixel_number
|= ((x
>> 0) & 1) << 0; // pn[0] = x[0]
364 pixel_number
|= ((x
>> 1) & 1) << 1; // pn[1] = x[1]
365 pixel_number
|= ((y
>> 0) & 1) << 2; // pn[2] = y[0]
366 pixel_number
|= ((x
>> 2) & 1) << 3; // pn[3] = x[2]
367 pixel_number
|= ((y
>> 1) & 1) << 4; // pn[4] = y[1]
368 pixel_number
|= ((y
>> 2) & 1) << 5; // pn[5] = y[2]
371 sample_offset
= sample_number
* (tile_bytes
/ num_samples
);
372 element_offset
= sample_offset
+ (pixel_number
* element_bytes
);
374 total_offset
= (slice_offset
+ macro_tile_offset
) >> (channel_bits
+ bank_bits
);
375 total_offset
+= element_offset
;
377 offset_low
= total_offset
& group_mask
;
378 offset_high
= (total_offset
& ~group_mask
) << (channel_bits
+ bank_bits
);
379 offset
= (bank
<< (group_bits
+ channel_bits
)) + (channel
<< group_bits
) + offset_low
+ offset_high
;
385 static GLubyte
*r600_ptr_depth(const struct radeon_renderbuffer
* rrb
,
388 GLubyte
*ptr
= rrb
->bo
->ptr
;
390 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
)
391 offset
= r600_2d_tile_helper(rrb
, x
, y
, 1, 0);
393 offset
= r600_1d_tile_helper(rrb
, x
, y
, 1, 0);
397 static GLubyte
*r600_ptr_stencil(const struct radeon_renderbuffer
* rrb
,
400 GLubyte
*ptr
= rrb
->bo
->ptr
;
402 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
)
403 offset
= r600_2d_tile_helper(rrb
, x
, y
, 1, 1);
405 offset
= r600_1d_tile_helper(rrb
, x
, y
, 1, 1);
409 static GLubyte
*r600_ptr_color(const struct radeon_renderbuffer
* rrb
,
412 GLubyte
*ptr
= rrb
->bo
->ptr
;
413 uint32_t mask
= RADEON_BO_FLAGS_MACRO_TILE
| RADEON_BO_FLAGS_MICRO_TILE
;
416 if (rrb
->has_surface
|| !(rrb
->bo
->flags
& mask
)) {
417 offset
= x
* rrb
->cpp
+ y
* rrb
->pitch
;
419 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
)
420 offset
= r600_2d_tile_helper(rrb
, x
, y
, 0, 0);
422 offset
= r600_1d_tile_helper(rrb
, x
, y
, 0, 0);
429 /* radeon tiling on r300-r500 has 4 states,
430 macro-linear/micro-linear
431 macro-linear/micro-tiled
432 macro-tiled /micro-linear
433 macro-tiled /micro-tiled
435 2 byte surface - two types - we only provide 8x2 microtiling
439 static GLubyte
*radeon_ptr_4byte(const struct radeon_renderbuffer
* rrb
,
442 GLubyte
*ptr
= rrb
->bo
->ptr
;
443 uint32_t mask
= RADEON_BO_FLAGS_MACRO_TILE
| RADEON_BO_FLAGS_MICRO_TILE
;
446 if (rrb
->has_surface
|| !(rrb
->bo
->flags
& mask
)) {
447 offset
= x
* rrb
->cpp
+ y
* rrb
->pitch
;
450 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
) {
451 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MICRO_TILE
) {
452 offset
= ((y
>> 4) * (rrb
->pitch
>> 7) + (x
>> 5)) << 11;
453 offset
+= (((y
>> 3) ^ (x
>> 5)) & 0x1) << 10;
454 offset
+= (((y
>> 4) ^ (x
>> 4)) & 0x1) << 9;
455 offset
+= (((y
>> 2) ^ (x
>> 4)) & 0x1) << 8;
456 offset
+= (((y
>> 3) ^ (x
>> 3)) & 0x1) << 7;
457 offset
+= ((y
>> 1) & 0x1) << 6;
458 offset
+= ((x
>> 2) & 0x1) << 5;
459 offset
+= (y
& 1) << 4;
460 offset
+= (x
& 3) << 2;
462 offset
= ((y
>> 3) * (rrb
->pitch
>> 8) + (x
>> 6)) << 11;
463 offset
+= (((y
>> 2) ^ (x
>> 6)) & 0x1) << 10;
464 offset
+= (((y
>> 3) ^ (x
>> 5)) & 0x1) << 9;
465 offset
+= (((y
>> 1) ^ (x
>> 5)) & 0x1) << 8;
466 offset
+= (((y
>> 2) ^ (x
>> 4)) & 0x1) << 7;
467 offset
+= (y
& 1) << 6;
468 offset
+= (x
& 15) << 2;
471 offset
= ((y
>> 1) * (rrb
->pitch
>> 4) + (x
>> 2)) << 5;
472 offset
+= (y
& 1) << 4;
473 offset
+= (x
& 3) << 2;
479 static GLubyte
*radeon_ptr_2byte_8x2(const struct radeon_renderbuffer
* rrb
,
482 GLubyte
*ptr
= rrb
->bo
->ptr
;
483 uint32_t mask
= RADEON_BO_FLAGS_MACRO_TILE
| RADEON_BO_FLAGS_MICRO_TILE
;
486 if (rrb
->has_surface
|| !(rrb
->bo
->flags
& mask
)) {
487 offset
= x
* rrb
->cpp
+ y
* rrb
->pitch
;
490 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
) {
491 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MICRO_TILE
) {
492 offset
= ((y
>> 4) * (rrb
->pitch
>> 7) + (x
>> 6)) << 11;
493 offset
+= (((y
>> 3) ^ (x
>> 6)) & 0x1) << 10;
494 offset
+= (((y
>> 4) ^ (x
>> 5)) & 0x1) << 9;
495 offset
+= (((y
>> 2) ^ (x
>> 5)) & 0x1) << 8;
496 offset
+= (((y
>> 3) ^ (x
>> 4)) & 0x1) << 7;
497 offset
+= ((y
>> 1) & 0x1) << 6;
498 offset
+= ((x
>> 3) & 0x1) << 5;
499 offset
+= (y
& 1) << 4;
500 offset
+= (x
& 3) << 2;
502 offset
= ((y
>> 3) * (rrb
->pitch
>> 8) + (x
>> 7)) << 11;
503 offset
+= (((y
>> 2) ^ (x
>> 7)) & 0x1) << 10;
504 offset
+= (((y
>> 3) ^ (x
>> 6)) & 0x1) << 9;
505 offset
+= (((y
>> 1) ^ (x
>> 6)) & 0x1) << 8;
506 offset
+= (((y
>> 2) ^ (x
>> 5)) & 0x1) << 7;
507 offset
+= (y
& 1) << 6;
508 offset
+= ((x
>> 4) & 0x1) << 5;
509 offset
+= (x
& 15) << 2;
512 offset
= ((y
>> 1) * (rrb
->pitch
>> 4) + (x
>> 3)) << 5;
513 offset
+= (y
& 0x1) << 4;
514 offset
+= (x
& 0x7) << 1;
523 * Note that all information needed to access pixels in a renderbuffer
524 * should be obtained through the gl_renderbuffer parameter, not per-context
528 struct radeon_context *radeon = RADEON_CONTEXT(ctx); \
529 struct radeon_renderbuffer *rrb = (void *) rb; \
530 const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1; \
531 const GLint yBias = ctx->DrawBuffer->Name ? 0 : rrb->base.Height - 1;\
532 unsigned int num_cliprects; \
533 struct drm_clip_rect *cliprects; \
537 radeon_get_cliprects(radeon, &cliprects, &num_cliprects, &x_off, &y_off);
539 #define LOCAL_DEPTH_VARS \
540 struct radeon_context *radeon = RADEON_CONTEXT(ctx); \
541 struct radeon_renderbuffer *rrb = (void *) rb; \
542 const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1; \
543 const GLint yBias = ctx->DrawBuffer->Name ? 0 : rrb->base.Height - 1;\
544 unsigned int num_cliprects; \
545 struct drm_clip_rect *cliprects; \
547 radeon_get_cliprects(radeon, &cliprects, &num_cliprects, &x_off, &y_off);
549 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
551 #define Y_FLIP(_y) ((_y) * yScale + yBias)
557 /* XXX FBO: this is identical to the macro in spantmp2.h except we get
558 * the cliprect info from the context, not the driDrawable.
559 * Move this into spantmp2.h someday.
561 #define HW_CLIPLOOP() \
563 int _nc = num_cliprects; \
565 int minx = cliprects[_nc].x1 - x_off; \
566 int miny = cliprects[_nc].y1 - y_off; \
567 int maxx = cliprects[_nc].x2 - x_off; \
568 int maxy = cliprects[_nc].y2 - y_off;
570 /* ================================================================
574 /* 16 bit, RGB565 color spanline and pixel functions
576 #define SPANTMP_PIXEL_FMT GL_RGB
577 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
579 #define TAG(x) radeon##x##_RGB565
580 #define TAG2(x,y) radeon##x##_RGB565##y
581 #if defined(RADEON_R600)
582 #define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
584 #define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
586 #include "spantmp2.h"
588 #define SPANTMP_PIXEL_FMT GL_RGB
589 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5_REV
591 #define TAG(x) radeon##x##_RGB565_REV
592 #define TAG2(x,y) radeon##x##_RGB565_REV##y
593 #if defined(RADEON_R600)
594 #define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
596 #define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
598 #include "spantmp2.h"
600 /* 16 bit, ARGB1555 color spanline and pixel functions
602 #define SPANTMP_PIXEL_FMT GL_BGRA
603 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
605 #define TAG(x) radeon##x##_ARGB1555
606 #define TAG2(x,y) radeon##x##_ARGB1555##y
607 #if defined(RADEON_R600)
608 #define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
610 #define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
612 #include "spantmp2.h"
614 #define SPANTMP_PIXEL_FMT GL_BGRA
615 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5
617 #define TAG(x) radeon##x##_ARGB1555_REV
618 #define TAG2(x,y) radeon##x##_ARGB1555_REV##y
619 #if defined(RADEON_R600)
620 #define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
622 #define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
624 #include "spantmp2.h"
626 /* 16 bit, RGBA4 color spanline and pixel functions
628 #define SPANTMP_PIXEL_FMT GL_BGRA
629 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
631 #define TAG(x) radeon##x##_ARGB4444
632 #define TAG2(x,y) radeon##x##_ARGB4444##y
633 #if defined(RADEON_R600)
634 #define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
636 #define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
638 #include "spantmp2.h"
640 #define SPANTMP_PIXEL_FMT GL_BGRA
641 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4
643 #define TAG(x) radeon##x##_ARGB4444_REV
644 #define TAG2(x,y) radeon##x##_ARGB4444_REV##y
645 #if defined(RADEON_R600)
646 #define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
648 #define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
650 #include "spantmp2.h"
652 /* 32 bit, xRGB8888 color spanline and pixel functions
654 #define SPANTMP_PIXEL_FMT GL_BGRA
655 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
657 #define TAG(x) radeon##x##_xRGB8888
658 #define TAG2(x,y) radeon##x##_xRGB8888##y
659 #if defined(RADEON_R600)
660 #define GET_VALUE(_x, _y) ((*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off)) | 0xff000000))
661 #define PUT_VALUE(_x, _y, d) { \
662 GLuint *_ptr = (GLuint*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
666 #define GET_VALUE(_x, _y) ((*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)) | 0xff000000))
667 #define PUT_VALUE(_x, _y, d) { \
668 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \
672 #include "spantmp2.h"
674 /* 32 bit, ARGB8888 color spanline and pixel functions
676 #define SPANTMP_PIXEL_FMT GL_BGRA
677 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
679 #define TAG(x) radeon##x##_ARGB8888
680 #define TAG2(x,y) radeon##x##_ARGB8888##y
681 #if defined(RADEON_R600)
682 #define GET_VALUE(_x, _y) (*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off)))
683 #define PUT_VALUE(_x, _y, d) { \
684 GLuint *_ptr = (GLuint*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
688 #define GET_VALUE(_x, _y) (*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)))
689 #define PUT_VALUE(_x, _y, d) { \
690 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \
694 #include "spantmp2.h"
696 /* 32 bit, BGRx8888 color spanline and pixel functions
698 #define SPANTMP_PIXEL_FMT GL_BGRA
699 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8
701 #define TAG(x) radeon##x##_BGRx8888
702 #define TAG2(x,y) radeon##x##_BGRx8888##y
703 #if defined(RADEON_R600)
704 #define GET_VALUE(_x, _y) ((*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off)) | 0x000000ff))
705 #define PUT_VALUE(_x, _y, d) { \
706 GLuint *_ptr = (GLuint*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
710 #define GET_VALUE(_x, _y) ((*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)) | 0x000000ff))
711 #define PUT_VALUE(_x, _y, d) { \
712 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \
716 #include "spantmp2.h"
718 /* 32 bit, BGRA8888 color spanline and pixel functions
720 #define SPANTMP_PIXEL_FMT GL_BGRA
721 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8
723 #define TAG(x) radeon##x##_BGRA8888
724 #define TAG2(x,y) radeon##x##_BGRA8888##y
725 #if defined(RADEON_R600)
726 #define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
728 #define GET_PTR(X,Y) radeon_ptr_4byte(rrb, (X) + x_off, (Y) + y_off)
730 #include "spantmp2.h"
732 /* ================================================================
736 /* The Radeon family has depth tiling on all the time, so we have to convert
737 * the x,y coordinates into the memory bus address (mba) in the same
738 * manner as the engine. In each case, the linear block address (ba)
739 * is calculated, and then wired with x and y to produce the final
741 * The chip will do address translation on its own if the surface registers
742 * are set up correctly. It is not quite enough to get it working with hyperz
746 /* 16-bit depth buffer functions
748 #define VALUE_TYPE GLushort
750 #if defined(RADEON_R200)
751 #define WRITE_DEPTH( _x, _y, d ) \
752 *(GLushort *)r200_depth_2byte(rrb, _x + x_off, _y + y_off) = d
753 #elif defined(RADEON_R600)
754 #define WRITE_DEPTH( _x, _y, d ) \
755 *(GLushort *)r600_ptr_depth(rrb, _x + x_off, _y + y_off) = d
757 #define WRITE_DEPTH( _x, _y, d ) \
758 *(GLushort *)radeon_ptr_2byte_8x2(rrb, _x + x_off, _y + y_off) = d
761 #if defined(RADEON_R200)
762 #define READ_DEPTH( d, _x, _y ) \
763 d = *(GLushort *)r200_depth_2byte(rrb, _x + x_off, _y + y_off)
764 #elif defined(RADEON_R600)
765 #define READ_DEPTH( d, _x, _y ) \
766 d = *(GLushort *)r600_ptr_depth(rrb, _x + x_off, _y + y_off)
768 #define READ_DEPTH( d, _x, _y ) \
769 d = *(GLushort *)radeon_ptr_2byte_8x2(rrb, _x + x_off, _y + y_off)
772 #define TAG(x) radeon##x##_z16
773 #include "depthtmp.h"
777 * Careful: It looks like the R300 uses ZZZS byte order while the R200
778 * uses SZZZ for 24 bit depth, 8 bit stencil mode.
780 #define VALUE_TYPE GLuint
782 #if defined(RADEON_R300)
783 #define WRITE_DEPTH( _x, _y, d ) \
785 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \
786 GLuint tmp = LE32_TO_CPU(*_ptr); \
788 tmp |= ((d << 8) & 0xffffff00); \
789 *_ptr = CPU_TO_LE32(tmp); \
791 #elif defined(RADEON_R600)
792 #define WRITE_DEPTH( _x, _y, d ) \
794 GLuint *_ptr = (GLuint*)r600_ptr_depth( rrb, _x + x_off, _y + y_off ); \
795 GLuint tmp = *_ptr; \
797 tmp |= ((d) & 0x00ffffff); \
800 #elif defined(RADEON_R200)
801 #define WRITE_DEPTH( _x, _y, d ) \
803 GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x + x_off, _y + y_off ); \
804 GLuint tmp = LE32_TO_CPU(*_ptr); \
806 tmp |= ((d) & 0x00ffffff); \
807 *_ptr = CPU_TO_LE32(tmp); \
810 #define WRITE_DEPTH( _x, _y, d ) \
812 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \
813 GLuint tmp = LE32_TO_CPU(*_ptr); \
815 tmp |= ((d) & 0x00ffffff); \
816 *_ptr = CPU_TO_LE32(tmp); \
820 #if defined(RADEON_R300)
821 #define READ_DEPTH( d, _x, _y ) \
823 d = (LE32_TO_CPU(*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off))) & 0xffffff00) >> 8; \
825 #elif defined(RADEON_R600)
826 #define READ_DEPTH( d, _x, _y ) \
828 d = (*(GLuint*)(r600_ptr_depth(rrb, _x + x_off, _y + y_off)) & 0x00ffffff); \
830 #elif defined(RADEON_R200)
831 #define READ_DEPTH( d, _x, _y ) \
833 d = LE32_TO_CPU(*(GLuint*)(r200_depth_4byte(rrb, _x + x_off, _y + y_off))) & 0x00ffffff; \
836 #define READ_DEPTH( d, _x, _y ) \
837 d = LE32_TO_CPU(*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off))) & 0x00ffffff;
840 #define TAG(x) radeon##x##_z24
841 #include "depthtmp.h"
843 /* 24 bit depth, 8 bit stencil depthbuffer functions
846 * Careful: It looks like the R300 uses ZZZS byte order while the R200
847 * uses SZZZ for 24 bit depth, 8 bit stencil mode.
849 #define VALUE_TYPE GLuint
851 #if defined(RADEON_R300)
852 #define WRITE_DEPTH( _x, _y, d ) \
854 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \
855 *_ptr = CPU_TO_LE32((((d) & 0xff000000) >> 24) | (((d) & 0x00ffffff) << 8)); \
857 #elif defined(RADEON_R600)
858 #define WRITE_DEPTH( _x, _y, d ) \
860 GLuint *_ptr = (GLuint*)r600_ptr_depth( rrb, _x + x_off, _y + y_off ); \
861 GLuint tmp = *_ptr; \
863 tmp |= ((d) & 0x00ffffff); \
865 _ptr = (GLuint*)r600_ptr_stencil(rrb, _x + x_off, _y + y_off); \
868 tmp |= ((d) >> 24) & 0xff; \
871 #elif defined(RADEON_R200)
872 #define WRITE_DEPTH( _x, _y, d ) \
874 GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x + x_off, _y + y_off ); \
875 *_ptr = CPU_TO_LE32(d); \
878 #define WRITE_DEPTH( _x, _y, d ) \
880 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \
881 *_ptr = CPU_TO_LE32(d); \
885 #if defined(RADEON_R300)
886 #define READ_DEPTH( d, _x, _y ) \
888 GLuint tmp = (*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off))); \
889 d = LE32_TO_CPU(((tmp & 0x000000ff) << 24) | ((tmp & 0xffffff00) >> 8)); \
891 #elif defined(RADEON_R600)
892 #define READ_DEPTH( d, _x, _y ) \
894 d = (*(GLuint*)(r600_ptr_depth(rrb, _x + x_off, _y + y_off))) & 0x00ffffff; \
895 d |= ((*(GLuint*)(r600_ptr_stencil(rrb, _x + x_off, _y + y_off))) << 24) & 0xff000000; \
897 #elif defined(RADEON_R200)
898 #define READ_DEPTH( d, _x, _y ) \
900 d = LE32_TO_CPU(*(GLuint*)(r200_depth_4byte(rrb, _x + x_off, _y + y_off))); \
903 #define READ_DEPTH( d, _x, _y ) do { \
904 d = LE32_TO_CPU(*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off))); \
908 #define TAG(x) radeon##x##_s8_z24
909 #include "depthtmp.h"
911 /* ================================================================
915 /* 24 bit depth, 8 bit stencil depthbuffer functions
918 #define WRITE_STENCIL( _x, _y, d ) \
920 GLuint *_ptr = (GLuint*)radeon_ptr_4byte(rrb, _x + x_off, _y + y_off); \
921 GLuint tmp = LE32_TO_CPU(*_ptr); \
924 *_ptr = CPU_TO_LE32(tmp); \
926 #elif defined(RADEON_R600)
927 #define WRITE_STENCIL( _x, _y, d ) \
929 GLuint *_ptr = (GLuint*)r600_ptr_stencil(rrb, _x + x_off, _y + y_off); \
930 GLuint tmp = *_ptr; \
935 #elif defined(RADEON_R200)
936 #define WRITE_STENCIL( _x, _y, d ) \
938 GLuint *_ptr = (GLuint*)r200_depth_4byte(rrb, _x + x_off, _y + y_off); \
939 GLuint tmp = LE32_TO_CPU(*_ptr); \
941 tmp |= (((d) & 0xff) << 24); \
942 *_ptr = CPU_TO_LE32(tmp); \
945 #define WRITE_STENCIL( _x, _y, d ) \
947 GLuint *_ptr = (GLuint*)radeon_ptr_4byte(rrb, _x + x_off, _y + y_off); \
948 GLuint tmp = LE32_TO_CPU(*_ptr); \
950 tmp |= (((d) & 0xff) << 24); \
951 *_ptr = CPU_TO_LE32(tmp); \
956 #define READ_STENCIL( d, _x, _y ) \
958 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \
959 GLuint tmp = LE32_TO_CPU(*_ptr); \
960 d = tmp & 0x000000ff; \
962 #elif defined(RADEON_R600)
963 #define READ_STENCIL( d, _x, _y ) \
965 GLuint *_ptr = (GLuint*)r600_ptr_stencil( rrb, _x + x_off, _y + y_off ); \
966 GLuint tmp = *_ptr; \
967 d = tmp & 0x000000ff; \
969 #elif defined(RADEON_R200)
970 #define READ_STENCIL( d, _x, _y ) \
972 GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x + x_off, _y + y_off ); \
973 GLuint tmp = LE32_TO_CPU(*_ptr); \
974 d = (tmp & 0xff000000) >> 24; \
977 #define READ_STENCIL( d, _x, _y ) \
979 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \
980 GLuint tmp = LE32_TO_CPU(*_ptr); \
981 d = (tmp & 0xff000000) >> 24; \
985 #define TAG(x) radeon##x##_s8_z24
986 #include "stenciltmp.h"
989 static void map_unmap_rb(struct gl_renderbuffer
*rb
, int flag
)
991 struct radeon_renderbuffer
*rrb
= radeon_renderbuffer(rb
);
994 if (rrb
== NULL
|| !rrb
->bo
)
997 radeon_print(RADEON_MEMORY
, RADEON_TRACE
,
998 "%s( rb %p, flag %s )\n",
999 __func__
, rb
, flag
? "true":"false");
1002 radeon_bo_wait(rrb
->bo
);
1003 r
= radeon_bo_map(rrb
->bo
, 1);
1005 fprintf(stderr
, "(%s) error(%d) mapping buffer.\n",
1009 radeonSetSpanFunctions(rrb
);
1011 radeon_bo_unmap(rrb
->bo
);
1018 radeon_map_unmap_framebuffer(struct gl_context
*ctx
, struct gl_framebuffer
*fb
,
1023 radeon_print(RADEON_MEMORY
, RADEON_TRACE
,
1024 "%s( %p , fb %p, map %s )\n",
1025 __func__
, ctx
, fb
, map
? "true":"false");
1027 /* color draw buffers */
1028 for (j
= 0; j
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; j
++)
1029 map_unmap_rb(fb
->_ColorDrawBuffers
[j
], map
);
1031 map_unmap_rb(fb
->_ColorReadBuffer
, map
);
1033 /* check for render to textures */
1034 for (i
= 0; i
< BUFFER_COUNT
; i
++) {
1035 struct gl_renderbuffer_attachment
*att
=
1037 struct gl_texture_object
*tex
= att
->Texture
;
1039 /* Render to texture. Note that a mipmapped texture need not
1040 * be complete for render to texture, so we must restrict to
1041 * mapping only the attached image.
1043 radeon_texture_image
*image
= get_radeon_texture_image(tex
->Image
[att
->CubeMapFace
][att
->TextureLevel
]);
1044 ASSERT(att
->Renderbuffer
);
1047 radeon_teximage_map(image
, GL_TRUE
);
1049 radeon_teximage_unmap(image
);
1053 /* depth buffer (Note wrapper!) */
1054 if (fb
->_DepthBuffer
)
1055 map_unmap_rb(fb
->_DepthBuffer
->Wrapped
, map
);
1057 if (fb
->_StencilBuffer
)
1058 map_unmap_rb(fb
->_StencilBuffer
->Wrapped
, map
);
1060 radeon_check_front_buffer_rendering(ctx
);
1063 static void radeonSpanRenderStart(struct gl_context
* ctx
)
1065 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1068 radeon_firevertices(rmesa
);
1070 /* The locking and wait for idle should really only be needed in classic mode.
1071 * In a future memory manager based implementation, this should become
1072 * unnecessary due to the fact that mapping our buffers, textures, etc.
1073 * should implicitly wait for any previous rendering commands that must
1075 if (!rmesa
->radeonScreen
->driScreen
->dri2
.enabled
) {
1076 LOCK_HARDWARE(rmesa
);
1077 radeonWaitForIdleLocked(rmesa
);
1080 for (i
= 0; i
< ctx
->Const
.MaxTextureImageUnits
; i
++) {
1081 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
)
1082 ctx
->Driver
.MapTexture(ctx
, ctx
->Texture
.Unit
[i
]._Current
);
1085 radeon_map_unmap_framebuffer(ctx
, ctx
->DrawBuffer
, GL_TRUE
);
1086 if (ctx
->ReadBuffer
!= ctx
->DrawBuffer
)
1087 radeon_map_unmap_framebuffer(ctx
, ctx
->ReadBuffer
, GL_TRUE
);
1090 static void radeonSpanRenderFinish(struct gl_context
* ctx
)
1092 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1097 for (i
= 0; i
< ctx
->Const
.MaxTextureImageUnits
; i
++) {
1098 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
)
1099 ctx
->Driver
.UnmapTexture(ctx
, ctx
->Texture
.Unit
[i
]._Current
);
1102 radeon_map_unmap_framebuffer(ctx
, ctx
->DrawBuffer
, GL_FALSE
);
1103 if (ctx
->ReadBuffer
!= ctx
->DrawBuffer
)
1104 radeon_map_unmap_framebuffer(ctx
, ctx
->ReadBuffer
, GL_FALSE
);
1106 if (!rmesa
->radeonScreen
->driScreen
->dri2
.enabled
) {
1107 UNLOCK_HARDWARE(rmesa
);
1111 void radeonInitSpanFuncs(struct gl_context
* ctx
)
1113 struct swrast_device_driver
*swdd
=
1114 _swrast_GetDeviceDriverReference(ctx
);
1115 swdd
->SpanRenderStart
= radeonSpanRenderStart
;
1116 swdd
->SpanRenderFinish
= radeonSpanRenderFinish
;
1120 * Plug in the Get/Put routines for the given driRenderbuffer.
1122 static void radeonSetSpanFunctions(struct radeon_renderbuffer
*rrb
)
1124 if (rrb
->base
.Format
== MESA_FORMAT_RGB565
) {
1125 radeonInitPointers_RGB565(&rrb
->base
);
1126 } else if (rrb
->base
.Format
== MESA_FORMAT_RGB565_REV
) {
1127 radeonInitPointers_RGB565_REV(&rrb
->base
);
1128 } else if (rrb
->base
.Format
== MESA_FORMAT_XRGB8888
) {
1129 radeonInitPointers_xRGB8888(&rrb
->base
);
1130 } else if (rrb
->base
.Format
== MESA_FORMAT_XRGB8888_REV
) {
1131 radeonInitPointers_BGRx8888(&rrb
->base
);
1132 } else if (rrb
->base
.Format
== MESA_FORMAT_ARGB8888
) {
1133 radeonInitPointers_ARGB8888(&rrb
->base
);
1134 } else if (rrb
->base
.Format
== MESA_FORMAT_ARGB8888_REV
) {
1135 radeonInitPointers_BGRA8888(&rrb
->base
);
1136 } else if (rrb
->base
.Format
== MESA_FORMAT_ARGB4444
) {
1137 radeonInitPointers_ARGB4444(&rrb
->base
);
1138 } else if (rrb
->base
.Format
== MESA_FORMAT_ARGB4444_REV
) {
1139 radeonInitPointers_ARGB4444_REV(&rrb
->base
);
1140 } else if (rrb
->base
.Format
== MESA_FORMAT_ARGB1555
) {
1141 radeonInitPointers_ARGB1555(&rrb
->base
);
1142 } else if (rrb
->base
.Format
== MESA_FORMAT_ARGB1555_REV
) {
1143 radeonInitPointers_ARGB1555_REV(&rrb
->base
);
1144 } else if (rrb
->base
.Format
== MESA_FORMAT_Z16
) {
1145 radeonInitDepthPointers_z16(&rrb
->base
);
1146 } else if (rrb
->base
.Format
== MESA_FORMAT_X8_Z24
) {
1147 radeonInitDepthPointers_z24(&rrb
->base
);
1148 } else if (rrb
->base
.Format
== MESA_FORMAT_S8_Z24
) {
1149 radeonInitDepthPointers_s8_z24(&rrb
->base
);
1150 } else if (rrb
->base
.Format
== MESA_FORMAT_S8
) {
1151 radeonInitStencilPointers_s8_z24(&rrb
->base
);
1153 fprintf(stderr
, "radeonSetSpanFunctions: bad format: 0x%04X\n", rrb
->base
.Format
);