r100: fixup radeon so gears seems to work
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_span.c
1 /**************************************************************************
2
3 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
6
7 The Weather Channel (TM) funded Tungsten Graphics to develop the
8 initial release of the Radeon 8500 driver under the XFree86 license.
9 This notice must be preserved.
10
11 All Rights Reserved.
12
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
20
21 The above copyright notice and this permission notice (including the
22 next paragraph) shall be included in all copies or substantial
23 portions of the Software.
24
25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32
33 **************************************************************************/
34
35 /*
36 * Authors:
37 * Kevin E. Martin <martin@valinux.com>
38 * Gareth Hughes <gareth@valinux.com>
39 * Keith Whitwell <keith@tungstengraphics.com>
40 *
41 */
42
43 #include "main/glheader.h"
44 #include "swrast/swrast.h"
45
46 #include "radeon_context.h"
47 #include "radeon_ioctl.h"
48 #include "radeon_state.h"
49 #include "radeon_span.h"
50 #include "radeon_tex.h"
51
52 #include "drirenderbuffer.h"
53
54 #define DBG 0
55
56 /*
57 * Note that all information needed to access pixels in a renderbuffer
58 * should be obtained through the gl_renderbuffer parameter, not per-context
59 * information.
60 */
61 #define LOCAL_VARS \
62 struct radeon_renderbuffer *rrb = (void *) rb; \
63 const __DRIdrawablePrivate *dPriv = rrb->dPriv; \
64 const GLuint bottom = dPriv->h - 1; \
65 GLuint p; \
66 (void) p;
67
68 #define LOCAL_DEPTH_VARS \
69 struct radeon_renderbuffer *rrb = (void *) rb; \
70 const __DRIdrawablePrivate *dPriv = rrb->dPriv; \
71 const GLuint bottom = dPriv->h - 1; \
72 GLuint xo = dPriv->x; \
73 GLuint yo = dPriv->y;
74
75 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
76
77 #define Y_FLIP(Y) (bottom - (Y))
78
79 #define HW_LOCK()
80
81 #define HW_UNLOCK()
82
83 /* ================================================================
84 * Color buffer
85 */
86
87 /* 16 bit, RGB565 color spanline and pixel functions
88 */
89 #define SPANTMP_PIXEL_FMT GL_RGB
90 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
91
92 #define TAG(x) radeon##x##_RGB565
93 #define TAG2(x,y) radeon##x##_RGB565##y
94 #define GET_PTR(X,Y) radeon_ptr16(rrb, (X), (Y))
95 #include "spantmp2.h"
96
97 /* 32 bit, ARGB8888 color spanline and pixel functions
98 */
99 #define SPANTMP_PIXEL_FMT GL_BGRA
100 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
101
102 #define TAG(x) radeon##x##_ARGB8888
103 #define TAG2(x,y) radeon##x##_ARGB8888##y
104 #define GET_PTR(X,Y) radeon_ptr32(rrb, (X), (Y))
105 #include "spantmp2.h"
106
107 /* 16-bit depth buffer functions
108 */
109 #define VALUE_TYPE GLushort
110
111 #define WRITE_DEPTH( _x, _y, d ) \
112 *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo) = d
113
114 #define READ_DEPTH( d, _x, _y ) \
115 d = *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo)
116
117 #define TAG(x) radeon##x##_z16
118 #include "depthtmp.h"
119
120 /* 24 bit depth, 8 bit stencil depthbuffer functions
121 *
122 * Careful: It looks like the R300 uses ZZZS byte order while the R200
123 * uses SZZZ for 24 bit depth, 8 bit stencil mode.
124 */
125 #define VALUE_TYPE GLuint
126
127 #ifdef COMPILE_R300
128 #define WRITE_DEPTH( _x, _y, d ) \
129 do { \
130 GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
131 GLuint tmp = *(GLuint *)(buf + offset); \
132 tmp &= 0x000000ff; \
133 tmp |= ((d << 8) & 0xffffff00); \
134 *(GLuint *)(buf + offset) = tmp; \
135 } while (0)
136 #else
137 #define WRITE_DEPTH( _x, _y, d ) \
138 do { \
139 GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \
140 GLuint tmp = *_ptr; \
141 tmp &= 0xff000000; \
142 tmp |= ((d) & 0x00ffffff); \
143 *_ptr = tmp; \
144 } while (0)
145 #endif
146
147 #ifdef COMPILE_R300
148 #define READ_DEPTH( d, _x, _y ) \
149 do { \
150 d = (*(GLuint *)(buf + radeon_mba_z32( drb, _x + xo, \
151 _y + yo )) & 0xffffff00) >> 8; \
152 }while(0)
153 #else
154 #define READ_DEPTH( d, _x, _y ) \
155 do { \
156 d = (*(GLuint*)(radeon_ptr32(rrb, _x + xo, _y + yo)) & 0x00ffffff); \
157 } while (0)
158 #endif
159
160 #define TAG(x) radeon##x##_z24_s8
161 #include "depthtmp.h"
162
163 /* ================================================================
164 * Stencil buffer
165 */
166
167 /* 24 bit depth, 8 bit stencil depthbuffer functions
168 */
169 #ifdef COMPILE_R300
170 #define WRITE_STENCIL( _x, _y, d ) \
171 do { \
172 GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
173 GLuint tmp = *(GLuint *)(buf + offset); \
174 tmp &= 0xffffff00; \
175 tmp |= (d) & 0xff; \
176 *(GLuint *)(buf + offset) = tmp; \
177 } while (0)
178 #else
179 #define WRITE_STENCIL( _x, _y, d ) \
180 do { \
181 GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \
182 GLuint tmp = *_ptr; \
183 tmp &= 0x00ffffff; \
184 tmp |= (((d) & 0xff) << 24); \
185 *_ptr = tmp; \
186 } while (0)
187 #endif
188
189 #ifdef COMPILE_R300
190 #define READ_STENCIL( d, _x, _y ) \
191 do { \
192 GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
193 GLuint tmp = *(GLuint *)(buf + offset); \
194 d = tmp & 0x000000ff; \
195 } while (0)
196 #else
197 #define READ_STENCIL( d, _x, _y ) \
198 do { \
199 GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \
200 GLuint tmp = *_ptr; \
201 d = (tmp & 0xff000000) >> 24; \
202 } while (0)
203 #endif
204
205 #define TAG(x) radeon##x##_z24_s8
206 #include "stenciltmp.h"
207
208 void radeonInitSpanFuncs(GLcontext * ctx)
209 {
210 struct swrast_device_driver *swdd =
211 _swrast_GetDeviceDriverReference(ctx);
212 swdd->SpanRenderStart = radeonSpanRenderStart;
213 swdd->SpanRenderFinish = radeonSpanRenderFinish;
214 }
215
216 /**
217 * Plug in the Get/Put routines for the given driRenderbuffer.
218 */
219 void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb)
220 {
221 if (rrb->base.InternalFormat == GL_RGB5) {
222 radeonInitPointers_RGB565(&rrb->base);
223 } else if (rrb->base.InternalFormat == GL_RGBA8) {
224 radeonInitPointers_ARGB8888(&rrb->base);
225 } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT16) {
226 radeonInitDepthPointers_z16(&rrb->base);
227 } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT24) {
228 radeonInitDepthPointers_z24_s8(&rrb->base);
229 } else if (rrb->base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
230 radeonInitStencilPointers_z24_s8(&rrb->base);
231 }
232 }