1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_span.c,v 1.6 2002/10/30 12:51:56 alanh Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
33 * Kevin E. Martin <martin@valinux.com>
34 * Gareth Hughes <gareth@valinux.com>
35 * Keith Whitwell <keith@tungstengraphics.com>
40 #include "swrast/swrast.h"
42 #include "radeon_context.h"
43 #include "radeon_ioctl.h"
44 #include "radeon_state.h"
45 #include "radeon_span.h"
46 #include "radeon_tex.h"
51 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
52 radeonScreenPtr radeonScreen = rmesa->radeonScreen; \
53 __DRIscreenPrivate *sPriv = rmesa->dri.screen; \
54 __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; \
55 GLuint pitch = radeonScreen->frontPitch * radeonScreen->cpp; \
56 GLuint height = dPriv->h; \
57 char *buf = (char *)(sPriv->pFB + \
58 rmesa->state.color.drawOffset + \
59 (dPriv->x * radeonScreen->cpp) + \
60 (dPriv->y * pitch)); \
61 char *read_buf = (char *)(sPriv->pFB + \
62 rmesa->state.pixel.readOffset + \
63 (dPriv->x * radeonScreen->cpp) + \
64 (dPriv->y * pitch)); \
66 (void) read_buf; (void) buf; (void) p
68 #define LOCAL_DEPTH_VARS \
69 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
70 radeonScreenPtr radeonScreen = rmesa->radeonScreen; \
71 __DRIscreenPrivate *sPriv = rmesa->dri.screen; \
72 __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; \
73 GLuint height = dPriv->h; \
74 GLuint xo = dPriv->x; \
75 GLuint yo = dPriv->y; \
76 char *buf = (char *)(sPriv->pFB + radeonScreen->depthOffset); \
79 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
82 #define CLIPPIXEL( _x, _y ) \
83 ((_x >= minx) && (_x < maxx) && (_y >= miny) && (_y < maxy))
86 #define CLIPSPAN( _x, _y, _n, _x1, _n1, _i ) \
87 if ( _y < miny || _y >= maxy ) { \
92 if ( _x1 < minx ) _i += (minx-_x1), n1 -= (minx-_x1), _x1 = minx; \
93 if ( _x1 + _n1 >= maxx ) n1 -= (_x1 + n1 - maxx); \
96 #define Y_FLIP( _y ) (height - _y - 1)
101 #define HW_CLIPLOOP() \
103 __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; \
104 int _nc = dPriv->numClipRects; \
107 int minx = dPriv->pClipRects[_nc].x1 - dPriv->x; \
108 int miny = dPriv->pClipRects[_nc].y1 - dPriv->y; \
109 int maxx = dPriv->pClipRects[_nc].x2 - dPriv->x; \
110 int maxy = dPriv->pClipRects[_nc].y2 - dPriv->y;
112 #define HW_ENDCLIPLOOP() \
120 /* ================================================================
124 /* 16 bit, RGB565 color spanline and pixel functions
126 #define INIT_MONO_PIXEL(p, color) \
127 p = PACK_COLOR_565( color[0], color[1], color[2] )
129 #define WRITE_RGBA( _x, _y, r, g, b, a ) \
130 *(GLushort *)(buf + _x*2 + _y*pitch) = ((((int)r & 0xf8) << 8) | \
131 (((int)g & 0xfc) << 3) | \
132 (((int)b & 0xf8) >> 3))
134 #define WRITE_PIXEL( _x, _y, p ) \
135 *(GLushort *)(buf + _x*2 + _y*pitch) = p
137 #define READ_RGBA( rgba, _x, _y ) \
139 GLushort p = *(GLushort *)(read_buf + _x*2 + _y*pitch); \
140 rgba[0] = ((p >> 8) & 0xf8) * 255 / 0xf8; \
141 rgba[1] = ((p >> 3) & 0xfc) * 255 / 0xfc; \
142 rgba[2] = ((p << 3) & 0xf8) * 255 / 0xf8; \
146 #define TAG(x) radeon##x##_RGB565
149 /* 32 bit, ARGB8888 color spanline and pixel functions
151 #undef INIT_MONO_PIXEL
152 #define INIT_MONO_PIXEL(p, color) \
153 p = PACK_COLOR_8888( color[3], color[0], color[1], color[2] )
155 #define WRITE_RGBA( _x, _y, r, g, b, a ) \
157 *(GLuint *)(buf + _x*4 + _y*pitch) = ((b << 0) | \
163 #define WRITE_PIXEL( _x, _y, p ) \
165 *(GLuint *)(buf + _x*4 + _y*pitch) = p; \
168 #define READ_RGBA( rgba, _x, _y ) \
170 volatile GLuint *ptr = (volatile GLuint *)(read_buf + _x*4 + _y*pitch); \
172 rgba[0] = (p >> 16) & 0xff; \
173 rgba[1] = (p >> 8) & 0xff; \
174 rgba[2] = (p >> 0) & 0xff; \
175 rgba[3] = (p >> 24) & 0xff; \
178 #define TAG(x) radeon##x##_ARGB8888
183 /* ================================================================
187 /* The Radeon family has depth tiling on all the time, so we have to convert
188 * the x,y coordinates into the memory bus address (mba) in the same
189 * manner as the engine. In each case, the linear block address (ba)
190 * is calculated, and then wired with x and y to produce the final
192 * The chip will do address translation on its own if the surface registers
193 * are set up correctly. It is not quite enough to get it working with hyperz too...
196 static GLuint
radeon_mba_z32( radeonContextPtr rmesa
,
199 GLuint pitch
= rmesa
->radeonScreen
->frontPitch
;
200 if (rmesa
->radeonScreen
->depthHasSurface
) {
201 return 4*(x
+ y
*pitch
);
204 GLuint ba
, address
= 0; /* a[0..1] = 0 */
206 ba
= (y
/ 16) * (pitch
/ 16) + (x
/ 16);
208 address
|= (x
& 0x7) << 2; /* a[2..4] = x[0..2] */
209 address
|= (y
& 0x3) << 5; /* a[5..6] = y[0..1] */
211 (((x
& 0x10) >> 2) ^ (y
& 0x4)) << 5; /* a[7] = x[4] ^ y[2] */
212 address
|= (ba
& 0x3) << 8; /* a[8..9] = ba[0..1] */
214 address
|= (y
& 0x8) << 7; /* a[10] = y[3] */
216 (((x
& 0x8) << 1) ^ (y
& 0x10)) << 7; /* a[11] = x[3] ^ y[4] */
217 address
|= (ba
& ~0x3) << 10; /* a[12..] = ba[2..] */
223 static __inline GLuint
radeon_mba_z16( radeonContextPtr rmesa
, GLint x
, GLint y
)
225 GLuint pitch
= rmesa
->radeonScreen
->frontPitch
;
226 if (rmesa
->radeonScreen
->depthHasSurface
) {
227 return 2*(x
+ y
*pitch
);
230 GLuint ba
, address
= 0; /* a[0] = 0 */
232 ba
= (y
/ 16) * (pitch
/ 32) + (x
/ 32);
234 address
|= (x
& 0x7) << 1; /* a[1..3] = x[0..2] */
235 address
|= (y
& 0x7) << 4; /* a[4..6] = y[0..2] */
236 address
|= (x
& 0x8) << 4; /* a[7] = x[3] */
237 address
|= (ba
& 0x3) << 8; /* a[8..9] = ba[0..1] */
238 address
|= (y
& 0x8) << 7; /* a[10] = y[3] */
239 address
|= ((x
& 0x10) ^ (y
& 0x10)) << 7; /* a[11] = x[4] ^ y[4] */
240 address
|= (ba
& ~0x3) << 10; /* a[12..] = ba[2..] */
247 /* 16-bit depth buffer functions
249 #define WRITE_DEPTH( _x, _y, d ) \
250 *(GLushort *)(buf + radeon_mba_z16( rmesa, _x + xo, _y + yo )) = d;
252 #define READ_DEPTH( d, _x, _y ) \
253 d = *(GLushort *)(buf + radeon_mba_z16( rmesa, _x + xo, _y + yo ));
255 #define TAG(x) radeon##x##_16
256 #include "depthtmp.h"
258 /* 24 bit depth, 8 bit stencil depthbuffer functions
260 #define WRITE_DEPTH( _x, _y, d ) \
262 GLuint offset = radeon_mba_z32( rmesa, _x + xo, _y + yo ); \
263 GLuint tmp = *(GLuint *)(buf + offset); \
265 tmp |= ((d) & 0x00ffffff); \
266 *(GLuint *)(buf + offset) = tmp; \
269 #define READ_DEPTH( d, _x, _y ) \
270 d = *(GLuint *)(buf + radeon_mba_z32( rmesa, _x + xo, \
271 _y + yo )) & 0x00ffffff;
273 #define TAG(x) radeon##x##_24_8
274 #include "depthtmp.h"
277 /* ================================================================
281 /* 24 bit depth, 8 bit stencil depthbuffer functions
283 #define WRITE_STENCIL( _x, _y, d ) \
285 GLuint offset = radeon_mba_z32( rmesa, _x + xo, _y + yo ); \
286 GLuint tmp = *(GLuint *)(buf + offset); \
288 tmp |= (((d) & 0xff) << 24); \
289 *(GLuint *)(buf + offset) = tmp; \
292 #define READ_STENCIL( d, _x, _y ) \
294 GLuint offset = radeon_mba_z32( rmesa, _x + xo, _y + yo ); \
295 GLuint tmp = *(GLuint *)(buf + offset); \
300 #define TAG(x) radeon##x##_24_8
301 #include "stenciltmp.h"
305 * This function is called to specify which buffer to read and write
306 * for software rasterization (swrast) fallbacks. This doesn't necessarily
307 * correspond to glDrawBuffer() or glReadBuffer() calls.
309 static void radeonSetBuffer( GLcontext
*ctx
,
310 GLframebuffer
*colorBuffer
,
313 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
315 switch ( bufferBit
) {
316 case DD_FRONT_LEFT_BIT
:
317 if ( rmesa
->sarea
->pfCurrentPage
== 1 ) {
318 rmesa
->state
.pixel
.readOffset
= rmesa
->radeonScreen
->backOffset
;
319 rmesa
->state
.pixel
.readPitch
= rmesa
->radeonScreen
->backPitch
;
320 rmesa
->state
.color
.drawOffset
= rmesa
->radeonScreen
->backOffset
;
321 rmesa
->state
.color
.drawPitch
= rmesa
->radeonScreen
->backPitch
;
323 rmesa
->state
.pixel
.readOffset
= rmesa
->radeonScreen
->frontOffset
;
324 rmesa
->state
.pixel
.readPitch
= rmesa
->radeonScreen
->frontPitch
;
325 rmesa
->state
.color
.drawOffset
= rmesa
->radeonScreen
->frontOffset
;
326 rmesa
->state
.color
.drawPitch
= rmesa
->radeonScreen
->frontPitch
;
329 case DD_BACK_LEFT_BIT
:
330 if ( rmesa
->sarea
->pfCurrentPage
== 1 ) {
331 rmesa
->state
.pixel
.readOffset
= rmesa
->radeonScreen
->frontOffset
;
332 rmesa
->state
.pixel
.readPitch
= rmesa
->radeonScreen
->frontPitch
;
333 rmesa
->state
.color
.drawOffset
= rmesa
->radeonScreen
->frontOffset
;
334 rmesa
->state
.color
.drawPitch
= rmesa
->radeonScreen
->frontPitch
;
336 rmesa
->state
.pixel
.readOffset
= rmesa
->radeonScreen
->backOffset
;
337 rmesa
->state
.pixel
.readPitch
= rmesa
->radeonScreen
->backPitch
;
338 rmesa
->state
.color
.drawOffset
= rmesa
->radeonScreen
->backOffset
;
339 rmesa
->state
.color
.drawPitch
= rmesa
->radeonScreen
->backPitch
;
348 /* Move locking out to get reasonable span performance (10x better
349 * than doing this in HW_LOCK above). WaitForIdle() is the main
353 static void radeonSpanRenderStart( GLcontext
*ctx
)
355 radeonContextPtr rmesa
= RADEON_CONTEXT( ctx
);
357 RADEON_FIREVERTICES( rmesa
);
358 LOCK_HARDWARE( rmesa
);
359 radeonWaitForIdleLocked( rmesa
);
362 static void radeonSpanRenderFinish( GLcontext
*ctx
)
364 radeonContextPtr rmesa
= RADEON_CONTEXT( ctx
);
365 _swrast_flush( ctx
);
366 UNLOCK_HARDWARE( rmesa
);
369 void radeonInitSpanFuncs( GLcontext
*ctx
)
371 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
372 struct swrast_device_driver
*swdd
= _swrast_GetDeviceDriverReference(ctx
);
374 swdd
->SetBuffer
= radeonSetBuffer
;
376 switch ( rmesa
->radeonScreen
->cpp
) {
378 swdd
->WriteRGBASpan
= radeonWriteRGBASpan_RGB565
;
379 swdd
->WriteRGBSpan
= radeonWriteRGBSpan_RGB565
;
380 swdd
->WriteMonoRGBASpan
= radeonWriteMonoRGBASpan_RGB565
;
381 swdd
->WriteRGBAPixels
= radeonWriteRGBAPixels_RGB565
;
382 swdd
->WriteMonoRGBAPixels
= radeonWriteMonoRGBAPixels_RGB565
;
383 swdd
->ReadRGBASpan
= radeonReadRGBASpan_RGB565
;
384 swdd
->ReadRGBAPixels
= radeonReadRGBAPixels_RGB565
;
388 swdd
->WriteRGBASpan
= radeonWriteRGBASpan_ARGB8888
;
389 swdd
->WriteRGBSpan
= radeonWriteRGBSpan_ARGB8888
;
390 swdd
->WriteMonoRGBASpan
= radeonWriteMonoRGBASpan_ARGB8888
;
391 swdd
->WriteRGBAPixels
= radeonWriteRGBAPixels_ARGB8888
;
392 swdd
->WriteMonoRGBAPixels
= radeonWriteMonoRGBAPixels_ARGB8888
;
393 swdd
->ReadRGBASpan
= radeonReadRGBASpan_ARGB8888
;
394 swdd
->ReadRGBAPixels
= radeonReadRGBAPixels_ARGB8888
;
401 switch ( rmesa
->glCtx
->Visual
.depthBits
) {
403 swdd
->ReadDepthSpan
= radeonReadDepthSpan_16
;
404 swdd
->WriteDepthSpan
= radeonWriteDepthSpan_16
;
405 swdd
->ReadDepthPixels
= radeonReadDepthPixels_16
;
406 swdd
->WriteDepthPixels
= radeonWriteDepthPixels_16
;
410 swdd
->ReadDepthSpan
= radeonReadDepthSpan_24_8
;
411 swdd
->WriteDepthSpan
= radeonWriteDepthSpan_24_8
;
412 swdd
->ReadDepthPixels
= radeonReadDepthPixels_24_8
;
413 swdd
->WriteDepthPixels
= radeonWriteDepthPixels_24_8
;
415 swdd
->ReadStencilSpan
= radeonReadStencilSpan_24_8
;
416 swdd
->WriteStencilSpan
= radeonWriteStencilSpan_24_8
;
417 swdd
->ReadStencilPixels
= radeonReadStencilPixels_24_8
;
418 swdd
->WriteStencilPixels
= radeonWriteStencilPixels_24_8
;
425 swdd
->SpanRenderStart
= radeonSpanRenderStart
;
426 swdd
->SpanRenderFinish
= radeonSpanRenderFinish
;