1 /**************************************************************************
3 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
7 The Weather Channel (TM) funded Tungsten Graphics to develop the
8 initial release of the Radeon 8500 driver under the XFree86 license.
9 This notice must be preserved.
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
21 The above copyright notice and this permission notice (including the
22 next paragraph) shall be included in all copies or substantial
23 portions of the Software.
25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 **************************************************************************/
37 * Kevin E. Martin <martin@valinux.com>
38 * Gareth Hughes <gareth@valinux.com>
39 * Keith Whitwell <keith@tungstengraphics.com>
43 #include "main/glheader.h"
44 #include "swrast/swrast.h"
46 #include "radeon_common.h"
47 #include "radeon_lock.h"
48 #include "radeon_span.h"
52 static GLubyte
*radeon_ptr32(const struct radeon_renderbuffer
* rrb
,
55 GLubyte
*ptr
= rrb
->bo
->ptr
;
56 const __DRIdrawablePrivate
*dPriv
= rrb
->dPriv
;
57 uint32_t mask
= RADEON_BO_FLAGS_MACRO_TILE
| RADEON_BO_FLAGS_MICRO_TILE
;
65 if (rrb
->has_surface
|| !(rrb
->bo
->flags
& mask
)) {
66 offset
= x
* rrb
->cpp
+ y
* rrb
->pitch
;
69 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
) {
70 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MICRO_TILE
) {
71 nmacroblkpl
= rrb
->pitch
>> 5;
72 offset
+= ((y
>> 4) * nmacroblkpl
) << 11;
73 offset
+= ((y
& 15) >> 1) << 8;
74 offset
+= (y
& 1) << 4;
75 offset
+= (x
>> 5) << 11;
76 offset
+= ((x
& 31) >> 2) << 5;
77 offset
+= (x
& 3) << 2;
79 nmacroblkpl
= rrb
->pitch
>> 6;
80 offset
+= ((y
>> 3) * nmacroblkpl
) << 11;
81 offset
+= (y
& 7) << 8;
82 offset
+= (x
>> 6) << 11;
83 offset
+= ((x
& 63) >> 3) << 5;
84 offset
+= (x
& 7) << 2;
87 nmicroblkpl
= ((rrb
->pitch
+ 31) & ~31) >> 5;
88 offset
+= (y
* nmicroblkpl
) << 5;
89 offset
+= (x
>> 3) << 5;
90 offset
+= (x
& 7) << 2;
96 static GLubyte
*radeon_ptr16(const struct radeon_renderbuffer
* rrb
,
99 GLubyte
*ptr
= rrb
->bo
->ptr
;
100 const __DRIdrawablePrivate
*dPriv
= rrb
->dPriv
;
101 uint32_t mask
= RADEON_BO_FLAGS_MACRO_TILE
| RADEON_BO_FLAGS_MICRO_TILE
;
109 if (rrb
->has_surface
|| !(rrb
->bo
->flags
& mask
)) {
110 offset
= x
* rrb
->cpp
+ y
* rrb
->pitch
;
113 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
) {
114 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MICRO_TILE
) {
115 nmacroblkpl
= rrb
->pitch
>> 6;
116 offset
+= ((y
>> 4) * nmacroblkpl
) << 11;
117 offset
+= ((y
& 15) >> 1) << 8;
118 offset
+= (y
& 1) << 4;
119 offset
+= (x
>> 6) << 11;
120 offset
+= ((x
& 63) >> 3) << 5;
121 offset
+= (x
& 7) << 1;
123 nmacroblkpl
= rrb
->pitch
>> 7;
124 offset
+= ((y
>> 3) * nmacroblkpl
) << 11;
125 offset
+= (y
& 7) << 8;
126 offset
+= (x
>> 7) << 11;
127 offset
+= ((x
& 127) >> 4) << 5;
128 offset
+= (x
& 15) << 2;
131 nmicroblkpl
= ((rrb
->pitch
+ 31) & ~31) >> 5;
132 offset
+= (y
* nmicroblkpl
) << 5;
133 offset
+= (x
>> 4) << 5;
134 offset
+= (x
& 15) << 2;
140 static GLubyte
*radeon_ptr(const struct radeon_renderbuffer
* rrb
,
143 GLubyte
*ptr
= rrb
->bo
->ptr
;
144 const __DRIdrawablePrivate
*dPriv
= rrb
->dPriv
;
145 uint32_t mask
= RADEON_BO_FLAGS_MACRO_TILE
| RADEON_BO_FLAGS_MICRO_TILE
;
155 if (rrb
->has_surface
|| !(rrb
->bo
->flags
& mask
)) {
156 offset
= x
* rrb
->cpp
+ y
* rrb
->pitch
;
159 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
) {
160 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MICRO_TILE
) {
161 microblkxs
= 16 / rrb
->cpp
;
162 macroblkxs
= 128 / rrb
->cpp
;
163 nmacroblkpl
= rrb
->pitch
/ macroblkxs
;
164 offset
+= ((y
>> 4) * nmacroblkpl
) << 11;
165 offset
+= ((y
& 15) >> 1) << 8;
166 offset
+= (y
& 1) << 4;
167 offset
+= (x
/ macroblkxs
) << 11;
168 offset
+= ((x
& (macroblkxs
- 1)) / microblkxs
) << 5;
169 offset
+= (x
& (microblkxs
- 1)) * rrb
->cpp
;
171 microblkxs
= 32 / rrb
->cpp
;
172 macroblkxs
= 256 / rrb
->cpp
;
173 nmacroblkpl
= rrb
->pitch
/ macroblkxs
;
174 offset
+= ((y
>> 3) * nmacroblkpl
) << 11;
175 offset
+= (y
& 7) << 8;
176 offset
+= (x
/ macroblkxs
) << 11;
177 offset
+= ((x
& (macroblkxs
- 1)) / microblkxs
) << 5;
178 offset
+= (x
& (microblkxs
- 1)) * rrb
->cpp
;
181 microblkxs
= 32 / rrb
->cpp
;
182 nmicroblkpl
= ((rrb
->pitch
+ 31) & ~31) >> 5;
183 offset
+= (y
* nmicroblkpl
) << 5;
184 offset
+= (x
/ microblkxs
) << 5;
185 offset
+= (x
& (microblkxs
- 1)) * rrb
->cpp
;
193 * Note that all information needed to access pixels in a renderbuffer
194 * should be obtained through the gl_renderbuffer parameter, not per-context
198 struct radeon_renderbuffer *rrb = (void *) rb; \
199 const __DRIdrawablePrivate *dPriv = rrb->dPriv; \
200 const GLuint bottom = dPriv->h - 1; \
204 #define LOCAL_DEPTH_VARS \
205 struct radeon_renderbuffer *rrb = (void *) rb; \
206 const __DRIdrawablePrivate *dPriv = rrb->dPriv; \
207 const GLuint bottom = dPriv->h - 1;
209 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
211 #define Y_FLIP(Y) (bottom - (Y))
217 /* ================================================================
221 /* 16 bit, RGB565 color spanline and pixel functions
223 #define SPANTMP_PIXEL_FMT GL_RGB
224 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
226 #define TAG(x) radeon##x##_RGB565
227 #define TAG2(x,y) radeon##x##_RGB565##y
228 #define GET_PTR(X,Y) radeon_ptr16(rrb, (X), (Y))
229 #include "spantmp2.h"
231 /* 32 bit, ARGB8888 color spanline and pixel functions
233 #define SPANTMP_PIXEL_FMT GL_BGRA
234 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
236 #define TAG(x) radeon##x##_ARGB8888
237 #define TAG2(x,y) radeon##x##_ARGB8888##y
238 #define GET_PTR(X,Y) radeon_ptr32(rrb, (X), (Y))
239 #include "spantmp2.h"
241 /* ================================================================
245 /* The Radeon family has depth tiling on all the time, so we have to convert
246 * the x,y coordinates into the memory bus address (mba) in the same
247 * manner as the engine. In each case, the linear block address (ba)
248 * is calculated, and then wired with x and y to produce the final
250 * The chip will do address translation on its own if the surface registers
251 * are set up correctly. It is not quite enough to get it working with hyperz
255 /* 16-bit depth buffer functions
257 #define VALUE_TYPE GLushort
259 #define WRITE_DEPTH( _x, _y, d ) \
260 *(GLushort *)radeon_ptr(rrb, _x, _y) = d
262 #define READ_DEPTH( d, _x, _y ) \
263 d = *(GLushort *)radeon_ptr(rrb, _x, _y)
265 #define TAG(x) radeon##x##_z16
266 #include "depthtmp.h"
268 /* 24 bit depth, 8 bit stencil depthbuffer functions
270 * Careful: It looks like the R300 uses ZZZS byte order while the R200
271 * uses SZZZ for 24 bit depth, 8 bit stencil mode.
273 #define VALUE_TYPE GLuint
276 #define WRITE_DEPTH( _x, _y, d ) \
278 GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x, _y ); \
279 GLuint tmp = *_ptr; \
281 tmp |= ((d << 8) & 0xffffff00); \
285 #define WRITE_DEPTH( _x, _y, d ) \
287 GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x, _y ); \
288 GLuint tmp = *_ptr; \
290 tmp |= ((d) & 0x00ffffff); \
296 #define READ_DEPTH( d, _x, _y ) \
298 d = (*(GLuint*)(radeon_ptr32(rrb, _x, _y)) & 0xffffff00) >> 8; \
301 #define READ_DEPTH( d, _x, _y ) \
302 d = *(GLuint*)(radeon_ptr32(rrb, _x, _y )) & 0x00ffffff;
305 fprintf(stderr, "dval(%d, %d, %d, %d)=0x%08X\n", _x, xo, _y, yo, d);\
306 d = *(GLuint*)(radeon_ptr(rrb, _x, _y )) & 0x00ffffff;
308 #define TAG(x) radeon##x##_z24_s8
309 #include "depthtmp.h"
311 /* ================================================================
315 /* 24 bit depth, 8 bit stencil depthbuffer functions
318 #define WRITE_STENCIL( _x, _y, d ) \
320 GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x, _y); \
321 GLuint tmp = *_ptr; \
327 #define WRITE_STENCIL( _x, _y, d ) \
329 GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x, _y); \
330 GLuint tmp = *_ptr; \
332 tmp |= (((d) & 0xff) << 24); \
338 #define READ_STENCIL( d, _x, _y ) \
340 GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x, _y ); \
341 GLuint tmp = *_ptr; \
342 d = tmp & 0x000000ff; \
345 #define READ_STENCIL( d, _x, _y ) \
347 GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x, _y ); \
348 GLuint tmp = *_ptr; \
349 d = (tmp & 0xff000000) >> 24; \
353 #define TAG(x) radeon##x##_z24_s8
354 #include "stenciltmp.h"
357 static void map_buffer(struct gl_renderbuffer
*rb
, GLboolean write
)
359 struct radeon_renderbuffer
*rrb
= (void*)rb
;
363 r
= radeon_bo_map(rrb
->bo
, write
);
365 fprintf(stderr
, "(%s) error(%d) mapping buffer.\n",
371 static void unmap_buffer(struct gl_renderbuffer
*rb
)
373 struct radeon_renderbuffer
*rrb
= (void*)rb
;
376 radeon_bo_unmap(rrb
->bo
);
380 static void radeonSpanRenderStart(GLcontext
* ctx
)
382 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
385 radeon_firevertices(rmesa
);
387 for (i
= 0; i
< ctx
->Const
.MaxTextureImageUnits
; i
++) {
388 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
)
389 ctx
->Driver
.MapTexture(ctx
, ctx
->Texture
.Unit
[i
]._Current
);
392 /* color draw buffers */
393 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++) {
394 map_buffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
], GL_TRUE
);
397 map_buffer(ctx
->ReadBuffer
->_ColorReadBuffer
, GL_FALSE
);
399 if (ctx
->DrawBuffer
->_DepthBuffer
) {
400 map_buffer(ctx
->DrawBuffer
->_DepthBuffer
->Wrapped
, GL_TRUE
);
402 if (ctx
->DrawBuffer
->_StencilBuffer
)
403 map_buffer(ctx
->DrawBuffer
->_StencilBuffer
->Wrapped
, GL_TRUE
);
405 /* The locking and wait for idle should really only be needed in classic mode.
406 * In a future memory manager based implementation, this should become
407 * unnecessary due to the fact that mapping our buffers, textures, etc.
408 * should implicitly wait for any previous rendering commands that must
410 LOCK_HARDWARE(rmesa
);
411 radeonWaitForIdleLocked(rmesa
);
414 static void radeonSpanRenderFinish(GLcontext
* ctx
)
416 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
419 UNLOCK_HARDWARE(rmesa
);
421 for (i
= 0; i
< ctx
->Const
.MaxTextureImageUnits
; i
++) {
422 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
)
423 ctx
->Driver
.UnmapTexture(ctx
, ctx
->Texture
.Unit
[i
]._Current
);
426 /* color draw buffers */
427 for (i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; i
++)
428 unmap_buffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
430 unmap_buffer(ctx
->ReadBuffer
->_ColorReadBuffer
);
432 if (ctx
->DrawBuffer
->_DepthBuffer
)
433 unmap_buffer(ctx
->DrawBuffer
->_DepthBuffer
->Wrapped
);
434 if (ctx
->DrawBuffer
->_StencilBuffer
)
435 unmap_buffer(ctx
->DrawBuffer
->_StencilBuffer
->Wrapped
);
438 void radeonInitSpanFuncs(GLcontext
* ctx
)
440 struct swrast_device_driver
*swdd
=
441 _swrast_GetDeviceDriverReference(ctx
);
442 swdd
->SpanRenderStart
= radeonSpanRenderStart
;
443 swdd
->SpanRenderFinish
= radeonSpanRenderFinish
;
447 * Plug in the Get/Put routines for the given driRenderbuffer.
449 void radeonSetSpanFunctions(struct radeon_renderbuffer
*rrb
)
451 if (rrb
->base
.InternalFormat
== GL_RGB5
) {
452 radeonInitPointers_RGB565(&rrb
->base
);
453 } else if (rrb
->base
.InternalFormat
== GL_RGBA8
) {
454 radeonInitPointers_ARGB8888(&rrb
->base
);
455 } else if (rrb
->base
.InternalFormat
== GL_DEPTH_COMPONENT16
) {
456 radeonInitDepthPointers_z16(&rrb
->base
);
457 } else if (rrb
->base
.InternalFormat
== GL_DEPTH_COMPONENT24
) {
458 radeonInitDepthPointers_z24_s8(&rrb
->base
);
459 } else if (rrb
->base
.InternalFormat
== GL_STENCIL_INDEX8_EXT
) {
460 radeonInitStencilPointers_z24_s8(&rrb
->base
);