src/mesa/drivers/dri/radeon/radeon_span.c

   1 /**************************************************************************
   2
   3 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   5                      VA Linux Systems Inc., Fremont, California.
   6
   7 The Weather Channel (TM) funded Tungsten Graphics to develop the
   8 initial release of the Radeon 8500 driver under the XFree86 license.
   9 This notice must be preserved.
  10
  11 All Rights Reserved.
  12
  13 Permission is hereby granted, free of charge, to any person obtaining
  14 a copy of this software and associated documentation files (the
  15 "Software"), to deal in the Software without restriction, including
  16 without limitation the rights to use, copy, modify, merge, publish,
  17 distribute, sublicense, and/or sell copies of the Software, and to
  18 permit persons to whom the Software is furnished to do so, subject to
  19 the following conditions:
  20
  21 The above copyright notice and this permission notice (including the
  22 next paragraph) shall be included in all copies or substantial
  23 portions of the Software.
  24
  25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  32
  33 **************************************************************************/
  34
  35 /*
  36  * Authors:
  37  *   Kevin E. Martin <martin@valinux.com>
  38  *   Gareth Hughes <gareth@valinux.com>
  39  *   Keith Whitwell <keith@tungstengraphics.com>
  40  *
  41  */
  42
  43 #include "glheader.h"
  44 #include "swrast/swrast.h"
  45
  46 #include "radeon_context.h"
  47 #include "radeon_ioctl.h"
  48 #include "radeon_state.h"
  49 #include "radeon_span.h"
  50 #include "radeon_tex.h"
  51
  52 #include "drirenderbuffer.h"
  53
  54 #define DBG 0
  55
  56 /*
  57  * Note that all information needed to access pixels in a renderbuffer
  58  * should be obtained through the gl_renderbuffer parameter, not per-context
  59  * information.
  60  */
  61 #define LOCAL_VARS                                              \
  62    driRenderbuffer *drb = (driRenderbuffer *) rb;               \
  63    const __DRIdrawablePrivate *dPriv = drb->dPriv;              \
  64    const GLuint bottom = dPriv->h - 1;                          \
  65    GLubyte *buf = (GLubyte *) drb->flippedData                  \
  66       + (dPriv->y * drb->flippedPitch + dPriv->x) * drb->cpp;   \
  67    GLuint p;                                                    \
  68    (void) p;
  69
  70 #define LOCAL_DEPTH_VARS                                \
  71    driRenderbuffer *drb = (driRenderbuffer *) rb;       \
  72    const __DRIdrawablePrivate *dPriv = drb->dPriv;      \
  73    const GLuint bottom = dPriv->h - 1;                  \
  74    GLuint xo = dPriv->x;                                \
  75    GLuint yo = dPriv->y;                                \
  76    GLubyte *buf = (GLubyte *) drb->Base.Data;
  77
  78 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
  79
  80 #define Y_FLIP(Y) (bottom - (Y))
  81
  82 #define HW_LOCK()
  83
  84 #define HW_UNLOCK()
  85
  86 /* ================================================================
  87  * Color buffer
  88  */
  89
  90 /* 16 bit, RGB565 color spanline and pixel functions
  91  */
  92 #define SPANTMP_PIXEL_FMT GL_RGB
  93 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
  94
  95 #define TAG(x)    radeon##x##_RGB565
  96 #define TAG2(x,y) radeon##x##_RGB565##y
  97 #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2)
  98 #include "spantmp2.h"
  99
 100 /* 32 bit, ARGB8888 color spanline and pixel functions
 101  */
 102 #define SPANTMP_PIXEL_FMT GL_BGRA
 103 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 104
 105 #define TAG(x)    radeon##x##_ARGB8888
 106 #define TAG2(x,y) radeon##x##_ARGB8888##y
 107 #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4)
 108 #include "spantmp2.h"
 109
 110 /* ================================================================
 111  * Depth buffer
 112  */
 113
 114 /* The Radeon family has depth tiling on all the time, so we have to convert
 115  * the x,y coordinates into the memory bus address (mba) in the same
 116  * manner as the engine.  In each case, the linear block address (ba)
 117  * is calculated, and then wired with x and y to produce the final
 118  * memory address.
 119  * The chip will do address translation on its own if the surface registers
 120  * are set up correctly. It is not quite enough to get it working with hyperz
 121  * too...
 122  */
 123
 124 static GLuint radeon_mba_z32(const driRenderbuffer * drb, GLint x, GLint y)
 125 {
 126         GLuint pitch = drb->pitch;
 127         if (drb->depthHasSurface) {
 128                 return 4 * (x + y * pitch);
 129         } else {
 130                 GLuint ba, address = 0; /* a[0..1] = 0           */
 131
 132 #ifdef COMPILE_R300
 133                 ba = (y / 8) * (pitch / 8) + (x / 8);
 134 #else
 135                 ba = (y / 16) * (pitch / 16) + (x / 16);
 136 #endif
 137
 138                 address |= (x & 0x7) << 2;      /* a[2..4] = x[0..2]     */
 139                 address |= (y & 0x3) << 5;      /* a[5..6] = y[0..1]     */
 140                 address |= (((x & 0x10) >> 2) ^ (y & 0x4)) << 5;        /* a[7]    = x[4] ^ y[2] */
 141                 address |= (ba & 0x3) << 8;     /* a[8..9] = ba[0..1]    */
 142
 143                 address |= (y & 0x8) << 7;      /* a[10]   = y[3]        */
 144                 address |= (((x & 0x8) << 1) ^ (y & 0x10)) << 7;        /* a[11]   = x[3] ^ y[4] */
 145                 address |= (ba & ~0x3) << 10;   /* a[12..] = ba[2..]     */
 146
 147                 return address;
 148         }
 149 }
 150
 151 static INLINE GLuint
 152 radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y)
 153 {
 154         GLuint pitch = drb->pitch;
 155         if (drb->depthHasSurface) {
 156                 return 2 * (x + y * pitch);
 157         } else {
 158                 GLuint ba, address = 0; /* a[0]    = 0           */
 159
 160                 ba = (y / 16) * (pitch / 32) + (x / 32);
 161
 162                 address |= (x & 0x7) << 1;      /* a[1..3] = x[0..2]     */
 163                 address |= (y & 0x7) << 4;      /* a[4..6] = y[0..2]     */
 164                 address |= (x & 0x8) << 4;      /* a[7]    = x[3]        */
 165                 address |= (ba & 0x3) << 8;     /* a[8..9] = ba[0..1]    */
 166                 address |= (y & 0x8) << 7;      /* a[10]   = y[3]        */
 167                 address |= ((x & 0x10) ^ (y & 0x10)) << 7;      /* a[11]   = x[4] ^ y[4] */
 168                 address |= (ba & ~0x3) << 10;   /* a[12..] = ba[2..]     */
 169
 170                 return address;
 171         }
 172 }
 173
 174 /* 16-bit depth buffer functions
 175  */
 176 #define WRITE_DEPTH( _x, _y, d )                                        \
 177    *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )) = d;
 178
 179 #define READ_DEPTH( d, _x, _y )                                         \
 180    d = *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo ));
 181
 182 #define TAG(x) radeon##x##_z16
 183 #include "depthtmp.h"
 184
 185 /* 24 bit depth, 8 bit stencil depthbuffer functions
 186  *
 187  * Careful: It looks like the R300 uses ZZZS byte order while the R200
 188  * uses SZZZ for 24 bit depth, 8 bit stencil mode.
 189  */
 190 #ifdef COMPILE_R300
 191 #define WRITE_DEPTH( _x, _y, d )                                        \
 192 do {                                                                    \
 193    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 194    GLuint tmp = *(GLuint *)(buf + offset);                              \
 195    tmp &= 0x000000ff;                                                   \
 196    tmp |= ((d << 8) & 0xffffff00);                                      \
 197    *(GLuint *)(buf + offset) = tmp;                                     \
 198 } while (0)
 199 #else
 200 #define WRITE_DEPTH( _x, _y, d )                                        \
 201 do {                                                                    \
 202    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 203    GLuint tmp = *(GLuint *)(buf + offset);                              \
 204    tmp &= 0xff000000;                                                   \
 205    tmp |= ((d) & 0x00ffffff);                                           \
 206    *(GLuint *)(buf + offset) = tmp;                                     \
 207 } while (0)
 208 #endif
 209
 210 #ifdef COMPILE_R300
 211 #define READ_DEPTH( d, _x, _y )                                         \
 212   do { \
 213     d = (*(GLuint *)(buf + radeon_mba_z32( drb, _x + xo,                \
 214                                          _y + yo )) & 0xffffff00) >> 8; \
 215   }while(0)
 216 #else
 217 #define READ_DEPTH( d, _x, _y )                                         \
 218    d = *(GLuint *)(buf + radeon_mba_z32( drb, _x + xo,                  \
 219                                          _y + yo )) & 0x00ffffff;
 220 #endif
 221
 222 #define TAG(x) radeon##x##_z24_s8
 223 #include "depthtmp.h"
 224
 225 /* ================================================================
 226  * Stencil buffer
 227  */
 228
 229 /* 24 bit depth, 8 bit stencil depthbuffer functions
 230  */
 231 #ifdef COMPILE_R300
 232 #define WRITE_STENCIL( _x, _y, d )                                      \
 233 do {                                                                    \
 234    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 235    GLuint tmp = *(GLuint *)(buf + offset);                              \
 236    tmp &= 0xffffff00;                                                   \
 237    tmp |= (d) & 0xff;                                                   \
 238    *(GLuint *)(buf + offset) = tmp;                                     \
 239 } while (0)
 240 #else
 241 #define WRITE_STENCIL( _x, _y, d )                                      \
 242 do {                                                                    \
 243    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 244    GLuint tmp = *(GLuint *)(buf + offset);                              \
 245    tmp &= 0x00ffffff;                                                   \
 246    tmp |= (((d) & 0xff) << 24);                                         \
 247    *(GLuint *)(buf + offset) = tmp;                                     \
 248 } while (0)
 249 #endif
 250
 251 #ifdef COMPILE_R300
 252 #define READ_STENCIL( d, _x, _y )                                       \
 253 do {                                                                    \
 254    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 255    GLuint tmp = *(GLuint *)(buf + offset);                              \
 256    d = tmp & 0x000000ff;                                                \
 257 } while (0)
 258 #else
 259 #define READ_STENCIL( d, _x, _y )                                       \
 260 do {                                                                    \
 261    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 262    GLuint tmp = *(GLuint *)(buf + offset);                              \
 263    d = (tmp & 0xff000000) >> 24;                                        \
 264 } while (0)
 265 #endif
 266
 267 #define TAG(x) radeon##x##_z24_s8
 268 #include "stenciltmp.h"
 269
 270 /* Move locking out to get reasonable span performance (10x better
 271  * than doing this in HW_LOCK above).  WaitForIdle() is the main
 272  * culprit.
 273  */
 274
 275 static void radeonSpanRenderStart(GLcontext * ctx)
 276 {
 277         radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 278 #ifdef COMPILE_R300
 279         r300ContextPtr r300 = (r300ContextPtr) rmesa;
 280         R300_FIREVERTICES(r300);
 281 #else
 282         RADEON_FIREVERTICES(rmesa);
 283 #endif
 284         LOCK_HARDWARE(rmesa);
 285         radeonWaitForIdleLocked(rmesa);
 286 }
 287
 288 static void radeonSpanRenderFinish(GLcontext * ctx)
 289 {
 290         radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 291         _swrast_flush(ctx);
 292         UNLOCK_HARDWARE(rmesa);
 293 }
 294
 295 void radeonInitSpanFuncs(GLcontext * ctx)
 296 {
 297         struct swrast_device_driver *swdd =
 298             _swrast_GetDeviceDriverReference(ctx);
 299         swdd->SpanRenderStart = radeonSpanRenderStart;
 300         swdd->SpanRenderFinish = radeonSpanRenderFinish;
 301 }
 302
 303 /**
 304  * Plug in the Get/Put routines for the given driRenderbuffer.
 305  */
 306 void radeonSetSpanFunctions(driRenderbuffer * drb, const GLvisual * vis)
 307 {
 308         if (drb->Base.InternalFormat == GL_RGBA) {
 309                 if (vis->redBits == 5 && vis->greenBits == 6
 310                     && vis->blueBits == 5) {
 311                         radeonInitPointers_RGB565(&drb->Base);
 312                 } else {
 313                         radeonInitPointers_ARGB8888(&drb->Base);
 314                 }
 315         } else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
 316                 radeonInitDepthPointers_z16(&drb->Base);
 317         } else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
 318                 radeonInitDepthPointers_z24_s8(&drb->Base);
 319         } else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
 320                 radeonInitStencilPointers_z24_s8(&drb->Base);
 321         }
 322 }