src/mesa/drivers/dri/radeon/radeon_span.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_span.c,v 1.6 2002/10/30 12:51:56 alanh Exp $ */
   2 /**************************************************************************
   3
   4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   5                      VA Linux Systems Inc., Fremont, California.
   6
   7 All Rights Reserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining
  10 a copy of this software and associated documentation files (the
  11 "Software"), to deal in the Software without restriction, including
  12 without limitation the rights to use, copy, modify, merge, publish,
  13 distribute, sublicense, and/or sell copies of the Software, and to
  14 permit persons to whom the Software is furnished to do so, subject to
  15 the following conditions:
  16
  17 The above copyright notice and this permission notice (including the
  18 next paragraph) shall be included in all copies or substantial
  19 portions of the Software.
  20
  21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28
  29 **************************************************************************/
  30
  31 /*
  32  * Authors:
  33  *   Kevin E. Martin <martin@valinux.com>
  34  *   Gareth Hughes <gareth@valinux.com>
  35  *   Keith Whitwell <keith@tungstengraphics.com>
  36  *
  37  */
  38
  39 #include "glheader.h"
  40 #include "swrast/swrast.h"
  41
  42 #include "radeon_context.h"
  43 #include "radeon_ioctl.h"
  44 #include "radeon_state.h"
  45 #include "radeon_span.h"
  46 #include "radeon_tex.h"
  47
  48 #include "drirenderbuffer.h"
  49
  50
  51 #define DBG 0
  52
  53
  54 /*
  55  * Note that all information needed to access pixels in a renderbuffer
  56  * should be obtained through the gl_renderbuffer parameter, not per-context
  57  * information.
  58  */
  59 #define LOCAL_VARS                                              \
  60    driRenderbuffer *drb = (driRenderbuffer *) rb;               \
  61    const __DRIdrawablePrivate *dPriv = drb->dPriv;              \
  62    const GLuint bottom = dPriv->h - 1;                          \
  63    GLubyte *buf = (GLubyte *) drb->flippedData                  \
  64       + (dPriv->y * drb->flippedPitch + dPriv->x) * drb->cpp;   \
  65    GLuint p;                                                    \
  66    (void) p;
  67
  68 #define LOCAL_DEPTH_VARS                                \
  69    driRenderbuffer *drb = (driRenderbuffer *) rb;       \
  70    const __DRIdrawablePrivate *dPriv = drb->dPriv;      \
  71    const GLuint bottom = dPriv->h - 1;                  \
  72    GLuint xo = dPriv->x;                                \
  73    GLuint yo = dPriv->y;                                \
  74    GLubyte *buf = (GLubyte *) drb->Base.Data;
  75
  76 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
  77
  78 #define Y_FLIP(Y) (bottom - (Y))
  79
  80 #define HW_LOCK()
  81
  82 #define HW_UNLOCK()
  83
  84
  85
  86 /* ================================================================
  87  * Color buffer
  88  */
  89
  90 /* 16 bit, RGB565 color spanline and pixel functions
  91  */
  92 #define SPANTMP_PIXEL_FMT GL_RGB
  93 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
  94
  95 #define TAG(x)    radeon##x##_RGB565
  96 #define TAG2(x,y) radeon##x##_RGB565##y
  97 #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2)
  98 #include "spantmp2.h"
  99
 100
 101 /* 32 bit, ARGB8888 color spanline and pixel functions
 102  */
 103 #define SPANTMP_PIXEL_FMT GL_BGRA
 104 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 105
 106 #define TAG(x)    radeon##x##_ARGB8888
 107 #define TAG2(x,y) radeon##x##_ARGB8888##y
 108 #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4)
 109 #include "spantmp2.h"
 110
 111
 112 /* ================================================================
 113  * Depth buffer
 114  */
 115
 116 /* The Radeon family has depth tiling on all the time, so we have to convert
 117  * the x,y coordinates into the memory bus address (mba) in the same
 118  * manner as the engine.  In each case, the linear block address (ba)
 119  * is calculated, and then wired with x and y to produce the final
 120  * memory address.
 121  * The chip will do address translation on its own if the surface registers
 122  * are set up correctly. It is not quite enough to get it working with hyperz
 123  * too...
 124  */
 125
 126 static GLuint
 127 radeon_mba_z32( const driRenderbuffer *drb, GLint x, GLint y )
 128 {
 129    GLuint pitch = drb->pitch;
 130    if (drb->depthHasSurface) {
 131       return 4 * (x + y * pitch);
 132    }
 133    else {
 134       GLuint ba, address = 0;                   /* a[0..1] = 0           */
 135
 136       ba = (y / 16) * (pitch / 16) + (x / 16);
 137
 138       address |= (x & 0x7) << 2;                /* a[2..4] = x[0..2]     */
 139       address |= (y & 0x3) << 5;                /* a[5..6] = y[0..1]     */
 140       address |=
 141          (((x & 0x10) >> 2) ^ (y & 0x4)) << 5;  /* a[7]    = x[4] ^ y[2] */
 142       address |= (ba & 0x3) << 8;               /* a[8..9] = ba[0..1]    */
 143
 144       address |= (y & 0x8) << 7;                /* a[10]   = y[3]        */
 145       address |=
 146          (((x & 0x8) << 1) ^ (y & 0x10)) << 7;  /* a[11]   = x[3] ^ y[4] */
 147       address |= (ba & ~0x3) << 10;             /* a[12..] = ba[2..]     */
 148
 149       return address;
 150    }
 151 }
 152
 153
 154 static INLINE GLuint
 155 radeon_mba_z16( const driRenderbuffer *drb, GLint x, GLint y )
 156 {
 157    GLuint pitch = drb->pitch;
 158    if (drb->depthHasSurface) {
 159       return 2 * (x + y * pitch);
 160    }
 161    else {
 162       GLuint ba, address = 0;                   /* a[0]    = 0           */
 163
 164       ba = (y / 16) * (pitch / 32) + (x / 32);
 165
 166       address |= (x & 0x7) << 1;                /* a[1..3] = x[0..2]     */
 167       address |= (y & 0x7) << 4;                /* a[4..6] = y[0..2]     */
 168       address |= (x & 0x8) << 4;                /* a[7]    = x[3]        */
 169       address |= (ba & 0x3) << 8;               /* a[8..9] = ba[0..1]    */
 170       address |= (y & 0x8) << 7;                /* a[10]   = y[3]        */
 171       address |= ((x & 0x10) ^ (y & 0x10)) << 7;/* a[11]   = x[4] ^ y[4] */
 172       address |= (ba & ~0x3) << 10;             /* a[12..] = ba[2..]     */
 173
 174       return address;
 175    }
 176 }
 177
 178
 179 /* 16-bit depth buffer functions
 180  */
 181 #define WRITE_DEPTH( _x, _y, d )                                        \
 182    *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )) = d;
 183
 184 #define READ_DEPTH( d, _x, _y )                                         \
 185    d = *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo ));
 186
 187 #define TAG(x) radeon##x##_z16
 188 #include "depthtmp.h"
 189
 190
 191 /* 24 bit depth, 8 bit stencil depthbuffer functions
 192  */
 193 #define WRITE_DEPTH( _x, _y, d )                                        \
 194 do {                                                                    \
 195    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 196    GLuint tmp = *(GLuint *)(buf + offset);                              \
 197    tmp &= 0xff000000;                                                   \
 198    tmp |= ((d) & 0x00ffffff);                                           \
 199    *(GLuint *)(buf + offset) = tmp;                                     \
 200 } while (0)
 201
 202 #define READ_DEPTH( d, _x, _y )                                         \
 203    d = *(GLuint *)(buf + radeon_mba_z32( drb, _x + xo,                  \
 204                                          _y + yo )) & 0x00ffffff;
 205
 206 #define TAG(x) radeon##x##_z24_s8
 207 #include "depthtmp.h"
 208
 209
 210 /* ================================================================
 211  * Stencil buffer
 212  */
 213
 214 /* 24 bit depth, 8 bit stencil depthbuffer functions
 215  */
 216 #define WRITE_STENCIL( _x, _y, d )                                      \
 217 do {                                                                    \
 218    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 219    GLuint tmp = *(GLuint *)(buf + offset);                              \
 220    tmp &= 0x00ffffff;                                                   \
 221    tmp |= (((d) & 0xff) << 24);                                         \
 222    *(GLuint *)(buf + offset) = tmp;                                     \
 223 } while (0)
 224
 225 #define READ_STENCIL( d, _x, _y )                                       \
 226 do {                                                                    \
 227    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 228    GLuint tmp = *(GLuint *)(buf + offset);                              \
 229    tmp &= 0xff000000;                                                   \
 230    d = tmp >> 24;                                                       \
 231 } while (0)
 232
 233 #define TAG(x) radeon##x##_z24_s8
 234 #include "stenciltmp.h"
 235
 236
 237
 238 /* Move locking out to get reasonable span performance (10x better
 239  * than doing this in HW_LOCK above).  WaitForIdle() is the main
 240  * culprit.
 241  */
 242
 243 static void radeonSpanRenderStart( GLcontext *ctx )
 244 {
 245    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
 246    RADEON_FIREVERTICES( rmesa );
 247    LOCK_HARDWARE( rmesa );
 248    radeonWaitForIdleLocked( rmesa );
 249 }
 250
 251 static void radeonSpanRenderFinish( GLcontext *ctx )
 252 {
 253    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
 254    _swrast_flush( ctx );
 255    UNLOCK_HARDWARE( rmesa );
 256 }
 257
 258 void radeonInitSpanFuncs( GLcontext *ctx )
 259 {
 260    struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
 261    swdd->SpanRenderStart          = radeonSpanRenderStart;
 262    swdd->SpanRenderFinish         = radeonSpanRenderFinish;
 263 }
 264
 265
 266 /**
 267  * Plug in the Get/Put routines for the given driRenderbuffer.
 268  */
 269 void
 270 radeonSetSpanFunctions(driRenderbuffer *drb, const GLvisual *vis)
 271 {
 272    if (drb->Base.InternalFormat == GL_RGBA) {
 273       if (vis->redBits == 5 && vis->greenBits == 6 && vis->blueBits == 5) {
 274          radeonInitPointers_RGB565(&drb->Base);
 275       }
 276       else {
 277          radeonInitPointers_ARGB8888(&drb->Base);
 278       }
 279    }
 280    else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
 281       radeonInitDepthPointers_z16(&drb->Base);
 282    }
 283    else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
 284       radeonInitDepthPointers_z24_s8(&drb->Base);
 285    }
 286    else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
 287       radeonInitStencilPointers_z24_s8(&drb->Base);
 288    }
 289 }