1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_span.c,v 1.6 2002/10/30 12:51:56 alanh Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
33 * Kevin E. Martin <martin@valinux.com>
34 * Gareth Hughes <gareth@valinux.com>
35 * Keith Whitwell <keith@tungstengraphics.com>
40 #include "swrast/swrast.h"
42 #include "radeon_context.h"
43 #include "radeon_ioctl.h"
44 #include "radeon_state.h"
45 #include "radeon_span.h"
46 #include "radeon_tex.h"
48 #include "drirenderbuffer.h"
55 * Note that all information needed to access pixels in a renderbuffer
56 * should be obtained through the gl_renderbuffer parameter, not per-context
60 driRenderbuffer *drb = (driRenderbuffer *) rb; \
61 const __DRIdrawablePrivate *dPriv = drb->dPriv; \
62 const GLuint bottom = dPriv->h - 1; \
63 GLubyte *buf = (GLubyte *) drb->flippedData \
64 + (dPriv->y * drb->flippedPitch + dPriv->x) * drb->cpp; \
68 #define LOCAL_DEPTH_VARS \
69 driRenderbuffer *drb = (driRenderbuffer *) rb; \
70 const __DRIdrawablePrivate *dPriv = drb->dPriv; \
71 const GLuint bottom = dPriv->h - 1; \
72 GLuint xo = dPriv->x; \
73 GLuint yo = dPriv->y; \
74 GLubyte *buf = (GLubyte *) drb->Base.Data;
76 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
78 #define Y_FLIP(Y) (bottom - (Y))
86 /* ================================================================
90 /* 16 bit, RGB565 color spanline and pixel functions
92 #define SPANTMP_PIXEL_FMT GL_RGB
93 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
95 #define TAG(x) radeon##x##_RGB565
96 #define TAG2(x,y) radeon##x##_RGB565##y
97 #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2)
101 /* 32 bit, ARGB8888 color spanline and pixel functions
103 #define SPANTMP_PIXEL_FMT GL_BGRA
104 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
106 #define TAG(x) radeon##x##_ARGB8888
107 #define TAG2(x,y) radeon##x##_ARGB8888##y
108 #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4)
109 #include "spantmp2.h"
112 /* ================================================================
116 /* The Radeon family has depth tiling on all the time, so we have to convert
117 * the x,y coordinates into the memory bus address (mba) in the same
118 * manner as the engine. In each case, the linear block address (ba)
119 * is calculated, and then wired with x and y to produce the final
121 * The chip will do address translation on its own if the surface registers
122 * are set up correctly. It is not quite enough to get it working with hyperz
127 radeon_mba_z32( const driRenderbuffer
*drb
, GLint x
, GLint y
)
129 GLuint pitch
= drb
->pitch
;
130 if (drb
->depthHasSurface
) {
131 return 4 * (x
+ y
* pitch
);
134 GLuint ba
, address
= 0; /* a[0..1] = 0 */
136 ba
= (y
/ 16) * (pitch
/ 16) + (x
/ 16);
138 address
|= (x
& 0x7) << 2; /* a[2..4] = x[0..2] */
139 address
|= (y
& 0x3) << 5; /* a[5..6] = y[0..1] */
141 (((x
& 0x10) >> 2) ^ (y
& 0x4)) << 5; /* a[7] = x[4] ^ y[2] */
142 address
|= (ba
& 0x3) << 8; /* a[8..9] = ba[0..1] */
144 address
|= (y
& 0x8) << 7; /* a[10] = y[3] */
146 (((x
& 0x8) << 1) ^ (y
& 0x10)) << 7; /* a[11] = x[3] ^ y[4] */
147 address
|= (ba
& ~0x3) << 10; /* a[12..] = ba[2..] */
155 radeon_mba_z16( const driRenderbuffer
*drb
, GLint x
, GLint y
)
157 GLuint pitch
= drb
->pitch
;
158 if (drb
->depthHasSurface
) {
159 return 2 * (x
+ y
* pitch
);
162 GLuint ba
, address
= 0; /* a[0] = 0 */
164 ba
= (y
/ 16) * (pitch
/ 32) + (x
/ 32);
166 address
|= (x
& 0x7) << 1; /* a[1..3] = x[0..2] */
167 address
|= (y
& 0x7) << 4; /* a[4..6] = y[0..2] */
168 address
|= (x
& 0x8) << 4; /* a[7] = x[3] */
169 address
|= (ba
& 0x3) << 8; /* a[8..9] = ba[0..1] */
170 address
|= (y
& 0x8) << 7; /* a[10] = y[3] */
171 address
|= ((x
& 0x10) ^ (y
& 0x10)) << 7;/* a[11] = x[4] ^ y[4] */
172 address
|= (ba
& ~0x3) << 10; /* a[12..] = ba[2..] */
179 /* 16-bit depth buffer functions
181 #define WRITE_DEPTH( _x, _y, d ) \
182 *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )) = d;
184 #define READ_DEPTH( d, _x, _y ) \
185 d = *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo ));
187 #define TAG(x) radeon##x##_z16
188 #include "depthtmp.h"
191 /* 24 bit depth, 8 bit stencil depthbuffer functions
193 #define WRITE_DEPTH( _x, _y, d ) \
195 GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
196 GLuint tmp = *(GLuint *)(buf + offset); \
198 tmp |= ((d) & 0x00ffffff); \
199 *(GLuint *)(buf + offset) = tmp; \
202 #define READ_DEPTH( d, _x, _y ) \
203 d = *(GLuint *)(buf + radeon_mba_z32( drb, _x + xo, \
204 _y + yo )) & 0x00ffffff;
206 #define TAG(x) radeon##x##_z24_s8
207 #include "depthtmp.h"
210 /* ================================================================
214 /* 24 bit depth, 8 bit stencil depthbuffer functions
216 #define WRITE_STENCIL( _x, _y, d ) \
218 GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
219 GLuint tmp = *(GLuint *)(buf + offset); \
221 tmp |= (((d) & 0xff) << 24); \
222 *(GLuint *)(buf + offset) = tmp; \
225 #define READ_STENCIL( d, _x, _y ) \
227 GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
228 GLuint tmp = *(GLuint *)(buf + offset); \
233 #define TAG(x) radeon##x##_z24_s8
234 #include "stenciltmp.h"
238 /* Move locking out to get reasonable span performance (10x better
239 * than doing this in HW_LOCK above). WaitForIdle() is the main
243 static void radeonSpanRenderStart( GLcontext
*ctx
)
245 radeonContextPtr rmesa
= RADEON_CONTEXT( ctx
);
246 RADEON_FIREVERTICES( rmesa
);
247 LOCK_HARDWARE( rmesa
);
248 radeonWaitForIdleLocked( rmesa
);
251 static void radeonSpanRenderFinish( GLcontext
*ctx
)
253 radeonContextPtr rmesa
= RADEON_CONTEXT( ctx
);
254 _swrast_flush( ctx
);
255 UNLOCK_HARDWARE( rmesa
);
258 void radeonInitSpanFuncs( GLcontext
*ctx
)
260 struct swrast_device_driver
*swdd
= _swrast_GetDeviceDriverReference(ctx
);
261 swdd
->SpanRenderStart
= radeonSpanRenderStart
;
262 swdd
->SpanRenderFinish
= radeonSpanRenderFinish
;
267 * Plug in the Get/Put routines for the given driRenderbuffer.
270 radeonSetSpanFunctions(driRenderbuffer
*drb
, const GLvisual
*vis
)
272 if (drb
->Base
.InternalFormat
== GL_RGBA
) {
273 if (vis
->redBits
== 5 && vis
->greenBits
== 6 && vis
->blueBits
== 5) {
274 radeonInitPointers_RGB565(&drb
->Base
);
277 radeonInitPointers_ARGB8888(&drb
->Base
);
280 else if (drb
->Base
.InternalFormat
== GL_DEPTH_COMPONENT16
) {
281 radeonInitDepthPointers_z16(&drb
->Base
);
283 else if (drb
->Base
.InternalFormat
== GL_DEPTH_COMPONENT24
) {
284 radeonInitDepthPointers_z24_s8(&drb
->Base
);
286 else if (drb
->Base
.InternalFormat
== GL_STENCIL_INDEX8_EXT
) {
287 radeonInitStencilPointers_z24_s8(&drb
->Base
);