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radeon: use mesa renderbuffer accessors for depth for now.
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_span.c
1 /**************************************************************************
2
3 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
6
7 The Weather Channel (TM) funded Tungsten Graphics to develop the
8 initial release of the Radeon 8500 driver under the XFree86 license.
9 This notice must be preserved.
10
11 All Rights Reserved.
12
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
20
21 The above copyright notice and this permission notice (including the
22 next paragraph) shall be included in all copies or substantial
23 portions of the Software.
24
25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32
33 **************************************************************************/
34
35 /*
36 * Authors:
37 * Kevin E. Martin <martin@valinux.com>
38 * Gareth Hughes <gareth@valinux.com>
39 * Keith Whitwell <keith@tungstengraphics.com>
40 *
41 */
42
43 #include "main/glheader.h"
44 #include "main/texformat.h"
45 #include "main/renderbuffer.h"
46 #include "swrast/swrast.h"
47
48 #include "radeon_common.h"
49 #include "radeon_span.h"
50
51 #define DBG 0
52
53 #if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && BYTE_ORDER == BIG_ENDIAN
54 #if defined(__linux__)
55 #include <byteswap.h>
56 #define CPU_TO_LE16( x ) bswap_16( x )
57 #define LE16_TO_CPU( x ) bswap_16( x )
58 #endif /* __linux__ */
59 #else
60 #define CPU_TO_LE16( x ) ( x )
61 #define LE16_TO_CPU( x ) ( x )
62 #endif
63
64 static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb);
65
66
67 /* r200 depth buffer is always tiled - this is the formula
68 according to the docs unless I typo'ed in it
69 */
70 #if defined(RADEON_R200)
71 static GLubyte *r200_depth_2byte(const struct radeon_renderbuffer * rrb,
72 GLint x, GLint y)
73 {
74 GLubyte *ptr = rrb->bo->ptr + rrb->draw_offset;
75 GLint offset;
76 if (rrb->has_surface) {
77 offset = x * rrb->cpp + y * rrb->pitch;
78 } else {
79 GLuint b;
80 offset = 0;
81 b = (((y >> 4) * (rrb->pitch >> 8) + (x >> 6)));
82 offset += (b >> 1) << 12;
83 offset += (((rrb->pitch >> 8) & 0x1) ? (b & 0x1) : ((b & 0x1) ^ ((y >> 4) & 0x1))) << 11;
84 offset += ((y >> 2) & 0x3) << 9;
85 offset += ((x >> 3) & 0x1) << 8;
86 offset += ((x >> 4) & 0x3) << 6;
87 offset += ((x >> 2) & 0x1) << 5;
88 offset += ((y >> 1) & 0x1) << 4;
89 offset += ((x >> 1) & 0x1) << 3;
90 offset += (y & 0x1) << 2;
91 offset += (x & 0x1) << 1;
92 }
93 return &ptr[offset];
94 }
95
96 static GLubyte *r200_depth_4byte(const struct radeon_renderbuffer * rrb,
97 GLint x, GLint y)
98 {
99 GLubyte *ptr = rrb->bo->ptr + rrb->draw_offset;
100 GLint offset;
101 if (rrb->has_surface) {
102 offset = x * rrb->cpp + y * rrb->pitch;
103 } else {
104 GLuint b;
105 offset = 0;
106 b = (((y & 0x7ff) >> 4) * (rrb->pitch >> 7) + (x >> 5));
107 offset += (b >> 1) << 12;
108 offset += (((rrb->pitch >> 7) & 0x1) ? (b & 0x1) : ((b & 0x1) ^ ((y >> 4) & 0x1))) << 11;
109 offset += ((y >> 2) & 0x3) << 9;
110 offset += ((x >> 2) & 0x1) << 8;
111 offset += ((x >> 3) & 0x3) << 6;
112 offset += ((y >> 1) & 0x1) << 5;
113 offset += ((x >> 1) & 0x1) << 4;
114 offset += (y & 0x1) << 3;
115 offset += (x & 0x1) << 2;
116 }
117 return &ptr[offset];
118 }
119 #endif
120
121
122 /* radeon tiling on r300-r500 has 4 states,
123 macro-linear/micro-linear
124 macro-linear/micro-tiled
125 macro-tiled /micro-linear
126 macro-tiled /micro-tiled
127 1 byte surface
128 2 byte surface - two types - we only provide 8x2 microtiling
129 4 byte surface
130 8/16 byte (unused)
131 */
132 static GLubyte *radeon_ptr_4byte(const struct radeon_renderbuffer * rrb,
133 GLint x, GLint y)
134 {
135 GLubyte *ptr = rrb->bo->ptr + rrb->draw_offset;
136 uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE;
137 GLint offset;
138
139 if (rrb->has_surface || !(rrb->bo->flags & mask)) {
140 offset = x * rrb->cpp + y * rrb->pitch;
141 } else {
142 offset = 0;
143 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
144 if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) {
145 offset = ((y >> 4) * (rrb->pitch >> 7) + (x >> 5)) << 11;
146 offset += (((y >> 3) ^ (x >> 5)) & 0x1) << 10;
147 offset += (((y >> 4) ^ (x >> 4)) & 0x1) << 9;
148 offset += (((y >> 2) ^ (x >> 4)) & 0x1) << 8;
149 offset += (((y >> 3) ^ (x >> 3)) & 0x1) << 7;
150 offset += ((y >> 1) & 0x1) << 6;
151 offset += ((x >> 2) & 0x1) << 5;
152 offset += (y & 1) << 4;
153 offset += (x & 3) << 2;
154 } else {
155 offset = ((y >> 3) * (rrb->pitch >> 8) + (x >> 6)) << 11;
156 offset += (((y >> 2) ^ (x >> 6)) & 0x1) << 10;
157 offset += (((y >> 3) ^ (x >> 5)) & 0x1) << 9;
158 offset += (((y >> 1) ^ (x >> 5)) & 0x1) << 8;
159 offset += (((y >> 2) ^ (x >> 4)) & 0x1) << 7;
160 offset += (y & 1) << 6;
161 offset += (x & 15) << 2;
162 }
163 } else {
164 offset = ((y >> 1) * (rrb->pitch >> 4) + (x >> 2)) << 5;
165 offset += (y & 1) << 4;
166 offset += (x & 3) << 2;
167 }
168 }
169 return &ptr[offset];
170 }
171
172 static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
173 GLint x, GLint y)
174 {
175 GLubyte *ptr = rrb->bo->ptr + rrb->draw_offset;
176 uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE;
177 GLint offset;
178
179 if (rrb->has_surface || !(rrb->bo->flags & mask)) {
180 offset = x * rrb->cpp + y * rrb->pitch;
181 } else {
182 offset = 0;
183 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
184 if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) {
185 offset = ((y >> 4) * (rrb->pitch >> 7) + (x >> 6)) << 11;
186 offset += (((y >> 3) ^ (x >> 6)) & 0x1) << 10;
187 offset += (((y >> 4) ^ (x >> 5)) & 0x1) << 9;
188 offset += (((y >> 2) ^ (x >> 5)) & 0x1) << 8;
189 offset += (((y >> 3) ^ (x >> 4)) & 0x1) << 7;
190 offset += ((y >> 1) & 0x1) << 6;
191 offset += ((x >> 3) & 0x1) << 5;
192 offset += (y & 1) << 4;
193 offset += (x & 3) << 2;
194 } else {
195 offset = ((y >> 3) * (rrb->pitch >> 8) + (x >> 7)) << 11;
196 offset += (((y >> 2) ^ (x >> 7)) & 0x1) << 10;
197 offset += (((y >> 3) ^ (x >> 6)) & 0x1) << 9;
198 offset += (((y >> 1) ^ (x >> 6)) & 0x1) << 8;
199 offset += (((y >> 2) ^ (x >> 5)) & 0x1) << 7;
200 offset += (y & 1) << 6;
201 offset += ((x >> 4) & 0x1) << 5;
202 offset += (x & 15) << 2;
203 }
204 } else {
205 offset = ((y >> 1) * (rrb->pitch >> 4) + (x >> 3)) << 5;
206 offset += (y & 0x1) << 4;
207 offset += (x & 0x7) << 1;
208 }
209 }
210 return &ptr[offset];
211 }
212
213 /*
214 * Note that all information needed to access pixels in a renderbuffer
215 * should be obtained through the gl_renderbuffer parameter, not per-context
216 * information.
217 */
218 #define LOCAL_VARS \
219 struct radeon_renderbuffer *rrb = (void *) rb; \
220 int minx = 0, miny = 0; \
221 int maxx = rb->Width; \
222 int maxy = rb->Height; \
223 void *buf = rb->Data; \
224 int pitch = rb->RowStride * rrb->cpp; \
225 GLuint p; \
226 (void)p;
227
228 #define LOCAL_DEPTH_VARS \
229 struct radeon_renderbuffer *rrb = (void *) rb; \
230 int minx = 0, miny = 0; \
231 const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1; \
232 const GLint yBias = ctx->DrawBuffer->Name ? 0 : rrb->base.Height - 1; \
233 int maxx = rb->Width; \
234 int maxy = rb->Height;
235
236 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
237
238 #define Y_FLIP(_y) (_y)
239
240 #define HW_LOCK()
241 #define HW_UNLOCK()
242 #define HW_CLIPLOOP()
243 #define HW_ENDCLIPLOOP()
244
245 /* ================================================================
246 * Color buffer
247 */
248
249 /* 16 bit, RGB565 color spanline and pixel functions
250 */
251 #define SPANTMP_PIXEL_FMT GL_RGB
252 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
253 #define TAG(x) radeon##x##_RGB565
254 #define TAG2(x,y) radeon##x##_RGB565##y
255 #include "spantmp2.h"
256
257 #define SPANTMP_PIXEL_FMT GL_RGB
258 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5_REV
259 #define TAG(x) radeon##x##_RGB565_REV
260 #define TAG2(x,y) radeon##x##_RGB565_REV##y
261 #include "spantmp2.h"
262
263 /* 16 bit, ARGB1555 color spanline and pixel functions
264 */
265 #define SPANTMP_PIXEL_FMT GL_BGRA
266 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
267 #define TAG(x) radeon##x##_ARGB1555
268 #define TAG2(x,y) radeon##x##_ARGB1555##y
269 #include "spantmp2.h"
270
271 #define SPANTMP_PIXEL_FMT GL_BGRA
272 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5
273 #define TAG(x) radeon##x##_ARGB1555_REV
274 #define TAG2(x,y) radeon##x##_ARGB1555_REV##y
275 #include "spantmp2.h"
276
277 /* 16 bit, RGBA4 color spanline and pixel functions
278 */
279 #define SPANTMP_PIXEL_FMT GL_BGRA
280 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
281 #define TAG(x) radeon##x##_ARGB4444
282 #define TAG2(x,y) radeon##x##_ARGB4444##y
283 #include "spantmp2.h"
284
285 #define SPANTMP_PIXEL_FMT GL_BGRA
286 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4
287 #define TAG(x) radeon##x##_ARGB4444_REV
288 #define TAG2(x,y) radeon##x##_ARGB4444_REV##y
289 #include "spantmp2.h"
290
291 /* 32 bit, xRGB8888 color spanline and pixel functions
292 */
293 #define SPANTMP_PIXEL_FMT GL_BGRA
294 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
295 #define TAG(x) radeon##x##_xRGB8888
296 #define TAG2(x,y) radeon##x##_xRGB8888##y
297 #include "spantmp2.h"
298
299 /* 32 bit, ARGB8888 color spanline and pixel functions
300 */
301 #define SPANTMP_PIXEL_FMT GL_BGRA
302 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
303 #define TAG(x) radeon##x##_ARGB8888
304 #define TAG2(x,y) radeon##x##_ARGB8888##y
305 #include "spantmp2.h"
306
307 /* 32 bit, BGRx8888 color spanline and pixel functions
308 */
309 #define SPANTMP_PIXEL_FMT GL_BGRA
310 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8
311 #define TAG(x) radeon##x##_BGRx8888
312 #define TAG2(x,y) radeon##x##_BGRx8888##y
313 #include "spantmp2.h"
314
315 /* 32 bit, BGRA8888 color spanline and pixel functions
316 */
317 #define SPANTMP_PIXEL_FMT GL_BGRA
318 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8
319 #define TAG(x) radeon##x##_BGRA8888
320 #define TAG2(x,y) radeon##x##_BGRA8888##y
321 #include "spantmp2.h"
322
323 #undef Y_FLIP
324 #define Y_FLIP(_y) ((_y) * yScale + yBias)
325 /* ================================================================
326 * Depth buffer
327 */
328
329 /* The Radeon family has depth tiling on all the time, so we have to convert
330 * the x,y coordinates into the memory bus address (mba) in the same
331 * manner as the engine. In each case, the linear block address (ba)
332 * is calculated, and then wired with x and y to produce the final
333 * memory address.
334 * The chip will do address translation on its own if the surface registers
335 * are set up correctly. It is not quite enough to get it working with hyperz
336 * too...
337 */
338
339 /* 16-bit depth buffer functions
340 */
341 #define VALUE_TYPE GLushort
342
343 #if defined(RADEON_R200)
344 #define WRITE_DEPTH( _x, _y, d ) \
345 *(GLushort *)r200_depth_2byte(rrb, _x, _y) = d
346 #else
347 #define WRITE_DEPTH( _x, _y, d ) \
348 *(GLushort *)radeon_ptr_2byte_8x2(rrb, _x, _y) = d
349 #endif
350
351 #if defined(RADEON_R200)
352 #define READ_DEPTH( d, _x, _y ) \
353 d = *(GLushort *)r200_depth_2byte(rrb, _x, _y)
354 #else
355 #define READ_DEPTH( d, _x, _y ) \
356 d = *(GLushort *)radeon_ptr_2byte_8x2(rrb, _x, _y)
357 #endif
358
359 #define TAG(x) radeon##x##_z16
360 #include "depthtmp.h"
361
362 /* 24 bit depth
363 *
364 * Careful: It looks like the R300 uses ZZZS byte order while the R200
365 * uses SZZZ for 24 bit depth, 8 bit stencil mode.
366 */
367 #define VALUE_TYPE GLuint
368
369 #if defined(RADEON_R200)
370 #define WRITE_DEPTH( _x, _y, d ) \
371 do { \
372 GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x, _y ); \
373 GLuint tmp = LE32_TO_CPU(*_ptr); \
374 tmp &= 0xff000000; \
375 tmp |= ((d) & 0x00ffffff); \
376 *_ptr = CPU_TO_LE32(tmp); \
377 } while (0)
378 #else
379 #define WRITE_DEPTH( _x, _y, d ) \
380 do { \
381 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x, _y ); \
382 GLuint tmp = LE32_TO_CPU(*_ptr); \
383 tmp &= 0xff000000; \
384 tmp |= ((d) & 0x00ffffff); \
385 *_ptr = CPU_TO_LE32(tmp); \
386 } while (0)
387 #endif
388
389 #if defined(RADEON_R200)
390 #define READ_DEPTH( d, _x, _y ) \
391 do { \
392 d = LE32_TO_CPU(*(GLuint*)(r200_depth_4byte(rrb, _x, _y))) & 0x00ffffff; \
393 }while(0)
394 #else
395 #define READ_DEPTH( d, _x, _y ) \
396 d = LE32_TO_CPU(*(GLuint*)(radeon_ptr_4byte(rrb, _x, _y))) & 0x00ffffff;
397 #endif
398
399 #define TAG(x) radeon##x##_z24
400 #include "depthtmp.h"
401
402 /* 24 bit depth, 8 bit stencil depthbuffer functions
403 * EXT_depth_stencil
404 *
405 * Careful: It looks like the R300 uses ZZZS byte order while the R200
406 * uses SZZZ for 24 bit depth, 8 bit stencil mode.
407 */
408 #define VALUE_TYPE GLuint
409
410 #if defined(RADEON_R200)
411 #define WRITE_DEPTH( _x, _y, d ) \
412 do { \
413 GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x, _y ); \
414 *_ptr = CPU_TO_LE32(d); \
415 } while (0)
416 #else
417 #define WRITE_DEPTH( _x, _y, d ) \
418 do { \
419 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x, _y ); \
420 *_ptr = CPU_TO_LE32(d); \
421 } while (0)
422 #endif
423
424 #if defined(RADEON_R200)
425 #define READ_DEPTH( d, _x, _y ) \
426 do { \
427 d = LE32_TO_CPU(*(GLuint*)(r200_depth_4byte(rrb, _x, _y))); \
428 }while(0)
429 #else
430 #define READ_DEPTH( d, _x, _y ) do { \
431 d = LE32_TO_CPU(*(GLuint*)(radeon_ptr_4byte(rrb, _x, _y))); \
432 } while (0)
433 #endif
434
435 #define TAG(x) radeon##x##_s8_z24
436 #include "depthtmp.h"
437
438 /* ================================================================
439 * Stencil buffer
440 */
441
442 /* 24 bit depth, 8 bit stencil depthbuffer functions
443 */
444 #if defined(RADEON_R200)
445 #define WRITE_STENCIL( _x, _y, d ) \
446 do { \
447 GLuint *_ptr = (GLuint*)r200_depth_4byte(rrb, _x, _y); \
448 GLuint tmp = LE32_TO_CPU(*_ptr); \
449 tmp &= 0x00ffffff; \
450 tmp |= (((d) & 0xff) << 24); \
451 *_ptr = CPU_TO_LE32(tmp); \
452 } while (0)
453 #else
454 #define WRITE_STENCIL( _x, _y, d ) \
455 do { \
456 GLuint *_ptr = (GLuint*)radeon_ptr_4byte(rrb, _x, _y); \
457 GLuint tmp = LE32_TO_CPU(*_ptr); \
458 tmp &= 0x00ffffff; \
459 tmp |= (((d) & 0xff) << 24); \
460 *_ptr = CPU_TO_LE32(tmp); \
461 } while (0)
462 #endif
463
464 #if defined(RADEON_R200)
465 #define READ_STENCIL( d, _x, _y ) \
466 do { \
467 GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x, _y ); \
468 GLuint tmp = LE32_TO_CPU(*_ptr); \
469 d = (tmp & 0xff000000) >> 24; \
470 } while (0)
471 #else
472 #define READ_STENCIL( d, _x, _y ) \
473 do { \
474 GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x, _y ); \
475 GLuint tmp = LE32_TO_CPU(*_ptr); \
476 d = (tmp & 0xff000000) >> 24; \
477 } while (0)
478 #endif
479
480 #define TAG(x) radeon##x##_s8_z24
481 #include "stenciltmp.h"
482
483 static void
484 radeon_renderbuffer_map(struct gl_context *ctx, struct gl_renderbuffer *rb)
485 {
486 struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
487 GLubyte *map;
488 int stride;
489
490 if (!rb || !rrb)
491 return;
492
493 ctx->Driver.MapRenderbuffer(ctx, rb, 0, 0, rb->Width, rb->Height,
494 GL_MAP_READ_BIT | GL_MAP_WRITE_BIT,
495 &map, &stride);
496
497 rb->Data = map;
498 rb->RowStride = stride / _mesa_get_format_bytes(rb->Format);
499
500 radeonSetSpanFunctions(rrb);
501 }
502
503 static void
504 radeon_renderbuffer_unmap(struct gl_context *ctx, struct gl_renderbuffer *rb)
505 {
506 struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
507 if (!rb || !rrb)
508 return;
509
510 ctx->Driver.UnmapRenderbuffer(ctx, rb);
511
512 rb->GetRow = NULL;
513 rb->PutRow = NULL;
514 rb->Data = NULL;
515 rb->RowStride = 0;
516 }
517
518 static void
519 radeon_map_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
520 {
521 GLuint i, j;
522
523 radeon_print(RADEON_MEMORY, RADEON_TRACE,
524 "%s( %p , fb %p )\n",
525 __func__, ctx, fb);
526
527 /* check for render to textures */
528 for (i = 0; i < BUFFER_COUNT; i++)
529 radeon_renderbuffer_map(ctx, fb->Attachment[i].Renderbuffer);
530
531 radeon_check_front_buffer_rendering(ctx);
532 }
533
534 static void
535 radeon_unmap_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
536 {
537 GLuint i, j;
538
539 radeon_print(RADEON_MEMORY, RADEON_TRACE,
540 "%s( %p , fb %p)\n",
541 __func__, ctx, fb);
542
543 /* check for render to textures */
544 for (i = 0; i < BUFFER_COUNT; i++)
545 radeon_renderbuffer_unmap(ctx, fb->Attachment[i].Renderbuffer);
546
547 radeon_check_front_buffer_rendering(ctx);
548 }
549
550 static void radeonSpanRenderStart(struct gl_context * ctx)
551 {
552 radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
553 int i;
554
555 radeon_firevertices(rmesa);
556
557 for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
558 if (ctx->Texture.Unit[i]._ReallyEnabled) {
559 radeon_validate_texture_miptree(ctx, ctx->Texture.Unit[i]._Current);
560 radeon_swrast_map_texture_images(ctx, ctx->Texture.Unit[i]._Current);
561 }
562 }
563
564 radeon_map_framebuffer(ctx, ctx->DrawBuffer);
565 if (ctx->ReadBuffer != ctx->DrawBuffer)
566 radeon_map_framebuffer(ctx, ctx->ReadBuffer);
567 }
568
569 static void radeonSpanRenderFinish(struct gl_context * ctx)
570 {
571 int i;
572
573 _swrast_flush(ctx);
574
575 for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++)
576 if (ctx->Texture.Unit[i]._ReallyEnabled)
577 radeon_swrast_unmap_texture_images(ctx, ctx->Texture.Unit[i]._Current);
578
579 radeon_unmap_framebuffer(ctx, ctx->DrawBuffer);
580 if (ctx->ReadBuffer != ctx->DrawBuffer)
581 radeon_unmap_framebuffer(ctx, ctx->ReadBuffer);
582 }
583
584 void radeonInitSpanFuncs(struct gl_context * ctx)
585 {
586 struct swrast_device_driver *swdd =
587 _swrast_GetDeviceDriverReference(ctx);
588 swdd->SpanRenderStart = radeonSpanRenderStart;
589 swdd->SpanRenderFinish = radeonSpanRenderFinish;
590 }
591
592 /**
593 * Plug in the Get/Put routines for the given driRenderbuffer.
594 */
595 static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb)
596 {
597 if (rrb->base.Format == MESA_FORMAT_RGB565) {
598 radeonInitPointers_RGB565(&rrb->base);
599 } else if (rrb->base.Format == MESA_FORMAT_RGB565_REV) {
600 radeonInitPointers_RGB565_REV(&rrb->base);
601 } else if (rrb->base.Format == MESA_FORMAT_XRGB8888) {
602 radeonInitPointers_xRGB8888(&rrb->base);
603 } else if (rrb->base.Format == MESA_FORMAT_XRGB8888_REV) {
604 radeonInitPointers_BGRx8888(&rrb->base);
605 } else if (rrb->base.Format == MESA_FORMAT_ARGB8888) {
606 radeonInitPointers_ARGB8888(&rrb->base);
607 } else if (rrb->base.Format == MESA_FORMAT_ARGB8888_REV) {
608 radeonInitPointers_BGRA8888(&rrb->base);
609 } else if (rrb->base.Format == MESA_FORMAT_ARGB4444) {
610 radeonInitPointers_ARGB4444(&rrb->base);
611 } else if (rrb->base.Format == MESA_FORMAT_ARGB4444_REV) {
612 radeonInitPointers_ARGB4444_REV(&rrb->base);
613 } else if (rrb->base.Format == MESA_FORMAT_ARGB1555) {
614 radeonInitPointers_ARGB1555(&rrb->base);
615 } else if (rrb->base.Format == MESA_FORMAT_ARGB1555_REV) {
616 radeonInitPointers_ARGB1555_REV(&rrb->base);
617 } else if (rrb->base.Format == MESA_FORMAT_Z16) {
618 _mesa_set_renderbuffer_accessors(&rrb->base);
619 } else if (rrb->base.Format == MESA_FORMAT_X8_Z24) {
620 _mesa_set_renderbuffer_accessors(&rrb->base);
621 } else if (rrb->base.Format == MESA_FORMAT_S8_Z24) {
622 _mesa_set_renderbuffer_accessors(&rrb->base);
623 } else if (rrb->base.Format == MESA_FORMAT_S8) {
624 _mesa_set_renderbuffer_accessors(&rrb->base);
625 } else {
626 fprintf(stderr, "radeonSetSpanFunctions: bad format: 0x%04X\n", rrb->base.Format);
627 }
628 }