src/mesa/drivers/dri/radeon/radeon_span.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_span.c,v 1.6 2002/10/30 12:51:56 alanh Exp $ */
   2 /**************************************************************************
   3
   4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   5                      VA Linux Systems Inc., Fremont, California.
   6
   7 All Rights Reserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining
  10 a copy of this software and associated documentation files (the
  11 "Software"), to deal in the Software without restriction, including
  12 without limitation the rights to use, copy, modify, merge, publish,
  13 distribute, sublicense, and/or sell copies of the Software, and to
  14 permit persons to whom the Software is furnished to do so, subject to
  15 the following conditions:
  16
  17 The above copyright notice and this permission notice (including the
  18 next paragraph) shall be included in all copies or substantial
  19 portions of the Software.
  20
  21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28
  29 **************************************************************************/
  30
  31 /*
  32  * Authors:
  33  *   Kevin E. Martin <martin@valinux.com>
  34  *   Gareth Hughes <gareth@valinux.com>
  35  *   Keith Whitwell <keith@tungstengraphics.com>
  36  *
  37  */
  38
  39 #include "glheader.h"
  40 #include "swrast/swrast.h"
  41
  42 #include "radeon_context.h"
  43 #include "radeon_ioctl.h"
  44 #include "radeon_state.h"
  45 #include "radeon_span.h"
  46 #include "radeon_tex.h"
  47
  48 #include "drirenderbuffer.h"
  49
  50
  51 #define DBG 0
  52
  53 #define GET_PTR(X,Y) (sPriv->pFB + drb->flippedOffset           \
  54      + ((dPriv->y + (Y)) * drb->flippedPitch + (dPriv->x + (X))) * drb->cpp)
  55
  56 /*
  57  * Eventually, try to remove all references to ctx/rmesa here.
  58  * The renderbuffer parameter to the span functions should provide all
  59  * the info needed to read/write the pixels.
  60  * We'll be a step closer to supporting Pbuffer and framebuffer objects then.
  61  */
  62 #define LOCAL_VARS                                                      \
  63    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);                        \
  64    __DRIscreenPrivate *sPriv = rmesa->dri.screen;                       \
  65    __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;                   \
  66    driRenderbuffer *drb = (driRenderbuffer *) rb;                       \
  67    GLuint height = dPriv->h;                                            \
  68    GLuint p;                                                            \
  69    (void) p;
  70
  71 #define LOCAL_DEPTH_VARS                                                \
  72    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);                        \
  73    __DRIscreenPrivate *sPriv = rmesa->dri.screen;                       \
  74    __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;                   \
  75    driRenderbuffer *drb = (driRenderbuffer *) rb;                       \
  76    GLuint height = dPriv->h;                                            \
  77    GLuint xo = dPriv->x;                                                \
  78    GLuint yo = dPriv->y;                                                \
  79    char *buf = (char *)(sPriv->pFB + drb->offset);
  80
  81
  82 #define LOCAL_STENCIL_VARS      LOCAL_DEPTH_VARS
  83
  84 #define Y_FLIP( _y )            (height - _y - 1)
  85
  86 #define HW_LOCK()
  87
  88 #define HW_UNLOCK()
  89
  90
  91
  92 /* ================================================================
  93  * Color buffer
  94  */
  95
  96 /* 16 bit, RGB565 color spanline and pixel functions
  97  */
  98 #define SPANTMP_PIXEL_FMT GL_RGB
  99 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
 100
 101 #define TAG(x)    radeon##x##_RGB565
 102 #define TAG2(x,y) radeon##x##_RGB565##y
 103 #define GET_SRC_PTR(X,Y) GET_PTR(X, Y)
 104 #define GET_DST_PTR(X,Y) GET_PTR(X, Y)
 105 #include "spantmp2.h"
 106
 107
 108 /* 32 bit, ARGB8888 color spanline and pixel functions
 109  */
 110 #define SPANTMP_PIXEL_FMT GL_BGRA
 111 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 112
 113 #define TAG(x)    radeon##x##_ARGB8888
 114 #define TAG2(x,y) radeon##x##_ARGB8888##y
 115 #define GET_SRC_PTR(X,Y) GET_PTR(X, Y)
 116 #define GET_DST_PTR(X,Y) GET_PTR(X, Y)
 117 #include "spantmp2.h"
 118
 119
 120 /* ================================================================
 121  * Depth buffer
 122  */
 123
 124 /* The Radeon family has depth tiling on all the time, so we have to convert
 125  * the x,y coordinates into the memory bus address (mba) in the same
 126  * manner as the engine.  In each case, the linear block address (ba)
 127  * is calculated, and then wired with x and y to produce the final
 128  * memory address.
 129  * The chip will do address translation on its own if the surface registers
 130  * are set up correctly. It is not quite enough to get it working with hyperz
 131  * too...
 132  */
 133
 134 static GLuint
 135 radeon_mba_z32( const driRenderbuffer *drb, GLint x, GLint y )
 136 {
 137    GLuint pitch = drb->pitch;
 138    if (drb->depthHasSurface) {
 139       return 4 * (x + y * pitch);
 140    }
 141    else {
 142       GLuint ba, address = 0;                   /* a[0..1] = 0           */
 143
 144       ba = (y / 16) * (pitch / 16) + (x / 16);
 145
 146       address |= (x & 0x7) << 2;                /* a[2..4] = x[0..2]     */
 147       address |= (y & 0x3) << 5;                /* a[5..6] = y[0..1]     */
 148       address |=
 149          (((x & 0x10) >> 2) ^ (y & 0x4)) << 5;  /* a[7]    = x[4] ^ y[2] */
 150       address |= (ba & 0x3) << 8;               /* a[8..9] = ba[0..1]    */
 151
 152       address |= (y & 0x8) << 7;                /* a[10]   = y[3]        */
 153       address |=
 154          (((x & 0x8) << 1) ^ (y & 0x10)) << 7;  /* a[11]   = x[3] ^ y[4] */
 155       address |= (ba & ~0x3) << 10;             /* a[12..] = ba[2..]     */
 156
 157       return address;
 158    }
 159 }
 160
 161
 162 static INLINE GLuint
 163 radeon_mba_z16( const driRenderbuffer *drb, GLint x, GLint y )
 164 {
 165    GLuint pitch = drb->pitch;
 166    if (drb->depthHasSurface) {
 167       return 2 * (x + y * pitch);
 168    }
 169    else {
 170       GLuint ba, address = 0;                   /* a[0]    = 0           */
 171
 172       ba = (y / 16) * (pitch / 32) + (x / 32);
 173
 174       address |= (x & 0x7) << 1;                /* a[1..3] = x[0..2]     */
 175       address |= (y & 0x7) << 4;                /* a[4..6] = y[0..2]     */
 176       address |= (x & 0x8) << 4;                /* a[7]    = x[3]        */
 177       address |= (ba & 0x3) << 8;               /* a[8..9] = ba[0..1]    */
 178       address |= (y & 0x8) << 7;                /* a[10]   = y[3]        */
 179       address |= ((x & 0x10) ^ (y & 0x10)) << 7;/* a[11]   = x[4] ^ y[4] */
 180       address |= (ba & ~0x3) << 10;             /* a[12..] = ba[2..]     */
 181
 182       return address;
 183    }
 184 }
 185
 186
 187 /* 16-bit depth buffer functions
 188  */
 189 #define WRITE_DEPTH( _x, _y, d )                                        \
 190    *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )) = d;
 191
 192 #define READ_DEPTH( d, _x, _y )                                         \
 193    d = *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo ));
 194
 195 #define TAG(x) radeon##x##_16
 196 #include "depthtmp.h"
 197
 198
 199 /* 24 bit depth, 8 bit stencil depthbuffer functions
 200  */
 201 #define WRITE_DEPTH( _x, _y, d )                                        \
 202 do {                                                                    \
 203    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 204    GLuint tmp = *(GLuint *)(buf + offset);                              \
 205    tmp &= 0xff000000;                                                   \
 206    tmp |= ((d) & 0x00ffffff);                                           \
 207    *(GLuint *)(buf + offset) = tmp;                                     \
 208 } while (0)
 209
 210 #define READ_DEPTH( d, _x, _y )                                         \
 211    d = *(GLuint *)(buf + radeon_mba_z32( drb, _x + xo,                  \
 212                                          _y + yo )) & 0x00ffffff;
 213
 214 #define TAG(x) radeon##x##_24_8
 215 #include "depthtmp.h"
 216
 217
 218 /* ================================================================
 219  * Stencil buffer
 220  */
 221
 222 /* 24 bit depth, 8 bit stencil depthbuffer functions
 223  */
 224 #define WRITE_STENCIL( _x, _y, d )                                      \
 225 do {                                                                    \
 226    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 227    GLuint tmp = *(GLuint *)(buf + offset);                              \
 228    tmp &= 0x00ffffff;                                                   \
 229    tmp |= (((d) & 0xff) << 24);                                         \
 230    *(GLuint *)(buf + offset) = tmp;                                     \
 231 } while (0)
 232
 233 #define READ_STENCIL( d, _x, _y )                                       \
 234 do {                                                                    \
 235    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 236    GLuint tmp = *(GLuint *)(buf + offset);                              \
 237    tmp &= 0xff000000;                                                   \
 238    d = tmp >> 24;                                                       \
 239 } while (0)
 240
 241 #define TAG(x) radeon##x##_24_8
 242 #include "stenciltmp.h"
 243
 244
 245
 246 /* Move locking out to get reasonable span performance (10x better
 247  * than doing this in HW_LOCK above).  WaitForIdle() is the main
 248  * culprit.
 249  */
 250
 251 static void radeonSpanRenderStart( GLcontext *ctx )
 252 {
 253    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
 254
 255    RADEON_FIREVERTICES( rmesa );
 256    LOCK_HARDWARE( rmesa );
 257    radeonWaitForIdleLocked( rmesa );
 258 }
 259
 260 static void radeonSpanRenderFinish( GLcontext *ctx )
 261 {
 262    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
 263    _swrast_flush( ctx );
 264    UNLOCK_HARDWARE( rmesa );
 265 }
 266
 267 void radeonInitSpanFuncs( GLcontext *ctx )
 268 {
 269    struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
 270    swdd->SpanRenderStart          = radeonSpanRenderStart;
 271    swdd->SpanRenderFinish         = radeonSpanRenderFinish;
 272 }
 273
 274
 275 /**
 276  * Plug in the Get/Put routines for the given driRenderbuffer.
 277  */
 278 void
 279 radeonSetSpanFunctions(driRenderbuffer *drb, const GLvisual *vis)
 280 {
 281    if (drb->Base.InternalFormat == GL_RGBA) {
 282       if (vis->redBits == 5 && vis->greenBits == 6 && vis->blueBits == 5) {
 283          radeonInitPointers_RGB565(&drb->Base);
 284       }
 285       else {
 286          radeonInitPointers_ARGB8888(&drb->Base);
 287       }
 288    }
 289    else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
 290       drb->Base.GetRow        = radeonReadDepthSpan_16;
 291       drb->Base.GetValues     = radeonReadDepthPixels_16;
 292       drb->Base.PutRow        = radeonWriteDepthSpan_16;
 293       drb->Base.PutMonoRow    = radeonWriteMonoDepthSpan_16;
 294       drb->Base.PutValues     = radeonWriteDepthPixels_16;
 295       drb->Base.PutMonoValues = NULL;
 296    }
 297    else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
 298       drb->Base.GetRow        = radeonReadDepthSpan_24_8;
 299       drb->Base.GetValues     = radeonReadDepthPixels_24_8;
 300       drb->Base.PutRow        = radeonWriteDepthSpan_24_8;
 301       drb->Base.PutMonoRow    = radeonWriteMonoDepthSpan_24_8;
 302       drb->Base.PutValues     = radeonWriteDepthPixels_24_8;
 303       drb->Base.PutMonoValues = NULL;
 304    }
 305    else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
 306       drb->Base.GetRow        = radeonReadStencilSpan_24_8;
 307       drb->Base.GetValues     = radeonReadStencilPixels_24_8;
 308       drb->Base.PutRow        = radeonWriteStencilSpan_24_8;
 309       drb->Base.PutMonoRow    = radeonWriteMonoStencilSpan_24_8;
 310       drb->Base.PutValues     = radeonWriteStencilPixels_24_8;
 311       drb->Base.PutMonoValues = NULL;
 312    }
 313 }