src/mesa/drivers/dri/radeon/radeon_state.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_state.c,v 1.8 2002/12/16 16:18:58 dawes Exp $ */
   2 /**************************************************************************
   3
   4 Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Gareth Hughes <gareth@valinux.com>
  33  *   Keith Whitwell <keith@tungstengraphics.com>
  34  */
  35
  36 #include "glheader.h"
  37 #include "imports.h"
  38 #include "api_arrayelt.h"
  39 #include "enums.h"
  40 #include "colormac.h"
  41 #include "state.h"
  42 #include "buffers.h"
  43 #include "context.h"
  44
  45 #include "array_cache/acache.h"
  46 #include "tnl/tnl.h"
  47 #include "tnl/t_pipeline.h"
  48 #include "main/light.h"
  49 #include "swrast_setup/swrast_setup.h"
  50
  51 #include "radeon_context.h"
  52 #include "radeon_ioctl.h"
  53 #include "radeon_state.h"
  54 #include "radeon_tcl.h"
  55 #include "radeon_tex.h"
  56 #include "radeon_swtcl.h"
  57 #include "radeon_vtxfmt.h"
  58 #include "drirenderbuffer.h"
  59
  60 /* =============================================================
  61  * Alpha blending
  62  */
  63
  64 static void radeonAlphaFunc( GLcontext *ctx, GLenum func, GLfloat ref )
  65 {
  66    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
  67    int pp_misc = rmesa->hw.ctx.cmd[CTX_PP_MISC];
  68    GLubyte refByte;
  69
  70    CLAMPED_FLOAT_TO_UBYTE(refByte, ref);
  71
  72    RADEON_STATECHANGE( rmesa, ctx );
  73
  74    pp_misc &= ~(RADEON_ALPHA_TEST_OP_MASK | RADEON_REF_ALPHA_MASK);
  75    pp_misc |= (refByte & RADEON_REF_ALPHA_MASK);
  76
  77    switch ( func ) {
  78    case GL_NEVER:
  79       pp_misc |= RADEON_ALPHA_TEST_FAIL;
  80       break;
  81    case GL_LESS:
  82       pp_misc |= RADEON_ALPHA_TEST_LESS;
  83       break;
  84    case GL_EQUAL:
  85       pp_misc |= RADEON_ALPHA_TEST_EQUAL;
  86       break;
  87    case GL_LEQUAL:
  88       pp_misc |= RADEON_ALPHA_TEST_LEQUAL;
  89       break;
  90    case GL_GREATER:
  91       pp_misc |= RADEON_ALPHA_TEST_GREATER;
  92       break;
  93    case GL_NOTEQUAL:
  94       pp_misc |= RADEON_ALPHA_TEST_NEQUAL;
  95       break;
  96    case GL_GEQUAL:
  97       pp_misc |= RADEON_ALPHA_TEST_GEQUAL;
  98       break;
  99    case GL_ALWAYS:
 100       pp_misc |= RADEON_ALPHA_TEST_PASS;
 101       break;
 102    }
 103
 104    rmesa->hw.ctx.cmd[CTX_PP_MISC] = pp_misc;
 105 }
 106
 107 static void radeonBlendEquationSeparate( GLcontext *ctx,
 108                                          GLenum modeRGB, GLenum modeA )
 109 {
 110    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 111    GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] & ~RADEON_COMB_FCN_MASK;
 112    GLboolean fallback = GL_FALSE;
 113
 114    assert( modeRGB == modeA );
 115
 116    switch ( modeRGB ) {
 117    case GL_FUNC_ADD:
 118    case GL_LOGIC_OP:
 119       b |= RADEON_COMB_FCN_ADD_CLAMP;
 120       break;
 121
 122    case GL_FUNC_SUBTRACT:
 123       b |= RADEON_COMB_FCN_SUB_CLAMP;
 124       break;
 125
 126    default:
 127       if (ctx->Color.BlendEnabled)
 128          fallback = GL_TRUE;
 129       else
 130          b |= RADEON_COMB_FCN_ADD_CLAMP;
 131       break;
 132    }
 133
 134    FALLBACK( rmesa, RADEON_FALLBACK_BLEND_EQ, fallback );
 135    if ( !fallback ) {
 136       RADEON_STATECHANGE( rmesa, ctx );
 137       rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = b;
 138       if ( ctx->Color._LogicOpEnabled ) {
 139          rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |=  RADEON_ROP_ENABLE;
 140       } else {
 141          rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE;
 142       }
 143    }
 144 }
 145
 146 static void radeonBlendFuncSeparate( GLcontext *ctx,
 147                                      GLenum sfactorRGB, GLenum dfactorRGB,
 148                                      GLenum sfactorA, GLenum dfactorA )
 149 {
 150    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 151    GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] &
 152       ~(RADEON_SRC_BLEND_MASK | RADEON_DST_BLEND_MASK);
 153    GLboolean fallback = GL_FALSE;
 154
 155    switch ( ctx->Color.BlendSrcRGB ) {
 156    case GL_ZERO:
 157       b |= RADEON_SRC_BLEND_GL_ZERO;
 158       break;
 159    case GL_ONE:
 160       b |= RADEON_SRC_BLEND_GL_ONE;
 161       break;
 162    case GL_DST_COLOR:
 163       b |= RADEON_SRC_BLEND_GL_DST_COLOR;
 164       break;
 165    case GL_ONE_MINUS_DST_COLOR:
 166       b |= RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR;
 167       break;
 168    case GL_SRC_COLOR:
 169       b |= RADEON_SRC_BLEND_GL_SRC_COLOR;
 170       break;
 171    case GL_ONE_MINUS_SRC_COLOR:
 172       b |= RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR;
 173       break;
 174    case GL_SRC_ALPHA:
 175       b |= RADEON_SRC_BLEND_GL_SRC_ALPHA;
 176       break;
 177    case GL_ONE_MINUS_SRC_ALPHA:
 178       b |= RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA;
 179       break;
 180    case GL_DST_ALPHA:
 181       b |= RADEON_SRC_BLEND_GL_DST_ALPHA;
 182       break;
 183    case GL_ONE_MINUS_DST_ALPHA:
 184       b |= RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA;
 185       break;
 186    case GL_SRC_ALPHA_SATURATE:
 187       b |= RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE;
 188       break;
 189    case GL_CONSTANT_COLOR:
 190    case GL_ONE_MINUS_CONSTANT_COLOR:
 191    case GL_CONSTANT_ALPHA:
 192    case GL_ONE_MINUS_CONSTANT_ALPHA:
 193       if (ctx->Color.BlendEnabled)
 194          fallback = GL_TRUE;
 195       else
 196          b |= RADEON_SRC_BLEND_GL_ONE;
 197       break;
 198    default:
 199       break;
 200    }
 201
 202    switch ( ctx->Color.BlendDstRGB ) {
 203    case GL_ZERO:
 204       b |= RADEON_DST_BLEND_GL_ZERO;
 205       break;
 206    case GL_ONE:
 207       b |= RADEON_DST_BLEND_GL_ONE;
 208       break;
 209    case GL_SRC_COLOR:
 210       b |= RADEON_DST_BLEND_GL_SRC_COLOR;
 211       break;
 212    case GL_ONE_MINUS_SRC_COLOR:
 213       b |= RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR;
 214       break;
 215    case GL_SRC_ALPHA:
 216       b |= RADEON_DST_BLEND_GL_SRC_ALPHA;
 217       break;
 218    case GL_ONE_MINUS_SRC_ALPHA:
 219       b |= RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA;
 220       break;
 221    case GL_DST_COLOR:
 222       b |= RADEON_DST_BLEND_GL_DST_COLOR;
 223       break;
 224    case GL_ONE_MINUS_DST_COLOR:
 225       b |= RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR;
 226       break;
 227    case GL_DST_ALPHA:
 228       b |= RADEON_DST_BLEND_GL_DST_ALPHA;
 229       break;
 230    case GL_ONE_MINUS_DST_ALPHA:
 231       b |= RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA;
 232       break;
 233    case GL_CONSTANT_COLOR:
 234    case GL_ONE_MINUS_CONSTANT_COLOR:
 235    case GL_CONSTANT_ALPHA:
 236    case GL_ONE_MINUS_CONSTANT_ALPHA:
 237       if (ctx->Color.BlendEnabled)
 238          fallback = GL_TRUE;
 239       else
 240          b |= RADEON_DST_BLEND_GL_ZERO;
 241       break;
 242    default:
 243       break;
 244    }
 245
 246    FALLBACK( rmesa, RADEON_FALLBACK_BLEND_FUNC, fallback );
 247    if ( !fallback ) {
 248       RADEON_STATECHANGE( rmesa, ctx );
 249       rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = b;
 250    }
 251 }
 252
 253
 254 /* =============================================================
 255  * Depth testing
 256  */
 257
 258 static void radeonDepthFunc( GLcontext *ctx, GLenum func )
 259 {
 260    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 261
 262    RADEON_STATECHANGE( rmesa, ctx );
 263    rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_Z_TEST_MASK;
 264
 265    switch ( ctx->Depth.Func ) {
 266    case GL_NEVER:
 267       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_NEVER;
 268       break;
 269    case GL_LESS:
 270       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_LESS;
 271       break;
 272    case GL_EQUAL:
 273       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_EQUAL;
 274       break;
 275    case GL_LEQUAL:
 276       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_LEQUAL;
 277       break;
 278    case GL_GREATER:
 279       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_GREATER;
 280       break;
 281    case GL_NOTEQUAL:
 282       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_NEQUAL;
 283       break;
 284    case GL_GEQUAL:
 285       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_GEQUAL;
 286       break;
 287    case GL_ALWAYS:
 288       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_ALWAYS;
 289       break;
 290    }
 291 }
 292
 293
 294 static void radeonDepthMask( GLcontext *ctx, GLboolean flag )
 295 {
 296    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 297    RADEON_STATECHANGE( rmesa, ctx );
 298
 299    if ( ctx->Depth.Mask ) {
 300       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |=  RADEON_Z_WRITE_ENABLE;
 301    } else {
 302       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_Z_WRITE_ENABLE;
 303    }
 304 }
 305
 306 static void radeonClearDepth( GLcontext *ctx, GLclampd d )
 307 {
 308    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 309    GLuint format = (rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &
 310                     RADEON_DEPTH_FORMAT_MASK);
 311
 312    switch ( format ) {
 313    case RADEON_DEPTH_FORMAT_16BIT_INT_Z:
 314       rmesa->state.depth.clear = d * 0x0000ffff;
 315       break;
 316    case RADEON_DEPTH_FORMAT_24BIT_INT_Z:
 317       rmesa->state.depth.clear = d * 0x00ffffff;
 318       break;
 319    }
 320 }
 321
 322
 323 /* =============================================================
 324  * Fog
 325  */
 326
 327
 328 static void radeonFogfv( GLcontext *ctx, GLenum pname, const GLfloat *param )
 329 {
 330    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 331    union { int i; float f; } c, d;
 332    GLchan col[4];
 333
 334    c.i = rmesa->hw.fog.cmd[FOG_C];
 335    d.i = rmesa->hw.fog.cmd[FOG_D];
 336
 337    switch (pname) {
 338    case GL_FOG_MODE:
 339       if (!ctx->Fog.Enabled)
 340          return;
 341       RADEON_STATECHANGE(rmesa, tcl);
 342       rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_TCL_FOG_MASK;
 343       switch (ctx->Fog.Mode) {
 344       case GL_LINEAR:
 345          rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_LINEAR;
 346          if (ctx->Fog.Start == ctx->Fog.End) {
 347             c.f = 1.0F;
 348             d.f = 1.0F;
 349          }
 350          else {
 351             c.f = ctx->Fog.End/(ctx->Fog.End-ctx->Fog.Start);
 352             d.f = 1.0/(ctx->Fog.End-ctx->Fog.Start);
 353          }
 354          break;
 355       case GL_EXP:
 356          rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP;
 357          c.f = 0.0;
 358          d.f = ctx->Fog.Density;
 359          break;
 360       case GL_EXP2:
 361          rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP2;
 362          c.f = 0.0;
 363          d.f = -(ctx->Fog.Density * ctx->Fog.Density);
 364          break;
 365       default:
 366          return;
 367       }
 368       break;
 369    case GL_FOG_DENSITY:
 370       switch (ctx->Fog.Mode) {
 371       case GL_EXP:
 372          c.f = 0.0;
 373          d.f = ctx->Fog.Density;
 374          break;
 375       case GL_EXP2:
 376          c.f = 0.0;
 377          d.f = -(ctx->Fog.Density * ctx->Fog.Density);
 378          break;
 379       default:
 380          break;
 381       }
 382       break;
 383    case GL_FOG_START:
 384    case GL_FOG_END:
 385       if (ctx->Fog.Mode == GL_LINEAR) {
 386          if (ctx->Fog.Start == ctx->Fog.End) {
 387             c.f = 1.0F;
 388             d.f = 1.0F;
 389          } else {
 390             c.f = ctx->Fog.End/(ctx->Fog.End-ctx->Fog.Start);
 391             d.f = 1.0/(ctx->Fog.End-ctx->Fog.Start);
 392          }
 393       }
 394       break;
 395    case GL_FOG_COLOR:
 396       RADEON_STATECHANGE( rmesa, ctx );
 397       UNCLAMPED_FLOAT_TO_RGB_CHAN( col, ctx->Fog.Color );
 398       rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] =
 399          radeonPackColor( 4, col[0], col[1], col[2], 0 );
 400       break;
 401    case GL_FOG_COORDINATE_SOURCE_EXT:
 402       /* What to do?
 403        */
 404       break;
 405    default:
 406       return;
 407    }
 408
 409    if (c.i != rmesa->hw.fog.cmd[FOG_C] || d.i != rmesa->hw.fog.cmd[FOG_D]) {
 410       RADEON_STATECHANGE( rmesa, fog );
 411       rmesa->hw.fog.cmd[FOG_C] = c.i;
 412       rmesa->hw.fog.cmd[FOG_D] = d.i;
 413    }
 414 }
 415
 416
 417 /* =============================================================
 418  * Scissoring
 419  */
 420
 421
 422 static GLboolean intersect_rect( drm_clip_rect_t *out,
 423                                  drm_clip_rect_t *a,
 424                                  drm_clip_rect_t *b )
 425 {
 426    *out = *a;
 427    if ( b->x1 > out->x1 ) out->x1 = b->x1;
 428    if ( b->y1 > out->y1 ) out->y1 = b->y1;
 429    if ( b->x2 < out->x2 ) out->x2 = b->x2;
 430    if ( b->y2 < out->y2 ) out->y2 = b->y2;
 431    if ( out->x1 >= out->x2 ) return GL_FALSE;
 432    if ( out->y1 >= out->y2 ) return GL_FALSE;
 433    return GL_TRUE;
 434 }
 435
 436
 437 void radeonRecalcScissorRects( radeonContextPtr rmesa )
 438 {
 439    drm_clip_rect_t *out;
 440    int i;
 441
 442    /* Grow cliprect store?
 443     */
 444    if (rmesa->state.scissor.numAllocedClipRects < rmesa->numClipRects) {
 445       while (rmesa->state.scissor.numAllocedClipRects < rmesa->numClipRects) {
 446          rmesa->state.scissor.numAllocedClipRects += 1; /* zero case */
 447          rmesa->state.scissor.numAllocedClipRects *= 2;
 448       }
 449
 450       if (rmesa->state.scissor.pClipRects)
 451          FREE(rmesa->state.scissor.pClipRects);
 452
 453       rmesa->state.scissor.pClipRects =
 454          MALLOC( rmesa->state.scissor.numAllocedClipRects *
 455                  sizeof(drm_clip_rect_t) );
 456
 457       if ( rmesa->state.scissor.pClipRects == NULL ) {
 458          rmesa->state.scissor.numAllocedClipRects = 0;
 459          return;
 460       }
 461    }
 462
 463    out = rmesa->state.scissor.pClipRects;
 464    rmesa->state.scissor.numClipRects = 0;
 465
 466    for ( i = 0 ; i < rmesa->numClipRects ;  i++ ) {
 467       if ( intersect_rect( out,
 468                            &rmesa->pClipRects[i],
 469                            &rmesa->state.scissor.rect ) ) {
 470          rmesa->state.scissor.numClipRects++;
 471          out++;
 472       }
 473    }
 474 }
 475
 476
 477 static void radeonUpdateScissor( GLcontext *ctx )
 478 {
 479    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 480
 481    if ( rmesa->dri.drawable ) {
 482       __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
 483
 484       int x = ctx->Scissor.X;
 485       int y = dPriv->h - ctx->Scissor.Y - ctx->Scissor.Height;
 486       int w = ctx->Scissor.X + ctx->Scissor.Width - 1;
 487       int h = dPriv->h - ctx->Scissor.Y - 1;
 488
 489       rmesa->state.scissor.rect.x1 = x + dPriv->x;
 490       rmesa->state.scissor.rect.y1 = y + dPriv->y;
 491       rmesa->state.scissor.rect.x2 = w + dPriv->x + 1;
 492       rmesa->state.scissor.rect.y2 = h + dPriv->y + 1;
 493
 494       radeonRecalcScissorRects( rmesa );
 495    }
 496 }
 497
 498
 499 static void radeonScissor( GLcontext *ctx,
 500                            GLint x, GLint y, GLsizei w, GLsizei h )
 501 {
 502    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 503
 504    if ( ctx->Scissor.Enabled ) {
 505       RADEON_FIREVERTICES( rmesa );     /* don't pipeline cliprect changes */
 506       radeonUpdateScissor( ctx );
 507    }
 508
 509 }
 510
 511
 512 /* =============================================================
 513  * Culling
 514  */
 515
 516 static void radeonCullFace( GLcontext *ctx, GLenum unused )
 517 {
 518    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 519    GLuint s = rmesa->hw.set.cmd[SET_SE_CNTL];
 520    GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL];
 521
 522    s |= RADEON_FFACE_SOLID | RADEON_BFACE_SOLID;
 523    t &= ~(RADEON_CULL_FRONT | RADEON_CULL_BACK);
 524
 525    if ( ctx->Polygon.CullFlag ) {
 526       switch ( ctx->Polygon.CullFaceMode ) {
 527       case GL_FRONT:
 528          s &= ~RADEON_FFACE_SOLID;
 529          t |= RADEON_CULL_FRONT;
 530          break;
 531       case GL_BACK:
 532          s &= ~RADEON_BFACE_SOLID;
 533          t |= RADEON_CULL_BACK;
 534          break;
 535       case GL_FRONT_AND_BACK:
 536          s &= ~(RADEON_FFACE_SOLID | RADEON_BFACE_SOLID);
 537          t |= (RADEON_CULL_FRONT | RADEON_CULL_BACK);
 538          break;
 539       }
 540    }
 541
 542    if ( rmesa->hw.set.cmd[SET_SE_CNTL] != s ) {
 543       RADEON_STATECHANGE(rmesa, set );
 544       rmesa->hw.set.cmd[SET_SE_CNTL] = s;
 545    }
 546
 547    if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) {
 548       RADEON_STATECHANGE(rmesa, tcl );
 549       rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t;
 550    }
 551 }
 552
 553 static void radeonFrontFace( GLcontext *ctx, GLenum mode )
 554 {
 555    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 556
 557    RADEON_STATECHANGE( rmesa, set );
 558    rmesa->hw.set.cmd[SET_SE_CNTL] &= ~RADEON_FFACE_CULL_DIR_MASK;
 559
 560    RADEON_STATECHANGE( rmesa, tcl );
 561    rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_CULL_FRONT_IS_CCW;
 562
 563    switch ( mode ) {
 564    case GL_CW:
 565       rmesa->hw.set.cmd[SET_SE_CNTL] |= RADEON_FFACE_CULL_CW;
 566       break;
 567    case GL_CCW:
 568       rmesa->hw.set.cmd[SET_SE_CNTL] |= RADEON_FFACE_CULL_CCW;
 569       rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_CULL_FRONT_IS_CCW;
 570       break;
 571    }
 572 }
 573
 574
 575 /* =============================================================
 576  * Line state
 577  */
 578 static void radeonLineWidth( GLcontext *ctx, GLfloat widthf )
 579 {
 580    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 581
 582    RADEON_STATECHANGE( rmesa, lin );
 583    RADEON_STATECHANGE( rmesa, set );
 584
 585    /* Line width is stored in U6.4 format.
 586     */
 587    rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (GLuint)(widthf * 16.0);
 588    if ( widthf > 1.0 ) {
 589       rmesa->hw.set.cmd[SET_SE_CNTL] |=  RADEON_WIDELINE_ENABLE;
 590    } else {
 591       rmesa->hw.set.cmd[SET_SE_CNTL] &= ~RADEON_WIDELINE_ENABLE;
 592    }
 593 }
 594
 595 static void radeonLineStipple( GLcontext *ctx, GLint factor, GLushort pattern )
 596 {
 597    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 598
 599    RADEON_STATECHANGE( rmesa, lin );
 600    rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] =
 601       ((((GLuint)factor & 0xff) << 16) | ((GLuint)pattern));
 602 }
 603
 604
 605 /* =============================================================
 606  * Masks
 607  */
 608 static void radeonColorMask( GLcontext *ctx,
 609                              GLboolean r, GLboolean g,
 610                              GLboolean b, GLboolean a )
 611 {
 612    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 613    GLuint mask = radeonPackColor( rmesa->radeonScreen->cpp,
 614                                   ctx->Color.ColorMask[RCOMP],
 615                                   ctx->Color.ColorMask[GCOMP],
 616                                   ctx->Color.ColorMask[BCOMP],
 617                                   ctx->Color.ColorMask[ACOMP] );
 618
 619    if ( rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] != mask ) {
 620       RADEON_STATECHANGE( rmesa, msk );
 621       rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = mask;
 622    }
 623 }
 624
 625
 626 /* =============================================================
 627  * Polygon state
 628  */
 629
 630 static void radeonPolygonOffset( GLcontext *ctx,
 631                                  GLfloat factor, GLfloat units )
 632 {
 633    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 634    GLfloat constant = units * rmesa->state.depth.scale;
 635
 636    RADEON_STATECHANGE( rmesa, zbs );
 637    rmesa->hw.zbs.cmd[ZBS_SE_ZBIAS_FACTOR]   = *(GLuint *)&factor;
 638    rmesa->hw.zbs.cmd[ZBS_SE_ZBIAS_CONSTANT] = *(GLuint *)&constant;
 639 }
 640
 641 static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask )
 642 {
 643    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 644    GLuint i;
 645    drm_radeon_stipple_t stipple;
 646
 647    /* Must flip pattern upside down.
 648     */
 649    for ( i = 0 ; i < 32 ; i++ ) {
 650       rmesa->state.stipple.mask[31 - i] = ((GLuint *) mask)[i];
 651    }
 652
 653    /* TODO: push this into cmd mechanism
 654     */
 655    RADEON_FIREVERTICES( rmesa );
 656    LOCK_HARDWARE( rmesa );
 657
 658    /* FIXME: Use window x,y offsets into stipple RAM.
 659     */
 660    stipple.mask = rmesa->state.stipple.mask;
 661    drmCommandWrite( rmesa->dri.fd, DRM_RADEON_STIPPLE,
 662                     &stipple, sizeof(drm_radeon_stipple_t) );
 663    UNLOCK_HARDWARE( rmesa );
 664 }
 665
 666 static void radeonPolygonMode( GLcontext *ctx, GLenum face, GLenum mode )
 667 {
 668    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 669    GLboolean flag = (ctx->_TriangleCaps & DD_TRI_UNFILLED) != 0;
 670
 671    /* Can't generally do unfilled via tcl, but some good special
 672     * cases work.
 673     */
 674    TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_UNFILLED, flag);
 675    if (rmesa->TclFallback) {
 676       radeonChooseRenderState( ctx );
 677       radeonChooseVertexState( ctx );
 678    }
 679 }
 680
 681
 682 /* =============================================================
 683  * Rendering attributes
 684  *
 685  * We really don't want to recalculate all this every time we bind a
 686  * texture.  These things shouldn't change all that often, so it makes
 687  * sense to break them out of the core texture state update routines.
 688  */
 689
 690 /* Examine lighting and texture state to determine if separate specular
 691  * should be enabled.
 692  */
 693 static void radeonUpdateSpecular( GLcontext *ctx )
 694 {
 695    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 696    u_int32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL];
 697
 698    RADEON_STATECHANGE( rmesa, tcl );
 699
 700    rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] &= ~RADEON_TCL_COMPUTE_SPECULAR;
 701    rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] &= ~RADEON_TCL_COMPUTE_DIFFUSE;
 702    rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~RADEON_TCL_VTX_PK_SPEC;
 703    rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~RADEON_TCL_VTX_PK_DIFFUSE;
 704    rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_LIGHTING_ENABLE;
 705
 706    p &= ~RADEON_SPECULAR_ENABLE;
 707
 708    rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_DIFFUSE_SPECULAR_COMBINE;
 709
 710
 711    if (ctx->Light.Enabled &&
 712        ctx->Light.Model.ColorControl == GL_SEPARATE_SPECULAR_COLOR) {
 713       rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] |= RADEON_TCL_COMPUTE_SPECULAR;
 714       rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] |= RADEON_TCL_COMPUTE_DIFFUSE;
 715       rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_SPEC;
 716       rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
 717       rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LIGHTING_ENABLE;
 718       p |=  RADEON_SPECULAR_ENABLE;
 719       rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &=
 720          ~RADEON_DIFFUSE_SPECULAR_COMBINE;
 721    }
 722    else if (ctx->Light.Enabled) {
 723       rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] |= RADEON_TCL_COMPUTE_DIFFUSE;
 724       rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
 725       rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LIGHTING_ENABLE;
 726    } else if (ctx->Fog.ColorSumEnabled ) {
 727       rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_SPEC;
 728       rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
 729       p |= RADEON_SPECULAR_ENABLE;
 730    } else {
 731       rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
 732    }
 733
 734    if (ctx->Fog.Enabled) {
 735       rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] |= RADEON_TCL_COMPUTE_SPECULAR;
 736       rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_SPEC;
 737
 738       /* Bizzare: have to leave lighting enabled to get fog.
 739        */
 740       rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LIGHTING_ENABLE;
 741    }
 742
 743    if (NEED_SECONDARY_COLOR(ctx)) {
 744       assert( (p & RADEON_SPECULAR_ENABLE) != 0 );
 745    } else {
 746       assert( (p & RADEON_SPECULAR_ENABLE) == 0 );
 747    }
 748
 749    if ( rmesa->hw.ctx.cmd[CTX_PP_CNTL] != p ) {
 750       RADEON_STATECHANGE( rmesa, ctx );
 751       rmesa->hw.ctx.cmd[CTX_PP_CNTL] = p;
 752    }
 753
 754    /* Update vertex/render formats
 755     */
 756    if (rmesa->TclFallback) {
 757       radeonChooseRenderState( ctx );
 758       radeonChooseVertexState( ctx );
 759    }
 760 }
 761
 762
 763 /* =============================================================
 764  * Materials
 765  */
 766
 767
 768 /* Update on colormaterial, material emmissive/ambient,
 769  * lightmodel.globalambient
 770  */
 771 static void update_global_ambient( GLcontext *ctx )
 772 {
 773    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 774    float *fcmd = (float *)RADEON_DB_STATE( glt );
 775
 776    /* Need to do more if both emmissive & ambient are PREMULT:
 777     * Hope this is not needed for MULT
 778     */
 779    if ((rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &
 780        ((3 << RADEON_EMISSIVE_SOURCE_SHIFT) |
 781         (3 << RADEON_AMBIENT_SOURCE_SHIFT))) == 0)
 782    {
 783       COPY_3V( &fcmd[GLT_RED],
 784                ctx->Light.Material.Attrib[MAT_ATTRIB_FRONT_EMISSION]);
 785       ACC_SCALE_3V( &fcmd[GLT_RED],
 786                    ctx->Light.Model.Ambient,
 787                    ctx->Light.Material.Attrib[MAT_ATTRIB_FRONT_AMBIENT]);
 788    }
 789    else
 790    {
 791       COPY_3V( &fcmd[GLT_RED], ctx->Light.Model.Ambient );
 792    }
 793
 794    RADEON_DB_STATECHANGE(rmesa, &rmesa->hw.glt);
 795 }
 796
 797 /* Update on change to
 798  *    - light[p].colors
 799  *    - light[p].enabled
 800  */
 801 static void update_light_colors( GLcontext *ctx, GLuint p )
 802 {
 803    struct gl_light *l = &ctx->Light.Light[p];
 804
 805 /*     fprintf(stderr, "%s\n", __FUNCTION__); */
 806
 807    if (l->Enabled) {
 808       radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 809       float *fcmd = (float *)RADEON_DB_STATE( lit[p] );
 810
 811       COPY_4V( &fcmd[LIT_AMBIENT_RED], l->Ambient );
 812       COPY_4V( &fcmd[LIT_DIFFUSE_RED], l->Diffuse );
 813       COPY_4V( &fcmd[LIT_SPECULAR_RED], l->Specular );
 814
 815       RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.lit[p] );
 816    }
 817 }
 818
 819 /* Also fallback for asym colormaterial mode in twoside lighting...
 820  */
 821 static void check_twoside_fallback( GLcontext *ctx )
 822 {
 823    GLboolean fallback = GL_FALSE;
 824    GLint i;
 825
 826    if (ctx->Light.Enabled && ctx->Light.Model.TwoSide) {
 827       if (ctx->Light.ColorMaterialEnabled &&
 828           (ctx->Light.ColorMaterialBitmask & BACK_MATERIAL_BITS) !=
 829           ((ctx->Light.ColorMaterialBitmask & FRONT_MATERIAL_BITS)<<1))
 830          fallback = GL_TRUE;
 831       else {
 832          for (i = MAT_ATTRIB_FRONT_AMBIENT; i < MAT_ATTRIB_FRONT_INDEXES; i+=2)
 833             if (memcmp( ctx->Light.Material.Attrib[i],
 834                         ctx->Light.Material.Attrib[i+1],
 835                         sizeof(GLfloat)*4) != 0) {
 836                fallback = GL_TRUE;
 837                break;
 838             }
 839       }
 840    }
 841
 842    TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_LIGHT_TWOSIDE, fallback );
 843 }
 844
 845
 846 static void radeonColorMaterial( GLcontext *ctx, GLenum face, GLenum mode )
 847 {
 848       radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 849       GLuint light_model_ctl1 = rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL];
 850
 851       light_model_ctl1 &= ~((3 << RADEON_EMISSIVE_SOURCE_SHIFT) |
 852                            (3 << RADEON_AMBIENT_SOURCE_SHIFT) |
 853                            (3 << RADEON_DIFFUSE_SOURCE_SHIFT) |
 854                            (3 << RADEON_SPECULAR_SOURCE_SHIFT));
 855
 856    if (ctx->Light.ColorMaterialEnabled) {
 857       GLuint mask = ctx->Light.ColorMaterialBitmask;
 858
 859       if (mask & MAT_BIT_FRONT_EMISSION) {
 860          light_model_ctl1 |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE <<
 861                              RADEON_EMISSIVE_SOURCE_SHIFT);
 862       }
 863       else {
 864          light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT <<
 865                              RADEON_EMISSIVE_SOURCE_SHIFT);
 866       }
 867
 868       if (mask & MAT_BIT_FRONT_AMBIENT) {
 869          light_model_ctl1 |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE <<
 870                              RADEON_AMBIENT_SOURCE_SHIFT);
 871       }
 872       else {
 873          light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT <<
 874                              RADEON_AMBIENT_SOURCE_SHIFT);
 875       }
 876
 877       if (mask & MAT_BIT_FRONT_DIFFUSE) {
 878          light_model_ctl1 |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE <<
 879                              RADEON_DIFFUSE_SOURCE_SHIFT);
 880       }
 881       else {
 882          light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT <<
 883                              RADEON_DIFFUSE_SOURCE_SHIFT);
 884       }
 885
 886       if (mask & MAT_BIT_FRONT_SPECULAR) {
 887          light_model_ctl1 |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE <<
 888                              RADEON_SPECULAR_SOURCE_SHIFT);
 889       }
 890       else {
 891          light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT <<
 892                              RADEON_SPECULAR_SOURCE_SHIFT);
 893       }
 894    }
 895    else {
 896    /* Default to MULT:
 897     */
 898       light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) |
 899                    (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) |
 900                    (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
 901                    (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT);
 902    }
 903
 904       if (light_model_ctl1 != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]) {
 905          RADEON_STATECHANGE( rmesa, tcl );
 906          rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = light_model_ctl1;
 907    }
 908 }
 909
 910 void radeonUpdateMaterial( GLcontext *ctx )
 911 {
 912    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 913    GLfloat (*mat)[4] = ctx->Light.Material.Attrib;
 914    GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( mtl );
 915    GLuint mask = ~0;
 916
 917    if (ctx->Light.ColorMaterialEnabled)
 918       mask &= ~ctx->Light.ColorMaterialBitmask;
 919
 920    if (RADEON_DEBUG & DEBUG_STATE)
 921       fprintf(stderr, "%s\n", __FUNCTION__);
 922
 923
 924    if (mask & MAT_BIT_FRONT_EMISSION) {
 925       fcmd[MTL_EMMISSIVE_RED]   = mat[MAT_ATTRIB_FRONT_EMISSION][0];
 926       fcmd[MTL_EMMISSIVE_GREEN] = mat[MAT_ATTRIB_FRONT_EMISSION][1];
 927       fcmd[MTL_EMMISSIVE_BLUE]  = mat[MAT_ATTRIB_FRONT_EMISSION][2];
 928       fcmd[MTL_EMMISSIVE_ALPHA] = mat[MAT_ATTRIB_FRONT_EMISSION][3];
 929    }
 930    if (mask & MAT_BIT_FRONT_AMBIENT) {
 931       fcmd[MTL_AMBIENT_RED]     = mat[MAT_ATTRIB_FRONT_AMBIENT][0];
 932       fcmd[MTL_AMBIENT_GREEN]   = mat[MAT_ATTRIB_FRONT_AMBIENT][1];
 933       fcmd[MTL_AMBIENT_BLUE]    = mat[MAT_ATTRIB_FRONT_AMBIENT][2];
 934       fcmd[MTL_AMBIENT_ALPHA]   = mat[MAT_ATTRIB_FRONT_AMBIENT][3];
 935    }
 936    if (mask & MAT_BIT_FRONT_DIFFUSE) {
 937       fcmd[MTL_DIFFUSE_RED]     = mat[MAT_ATTRIB_FRONT_DIFFUSE][0];
 938       fcmd[MTL_DIFFUSE_GREEN]   = mat[MAT_ATTRIB_FRONT_DIFFUSE][1];
 939       fcmd[MTL_DIFFUSE_BLUE]    = mat[MAT_ATTRIB_FRONT_DIFFUSE][2];
 940       fcmd[MTL_DIFFUSE_ALPHA]   = mat[MAT_ATTRIB_FRONT_DIFFUSE][3];
 941    }
 942    if (mask & MAT_BIT_FRONT_SPECULAR) {
 943       fcmd[MTL_SPECULAR_RED]    = mat[MAT_ATTRIB_FRONT_SPECULAR][0];
 944       fcmd[MTL_SPECULAR_GREEN]  = mat[MAT_ATTRIB_FRONT_SPECULAR][1];
 945       fcmd[MTL_SPECULAR_BLUE]   = mat[MAT_ATTRIB_FRONT_SPECULAR][2];
 946       fcmd[MTL_SPECULAR_ALPHA]  = mat[MAT_ATTRIB_FRONT_SPECULAR][3];
 947    }
 948    if (mask & MAT_BIT_FRONT_SHININESS) {
 949       fcmd[MTL_SHININESS]       = mat[MAT_ATTRIB_FRONT_SHININESS][0];
 950    }
 951
 952    RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.mtl );
 953
 954    check_twoside_fallback( ctx );
 955 /*   update_global_ambient( ctx );*/
 956 }
 957
 958 /* _NEW_LIGHT
 959  * _NEW_MODELVIEW
 960  * _MESA_NEW_NEED_EYE_COORDS
 961  *
 962  * Uses derived state from mesa:
 963  *       _VP_inf_norm
 964  *       _h_inf_norm
 965  *       _Position
 966  *       _NormDirection
 967  *       _ModelViewInvScale
 968  *       _NeedEyeCoords
 969  *       _EyeZDir
 970  *
 971  * which are calculated in light.c and are correct for the current
 972  * lighting space (model or eye), hence dependencies on _NEW_MODELVIEW
 973  * and _MESA_NEW_NEED_EYE_COORDS.
 974  */
 975 static void update_light( GLcontext *ctx )
 976 {
 977    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 978
 979    /* Have to check these, or have an automatic shortcircuit mechanism
 980     * to remove noop statechanges. (Or just do a better job on the
 981     * front end).
 982     */
 983    {
 984       GLuint tmp = rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL];
 985
 986       if (ctx->_NeedEyeCoords)
 987          tmp &= ~RADEON_LIGHT_IN_MODELSPACE;
 988       else
 989          tmp |= RADEON_LIGHT_IN_MODELSPACE;
 990
 991
 992       /* Leave this test disabled: (unexplained q3 lockup) (even with
 993          new packets)
 994       */
 995       if (tmp != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL])
 996       {
 997          RADEON_STATECHANGE( rmesa, tcl );
 998          rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = tmp;
 999       }
1000    }
1001
1002    {
1003       GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( eye );
1004       fcmd[EYE_X] = ctx->_EyeZDir[0];
1005       fcmd[EYE_Y] = ctx->_EyeZDir[1];
1006       fcmd[EYE_Z] = - ctx->_EyeZDir[2];
1007       fcmd[EYE_RESCALE_FACTOR] = ctx->_ModelViewInvScale;
1008       RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.eye );
1009    }
1010
1011
1012
1013    if (ctx->Light.Enabled) {
1014       GLint p;
1015       for (p = 0 ; p < MAX_LIGHTS; p++) {
1016          if (ctx->Light.Light[p].Enabled) {
1017             struct gl_light *l = &ctx->Light.Light[p];
1018             GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( lit[p] );
1019
1020             if (l->EyePosition[3] == 0.0) {
1021                COPY_3FV( &fcmd[LIT_POSITION_X], l->_VP_inf_norm );
1022                COPY_3FV( &fcmd[LIT_DIRECTION_X], l->_h_inf_norm );
1023                fcmd[LIT_POSITION_W] = 0;
1024                fcmd[LIT_DIRECTION_W] = 0;
1025             } else {
1026                COPY_4V( &fcmd[LIT_POSITION_X], l->_Position );
1027                fcmd[LIT_DIRECTION_X] = -l->_NormDirection[0];
1028                fcmd[LIT_DIRECTION_Y] = -l->_NormDirection[1];
1029                fcmd[LIT_DIRECTION_Z] = -l->_NormDirection[2];
1030                fcmd[LIT_DIRECTION_W] = 0;
1031             }
1032
1033             RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.lit[p] );
1034          }
1035       }
1036    }
1037 }
1038
1039 static void radeonLightfv( GLcontext *ctx, GLenum light,
1040                            GLenum pname, const GLfloat *params )
1041 {
1042    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
1043    GLint p = light - GL_LIGHT0;
1044    struct gl_light *l = &ctx->Light.Light[p];
1045    GLfloat *fcmd = (GLfloat *)rmesa->hw.lit[p].cmd;
1046
1047
1048    switch (pname) {
1049    case GL_AMBIENT:
1050    case GL_DIFFUSE:
1051    case GL_SPECULAR:
1052       update_light_colors( ctx, p );
1053       break;
1054
1055    case GL_SPOT_DIRECTION:
1056       /* picked up in update_light */
1057       break;
1058
1059    case GL_POSITION: {
1060       /* positions picked up in update_light, but can do flag here */
1061       GLuint flag;
1062       GLuint idx = TCL_PER_LIGHT_CTL_0 + p/2;
1063
1064       /* FIXME: Set RANGE_ATTEN only when needed */
1065       if (p&1)
1066          flag = RADEON_LIGHT_1_IS_LOCAL;
1067       else
1068          flag = RADEON_LIGHT_0_IS_LOCAL;
1069
1070       RADEON_STATECHANGE(rmesa, tcl);
1071       if (l->EyePosition[3] != 0.0F)
1072          rmesa->hw.tcl.cmd[idx] |= flag;
1073       else
1074          rmesa->hw.tcl.cmd[idx] &= ~flag;
1075       break;
1076    }
1077
1078    case GL_SPOT_EXPONENT:
1079       RADEON_STATECHANGE(rmesa, lit[p]);
1080       fcmd[LIT_SPOT_EXPONENT] = params[0];
1081       break;
1082
1083    case GL_SPOT_CUTOFF: {
1084       GLuint flag = (p&1) ? RADEON_LIGHT_1_IS_SPOT : RADEON_LIGHT_0_IS_SPOT;
1085       GLuint idx = TCL_PER_LIGHT_CTL_0 + p/2;
1086
1087       RADEON_STATECHANGE(rmesa, lit[p]);
1088       fcmd[LIT_SPOT_CUTOFF] = l->_CosCutoff;
1089
1090       RADEON_STATECHANGE(rmesa, tcl);
1091       if (l->SpotCutoff != 180.0F)
1092          rmesa->hw.tcl.cmd[idx] |= flag;
1093       else
1094          rmesa->hw.tcl.cmd[idx] &= ~flag;
1095
1096       break;
1097    }
1098
1099    case GL_CONSTANT_ATTENUATION:
1100       RADEON_STATECHANGE(rmesa, lit[p]);
1101       fcmd[LIT_ATTEN_CONST] = params[0];
1102       if ( params[0] == 0.0 )
1103          fcmd[LIT_ATTEN_CONST_INV] = FLT_MAX;
1104       else
1105          fcmd[LIT_ATTEN_CONST_INV] = 1.0 / params[0];
1106       break;
1107    case GL_LINEAR_ATTENUATION:
1108       RADEON_STATECHANGE(rmesa, lit[p]);
1109       fcmd[LIT_ATTEN_LINEAR] = params[0];
1110       break;
1111    case GL_QUADRATIC_ATTENUATION:
1112       RADEON_STATECHANGE(rmesa, lit[p]);
1113       fcmd[LIT_ATTEN_QUADRATIC] = params[0];
1114       break;
1115    default:
1116       return;
1117    }
1118
1119    /* Set RANGE_ATTEN only when needed */
1120    switch (pname) {
1121    case GL_POSITION:
1122    case GL_CONSTANT_ATTENUATION:
1123    case GL_LINEAR_ATTENUATION:
1124    case GL_QUADRATIC_ATTENUATION:
1125    {
1126       GLuint *icmd = (GLuint *)RADEON_DB_STATE( tcl );
1127       GLuint idx = TCL_PER_LIGHT_CTL_0 + p/2;
1128       GLuint atten_flag = ( p&1 ) ? RADEON_LIGHT_1_ENABLE_RANGE_ATTEN
1129                                   : RADEON_LIGHT_0_ENABLE_RANGE_ATTEN;
1130       GLuint atten_const_flag = ( p&1 ) ? RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN
1131                                   : RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN;
1132
1133       if ( l->EyePosition[3] == 0.0F ||
1134            ( ( fcmd[LIT_ATTEN_CONST] == 0.0 || fcmd[LIT_ATTEN_CONST] == 1.0 ) &&
1135              fcmd[LIT_ATTEN_QUADRATIC] == 0.0 && fcmd[LIT_ATTEN_LINEAR] == 0.0 ) ) {
1136          /* Disable attenuation */
1137          icmd[idx] &= ~atten_flag;
1138       } else {
1139          if ( fcmd[LIT_ATTEN_QUADRATIC] == 0.0 && fcmd[LIT_ATTEN_LINEAR] == 0.0 ) {
1140             /* Enable only constant portion of attenuation calculation */
1141             icmd[idx] |= ( atten_flag | atten_const_flag );
1142          } else {
1143             /* Enable full attenuation calculation */
1144             icmd[idx] &= ~atten_const_flag;
1145             icmd[idx] |= atten_flag;
1146          }
1147       }
1148
1149       RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.tcl );
1150       break;
1151    }
1152    default:
1153       break;
1154    }
1155 }
1156
1157
1158
1159
1160 static void radeonLightModelfv( GLcontext *ctx, GLenum pname,
1161                                 const GLfloat *param )
1162 {
1163    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
1164
1165    switch (pname) {
1166       case GL_LIGHT_MODEL_AMBIENT:
1167          update_global_ambient( ctx );
1168          break;
1169
1170       case GL_LIGHT_MODEL_LOCAL_VIEWER:
1171          RADEON_STATECHANGE( rmesa, tcl );
1172          if (ctx->Light.Model.LocalViewer)
1173             rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LOCAL_VIEWER;
1174          else
1175             rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_LOCAL_VIEWER;
1176          break;
1177
1178       case GL_LIGHT_MODEL_TWO_SIDE:
1179          RADEON_STATECHANGE( rmesa, tcl );
1180          if (ctx->Light.Model.TwoSide)
1181             rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_LIGHT_TWOSIDE;
1182          else
1183             rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_LIGHT_TWOSIDE;
1184
1185          check_twoside_fallback( ctx );
1186
1187          if (rmesa->TclFallback) {
1188             radeonChooseRenderState( ctx );
1189             radeonChooseVertexState( ctx );
1190          }
1191          break;
1192
1193       case GL_LIGHT_MODEL_COLOR_CONTROL:
1194          radeonUpdateSpecular(ctx);
1195          break;
1196
1197       default:
1198          break;
1199    }
1200 }
1201
1202 static void radeonShadeModel( GLcontext *ctx, GLenum mode )
1203 {
1204    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
1205    GLuint s = rmesa->hw.set.cmd[SET_SE_CNTL];
1206
1207    s &= ~(RADEON_DIFFUSE_SHADE_MASK |
1208           RADEON_ALPHA_SHADE_MASK |
1209           RADEON_SPECULAR_SHADE_MASK |
1210           RADEON_FOG_SHADE_MASK);
1211
1212    switch ( mode ) {
1213    case GL_FLAT:
1214       s |= (RADEON_DIFFUSE_SHADE_FLAT |
1215             RADEON_ALPHA_SHADE_FLAT |
1216             RADEON_SPECULAR_SHADE_FLAT |
1217             RADEON_FOG_SHADE_FLAT);
1218       break;
1219    case GL_SMOOTH:
1220       s |= (RADEON_DIFFUSE_SHADE_GOURAUD |
1221             RADEON_ALPHA_SHADE_GOURAUD |
1222             RADEON_SPECULAR_SHADE_GOURAUD |
1223             RADEON_FOG_SHADE_GOURAUD);
1224       break;
1225    default:
1226       return;
1227    }
1228
1229    if ( rmesa->hw.set.cmd[SET_SE_CNTL] != s ) {
1230       RADEON_STATECHANGE( rmesa, set );
1231       rmesa->hw.set.cmd[SET_SE_CNTL] = s;
1232    }
1233 }
1234
1235
1236 /* =============================================================
1237  * User clip planes
1238  */
1239
1240 static void radeonClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1241 {
1242    GLint p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1243    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
1244    GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1245
1246    RADEON_STATECHANGE( rmesa, ucp[p] );
1247    rmesa->hw.ucp[p].cmd[UCP_X] = ip[0];
1248    rmesa->hw.ucp[p].cmd[UCP_Y] = ip[1];
1249    rmesa->hw.ucp[p].cmd[UCP_Z] = ip[2];
1250    rmesa->hw.ucp[p].cmd[UCP_W] = ip[3];
1251 }
1252
1253 static void radeonUpdateClipPlanes( GLcontext *ctx )
1254 {
1255    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
1256    GLuint p;
1257
1258    for (p = 0; p < ctx->Const.MaxClipPlanes; p++) {
1259       if (ctx->Transform.ClipPlanesEnabled & (1 << p)) {
1260          GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1261
1262          RADEON_STATECHANGE( rmesa, ucp[p] );
1263          rmesa->hw.ucp[p].cmd[UCP_X] = ip[0];
1264          rmesa->hw.ucp[p].cmd[UCP_Y] = ip[1];
1265          rmesa->hw.ucp[p].cmd[UCP_Z] = ip[2];
1266          rmesa->hw.ucp[p].cmd[UCP_W] = ip[3];
1267       }
1268    }
1269 }
1270
1271
1272 /* =============================================================
1273  * Stencil
1274  */
1275
1276 static void
1277 radeonStencilFuncSeparate( GLcontext *ctx, GLenum face, GLenum func,
1278                            GLint ref, GLuint mask )
1279 {
1280    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
1281    GLuint refmask = ((ctx->Stencil.Ref[0] << RADEON_STENCIL_REF_SHIFT) |
1282                      (ctx->Stencil.ValueMask[0] << RADEON_STENCIL_MASK_SHIFT));
1283
1284    RADEON_STATECHANGE( rmesa, ctx );
1285    RADEON_STATECHANGE( rmesa, msk );
1286
1287    rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_STENCIL_TEST_MASK;
1288    rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] &= ~(RADEON_STENCIL_REF_MASK|
1289                                                    RADEON_STENCIL_VALUE_MASK);
1290
1291    switch ( ctx->Stencil.Function[0] ) {
1292    case GL_NEVER:
1293       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_NEVER;
1294       break;
1295    case GL_LESS:
1296       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_LESS;
1297       break;
1298    case GL_EQUAL:
1299       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_EQUAL;
1300       break;
1301    case GL_LEQUAL:
1302       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_LEQUAL;
1303       break;
1304    case GL_GREATER:
1305       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_GREATER;
1306       break;
1307    case GL_NOTEQUAL:
1308       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_NEQUAL;
1309       break;
1310    case GL_GEQUAL:
1311       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_GEQUAL;
1312       break;
1313    case GL_ALWAYS:
1314       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_ALWAYS;
1315       break;
1316    }
1317
1318    rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] |= refmask;
1319 }
1320
1321 static void
1322 radeonStencilMaskSeparate( GLcontext *ctx, GLenum face, GLuint mask )
1323 {
1324    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
1325
1326    RADEON_STATECHANGE( rmesa, msk );
1327    rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] &= ~RADEON_STENCIL_WRITE_MASK;
1328    rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] |=
1329       (ctx->Stencil.WriteMask[0] << RADEON_STENCIL_WRITEMASK_SHIFT);
1330 }
1331
1332 static void radeonStencilOpSeparate( GLcontext *ctx, GLenum face, GLenum fail,
1333                                      GLenum zfail, GLenum zpass )
1334 {
1335    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
1336
1337    /* radeon 7200 have stencil bug, DEC and INC_WRAP will actually both do DEC_WRAP,
1338       and DEC_WRAP (and INVERT) will do INVERT. No way to get correct INC_WRAP and DEC,
1339       but DEC_WRAP can be fixed by using DEC and INC_WRAP at least use INC. */
1340
1341    GLuint tempRADEON_STENCIL_FAIL_DEC_WRAP;
1342    GLuint tempRADEON_STENCIL_FAIL_INC_WRAP;
1343    GLuint tempRADEON_STENCIL_ZFAIL_DEC_WRAP;
1344    GLuint tempRADEON_STENCIL_ZFAIL_INC_WRAP;
1345    GLuint tempRADEON_STENCIL_ZPASS_DEC_WRAP;
1346    GLuint tempRADEON_STENCIL_ZPASS_INC_WRAP;
1347
1348    if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_BROKEN_STENCIL) {
1349       tempRADEON_STENCIL_FAIL_DEC_WRAP = RADEON_STENCIL_FAIL_DEC;
1350       tempRADEON_STENCIL_FAIL_INC_WRAP = RADEON_STENCIL_FAIL_INC;
1351       tempRADEON_STENCIL_ZFAIL_DEC_WRAP = RADEON_STENCIL_ZFAIL_DEC;
1352       tempRADEON_STENCIL_ZFAIL_INC_WRAP = RADEON_STENCIL_ZFAIL_INC;
1353       tempRADEON_STENCIL_ZPASS_DEC_WRAP = RADEON_STENCIL_ZPASS_DEC;
1354       tempRADEON_STENCIL_ZPASS_INC_WRAP = RADEON_STENCIL_ZPASS_INC;
1355    }
1356    else {
1357       tempRADEON_STENCIL_FAIL_DEC_WRAP = RADEON_STENCIL_FAIL_DEC_WRAP;
1358       tempRADEON_STENCIL_FAIL_INC_WRAP = RADEON_STENCIL_FAIL_INC_WRAP;
1359       tempRADEON_STENCIL_ZFAIL_DEC_WRAP = RADEON_STENCIL_ZFAIL_DEC_WRAP;
1360       tempRADEON_STENCIL_ZFAIL_INC_WRAP = RADEON_STENCIL_ZFAIL_INC_WRAP;
1361       tempRADEON_STENCIL_ZPASS_DEC_WRAP = RADEON_STENCIL_ZPASS_DEC_WRAP;
1362       tempRADEON_STENCIL_ZPASS_INC_WRAP = RADEON_STENCIL_ZPASS_INC_WRAP;
1363    }
1364
1365    RADEON_STATECHANGE( rmesa, ctx );
1366    rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~(RADEON_STENCIL_FAIL_MASK |
1367                                                RADEON_STENCIL_ZFAIL_MASK |
1368                                                RADEON_STENCIL_ZPASS_MASK);
1369
1370    switch ( ctx->Stencil.FailFunc[0] ) {
1371    case GL_KEEP:
1372       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_KEEP;
1373       break;
1374    case GL_ZERO:
1375       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_ZERO;
1376       break;
1377    case GL_REPLACE:
1378       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_REPLACE;
1379       break;
1380    case GL_INCR:
1381       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_INC;
1382       break;
1383    case GL_DECR:
1384       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_DEC;
1385       break;
1386    case GL_INCR_WRAP:
1387       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_FAIL_INC_WRAP;
1388       break;
1389    case GL_DECR_WRAP:
1390       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_FAIL_DEC_WRAP;
1391       break;
1392    case GL_INVERT:
1393       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_INVERT;
1394       break;
1395    }
1396
1397    switch ( ctx->Stencil.ZFailFunc[0] ) {
1398    case GL_KEEP:
1399       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_KEEP;
1400       break;
1401    case GL_ZERO:
1402       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_ZERO;
1403       break;
1404    case GL_REPLACE:
1405       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_REPLACE;
1406       break;
1407    case GL_INCR:
1408       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_INC;
1409       break;
1410    case GL_DECR:
1411       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_DEC;
1412       break;
1413    case GL_INCR_WRAP:
1414       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZFAIL_INC_WRAP;
1415       break;
1416    case GL_DECR_WRAP:
1417       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZFAIL_DEC_WRAP;
1418       break;
1419    case GL_INVERT:
1420       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_INVERT;
1421       break;
1422    }
1423
1424    switch ( ctx->Stencil.ZPassFunc[0] ) {
1425    case GL_KEEP:
1426       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_KEEP;
1427       break;
1428    case GL_ZERO:
1429       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_ZERO;
1430       break;
1431    case GL_REPLACE:
1432       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_REPLACE;
1433       break;
1434    case GL_INCR:
1435       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_INC;
1436       break;
1437    case GL_DECR:
1438       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_DEC;
1439       break;
1440    case GL_INCR_WRAP:
1441       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZPASS_INC_WRAP;
1442       break;
1443    case GL_DECR_WRAP:
1444       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZPASS_DEC_WRAP;
1445       break;
1446    case GL_INVERT:
1447       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_INVERT;
1448       break;
1449    }
1450 }
1451
1452 static void radeonClearStencil( GLcontext *ctx, GLint s )
1453 {
1454    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
1455
1456    rmesa->state.stencil.clear =
1457       ((GLuint) ctx->Stencil.Clear |
1458        (0xff << RADEON_STENCIL_MASK_SHIFT) |
1459        (ctx->Stencil.WriteMask[0] << RADEON_STENCIL_WRITEMASK_SHIFT));
1460 }
1461
1462
1463 /* =============================================================
1464  * Window position and viewport transformation
1465  */
1466
1467 /*
1468  * To correctly position primitives:
1469  */
1470 #define SUBPIXEL_X 0.125
1471 #define SUBPIXEL_Y 0.125
1472
1473
1474 /**
1475  * Called when window size or position changes or viewport or depth range
1476  * state is changed.  We update the hardware viewport state here.
1477  */
1478 void radeonUpdateWindow( GLcontext *ctx )
1479 {
1480    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
1481    __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
1482    GLfloat xoffset = (GLfloat)dPriv->x;
1483    GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h;
1484    const GLfloat *v = ctx->Viewport._WindowMap.m;
1485
1486    GLfloat sx = v[MAT_SX];
1487    GLfloat tx = v[MAT_TX] + xoffset + SUBPIXEL_X;
1488    GLfloat sy = - v[MAT_SY];
1489    GLfloat ty = (- v[MAT_TY]) + yoffset + SUBPIXEL_Y;
1490    GLfloat sz = v[MAT_SZ] * rmesa->state.depth.scale;
1491    GLfloat tz = v[MAT_TZ] * rmesa->state.depth.scale;
1492    RADEON_FIREVERTICES( rmesa );
1493    RADEON_STATECHANGE( rmesa, vpt );
1494
1495    rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE]  = *(GLuint *)&sx;
1496    rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = *(GLuint *)&tx;
1497    rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE]  = *(GLuint *)&sy;
1498    rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = *(GLuint *)&ty;
1499    rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE]  = *(GLuint *)&sz;
1500    rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = *(GLuint *)&tz;
1501 }
1502
1503
1504
1505 static void radeonViewport( GLcontext *ctx, GLint x, GLint y,
1506                             GLsizei width, GLsizei height )
1507 {
1508    /* update size of Mesa/software ancillary buffers */
1509    _mesa_ResizeBuffersMESA();
1510    /* Don't pipeline viewport changes, conflict with window offset
1511     * setting below.  Could apply deltas to rescue pipelined viewport
1512     * values, or keep the originals hanging around.
1513     */
1514    RADEON_FIREVERTICES( RADEON_CONTEXT(ctx) );
1515    radeonUpdateWindow( ctx );
1516 }
1517
1518 static void radeonDepthRange( GLcontext *ctx, GLclampd nearval,
1519                               GLclampd farval )
1520 {
1521    radeonUpdateWindow( ctx );
1522 }
1523
1524 void radeonUpdateViewportOffset( GLcontext *ctx )
1525 {
1526    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
1527    __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
1528    GLfloat xoffset = (GLfloat)dPriv->x;
1529    GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h;
1530    const GLfloat *v = ctx->Viewport._WindowMap.m;
1531
1532    GLfloat tx = v[MAT_TX] + xoffset + SUBPIXEL_X;
1533    GLfloat ty = (- v[MAT_TY]) + yoffset + SUBPIXEL_Y;
1534
1535    if ( rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] != *(GLuint *)&tx ||
1536         rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] != *(GLuint *)&ty )
1537    {
1538       /* Note: this should also modify whatever data the context reset
1539        * code uses...
1540        */
1541       rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = *(GLuint *)&tx;
1542       rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = *(GLuint *)&ty;
1543
1544       /* update polygon stipple x/y screen offset */
1545       {
1546          GLuint stx, sty;
1547          GLuint m = rmesa->hw.msc.cmd[MSC_RE_MISC];
1548
1549          m &= ~(RADEON_STIPPLE_X_OFFSET_MASK |
1550                 RADEON_STIPPLE_Y_OFFSET_MASK);
1551
1552          /* add magic offsets, then invert */
1553          stx = 31 - ((rmesa->dri.drawable->x - 1) & RADEON_STIPPLE_COORD_MASK);
1554          sty = 31 - ((rmesa->dri.drawable->y + rmesa->dri.drawable->h - 1)
1555                      & RADEON_STIPPLE_COORD_MASK);
1556
1557          m |= ((stx << RADEON_STIPPLE_X_OFFSET_SHIFT) |
1558                (sty << RADEON_STIPPLE_Y_OFFSET_SHIFT));
1559
1560          if ( rmesa->hw.msc.cmd[MSC_RE_MISC] != m ) {
1561             RADEON_STATECHANGE( rmesa, msc );
1562             rmesa->hw.msc.cmd[MSC_RE_MISC] = m;
1563          }
1564       }
1565    }
1566
1567    radeonUpdateScissor( ctx );
1568 }
1569
1570
1571
1572 /* =============================================================
1573  * Miscellaneous
1574  */
1575
1576 static void radeonClearColor( GLcontext *ctx, const GLfloat color[4] )
1577 {
1578    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
1579    GLubyte c[4];
1580    CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]);
1581    CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]);
1582    CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]);
1583    CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]);
1584    rmesa->state.color.clear = radeonPackColor( rmesa->radeonScreen->cpp,
1585                                                c[0], c[1], c[2], c[3] );
1586 }
1587
1588
1589 static void radeonRenderMode( GLcontext *ctx, GLenum mode )
1590 {
1591    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
1592    FALLBACK( rmesa, RADEON_FALLBACK_RENDER_MODE, (mode != GL_RENDER) );
1593 }
1594
1595
1596 static GLuint radeon_rop_tab[] = {
1597    RADEON_ROP_CLEAR,
1598    RADEON_ROP_AND,
1599    RADEON_ROP_AND_REVERSE,
1600    RADEON_ROP_COPY,
1601    RADEON_ROP_AND_INVERTED,
1602    RADEON_ROP_NOOP,
1603    RADEON_ROP_XOR,
1604    RADEON_ROP_OR,
1605    RADEON_ROP_NOR,
1606    RADEON_ROP_EQUIV,
1607    RADEON_ROP_INVERT,
1608    RADEON_ROP_OR_REVERSE,
1609    RADEON_ROP_COPY_INVERTED,
1610    RADEON_ROP_OR_INVERTED,
1611    RADEON_ROP_NAND,
1612    RADEON_ROP_SET,
1613 };
1614
1615 static void radeonLogicOpCode( GLcontext *ctx, GLenum opcode )
1616 {
1617    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
1618    GLuint rop = (GLuint)opcode - GL_CLEAR;
1619
1620    ASSERT( rop < 16 );
1621
1622    RADEON_STATECHANGE( rmesa, msk );
1623    rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = radeon_rop_tab[rop];
1624 }
1625
1626
1627 /**
1628  * Set up the cliprects for either front or back-buffer drawing.
1629  */
1630 void radeonSetCliprects( radeonContextPtr rmesa )
1631 {
1632    __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
1633
1634    if (rmesa->glCtx->DrawBuffer->_ColorDrawBufferMask[0]
1635        == BUFFER_BIT_BACK_LEFT) {
1636       /* Can't ignore 2d windows if we are page flipping.
1637        */
1638       if ( dPriv->numBackClipRects == 0 || rmesa->doPageFlip ) {
1639          rmesa->numClipRects = dPriv->numClipRects;
1640          rmesa->pClipRects = dPriv->pClipRects;
1641       }
1642       else {
1643          rmesa->numClipRects = dPriv->numBackClipRects;
1644          rmesa->pClipRects = dPriv->pBackClipRects;
1645       }
1646    }
1647    else {
1648       /* front buffer (or none, or multiple buffers */
1649       rmesa->numClipRects = dPriv->numClipRects;
1650       rmesa->pClipRects = dPriv->pClipRects;
1651    }
1652
1653    if (rmesa->state.scissor.enabled)
1654       radeonRecalcScissorRects( rmesa );
1655 }
1656
1657
1658 /**
1659  * Called via glDrawBuffer.
1660  */
1661 static void radeonDrawBuffer( GLcontext *ctx, GLenum mode )
1662 {
1663    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
1664
1665    if (RADEON_DEBUG & DEBUG_DRI)
1666       fprintf(stderr, "%s %s\n", __FUNCTION__,
1667               _mesa_lookup_enum_by_nr( mode ));
1668
1669    RADEON_FIREVERTICES(rmesa);  /* don't pipeline cliprect changes */
1670
1671    /*
1672     * _ColorDrawBufferMask is easier to cope with than <mode>.
1673     * Check for software fallback, update cliprects.
1674     */
1675    switch ( ctx->DrawBuffer->_ColorDrawBufferMask[0] ) {
1676    case BUFFER_BIT_FRONT_LEFT:
1677    case BUFFER_BIT_BACK_LEFT:
1678       FALLBACK( rmesa, RADEON_FALLBACK_DRAW_BUFFER, GL_FALSE );
1679       break;
1680    default:
1681       /* 0 (GL_NONE) buffers or multiple color drawing buffers */
1682       FALLBACK( rmesa, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE );
1683       return;
1684    }
1685
1686    radeonSetCliprects( rmesa );
1687
1688    /* We'll set the drawing engine's offset/pitch parameters later
1689     * when we update other state.
1690     */
1691 }
1692
1693 static void radeonReadBuffer( GLcontext *ctx, GLenum mode )
1694 {
1695    /* nothing, until we implement h/w glRead/CopyPixels or CopyTexImage */
1696 }
1697
1698
1699 /* =============================================================
1700  * State enable/disable
1701  */
1702
1703 static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state )
1704 {
1705    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
1706    GLuint p, flag;
1707
1708    if ( RADEON_DEBUG & DEBUG_STATE )
1709       fprintf( stderr, "%s( %s = %s )\n", __FUNCTION__,
1710                _mesa_lookup_enum_by_nr( cap ),
1711                state ? "GL_TRUE" : "GL_FALSE" );
1712
1713    switch ( cap ) {
1714       /* Fast track this one...
1715        */
1716    case GL_TEXTURE_1D:
1717    case GL_TEXTURE_2D:
1718    case GL_TEXTURE_3D:
1719       break;
1720
1721    case GL_ALPHA_TEST:
1722       RADEON_STATECHANGE( rmesa, ctx );
1723       if (state) {
1724          rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_ALPHA_TEST_ENABLE;
1725       } else {
1726          rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_ALPHA_TEST_ENABLE;
1727       }
1728       break;
1729
1730    case GL_BLEND:
1731       RADEON_STATECHANGE( rmesa, ctx );
1732       if (state) {
1733          rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |=  RADEON_ALPHA_BLEND_ENABLE;
1734       } else {
1735          rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ALPHA_BLEND_ENABLE;
1736       }
1737       if ( ctx->Color._LogicOpEnabled ) {
1738          rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |=  RADEON_ROP_ENABLE;
1739       } else {
1740          rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE;
1741       }
1742
1743       /* Catch a possible fallback:
1744        */
1745       if (state) {
1746          ctx->Driver.BlendEquationSeparate( ctx,
1747                                             ctx->Color.BlendEquationRGB,
1748                                             ctx->Color.BlendEquationA );
1749          ctx->Driver.BlendFuncSeparate( ctx, ctx->Color.BlendSrcRGB,
1750                                         ctx->Color.BlendDstRGB,
1751                                         ctx->Color.BlendSrcA,
1752                                         ctx->Color.BlendDstA );
1753       }
1754       else {
1755          FALLBACK( rmesa, RADEON_FALLBACK_BLEND_FUNC, GL_FALSE );
1756          FALLBACK( rmesa, RADEON_FALLBACK_BLEND_EQ, GL_FALSE );
1757       }
1758       break;
1759
1760    case GL_CLIP_PLANE0:
1761    case GL_CLIP_PLANE1:
1762    case GL_CLIP_PLANE2:
1763    case GL_CLIP_PLANE3:
1764    case GL_CLIP_PLANE4:
1765    case GL_CLIP_PLANE5:
1766       p = cap-GL_CLIP_PLANE0;
1767       RADEON_STATECHANGE( rmesa, tcl );
1768       if (state) {
1769          rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= (RADEON_UCP_ENABLE_0<<p);
1770          radeonClipPlane( ctx, cap, NULL );
1771       }
1772       else {
1773          rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~(RADEON_UCP_ENABLE_0<<p);
1774       }
1775       break;
1776
1777    case GL_COLOR_MATERIAL:
1778       radeonColorMaterial( ctx, 0, 0 );
1779       radeonUpdateMaterial( ctx );
1780       break;
1781
1782    case GL_CULL_FACE:
1783       radeonCullFace( ctx, 0 );
1784       break;
1785
1786    case GL_DEPTH_TEST:
1787       RADEON_STATECHANGE(rmesa, ctx );
1788       if ( state ) {
1789          rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |=  RADEON_Z_ENABLE;
1790       } else {
1791          rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_Z_ENABLE;
1792       }
1793       break;
1794
1795    case GL_DITHER:
1796       RADEON_STATECHANGE(rmesa, ctx );
1797       if ( state ) {
1798          rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |=  RADEON_DITHER_ENABLE;
1799          rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~rmesa->state.color.roundEnable;
1800       } else {
1801          rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_DITHER_ENABLE;
1802          rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |=  rmesa->state.color.roundEnable;
1803       }
1804       break;
1805
1806    case GL_FOG:
1807       RADEON_STATECHANGE(rmesa, ctx );
1808       if ( state ) {
1809          rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_FOG_ENABLE;
1810          radeonFogfv( ctx, GL_FOG_MODE, NULL );
1811       } else {
1812          rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_FOG_ENABLE;
1813          RADEON_STATECHANGE(rmesa, tcl);
1814          rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_TCL_FOG_MASK;
1815       }
1816       radeonUpdateSpecular( ctx ); /* for PK_SPEC */
1817       if (rmesa->TclFallback)
1818          radeonChooseVertexState( ctx );
1819       _mesa_allow_light_in_model( ctx, !state );
1820       break;
1821
1822    case GL_LIGHT0:
1823    case GL_LIGHT1:
1824    case GL_LIGHT2:
1825    case GL_LIGHT3:
1826    case GL_LIGHT4:
1827    case GL_LIGHT5:
1828    case GL_LIGHT6:
1829    case GL_LIGHT7:
1830       RADEON_STATECHANGE(rmesa, tcl);
1831       p = cap - GL_LIGHT0;
1832       if (p&1)
1833          flag = (RADEON_LIGHT_1_ENABLE |
1834                  RADEON_LIGHT_1_ENABLE_AMBIENT |
1835                  RADEON_LIGHT_1_ENABLE_SPECULAR);
1836       else
1837          flag = (RADEON_LIGHT_0_ENABLE |
1838                  RADEON_LIGHT_0_ENABLE_AMBIENT |
1839                  RADEON_LIGHT_0_ENABLE_SPECULAR);
1840
1841       if (state)
1842          rmesa->hw.tcl.cmd[p/2 + TCL_PER_LIGHT_CTL_0] |= flag;
1843       else
1844          rmesa->hw.tcl.cmd[p/2 + TCL_PER_LIGHT_CTL_0] &= ~flag;
1845
1846       /*
1847        */
1848       update_light_colors( ctx, p );
1849       break;
1850
1851    case GL_LIGHTING:
1852       RADEON_STATECHANGE(rmesa, tcl);
1853       radeonUpdateSpecular(ctx);
1854       check_twoside_fallback( ctx );
1855       break;
1856
1857    case GL_LINE_SMOOTH:
1858       RADEON_STATECHANGE( rmesa, ctx );
1859       if ( state ) {
1860          rmesa->hw.ctx.cmd[CTX_PP_CNTL] |=  RADEON_ANTI_ALIAS_LINE;
1861       } else {
1862          rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_ANTI_ALIAS_LINE;
1863       }
1864       break;
1865
1866    case GL_LINE_STIPPLE:
1867       RADEON_STATECHANGE( rmesa, ctx );
1868       if ( state ) {
1869          rmesa->hw.ctx.cmd[CTX_PP_CNTL] |=  RADEON_PATTERN_ENABLE;
1870       } else {
1871          rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_PATTERN_ENABLE;
1872       }
1873       break;
1874
1875    case GL_COLOR_LOGIC_OP:
1876       RADEON_STATECHANGE( rmesa, ctx );
1877       if ( ctx->Color._LogicOpEnabled ) {
1878          rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |=  RADEON_ROP_ENABLE;
1879       } else {
1880          rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE;
1881       }
1882       break;
1883
1884    case GL_NORMALIZE:
1885       RADEON_STATECHANGE( rmesa, tcl );
1886       if ( state ) {
1887          rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |=  RADEON_NORMALIZE_NORMALS;
1888       } else {
1889          rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_NORMALIZE_NORMALS;
1890       }
1891       break;
1892
1893    case GL_POLYGON_OFFSET_POINT:
1894       if (rmesa->dri.drmMinor == 1) {
1895          radeonChooseRenderState( ctx );
1896       }
1897       else {
1898          RADEON_STATECHANGE( rmesa, set );
1899          if ( state ) {
1900             rmesa->hw.set.cmd[SET_SE_CNTL] |=  RADEON_ZBIAS_ENABLE_POINT;
1901          } else {
1902             rmesa->hw.set.cmd[SET_SE_CNTL] &= ~RADEON_ZBIAS_ENABLE_POINT;
1903          }
1904       }
1905       break;
1906
1907    case GL_POLYGON_OFFSET_LINE:
1908       if (rmesa->dri.drmMinor == 1) {
1909          radeonChooseRenderState( ctx );
1910       }
1911       else {
1912          RADEON_STATECHANGE( rmesa, set );
1913          if ( state ) {
1914             rmesa->hw.set.cmd[SET_SE_CNTL] |=  RADEON_ZBIAS_ENABLE_LINE;
1915          } else {
1916             rmesa->hw.set.cmd[SET_SE_CNTL] &= ~RADEON_ZBIAS_ENABLE_LINE;
1917          }
1918       }
1919       break;
1920
1921    case GL_POLYGON_OFFSET_FILL:
1922       if (rmesa->dri.drmMinor == 1) {
1923          radeonChooseRenderState( ctx );
1924       }
1925       else {
1926          RADEON_STATECHANGE( rmesa, set );
1927          if ( state ) {
1928             rmesa->hw.set.cmd[SET_SE_CNTL] |=  RADEON_ZBIAS_ENABLE_TRI;
1929          } else {
1930             rmesa->hw.set.cmd[SET_SE_CNTL] &= ~RADEON_ZBIAS_ENABLE_TRI;
1931          }
1932       }
1933       break;
1934
1935    case GL_POLYGON_SMOOTH:
1936       RADEON_STATECHANGE( rmesa, ctx );
1937       if ( state ) {
1938          rmesa->hw.ctx.cmd[CTX_PP_CNTL] |=  RADEON_ANTI_ALIAS_POLY;
1939       } else {
1940          rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_ANTI_ALIAS_POLY;
1941       }
1942       break;
1943
1944    case GL_POLYGON_STIPPLE:
1945       RADEON_STATECHANGE(rmesa, ctx );
1946       if ( state ) {
1947          rmesa->hw.ctx.cmd[CTX_PP_CNTL] |=  RADEON_STIPPLE_ENABLE;
1948       } else {
1949          rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_STIPPLE_ENABLE;
1950       }
1951       break;
1952
1953    case GL_RESCALE_NORMAL_EXT: {
1954       GLboolean tmp = ctx->_NeedEyeCoords ? state : !state;
1955       RADEON_STATECHANGE( rmesa, tcl );
1956       if ( tmp ) {
1957          rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |=  RADEON_RESCALE_NORMALS;
1958       } else {
1959          rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_RESCALE_NORMALS;
1960       }
1961       break;
1962    }
1963
1964    case GL_SCISSOR_TEST:
1965       RADEON_FIREVERTICES( rmesa );
1966       rmesa->state.scissor.enabled = state;
1967       radeonUpdateScissor( ctx );
1968       break;
1969
1970    case GL_STENCIL_TEST:
1971       if ( rmesa->state.stencil.hwBuffer ) {
1972          RADEON_STATECHANGE( rmesa, ctx );
1973          if ( state ) {
1974             rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |=  RADEON_STENCIL_ENABLE;
1975          } else {
1976             rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_STENCIL_ENABLE;
1977          }
1978       } else {
1979          FALLBACK( rmesa, RADEON_FALLBACK_STENCIL, state );
1980       }
1981       break;
1982
1983    case GL_TEXTURE_GEN_Q:
1984    case GL_TEXTURE_GEN_R:
1985    case GL_TEXTURE_GEN_S:
1986    case GL_TEXTURE_GEN_T:
1987       /* Picked up in radeonUpdateTextureState.
1988        */
1989       rmesa->recheck_texgen[ctx->Texture.CurrentUnit] = GL_TRUE;
1990       break;
1991
1992    case GL_COLOR_SUM_EXT:
1993       radeonUpdateSpecular ( ctx );
1994       break;
1995
1996    default:
1997       return;
1998    }
1999 }
2000
2001
2002 static void radeonLightingSpaceChange( GLcontext *ctx )
2003 {
2004    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
2005    GLboolean tmp;
2006    RADEON_STATECHANGE( rmesa, tcl );
2007
2008    if (RADEON_DEBUG & DEBUG_STATE)
2009       fprintf(stderr, "%s %d BEFORE %x\n", __FUNCTION__, ctx->_NeedEyeCoords,
2010               rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]);
2011
2012    if (ctx->_NeedEyeCoords)
2013       tmp = ctx->Transform.RescaleNormals;
2014    else
2015       tmp = !ctx->Transform.RescaleNormals;
2016
2017    if ( tmp ) {
2018       rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |=  RADEON_RESCALE_NORMALS;
2019    } else {
2020       rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_RESCALE_NORMALS;
2021    }
2022
2023    if (RADEON_DEBUG & DEBUG_STATE)
2024       fprintf(stderr, "%s %d AFTER %x\n", __FUNCTION__, ctx->_NeedEyeCoords,
2025               rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]);
2026 }
2027
2028 /* =============================================================
2029  * Deferred state management - matrices, textures, other?
2030  */
2031
2032
2033
2034
2035 static void upload_matrix( radeonContextPtr rmesa, GLfloat *src, int idx )
2036 {
2037    float *dest = ((float *)RADEON_DB_STATE( mat[idx] ))+MAT_ELT_0;
2038    int i;
2039
2040
2041    for (i = 0 ; i < 4 ; i++) {
2042       *dest++ = src[i];
2043       *dest++ = src[i+4];
2044       *dest++ = src[i+8];
2045       *dest++ = src[i+12];
2046    }
2047
2048    RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.mat[idx] );
2049 }
2050
2051 static void upload_matrix_t( radeonContextPtr rmesa, GLfloat *src, int idx )
2052 {
2053    float *dest = ((float *)RADEON_DB_STATE( mat[idx] ))+MAT_ELT_0;
2054    memcpy(dest, src, 16*sizeof(float));
2055    RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.mat[idx] );
2056 }
2057
2058
2059 static void update_texturematrix( GLcontext *ctx )
2060 {
2061    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
2062    GLuint tpc = rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL];
2063    GLuint vs = rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL];
2064    int unit;
2065
2066    rmesa->TexMatEnabled = 0;
2067
2068    for (unit = 0 ; unit < 2; unit++) {
2069       if (!ctx->Texture.Unit[unit]._ReallyEnabled) {
2070       }
2071       else if (ctx->TextureMatrixStack[unit].Top->type != MATRIX_IDENTITY) {
2072          GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4;
2073
2074          rmesa->TexMatEnabled |= (RADEON_TEXGEN_TEXMAT_0_ENABLE|
2075                                   RADEON_TEXMAT_0_ENABLE) << unit;
2076
2077          if (rmesa->TexGenEnabled & (RADEON_TEXMAT_0_ENABLE << unit)) {
2078             /* Need to preconcatenate any active texgen
2079              * obj/eyeplane matrices:
2080              */
2081             _math_matrix_mul_matrix( &rmesa->tmpmat,
2082                                      &rmesa->TexGenMatrix[unit],
2083                                      ctx->TextureMatrixStack[unit].Top );
2084             upload_matrix( rmesa, rmesa->tmpmat.m, TEXMAT_0+unit );
2085          }
2086          else {
2087             rmesa->TexMatEnabled |=
2088                (RADEON_TEXGEN_INPUT_TEXCOORD_0+unit) << inputshift;
2089             upload_matrix( rmesa, ctx->TextureMatrixStack[unit].Top->m,
2090                            TEXMAT_0+unit );
2091          }
2092       }
2093       else if (rmesa->TexGenEnabled & (RADEON_TEXMAT_0_ENABLE << unit)) {
2094          upload_matrix( rmesa, rmesa->TexGenMatrix[unit].m,
2095                         TEXMAT_0+unit );
2096       }
2097    }
2098
2099
2100    tpc = (rmesa->TexMatEnabled | rmesa->TexGenEnabled);
2101
2102    vs &= ~((0xf << RADEON_TCL_TEX_0_OUTPUT_SHIFT) |
2103            (0xf << RADEON_TCL_TEX_1_OUTPUT_SHIFT));
2104
2105    if (tpc & RADEON_TEXGEN_TEXMAT_0_ENABLE)
2106       vs |= RADEON_TCL_TEX_COMPUTED_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT;
2107    else
2108       vs |= RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT;
2109
2110    if (tpc & RADEON_TEXGEN_TEXMAT_1_ENABLE)
2111       vs |= RADEON_TCL_TEX_COMPUTED_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT;
2112    else
2113       vs |= RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT;
2114
2115    if (tpc != rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] ||
2116        vs != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL]) {
2117
2118       RADEON_STATECHANGE(rmesa, tcl);
2119       rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = tpc;
2120       rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] = vs;
2121    }
2122 }
2123
2124
2125 /**
2126  * Tell the card where to render (offset, pitch).
2127  * Effected by glDrawBuffer, etc
2128  */
2129 void
2130 radeonUpdateDrawBuffer(GLcontext *ctx)
2131 {
2132    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
2133    struct gl_framebuffer *fb = ctx->DrawBuffer;
2134    driRenderbuffer *drb;
2135
2136    if (fb->_ColorDrawBufferMask[0] == BUFFER_BIT_FRONT_LEFT) {
2137       /* draw to front */
2138       drb = (driRenderbuffer *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
2139    }
2140    else if (fb->_ColorDrawBufferMask[0] == BUFFER_BIT_BACK_LEFT) {
2141       /* draw to back */
2142       drb = (driRenderbuffer *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
2143    }
2144    else {
2145       /* drawing to multiple buffers, or none */
2146       return;
2147    }
2148
2149    assert(drb);
2150    assert(drb->flippedPitch);
2151
2152    RADEON_STATECHANGE( rmesa, ctx );
2153
2154    /* Note: we used the (possibly) page-flipped values */
2155    rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET]
2156      = ((drb->flippedOffset + rmesa->radeonScreen->fbLocation)
2157         & RADEON_COLOROFFSET_MASK);
2158    rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = drb->flippedPitch;
2159    if (rmesa->sarea->tiling_enabled) {
2160       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
2161    }
2162 }
2163
2164
2165 void radeonValidateState( GLcontext *ctx )
2166 {
2167    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
2168    GLuint new_state = rmesa->NewGLState;
2169
2170    if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) {
2171      radeonUpdateDrawBuffer(ctx);
2172    }
2173
2174    if (new_state & _NEW_TEXTURE) {
2175       radeonUpdateTextureState( ctx );
2176       new_state |= rmesa->NewGLState; /* may add TEXTURE_MATRIX */
2177    }
2178
2179    /* Need an event driven matrix update?
2180     */
2181    if (new_state & (_NEW_MODELVIEW|_NEW_PROJECTION))
2182       upload_matrix( rmesa, ctx->_ModelProjectMatrix.m, MODEL_PROJ );
2183
2184    /* Need these for lighting (shouldn't upload otherwise)
2185     */
2186    if (new_state & (_NEW_MODELVIEW)) {
2187       upload_matrix( rmesa, ctx->ModelviewMatrixStack.Top->m, MODEL );
2188       upload_matrix_t( rmesa, ctx->ModelviewMatrixStack.Top->inv, MODEL_IT );
2189    }
2190
2191    /* Does this need to be triggered on eg. modelview for
2192     * texgen-derived objplane/eyeplane matrices?
2193     */
2194    if (new_state & _NEW_TEXTURE_MATRIX) {
2195       update_texturematrix( ctx );
2196    }
2197
2198    if (new_state & (_NEW_LIGHT|_NEW_MODELVIEW|_MESA_NEW_NEED_EYE_COORDS)) {
2199       update_light( ctx );
2200    }
2201
2202    /* emit all active clip planes if projection matrix changes.
2203     */
2204    if (new_state & (_NEW_PROJECTION)) {
2205       if (ctx->Transform.ClipPlanesEnabled)
2206          radeonUpdateClipPlanes( ctx );
2207    }
2208
2209
2210    rmesa->NewGLState = 0;
2211 }
2212
2213
2214 static void radeonInvalidateState( GLcontext *ctx, GLuint new_state )
2215 {
2216    _swrast_InvalidateState( ctx, new_state );
2217    _swsetup_InvalidateState( ctx, new_state );
2218    _ac_InvalidateState( ctx, new_state );
2219    _tnl_InvalidateState( ctx, new_state );
2220    _ae_invalidate_state( ctx, new_state );
2221    RADEON_CONTEXT(ctx)->NewGLState |= new_state;
2222    radeonVtxfmtInvalidate( ctx );
2223 }
2224
2225
2226 /* A hack.  Need a faster way to find this out.
2227  */
2228 static GLboolean check_material( GLcontext *ctx )
2229 {
2230    TNLcontext *tnl = TNL_CONTEXT(ctx);
2231    GLint i;
2232
2233    for (i = _TNL_ATTRIB_MAT_FRONT_AMBIENT;
2234         i < _TNL_ATTRIB_MAT_BACK_INDEXES;
2235         i++)
2236       if (tnl->vb.AttribPtr[i] &&
2237           tnl->vb.AttribPtr[i]->stride)
2238          return GL_TRUE;
2239
2240    return GL_FALSE;
2241 }
2242
2243
2244 static void radeonWrapRunPipeline( GLcontext *ctx )
2245 {
2246    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
2247    GLboolean has_material;
2248
2249    if (0)
2250       fprintf(stderr, "%s, newstate: %x\n", __FUNCTION__, rmesa->NewGLState);
2251
2252    /* Validate state:
2253     */
2254    if (rmesa->NewGLState)
2255       radeonValidateState( ctx );
2256
2257    has_material = (ctx->Light.Enabled && check_material( ctx ));
2258
2259    if (has_material) {
2260       TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_MATERIAL, GL_TRUE );
2261    }
2262
2263    /* Run the pipeline.
2264     */
2265    _tnl_run_pipeline( ctx );
2266
2267    if (has_material) {
2268       TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_MATERIAL, GL_FALSE );
2269    }
2270 }
2271
2272
2273 /* Initialize the driver's state functions.
2274  * Many of the ctx->Driver functions might have been initialized to
2275  * software defaults in the earlier _mesa_init_driver_functions() call.
2276  */
2277 void radeonInitStateFuncs( GLcontext *ctx )
2278 {
2279    ctx->Driver.UpdateState              = radeonInvalidateState;
2280    ctx->Driver.LightingSpaceChange      = radeonLightingSpaceChange;
2281
2282    ctx->Driver.DrawBuffer               = radeonDrawBuffer;
2283    ctx->Driver.ReadBuffer               = radeonReadBuffer;
2284
2285    ctx->Driver.AlphaFunc                = radeonAlphaFunc;
2286    ctx->Driver.BlendEquationSeparate    = radeonBlendEquationSeparate;
2287    ctx->Driver.BlendFuncSeparate        = radeonBlendFuncSeparate;
2288    ctx->Driver.ClearColor               = radeonClearColor;
2289    ctx->Driver.ClearDepth               = radeonClearDepth;
2290    ctx->Driver.ClearIndex               = NULL;
2291    ctx->Driver.ClearStencil             = radeonClearStencil;
2292    ctx->Driver.ClipPlane                = radeonClipPlane;
2293    ctx->Driver.ColorMask                = radeonColorMask;
2294    ctx->Driver.CullFace                 = radeonCullFace;
2295    ctx->Driver.DepthFunc                = radeonDepthFunc;
2296    ctx->Driver.DepthMask                = radeonDepthMask;
2297    ctx->Driver.DepthRange               = radeonDepthRange;
2298    ctx->Driver.Enable                   = radeonEnable;
2299    ctx->Driver.Fogfv                    = radeonFogfv;
2300    ctx->Driver.FrontFace                = radeonFrontFace;
2301    ctx->Driver.Hint                     = NULL;
2302    ctx->Driver.IndexMask                = NULL;
2303    ctx->Driver.LightModelfv             = radeonLightModelfv;
2304    ctx->Driver.Lightfv                  = radeonLightfv;
2305    ctx->Driver.LineStipple              = radeonLineStipple;
2306    ctx->Driver.LineWidth                = radeonLineWidth;
2307    ctx->Driver.LogicOpcode              = radeonLogicOpCode;
2308    ctx->Driver.PolygonMode              = radeonPolygonMode;
2309
2310    if (RADEON_CONTEXT(ctx)->dri.drmMinor > 1)
2311       ctx->Driver.PolygonOffset         = radeonPolygonOffset;
2312
2313    ctx->Driver.PolygonStipple           = radeonPolygonStipple;
2314    ctx->Driver.RenderMode               = radeonRenderMode;
2315    ctx->Driver.Scissor                  = radeonScissor;
2316    ctx->Driver.ShadeModel               = radeonShadeModel;
2317    ctx->Driver.StencilFuncSeparate      = radeonStencilFuncSeparate;
2318    ctx->Driver.StencilMaskSeparate      = radeonStencilMaskSeparate;
2319    ctx->Driver.StencilOpSeparate        = radeonStencilOpSeparate;
2320    ctx->Driver.Viewport                 = radeonViewport;
2321
2322    TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange = radeonUpdateMaterial;
2323    TNL_CONTEXT(ctx)->Driver.RunPipeline = radeonWrapRunPipeline;
2324 }