1 /**************************************************************************
3 Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
7 Permission is hereby granted, free of charge, to any person obtaining
8 a copy of this software and associated documentation files (the
9 "Software"), to deal in the Software without restriction, including
10 without limitation the rights to use, copy, modify, merge, publish,
11 distribute, sublicense, and/or sell copies of the Software, and to
12 permit persons to whom the Software is furnished to do so, subject to
13 the following conditions:
15 The above copyright notice and this permission notice (including the
16 next paragraph) shall be included in all copies or substantial
17 portions of the Software.
19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
23 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
24 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
25 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
31 * Gareth Hughes <gareth@valinux.com>
32 * Keith Whitwell <keithw@vmware.com>
35 #include "main/glheader.h"
36 #include "main/imports.h"
37 #include "main/api_arrayelt.h"
38 #include "main/enums.h"
39 #include "main/light.h"
40 #include "main/context.h"
41 #include "main/framebuffer.h"
42 #include "main/fbobject.h"
43 #include "util/simple_list.h"
44 #include "main/state.h"
45 #include "main/core.h"
46 #include "main/stencil.h"
50 #include "tnl/t_pipeline.h"
51 #include "swrast_setup/swrast_setup.h"
52 #include "drivers/common/meta.h"
54 #include "radeon_context.h"
55 #include "radeon_mipmap_tree.h"
56 #include "radeon_ioctl.h"
57 #include "radeon_state.h"
58 #include "radeon_tcl.h"
59 #include "radeon_tex.h"
60 #include "radeon_swtcl.h"
62 static void radeonUpdateSpecular( struct gl_context
*ctx
);
64 /* =============================================================
68 static void radeonAlphaFunc( struct gl_context
*ctx
, GLenum func
, GLfloat ref
)
70 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
71 int pp_misc
= rmesa
->hw
.ctx
.cmd
[CTX_PP_MISC
];
74 CLAMPED_FLOAT_TO_UBYTE(refByte
, ref
);
76 RADEON_STATECHANGE( rmesa
, ctx
);
78 pp_misc
&= ~(RADEON_ALPHA_TEST_OP_MASK
| RADEON_REF_ALPHA_MASK
);
79 pp_misc
|= (refByte
& RADEON_REF_ALPHA_MASK
);
83 pp_misc
|= RADEON_ALPHA_TEST_FAIL
;
86 pp_misc
|= RADEON_ALPHA_TEST_LESS
;
89 pp_misc
|= RADEON_ALPHA_TEST_EQUAL
;
92 pp_misc
|= RADEON_ALPHA_TEST_LEQUAL
;
95 pp_misc
|= RADEON_ALPHA_TEST_GREATER
;
98 pp_misc
|= RADEON_ALPHA_TEST_NEQUAL
;
101 pp_misc
|= RADEON_ALPHA_TEST_GEQUAL
;
104 pp_misc
|= RADEON_ALPHA_TEST_PASS
;
108 rmesa
->hw
.ctx
.cmd
[CTX_PP_MISC
] = pp_misc
;
111 static void radeonBlendEquationSeparate( struct gl_context
*ctx
,
112 GLenum modeRGB
, GLenum modeA
)
114 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
115 GLuint b
= rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] & ~RADEON_COMB_FCN_MASK
;
116 GLboolean fallback
= GL_FALSE
;
118 assert( modeRGB
== modeA
);
123 b
|= RADEON_COMB_FCN_ADD_CLAMP
;
126 case GL_FUNC_SUBTRACT
:
127 b
|= RADEON_COMB_FCN_SUB_CLAMP
;
131 if (ctx
->Color
.BlendEnabled
)
134 b
|= RADEON_COMB_FCN_ADD_CLAMP
;
138 FALLBACK( rmesa
, RADEON_FALLBACK_BLEND_EQ
, fallback
);
140 RADEON_STATECHANGE( rmesa
, ctx
);
141 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] = b
;
142 if ( (ctx
->Color
.ColorLogicOpEnabled
|| (ctx
->Color
.BlendEnabled
143 && ctx
->Color
.Blend
[0].EquationRGB
== GL_LOGIC_OP
)) ) {
144 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_ROP_ENABLE
;
146 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_ROP_ENABLE
;
151 static void radeonBlendFuncSeparate( struct gl_context
*ctx
,
152 GLenum sfactorRGB
, GLenum dfactorRGB
,
153 GLenum sfactorA
, GLenum dfactorA
)
155 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
156 GLuint b
= rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] &
157 ~(RADEON_SRC_BLEND_MASK
| RADEON_DST_BLEND_MASK
);
158 GLboolean fallback
= GL_FALSE
;
160 switch ( ctx
->Color
.Blend
[0].SrcRGB
) {
162 b
|= RADEON_SRC_BLEND_GL_ZERO
;
165 b
|= RADEON_SRC_BLEND_GL_ONE
;
168 b
|= RADEON_SRC_BLEND_GL_DST_COLOR
;
170 case GL_ONE_MINUS_DST_COLOR
:
171 b
|= RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR
;
174 b
|= RADEON_SRC_BLEND_GL_SRC_COLOR
;
176 case GL_ONE_MINUS_SRC_COLOR
:
177 b
|= RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR
;
180 b
|= RADEON_SRC_BLEND_GL_SRC_ALPHA
;
182 case GL_ONE_MINUS_SRC_ALPHA
:
183 b
|= RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA
;
186 b
|= RADEON_SRC_BLEND_GL_DST_ALPHA
;
188 case GL_ONE_MINUS_DST_ALPHA
:
189 b
|= RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA
;
191 case GL_SRC_ALPHA_SATURATE
:
192 b
|= RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE
;
194 case GL_CONSTANT_COLOR
:
195 case GL_ONE_MINUS_CONSTANT_COLOR
:
196 case GL_CONSTANT_ALPHA
:
197 case GL_ONE_MINUS_CONSTANT_ALPHA
:
198 if (ctx
->Color
.BlendEnabled
)
201 b
|= RADEON_SRC_BLEND_GL_ONE
;
207 switch ( ctx
->Color
.Blend
[0].DstRGB
) {
209 b
|= RADEON_DST_BLEND_GL_ZERO
;
212 b
|= RADEON_DST_BLEND_GL_ONE
;
215 b
|= RADEON_DST_BLEND_GL_SRC_COLOR
;
217 case GL_ONE_MINUS_SRC_COLOR
:
218 b
|= RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR
;
221 b
|= RADEON_DST_BLEND_GL_SRC_ALPHA
;
223 case GL_ONE_MINUS_SRC_ALPHA
:
224 b
|= RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA
;
227 b
|= RADEON_DST_BLEND_GL_DST_COLOR
;
229 case GL_ONE_MINUS_DST_COLOR
:
230 b
|= RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR
;
233 b
|= RADEON_DST_BLEND_GL_DST_ALPHA
;
235 case GL_ONE_MINUS_DST_ALPHA
:
236 b
|= RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA
;
238 case GL_CONSTANT_COLOR
:
239 case GL_ONE_MINUS_CONSTANT_COLOR
:
240 case GL_CONSTANT_ALPHA
:
241 case GL_ONE_MINUS_CONSTANT_ALPHA
:
242 if (ctx
->Color
.BlendEnabled
)
245 b
|= RADEON_DST_BLEND_GL_ZERO
;
251 FALLBACK( rmesa
, RADEON_FALLBACK_BLEND_FUNC
, fallback
);
253 RADEON_STATECHANGE( rmesa
, ctx
);
254 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] = b
;
259 /* =============================================================
263 static void radeonDepthFunc( struct gl_context
*ctx
, GLenum func
)
265 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
267 RADEON_STATECHANGE( rmesa
, ctx
);
268 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &= ~RADEON_Z_TEST_MASK
;
270 switch ( ctx
->Depth
.Func
) {
272 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_NEVER
;
275 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_LESS
;
278 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_EQUAL
;
281 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_LEQUAL
;
284 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_GREATER
;
287 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_NEQUAL
;
290 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_GEQUAL
;
293 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_ALWAYS
;
299 static void radeonDepthMask( struct gl_context
*ctx
, GLboolean flag
)
301 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
302 RADEON_STATECHANGE( rmesa
, ctx
);
304 if ( ctx
->Depth
.Mask
) {
305 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_WRITE_ENABLE
;
307 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &= ~RADEON_Z_WRITE_ENABLE
;
312 /* =============================================================
317 static void radeonFogfv( struct gl_context
*ctx
, GLenum pname
, const GLfloat
*param
)
319 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
320 union { int i
; float f
; } c
, d
;
325 if (!ctx
->Fog
.Enabled
)
327 RADEON_STATECHANGE(rmesa
, tcl
);
328 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~RADEON_TCL_FOG_MASK
;
329 switch (ctx
->Fog
.Mode
) {
331 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_TCL_FOG_LINEAR
;
334 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_TCL_FOG_EXP
;
337 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_TCL_FOG_EXP2
;
346 if (!ctx
->Fog
.Enabled
)
348 c
.i
= rmesa
->hw
.fog
.cmd
[FOG_C
];
349 d
.i
= rmesa
->hw
.fog
.cmd
[FOG_D
];
350 switch (ctx
->Fog
.Mode
) {
353 /* While this is the opposite sign from the DDK, it makes the fog test
354 * pass, and matches r200.
356 d
.f
= -ctx
->Fog
.Density
;
360 d
.f
= -(ctx
->Fog
.Density
* ctx
->Fog
.Density
);
363 if (ctx
->Fog
.Start
== ctx
->Fog
.End
) {
367 c
.f
= ctx
->Fog
.End
/(ctx
->Fog
.End
-ctx
->Fog
.Start
);
368 /* While this is the opposite sign from the DDK, it makes the fog
369 * test pass, and matches r200.
371 d
.f
= -1.0/(ctx
->Fog
.End
-ctx
->Fog
.Start
);
377 if (c
.i
!= rmesa
->hw
.fog
.cmd
[FOG_C
] || d
.i
!= rmesa
->hw
.fog
.cmd
[FOG_D
]) {
378 RADEON_STATECHANGE( rmesa
, fog
);
379 rmesa
->hw
.fog
.cmd
[FOG_C
] = c
.i
;
380 rmesa
->hw
.fog
.cmd
[FOG_D
] = d
.i
;
384 RADEON_STATECHANGE( rmesa
, ctx
);
385 _mesa_unclamped_float_rgba_to_ubyte(col
, ctx
->Fog
.Color
);
386 rmesa
->hw
.ctx
.cmd
[CTX_PP_FOG_COLOR
] &= ~RADEON_FOG_COLOR_MASK
;
387 rmesa
->hw
.ctx
.cmd
[CTX_PP_FOG_COLOR
] |=
388 radeonPackColor( 4, col
[0], col
[1], col
[2], 0 );
390 case GL_FOG_COORD_SRC
:
391 radeonUpdateSpecular( ctx
);
398 /* =============================================================
402 static void radeonCullFace( struct gl_context
*ctx
, GLenum unused
)
404 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
405 GLuint s
= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
];
406 GLuint t
= rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
];
408 s
|= RADEON_FFACE_SOLID
| RADEON_BFACE_SOLID
;
409 t
&= ~(RADEON_CULL_FRONT
| RADEON_CULL_BACK
);
411 if ( ctx
->Polygon
.CullFlag
) {
412 switch ( ctx
->Polygon
.CullFaceMode
) {
414 s
&= ~RADEON_FFACE_SOLID
;
415 t
|= RADEON_CULL_FRONT
;
418 s
&= ~RADEON_BFACE_SOLID
;
419 t
|= RADEON_CULL_BACK
;
421 case GL_FRONT_AND_BACK
:
422 s
&= ~(RADEON_FFACE_SOLID
| RADEON_BFACE_SOLID
);
423 t
|= (RADEON_CULL_FRONT
| RADEON_CULL_BACK
);
428 if ( rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] != s
) {
429 RADEON_STATECHANGE(rmesa
, set
);
430 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = s
;
433 if ( rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] != t
) {
434 RADEON_STATECHANGE(rmesa
, tcl
);
435 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] = t
;
439 static void radeonFrontFace( struct gl_context
*ctx
, GLenum mode
)
441 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
442 int cull_face
= (mode
== GL_CW
) ? RADEON_FFACE_CULL_CW
: RADEON_FFACE_CULL_CCW
;
444 RADEON_STATECHANGE( rmesa
, set
);
445 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_FFACE_CULL_DIR_MASK
;
447 RADEON_STATECHANGE( rmesa
, tcl
);
448 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~RADEON_CULL_FRONT_IS_CCW
;
450 /* Winding is inverted when rendering to FBO */
451 if (ctx
->DrawBuffer
&& _mesa_is_user_fbo(ctx
->DrawBuffer
))
452 cull_face
= (mode
== GL_CCW
) ? RADEON_FFACE_CULL_CW
: RADEON_FFACE_CULL_CCW
;
453 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= cull_face
;
455 if ( mode
== GL_CCW
)
456 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_CULL_FRONT_IS_CCW
;
460 /* =============================================================
463 static void radeonLineWidth( struct gl_context
*ctx
, GLfloat widthf
)
465 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
467 RADEON_STATECHANGE( rmesa
, lin
);
468 RADEON_STATECHANGE( rmesa
, set
);
470 /* Line width is stored in U6.4 format.
472 rmesa
->hw
.lin
.cmd
[LIN_SE_LINE_WIDTH
] = (GLuint
)(widthf
* 16.0);
473 if ( widthf
> 1.0 ) {
474 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_WIDELINE_ENABLE
;
476 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_WIDELINE_ENABLE
;
480 static void radeonLineStipple( struct gl_context
*ctx
, GLint factor
, GLushort pattern
)
482 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
484 RADEON_STATECHANGE( rmesa
, lin
);
485 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_PATTERN
] =
486 ((((GLuint
)factor
& 0xff) << 16) | ((GLuint
)pattern
));
490 /* =============================================================
493 static void radeonColorMask( struct gl_context
*ctx
,
494 GLboolean r
, GLboolean g
,
495 GLboolean b
, GLboolean a
)
497 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
498 struct radeon_renderbuffer
*rrb
;
501 rrb
= radeon_get_colorbuffer(&rmesa
->radeon
);
505 mask
= radeonPackColor( rrb
->cpp
,
506 ctx
->Color
.ColorMask
[0][RCOMP
],
507 ctx
->Color
.ColorMask
[0][GCOMP
],
508 ctx
->Color
.ColorMask
[0][BCOMP
],
509 ctx
->Color
.ColorMask
[0][ACOMP
] );
511 if ( rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
] != mask
) {
512 RADEON_STATECHANGE( rmesa
, msk
);
513 rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
] = mask
;
518 /* =============================================================
522 static void radeonPolygonOffset( struct gl_context
*ctx
,
523 GLfloat factor
, GLfloat units
)
525 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
526 const GLfloat depthScale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
527 float_ui32_type constant
= { units
* depthScale
};
528 float_ui32_type factoru
= { factor
};
530 RADEON_STATECHANGE( rmesa
, zbs
);
531 rmesa
->hw
.zbs
.cmd
[ZBS_SE_ZBIAS_FACTOR
] = factoru
.ui32
;
532 rmesa
->hw
.zbs
.cmd
[ZBS_SE_ZBIAS_CONSTANT
] = constant
.ui32
;
535 static void radeonPolygonMode( struct gl_context
*ctx
, GLenum face
, GLenum mode
)
537 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
538 GLboolean unfilled
= (ctx
->Polygon
.FrontMode
!= GL_FILL
||
539 ctx
->Polygon
.BackMode
!= GL_FILL
);
541 /* Can't generally do unfilled via tcl, but some good special
544 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_UNFILLED
, unfilled
);
545 if (rmesa
->radeon
.TclFallback
) {
546 radeonChooseRenderState( ctx
);
547 radeonChooseVertexState( ctx
);
552 /* =============================================================
553 * Rendering attributes
555 * We really don't want to recalculate all this every time we bind a
556 * texture. These things shouldn't change all that often, so it makes
557 * sense to break them out of the core texture state update routines.
560 /* Examine lighting and texture state to determine if separate specular
563 static void radeonUpdateSpecular( struct gl_context
*ctx
)
565 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
566 uint32_t p
= rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
];
569 RADEON_STATECHANGE( rmesa
, tcl
);
571 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] &= ~RADEON_TCL_COMPUTE_SPECULAR
;
572 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] &= ~RADEON_TCL_COMPUTE_DIFFUSE
;
573 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] &= ~RADEON_TCL_VTX_PK_SPEC
;
574 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] &= ~RADEON_TCL_VTX_PK_DIFFUSE
;
575 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_LIGHTING_ENABLE
;
577 p
&= ~RADEON_SPECULAR_ENABLE
;
579 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_DIFFUSE_SPECULAR_COMBINE
;
582 if (ctx
->Light
.Enabled
&&
583 ctx
->Light
.Model
.ColorControl
== GL_SEPARATE_SPECULAR_COLOR
) {
584 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] |= RADEON_TCL_COMPUTE_SPECULAR
;
585 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] |= RADEON_TCL_COMPUTE_DIFFUSE
;
586 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_SPEC
;
587 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_DIFFUSE
;
588 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_LIGHTING_ENABLE
;
589 p
|= RADEON_SPECULAR_ENABLE
;
590 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &=
591 ~RADEON_DIFFUSE_SPECULAR_COMBINE
;
593 else if (ctx
->Light
.Enabled
) {
594 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] |= RADEON_TCL_COMPUTE_DIFFUSE
;
595 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_DIFFUSE
;
596 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_LIGHTING_ENABLE
;
597 } else if (ctx
->Fog
.ColorSumEnabled
) {
598 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_SPEC
;
599 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_DIFFUSE
;
600 p
|= RADEON_SPECULAR_ENABLE
;
602 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_DIFFUSE
;
605 if (ctx
->Fog
.Enabled
) {
606 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_SPEC
;
607 if (ctx
->Fog
.FogCoordinateSource
== GL_FRAGMENT_DEPTH
) {
608 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] |= RADEON_TCL_COMPUTE_SPECULAR
;
609 /* Bizzare: have to leave lighting enabled to get fog. */
610 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_LIGHTING_ENABLE
;
613 /* cannot do tcl fog factor calculation with fog coord source
614 * (send precomputed factors). Cannot use precomputed fog
615 * factors together with tcl spec light (need tcl fallback) */
616 flag
= (rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] &
617 RADEON_TCL_COMPUTE_SPECULAR
) != 0;
621 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_FOGCOORDSPEC
, flag
);
623 if (_mesa_need_secondary_color(ctx
)) {
624 assert( (p
& RADEON_SPECULAR_ENABLE
) != 0 );
626 assert( (p
& RADEON_SPECULAR_ENABLE
) == 0 );
629 if ( rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] != p
) {
630 RADEON_STATECHANGE( rmesa
, ctx
);
631 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] = p
;
634 /* Update vertex/render formats
636 if (rmesa
->radeon
.TclFallback
) {
637 radeonChooseRenderState( ctx
);
638 radeonChooseVertexState( ctx
);
643 /* =============================================================
648 /* Update on colormaterial, material emmissive/ambient,
649 * lightmodel.globalambient
651 static void update_global_ambient( struct gl_context
*ctx
)
653 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
654 float *fcmd
= (float *)RADEON_DB_STATE( glt
);
656 /* Need to do more if both emmissive & ambient are PREMULT:
657 * Hope this is not needed for MULT
659 if ((rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &
660 ((3 << RADEON_EMISSIVE_SOURCE_SHIFT
) |
661 (3 << RADEON_AMBIENT_SOURCE_SHIFT
))) == 0)
663 COPY_3V( &fcmd
[GLT_RED
],
664 ctx
->Light
.Material
.Attrib
[MAT_ATTRIB_FRONT_EMISSION
]);
665 ACC_SCALE_3V( &fcmd
[GLT_RED
],
666 ctx
->Light
.Model
.Ambient
,
667 ctx
->Light
.Material
.Attrib
[MAT_ATTRIB_FRONT_AMBIENT
]);
671 COPY_3V( &fcmd
[GLT_RED
], ctx
->Light
.Model
.Ambient
);
674 RADEON_DB_STATECHANGE(rmesa
, &rmesa
->hw
.glt
);
677 /* Update on change to
681 static void update_light_colors( struct gl_context
*ctx
, GLuint p
)
683 struct gl_light
*l
= &ctx
->Light
.Light
[p
];
685 /* fprintf(stderr, "%s\n", __FUNCTION__); */
688 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
689 float *fcmd
= (float *)RADEON_DB_STATE( lit
[p
] );
691 COPY_4V( &fcmd
[LIT_AMBIENT_RED
], l
->Ambient
);
692 COPY_4V( &fcmd
[LIT_DIFFUSE_RED
], l
->Diffuse
);
693 COPY_4V( &fcmd
[LIT_SPECULAR_RED
], l
->Specular
);
695 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.lit
[p
] );
699 /* Also fallback for asym colormaterial mode in twoside lighting...
701 static void check_twoside_fallback( struct gl_context
*ctx
)
703 GLboolean fallback
= GL_FALSE
;
706 if (ctx
->Light
.Enabled
&& ctx
->Light
.Model
.TwoSide
) {
707 if (ctx
->Light
.ColorMaterialEnabled
&&
708 (ctx
->Light
._ColorMaterialBitmask
& BACK_MATERIAL_BITS
) !=
709 ((ctx
->Light
._ColorMaterialBitmask
& FRONT_MATERIAL_BITS
)<<1))
712 for (i
= MAT_ATTRIB_FRONT_AMBIENT
; i
< MAT_ATTRIB_FRONT_INDEXES
; i
+=2)
713 if (memcmp( ctx
->Light
.Material
.Attrib
[i
],
714 ctx
->Light
.Material
.Attrib
[i
+1],
715 sizeof(GLfloat
)*4) != 0) {
722 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_LIGHT_TWOSIDE
, fallback
);
726 static void radeonColorMaterial( struct gl_context
*ctx
, GLenum face
, GLenum mode
)
728 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
729 GLuint light_model_ctl1
= rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
];
731 light_model_ctl1
&= ~((3 << RADEON_EMISSIVE_SOURCE_SHIFT
) |
732 (3 << RADEON_AMBIENT_SOURCE_SHIFT
) |
733 (3 << RADEON_DIFFUSE_SOURCE_SHIFT
) |
734 (3 << RADEON_SPECULAR_SOURCE_SHIFT
));
736 if (ctx
->Light
.ColorMaterialEnabled
) {
737 GLuint mask
= ctx
->Light
._ColorMaterialBitmask
;
739 if (mask
& MAT_BIT_FRONT_EMISSION
) {
740 light_model_ctl1
|= (RADEON_LM_SOURCE_VERTEX_DIFFUSE
<<
741 RADEON_EMISSIVE_SOURCE_SHIFT
);
744 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<<
745 RADEON_EMISSIVE_SOURCE_SHIFT
);
748 if (mask
& MAT_BIT_FRONT_AMBIENT
) {
749 light_model_ctl1
|= (RADEON_LM_SOURCE_VERTEX_DIFFUSE
<<
750 RADEON_AMBIENT_SOURCE_SHIFT
);
753 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<<
754 RADEON_AMBIENT_SOURCE_SHIFT
);
757 if (mask
& MAT_BIT_FRONT_DIFFUSE
) {
758 light_model_ctl1
|= (RADEON_LM_SOURCE_VERTEX_DIFFUSE
<<
759 RADEON_DIFFUSE_SOURCE_SHIFT
);
762 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<<
763 RADEON_DIFFUSE_SOURCE_SHIFT
);
766 if (mask
& MAT_BIT_FRONT_SPECULAR
) {
767 light_model_ctl1
|= (RADEON_LM_SOURCE_VERTEX_DIFFUSE
<<
768 RADEON_SPECULAR_SOURCE_SHIFT
);
771 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<<
772 RADEON_SPECULAR_SOURCE_SHIFT
);
778 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_EMISSIVE_SOURCE_SHIFT
) |
779 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_AMBIENT_SOURCE_SHIFT
) |
780 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_DIFFUSE_SOURCE_SHIFT
) |
781 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_SPECULAR_SOURCE_SHIFT
);
784 if (light_model_ctl1
!= rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
]) {
785 RADEON_STATECHANGE( rmesa
, tcl
);
786 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] = light_model_ctl1
;
790 void radeonUpdateMaterial( struct gl_context
*ctx
)
792 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
793 GLfloat (*mat
)[4] = ctx
->Light
.Material
.Attrib
;
794 GLfloat
*fcmd
= (GLfloat
*)RADEON_DB_STATE( mtl
);
797 if (ctx
->Light
.ColorMaterialEnabled
)
798 mask
&= ~ctx
->Light
._ColorMaterialBitmask
;
800 if (RADEON_DEBUG
& RADEON_STATE
)
801 fprintf(stderr
, "%s\n", __FUNCTION__
);
804 if (mask
& MAT_BIT_FRONT_EMISSION
) {
805 fcmd
[MTL_EMMISSIVE_RED
] = mat
[MAT_ATTRIB_FRONT_EMISSION
][0];
806 fcmd
[MTL_EMMISSIVE_GREEN
] = mat
[MAT_ATTRIB_FRONT_EMISSION
][1];
807 fcmd
[MTL_EMMISSIVE_BLUE
] = mat
[MAT_ATTRIB_FRONT_EMISSION
][2];
808 fcmd
[MTL_EMMISSIVE_ALPHA
] = mat
[MAT_ATTRIB_FRONT_EMISSION
][3];
810 if (mask
& MAT_BIT_FRONT_AMBIENT
) {
811 fcmd
[MTL_AMBIENT_RED
] = mat
[MAT_ATTRIB_FRONT_AMBIENT
][0];
812 fcmd
[MTL_AMBIENT_GREEN
] = mat
[MAT_ATTRIB_FRONT_AMBIENT
][1];
813 fcmd
[MTL_AMBIENT_BLUE
] = mat
[MAT_ATTRIB_FRONT_AMBIENT
][2];
814 fcmd
[MTL_AMBIENT_ALPHA
] = mat
[MAT_ATTRIB_FRONT_AMBIENT
][3];
816 if (mask
& MAT_BIT_FRONT_DIFFUSE
) {
817 fcmd
[MTL_DIFFUSE_RED
] = mat
[MAT_ATTRIB_FRONT_DIFFUSE
][0];
818 fcmd
[MTL_DIFFUSE_GREEN
] = mat
[MAT_ATTRIB_FRONT_DIFFUSE
][1];
819 fcmd
[MTL_DIFFUSE_BLUE
] = mat
[MAT_ATTRIB_FRONT_DIFFUSE
][2];
820 fcmd
[MTL_DIFFUSE_ALPHA
] = mat
[MAT_ATTRIB_FRONT_DIFFUSE
][3];
822 if (mask
& MAT_BIT_FRONT_SPECULAR
) {
823 fcmd
[MTL_SPECULAR_RED
] = mat
[MAT_ATTRIB_FRONT_SPECULAR
][0];
824 fcmd
[MTL_SPECULAR_GREEN
] = mat
[MAT_ATTRIB_FRONT_SPECULAR
][1];
825 fcmd
[MTL_SPECULAR_BLUE
] = mat
[MAT_ATTRIB_FRONT_SPECULAR
][2];
826 fcmd
[MTL_SPECULAR_ALPHA
] = mat
[MAT_ATTRIB_FRONT_SPECULAR
][3];
828 if (mask
& MAT_BIT_FRONT_SHININESS
) {
829 fcmd
[MTL_SHININESS
] = mat
[MAT_ATTRIB_FRONT_SHININESS
][0];
832 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.mtl
);
834 check_twoside_fallback( ctx
);
835 /* update_global_ambient( ctx );*/
840 * _MESA_NEW_NEED_EYE_COORDS
842 * Uses derived state from mesa:
851 * which are calculated in light.c and are correct for the current
852 * lighting space (model or eye), hence dependencies on _NEW_MODELVIEW
853 * and _MESA_NEW_NEED_EYE_COORDS.
855 static void update_light( struct gl_context
*ctx
)
857 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
859 /* Have to check these, or have an automatic shortcircuit mechanism
860 * to remove noop statechanges. (Or just do a better job on the
864 GLuint tmp
= rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
];
866 if (ctx
->_NeedEyeCoords
)
867 tmp
&= ~RADEON_LIGHT_IN_MODELSPACE
;
869 tmp
|= RADEON_LIGHT_IN_MODELSPACE
;
872 /* Leave this test disabled: (unexplained q3 lockup) (even with
875 if (tmp
!= rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
])
877 RADEON_STATECHANGE( rmesa
, tcl
);
878 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] = tmp
;
883 GLfloat
*fcmd
= (GLfloat
*)RADEON_DB_STATE( eye
);
884 fcmd
[EYE_X
] = ctx
->_EyeZDir
[0];
885 fcmd
[EYE_Y
] = ctx
->_EyeZDir
[1];
886 fcmd
[EYE_Z
] = - ctx
->_EyeZDir
[2];
887 fcmd
[EYE_RESCALE_FACTOR
] = ctx
->_ModelViewInvScale
;
888 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.eye
);
893 if (ctx
->Light
.Enabled
) {
895 for (p
= 0 ; p
< MAX_LIGHTS
; p
++) {
896 if (ctx
->Light
.Light
[p
].Enabled
) {
897 struct gl_light
*l
= &ctx
->Light
.Light
[p
];
898 GLfloat
*fcmd
= (GLfloat
*)RADEON_DB_STATE( lit
[p
] );
900 if (l
->EyePosition
[3] == 0.0) {
901 COPY_3FV( &fcmd
[LIT_POSITION_X
], l
->_VP_inf_norm
);
902 COPY_3FV( &fcmd
[LIT_DIRECTION_X
], l
->_h_inf_norm
);
903 fcmd
[LIT_POSITION_W
] = 0;
904 fcmd
[LIT_DIRECTION_W
] = 0;
906 COPY_4V( &fcmd
[LIT_POSITION_X
], l
->_Position
);
907 fcmd
[LIT_DIRECTION_X
] = -l
->_NormSpotDirection
[0];
908 fcmd
[LIT_DIRECTION_Y
] = -l
->_NormSpotDirection
[1];
909 fcmd
[LIT_DIRECTION_Z
] = -l
->_NormSpotDirection
[2];
910 fcmd
[LIT_DIRECTION_W
] = 0;
913 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.lit
[p
] );
919 static void radeonLightfv( struct gl_context
*ctx
, GLenum light
,
920 GLenum pname
, const GLfloat
*params
)
922 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
923 GLint p
= light
- GL_LIGHT0
;
924 struct gl_light
*l
= &ctx
->Light
.Light
[p
];
925 GLfloat
*fcmd
= (GLfloat
*)rmesa
->hw
.lit
[p
].cmd
;
932 update_light_colors( ctx
, p
);
935 case GL_SPOT_DIRECTION
:
936 /* picked up in update_light */
940 /* positions picked up in update_light, but can do flag here */
942 GLuint idx
= TCL_PER_LIGHT_CTL_0
+ p
/2;
944 /* FIXME: Set RANGE_ATTEN only when needed */
946 flag
= RADEON_LIGHT_1_IS_LOCAL
;
948 flag
= RADEON_LIGHT_0_IS_LOCAL
;
950 RADEON_STATECHANGE(rmesa
, tcl
);
951 if (l
->EyePosition
[3] != 0.0F
)
952 rmesa
->hw
.tcl
.cmd
[idx
] |= flag
;
954 rmesa
->hw
.tcl
.cmd
[idx
] &= ~flag
;
958 case GL_SPOT_EXPONENT
:
959 RADEON_STATECHANGE(rmesa
, lit
[p
]);
960 fcmd
[LIT_SPOT_EXPONENT
] = params
[0];
963 case GL_SPOT_CUTOFF
: {
964 GLuint flag
= (p
&1) ? RADEON_LIGHT_1_IS_SPOT
: RADEON_LIGHT_0_IS_SPOT
;
965 GLuint idx
= TCL_PER_LIGHT_CTL_0
+ p
/2;
967 RADEON_STATECHANGE(rmesa
, lit
[p
]);
968 fcmd
[LIT_SPOT_CUTOFF
] = l
->_CosCutoff
;
970 RADEON_STATECHANGE(rmesa
, tcl
);
971 if (l
->SpotCutoff
!= 180.0F
)
972 rmesa
->hw
.tcl
.cmd
[idx
] |= flag
;
974 rmesa
->hw
.tcl
.cmd
[idx
] &= ~flag
;
979 case GL_CONSTANT_ATTENUATION
:
980 RADEON_STATECHANGE(rmesa
, lit
[p
]);
981 fcmd
[LIT_ATTEN_CONST
] = params
[0];
982 if ( params
[0] == 0.0 )
983 fcmd
[LIT_ATTEN_CONST_INV
] = FLT_MAX
;
985 fcmd
[LIT_ATTEN_CONST_INV
] = 1.0 / params
[0];
987 case GL_LINEAR_ATTENUATION
:
988 RADEON_STATECHANGE(rmesa
, lit
[p
]);
989 fcmd
[LIT_ATTEN_LINEAR
] = params
[0];
991 case GL_QUADRATIC_ATTENUATION
:
992 RADEON_STATECHANGE(rmesa
, lit
[p
]);
993 fcmd
[LIT_ATTEN_QUADRATIC
] = params
[0];
999 /* Set RANGE_ATTEN only when needed */
1002 case GL_CONSTANT_ATTENUATION
:
1003 case GL_LINEAR_ATTENUATION
:
1004 case GL_QUADRATIC_ATTENUATION
:
1006 GLuint
*icmd
= (GLuint
*)RADEON_DB_STATE( tcl
);
1007 GLuint idx
= TCL_PER_LIGHT_CTL_0
+ p
/2;
1008 GLuint atten_flag
= ( p
&1 ) ? RADEON_LIGHT_1_ENABLE_RANGE_ATTEN
1009 : RADEON_LIGHT_0_ENABLE_RANGE_ATTEN
;
1010 GLuint atten_const_flag
= ( p
&1 ) ? RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN
1011 : RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN
;
1013 if ( l
->EyePosition
[3] == 0.0F
||
1014 ( ( fcmd
[LIT_ATTEN_CONST
] == 0.0 || fcmd
[LIT_ATTEN_CONST
] == 1.0 ) &&
1015 fcmd
[LIT_ATTEN_QUADRATIC
] == 0.0 && fcmd
[LIT_ATTEN_LINEAR
] == 0.0 ) ) {
1016 /* Disable attenuation */
1017 icmd
[idx
] &= ~atten_flag
;
1019 if ( fcmd
[LIT_ATTEN_QUADRATIC
] == 0.0 && fcmd
[LIT_ATTEN_LINEAR
] == 0.0 ) {
1020 /* Enable only constant portion of attenuation calculation */
1021 icmd
[idx
] |= ( atten_flag
| atten_const_flag
);
1023 /* Enable full attenuation calculation */
1024 icmd
[idx
] &= ~atten_const_flag
;
1025 icmd
[idx
] |= atten_flag
;
1029 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.tcl
);
1040 static void radeonLightModelfv( struct gl_context
*ctx
, GLenum pname
,
1041 const GLfloat
*param
)
1043 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1046 case GL_LIGHT_MODEL_AMBIENT
:
1047 update_global_ambient( ctx
);
1050 case GL_LIGHT_MODEL_LOCAL_VIEWER
:
1051 RADEON_STATECHANGE( rmesa
, tcl
);
1052 if (ctx
->Light
.Model
.LocalViewer
)
1053 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_LOCAL_VIEWER
;
1055 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_LOCAL_VIEWER
;
1058 case GL_LIGHT_MODEL_TWO_SIDE
:
1059 RADEON_STATECHANGE( rmesa
, tcl
);
1060 if (ctx
->Light
.Model
.TwoSide
)
1061 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_LIGHT_TWOSIDE
;
1063 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~RADEON_LIGHT_TWOSIDE
;
1065 check_twoside_fallback( ctx
);
1067 if (rmesa
->radeon
.TclFallback
) {
1068 radeonChooseRenderState( ctx
);
1069 radeonChooseVertexState( ctx
);
1073 case GL_LIGHT_MODEL_COLOR_CONTROL
:
1074 radeonUpdateSpecular(ctx
);
1082 static void radeonShadeModel( struct gl_context
*ctx
, GLenum mode
)
1084 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1085 GLuint s
= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
];
1087 s
&= ~(RADEON_DIFFUSE_SHADE_MASK
|
1088 RADEON_ALPHA_SHADE_MASK
|
1089 RADEON_SPECULAR_SHADE_MASK
|
1090 RADEON_FOG_SHADE_MASK
);
1094 s
|= (RADEON_DIFFUSE_SHADE_FLAT
|
1095 RADEON_ALPHA_SHADE_FLAT
|
1096 RADEON_SPECULAR_SHADE_FLAT
|
1097 RADEON_FOG_SHADE_FLAT
);
1100 s
|= (RADEON_DIFFUSE_SHADE_GOURAUD
|
1101 RADEON_ALPHA_SHADE_GOURAUD
|
1102 RADEON_SPECULAR_SHADE_GOURAUD
|
1103 RADEON_FOG_SHADE_GOURAUD
);
1109 if ( rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] != s
) {
1110 RADEON_STATECHANGE( rmesa
, set
);
1111 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = s
;
1116 /* =============================================================
1120 static void radeonClipPlane( struct gl_context
*ctx
, GLenum plane
, const GLfloat
*eq
)
1122 GLint p
= (GLint
) plane
- (GLint
) GL_CLIP_PLANE0
;
1123 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1124 GLint
*ip
= (GLint
*)ctx
->Transform
._ClipUserPlane
[p
];
1126 RADEON_STATECHANGE( rmesa
, ucp
[p
] );
1127 rmesa
->hw
.ucp
[p
].cmd
[UCP_X
] = ip
[0];
1128 rmesa
->hw
.ucp
[p
].cmd
[UCP_Y
] = ip
[1];
1129 rmesa
->hw
.ucp
[p
].cmd
[UCP_Z
] = ip
[2];
1130 rmesa
->hw
.ucp
[p
].cmd
[UCP_W
] = ip
[3];
1133 static void radeonUpdateClipPlanes( struct gl_context
*ctx
)
1135 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1138 for (p
= 0; p
< ctx
->Const
.MaxClipPlanes
; p
++) {
1139 if (ctx
->Transform
.ClipPlanesEnabled
& (1 << p
)) {
1140 GLint
*ip
= (GLint
*)ctx
->Transform
._ClipUserPlane
[p
];
1142 RADEON_STATECHANGE( rmesa
, ucp
[p
] );
1143 rmesa
->hw
.ucp
[p
].cmd
[UCP_X
] = ip
[0];
1144 rmesa
->hw
.ucp
[p
].cmd
[UCP_Y
] = ip
[1];
1145 rmesa
->hw
.ucp
[p
].cmd
[UCP_Z
] = ip
[2];
1146 rmesa
->hw
.ucp
[p
].cmd
[UCP_W
] = ip
[3];
1152 /* =============================================================
1157 radeonStencilFuncSeparate( struct gl_context
*ctx
, GLenum face
, GLenum func
,
1158 GLint ref
, GLuint mask
)
1160 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1161 GLuint refmask
= ((_mesa_get_stencil_ref(ctx
, 0) << RADEON_STENCIL_REF_SHIFT
) |
1162 ((ctx
->Stencil
.ValueMask
[0] & 0xff) << RADEON_STENCIL_MASK_SHIFT
));
1164 RADEON_STATECHANGE( rmesa
, ctx
);
1165 RADEON_STATECHANGE( rmesa
, msk
);
1167 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &= ~RADEON_STENCIL_TEST_MASK
;
1168 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] &= ~(RADEON_STENCIL_REF_MASK
|
1169 RADEON_STENCIL_VALUE_MASK
);
1171 switch ( ctx
->Stencil
.Function
[0] ) {
1173 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_NEVER
;
1176 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_LESS
;
1179 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_EQUAL
;
1182 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_LEQUAL
;
1185 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_GREATER
;
1188 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_NEQUAL
;
1191 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_GEQUAL
;
1194 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_ALWAYS
;
1198 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] |= refmask
;
1202 radeonStencilMaskSeparate( struct gl_context
*ctx
, GLenum face
, GLuint mask
)
1204 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1206 RADEON_STATECHANGE( rmesa
, msk
);
1207 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] &= ~RADEON_STENCIL_WRITE_MASK
;
1208 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] |=
1209 ((ctx
->Stencil
.WriteMask
[0] & 0xff) << RADEON_STENCIL_WRITEMASK_SHIFT
);
1212 static void radeonStencilOpSeparate( struct gl_context
*ctx
, GLenum face
, GLenum fail
,
1213 GLenum zfail
, GLenum zpass
)
1215 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1217 /* radeon 7200 have stencil bug, DEC and INC_WRAP will actually both do DEC_WRAP,
1218 and DEC_WRAP (and INVERT) will do INVERT. No way to get correct INC_WRAP and DEC,
1219 but DEC_WRAP can be fixed by using DEC and INC_WRAP at least use INC. */
1221 GLuint tempRADEON_STENCIL_FAIL_DEC_WRAP
;
1222 GLuint tempRADEON_STENCIL_FAIL_INC_WRAP
;
1223 GLuint tempRADEON_STENCIL_ZFAIL_DEC_WRAP
;
1224 GLuint tempRADEON_STENCIL_ZFAIL_INC_WRAP
;
1225 GLuint tempRADEON_STENCIL_ZPASS_DEC_WRAP
;
1226 GLuint tempRADEON_STENCIL_ZPASS_INC_WRAP
;
1228 if (rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_BROKEN_STENCIL
) {
1229 tempRADEON_STENCIL_FAIL_DEC_WRAP
= RADEON_STENCIL_FAIL_DEC
;
1230 tempRADEON_STENCIL_FAIL_INC_WRAP
= RADEON_STENCIL_FAIL_INC
;
1231 tempRADEON_STENCIL_ZFAIL_DEC_WRAP
= RADEON_STENCIL_ZFAIL_DEC
;
1232 tempRADEON_STENCIL_ZFAIL_INC_WRAP
= RADEON_STENCIL_ZFAIL_INC
;
1233 tempRADEON_STENCIL_ZPASS_DEC_WRAP
= RADEON_STENCIL_ZPASS_DEC
;
1234 tempRADEON_STENCIL_ZPASS_INC_WRAP
= RADEON_STENCIL_ZPASS_INC
;
1237 tempRADEON_STENCIL_FAIL_DEC_WRAP
= RADEON_STENCIL_FAIL_DEC_WRAP
;
1238 tempRADEON_STENCIL_FAIL_INC_WRAP
= RADEON_STENCIL_FAIL_INC_WRAP
;
1239 tempRADEON_STENCIL_ZFAIL_DEC_WRAP
= RADEON_STENCIL_ZFAIL_DEC_WRAP
;
1240 tempRADEON_STENCIL_ZFAIL_INC_WRAP
= RADEON_STENCIL_ZFAIL_INC_WRAP
;
1241 tempRADEON_STENCIL_ZPASS_DEC_WRAP
= RADEON_STENCIL_ZPASS_DEC_WRAP
;
1242 tempRADEON_STENCIL_ZPASS_INC_WRAP
= RADEON_STENCIL_ZPASS_INC_WRAP
;
1245 RADEON_STATECHANGE( rmesa
, ctx
);
1246 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &= ~(RADEON_STENCIL_FAIL_MASK
|
1247 RADEON_STENCIL_ZFAIL_MASK
|
1248 RADEON_STENCIL_ZPASS_MASK
);
1250 switch ( ctx
->Stencil
.FailFunc
[0] ) {
1252 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_KEEP
;
1255 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_ZERO
;
1258 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_REPLACE
;
1261 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_INC
;
1264 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_DEC
;
1267 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_FAIL_INC_WRAP
;
1270 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_FAIL_DEC_WRAP
;
1273 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_INVERT
;
1277 switch ( ctx
->Stencil
.ZFailFunc
[0] ) {
1279 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_KEEP
;
1282 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_ZERO
;
1285 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_REPLACE
;
1288 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_INC
;
1291 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_DEC
;
1294 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_ZFAIL_INC_WRAP
;
1297 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_ZFAIL_DEC_WRAP
;
1300 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_INVERT
;
1304 switch ( ctx
->Stencil
.ZPassFunc
[0] ) {
1306 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_KEEP
;
1309 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_ZERO
;
1312 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_REPLACE
;
1315 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_INC
;
1318 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_DEC
;
1321 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_ZPASS_INC_WRAP
;
1324 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_ZPASS_DEC_WRAP
;
1327 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_INVERT
;
1334 /* =============================================================
1335 * Window position and viewport transformation
1339 * To correctly position primitives:
1341 #define SUBPIXEL_X 0.125
1342 #define SUBPIXEL_Y 0.125
1346 * Called when window size or position changes or viewport or depth range
1347 * state is changed. We update the hardware viewport state here.
1349 void radeonUpdateWindow( struct gl_context
*ctx
)
1351 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1352 __DRIdrawable
*dPriv
= radeon_get_drawable(&rmesa
->radeon
);
1353 GLfloat xoffset
= 0.0;
1354 GLfloat yoffset
= dPriv
? (GLfloat
) dPriv
->h
: 0;
1355 const GLfloat
*v
= ctx
->ViewportArray
[0]._WindowMap
.m
;
1356 const GLboolean render_to_fbo
= (ctx
->DrawBuffer
? _mesa_is_user_fbo(ctx
->DrawBuffer
) : 0);
1357 const GLfloat depthScale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
1358 GLfloat y_scale
, y_bias
;
1360 if (render_to_fbo
) {
1368 float_ui32_type sx
= { v
[MAT_SX
] };
1369 float_ui32_type tx
= { v
[MAT_TX
] + xoffset
+ SUBPIXEL_X
};
1370 float_ui32_type sy
= { v
[MAT_SY
] * y_scale
};
1371 float_ui32_type ty
= { (v
[MAT_TY
] * y_scale
) + y_bias
+ SUBPIXEL_Y
};
1372 float_ui32_type sz
= { v
[MAT_SZ
] * depthScale
};
1373 float_ui32_type tz
= { v
[MAT_TZ
] * depthScale
};
1375 RADEON_STATECHANGE( rmesa
, vpt
);
1377 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XSCALE
] = sx
.ui32
;
1378 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] = tx
.ui32
;
1379 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YSCALE
] = sy
.ui32
;
1380 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] = ty
.ui32
;
1381 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZSCALE
] = sz
.ui32
;
1382 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZOFFSET
] = tz
.ui32
;
1386 static void radeonViewport(struct gl_context
*ctx
)
1388 /* Don't pipeline viewport changes, conflict with window offset
1389 * setting below. Could apply deltas to rescue pipelined viewport
1390 * values, or keep the originals hanging around.
1392 radeonUpdateWindow( ctx
);
1394 radeon_viewport(ctx
);
1397 static void radeonDepthRange(struct gl_context
*ctx
)
1399 radeonUpdateWindow( ctx
);
1402 /* =============================================================
1406 static void radeonRenderMode( struct gl_context
*ctx
, GLenum mode
)
1408 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1409 FALLBACK( rmesa
, RADEON_FALLBACK_RENDER_MODE
, (mode
!= GL_RENDER
) );
1413 static GLuint radeon_rop_tab
[] = {
1416 RADEON_ROP_AND_REVERSE
,
1418 RADEON_ROP_AND_INVERTED
,
1425 RADEON_ROP_OR_REVERSE
,
1426 RADEON_ROP_COPY_INVERTED
,
1427 RADEON_ROP_OR_INVERTED
,
1432 static void radeonLogicOpCode( struct gl_context
*ctx
, GLenum opcode
)
1434 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1435 GLuint rop
= (GLuint
)opcode
- GL_CLEAR
;
1439 RADEON_STATECHANGE( rmesa
, msk
);
1440 rmesa
->hw
.msk
.cmd
[MSK_RB3D_ROPCNTL
] = radeon_rop_tab
[rop
];
1443 /* =============================================================
1444 * State enable/disable
1447 static void radeonEnable( struct gl_context
*ctx
, GLenum cap
, GLboolean state
)
1449 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1452 if ( RADEON_DEBUG
& RADEON_STATE
)
1453 fprintf( stderr
, "%s( %s = %s )\n", __FUNCTION__
,
1454 _mesa_lookup_enum_by_nr( cap
),
1455 state
? "GL_TRUE" : "GL_FALSE" );
1458 /* Fast track this one...
1466 RADEON_STATECHANGE( rmesa
, ctx
);
1468 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_ALPHA_TEST_ENABLE
;
1470 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_ALPHA_TEST_ENABLE
;
1475 RADEON_STATECHANGE( rmesa
, ctx
);
1477 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_ALPHA_BLEND_ENABLE
;
1479 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_ALPHA_BLEND_ENABLE
;
1481 if ( (ctx
->Color
.ColorLogicOpEnabled
|| (ctx
->Color
.BlendEnabled
1482 && ctx
->Color
.Blend
[0].EquationRGB
== GL_LOGIC_OP
)) ) {
1483 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_ROP_ENABLE
;
1485 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_ROP_ENABLE
;
1488 /* Catch a possible fallback:
1491 ctx
->Driver
.BlendEquationSeparate( ctx
,
1492 ctx
->Color
.Blend
[0].EquationRGB
,
1493 ctx
->Color
.Blend
[0].EquationA
);
1494 ctx
->Driver
.BlendFuncSeparate( ctx
, ctx
->Color
.Blend
[0].SrcRGB
,
1495 ctx
->Color
.Blend
[0].DstRGB
,
1496 ctx
->Color
.Blend
[0].SrcA
,
1497 ctx
->Color
.Blend
[0].DstA
);
1500 FALLBACK( rmesa
, RADEON_FALLBACK_BLEND_FUNC
, GL_FALSE
);
1501 FALLBACK( rmesa
, RADEON_FALLBACK_BLEND_EQ
, GL_FALSE
);
1505 case GL_CLIP_PLANE0
:
1506 case GL_CLIP_PLANE1
:
1507 case GL_CLIP_PLANE2
:
1508 case GL_CLIP_PLANE3
:
1509 case GL_CLIP_PLANE4
:
1510 case GL_CLIP_PLANE5
:
1511 p
= cap
-GL_CLIP_PLANE0
;
1512 RADEON_STATECHANGE( rmesa
, tcl
);
1514 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= (RADEON_UCP_ENABLE_0
<<p
);
1515 radeonClipPlane( ctx
, cap
, NULL
);
1518 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~(RADEON_UCP_ENABLE_0
<<p
);
1522 case GL_COLOR_MATERIAL
:
1523 radeonColorMaterial( ctx
, 0, 0 );
1524 radeonUpdateMaterial( ctx
);
1528 radeonCullFace( ctx
, 0 );
1532 RADEON_STATECHANGE(rmesa
, ctx
);
1534 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_Z_ENABLE
;
1536 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_Z_ENABLE
;
1541 RADEON_STATECHANGE(rmesa
, ctx
);
1543 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_DITHER_ENABLE
;
1544 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~rmesa
->radeon
.state
.color
.roundEnable
;
1546 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_DITHER_ENABLE
;
1547 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= rmesa
->radeon
.state
.color
.roundEnable
;
1552 RADEON_STATECHANGE(rmesa
, ctx
);
1554 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_FOG_ENABLE
;
1555 radeonFogfv( ctx
, GL_FOG_MODE
, NULL
);
1557 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_FOG_ENABLE
;
1558 RADEON_STATECHANGE(rmesa
, tcl
);
1559 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~RADEON_TCL_FOG_MASK
;
1561 radeonUpdateSpecular( ctx
); /* for PK_SPEC */
1562 _mesa_allow_light_in_model( ctx
, !state
);
1573 RADEON_STATECHANGE(rmesa
, tcl
);
1574 p
= cap
- GL_LIGHT0
;
1576 flag
= (RADEON_LIGHT_1_ENABLE
|
1577 RADEON_LIGHT_1_ENABLE_AMBIENT
|
1578 RADEON_LIGHT_1_ENABLE_SPECULAR
);
1580 flag
= (RADEON_LIGHT_0_ENABLE
|
1581 RADEON_LIGHT_0_ENABLE_AMBIENT
|
1582 RADEON_LIGHT_0_ENABLE_SPECULAR
);
1585 rmesa
->hw
.tcl
.cmd
[p
/2 + TCL_PER_LIGHT_CTL_0
] |= flag
;
1587 rmesa
->hw
.tcl
.cmd
[p
/2 + TCL_PER_LIGHT_CTL_0
] &= ~flag
;
1591 update_light_colors( ctx
, p
);
1595 RADEON_STATECHANGE(rmesa
, tcl
);
1596 radeonUpdateSpecular(ctx
);
1597 check_twoside_fallback( ctx
);
1600 case GL_LINE_SMOOTH
:
1601 RADEON_STATECHANGE( rmesa
, ctx
);
1603 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_ANTI_ALIAS_LINE
;
1605 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_ANTI_ALIAS_LINE
;
1609 case GL_LINE_STIPPLE
:
1610 RADEON_STATECHANGE( rmesa
, ctx
);
1612 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_PATTERN_ENABLE
;
1614 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_PATTERN_ENABLE
;
1618 case GL_COLOR_LOGIC_OP
:
1619 RADEON_STATECHANGE( rmesa
, ctx
);
1620 if ( (ctx
->Color
.ColorLogicOpEnabled
|| (ctx
->Color
.BlendEnabled
1621 && ctx
->Color
.Blend
[0].EquationRGB
== GL_LOGIC_OP
)) ) {
1622 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_ROP_ENABLE
;
1624 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_ROP_ENABLE
;
1629 RADEON_STATECHANGE( rmesa
, tcl
);
1631 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_NORMALIZE_NORMALS
;
1633 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_NORMALIZE_NORMALS
;
1637 case GL_POLYGON_OFFSET_POINT
:
1638 RADEON_STATECHANGE( rmesa
, set
);
1640 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_ZBIAS_ENABLE_POINT
;
1642 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_ZBIAS_ENABLE_POINT
;
1646 case GL_POLYGON_OFFSET_LINE
:
1647 RADEON_STATECHANGE( rmesa
, set
);
1649 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_ZBIAS_ENABLE_LINE
;
1651 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_ZBIAS_ENABLE_LINE
;
1655 case GL_POLYGON_OFFSET_FILL
:
1656 RADEON_STATECHANGE( rmesa
, set
);
1658 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_ZBIAS_ENABLE_TRI
;
1660 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_ZBIAS_ENABLE_TRI
;
1664 case GL_POLYGON_SMOOTH
:
1665 RADEON_STATECHANGE( rmesa
, ctx
);
1667 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_ANTI_ALIAS_POLY
;
1669 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_ANTI_ALIAS_POLY
;
1673 case GL_POLYGON_STIPPLE
:
1674 RADEON_STATECHANGE(rmesa
, ctx
);
1676 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_STIPPLE_ENABLE
;
1678 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_STIPPLE_ENABLE
;
1682 case GL_RESCALE_NORMAL_EXT
: {
1683 GLboolean tmp
= ctx
->_NeedEyeCoords
? state
: !state
;
1684 RADEON_STATECHANGE( rmesa
, tcl
);
1686 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_RESCALE_NORMALS
;
1688 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_RESCALE_NORMALS
;
1693 case GL_SCISSOR_TEST
:
1694 radeon_firevertices(&rmesa
->radeon
);
1695 rmesa
->radeon
.state
.scissor
.enabled
= state
;
1696 radeonUpdateScissor( ctx
);
1699 case GL_STENCIL_TEST
:
1701 GLboolean hw_stencil
= GL_FALSE
;
1702 if (ctx
->DrawBuffer
) {
1703 struct radeon_renderbuffer
*rrbStencil
1704 = radeon_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_STENCIL
);
1705 hw_stencil
= (rrbStencil
&& rrbStencil
->bo
);
1709 RADEON_STATECHANGE( rmesa
, ctx
);
1711 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_STENCIL_ENABLE
;
1713 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_STENCIL_ENABLE
;
1716 FALLBACK( rmesa
, RADEON_FALLBACK_STENCIL
, state
);
1721 case GL_TEXTURE_GEN_Q
:
1722 case GL_TEXTURE_GEN_R
:
1723 case GL_TEXTURE_GEN_S
:
1724 case GL_TEXTURE_GEN_T
:
1725 /* Picked up in radeonUpdateTextureState.
1727 rmesa
->recheck_texgen
[ctx
->Texture
.CurrentUnit
] = GL_TRUE
;
1730 case GL_COLOR_SUM_EXT
:
1731 radeonUpdateSpecular ( ctx
);
1740 static void radeonLightingSpaceChange( struct gl_context
*ctx
)
1742 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1744 RADEON_STATECHANGE( rmesa
, tcl
);
1746 if (RADEON_DEBUG
& RADEON_STATE
)
1747 fprintf(stderr
, "%s %d BEFORE %x\n", __FUNCTION__
, ctx
->_NeedEyeCoords
,
1748 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
]);
1750 if (ctx
->_NeedEyeCoords
)
1751 tmp
= ctx
->Transform
.RescaleNormals
;
1753 tmp
= !ctx
->Transform
.RescaleNormals
;
1756 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_RESCALE_NORMALS
;
1758 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_RESCALE_NORMALS
;
1761 if (RADEON_DEBUG
& RADEON_STATE
)
1762 fprintf(stderr
, "%s %d AFTER %x\n", __FUNCTION__
, ctx
->_NeedEyeCoords
,
1763 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
]);
1766 /* =============================================================
1767 * Deferred state management - matrices, textures, other?
1771 void radeonUploadTexMatrix( r100ContextPtr rmesa
,
1772 int unit
, GLboolean swapcols
)
1774 /* Here's how this works: on r100, only 3 tex coords can be submitted, so the
1775 vector looks like this probably: (s t r|q 0) (not sure if the last coord
1776 is hardwired to 0, could be 1 too). Interestingly, it actually looks like
1777 texgen generates all 4 coords, at least tests with projtex indicated that.
1778 So: if we need the q coord in the end (solely determined by the texture
1779 target, i.e. 2d / 1d / texrect targets) we swap the third and 4th row.
1780 Additionally, if we don't have texgen but 4 tex coords submitted, we swap
1781 column 3 and 4 (for the 2d / 1d / texrect targets) since the q coord
1782 will get submitted in the "wrong", i.e. 3rd, slot.
1783 If an app submits 3 coords for 2d targets, we assume it is saving on vertex
1784 size and using the texture matrix to swap the r and q coords around (ut2k3
1785 does exactly that), so we don't need the 3rd / 4th column swap - still need
1786 the 3rd / 4th row swap of course. This will potentially break for apps which
1787 use TexCoord3x just for fun. Additionally, it will never work if an app uses
1788 an "advanced" texture matrix and relies on all 4 texcoord inputs to generate
1789 the maximum needed 3. This seems impossible to do with hw tcl on r100, and
1790 incredibly hard to detect so we can't just fallback in such a case. Assume
1791 it never happens... - rs
1794 int idx
= TEXMAT_0
+ unit
;
1795 float *dest
= ((float *)RADEON_DB_STATE( mat
[idx
] )) + MAT_ELT_0
;
1797 struct gl_texture_unit tUnit
= rmesa
->radeon
.glCtx
.Texture
.Unit
[unit
];
1798 GLfloat
*src
= rmesa
->tmpmat
[unit
].m
;
1800 rmesa
->TexMatColSwap
&= ~(1 << unit
);
1801 if (!tUnit
._Current
||
1802 (tUnit
._Current
->Target
!= GL_TEXTURE_3D
&&
1803 tUnit
._Current
->Target
!= GL_TEXTURE_CUBE_MAP
)) {
1805 rmesa
->TexMatColSwap
|= 1 << unit
;
1806 /* attention some elems are swapped 2 times! */
1819 /* those last 4 are probably never used */
1826 for (i
= 0; i
< 2; i
++) {
1830 *dest
++ = src
[i
+12];
1832 for (i
= 3; i
>= 2; i
--) {
1836 *dest
++ = src
[i
+12];
1841 for (i
= 0 ; i
< 4 ; i
++) {
1845 *dest
++ = src
[i
+12];
1849 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.mat
[idx
] );
1853 static void upload_matrix( r100ContextPtr rmesa
, GLfloat
*src
, int idx
)
1855 float *dest
= ((float *)RADEON_DB_STATE( mat
[idx
] ))+MAT_ELT_0
;
1859 for (i
= 0 ; i
< 4 ; i
++) {
1863 *dest
++ = src
[i
+12];
1866 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.mat
[idx
] );
1869 static void upload_matrix_t( r100ContextPtr rmesa
, GLfloat
*src
, int idx
)
1871 float *dest
= ((float *)RADEON_DB_STATE( mat
[idx
] ))+MAT_ELT_0
;
1872 memcpy(dest
, src
, 16*sizeof(float));
1873 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.mat
[idx
] );
1877 static void update_texturematrix( struct gl_context
*ctx
)
1879 r100ContextPtr rmesa
= R100_CONTEXT( ctx
);
1880 GLuint tpc
= rmesa
->hw
.tcl
.cmd
[TCL_TEXTURE_PROC_CTL
];
1881 GLuint vs
= rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
];
1883 GLuint texMatEnabled
= 0;
1884 rmesa
->NeedTexMatrix
= 0;
1885 rmesa
->TexMatColSwap
= 0;
1887 for (unit
= 0 ; unit
< ctx
->Const
.MaxTextureUnits
; unit
++) {
1888 if (ctx
->Texture
.Unit
[unit
]._Current
) {
1889 GLboolean needMatrix
= GL_FALSE
;
1890 if (ctx
->TextureMatrixStack
[unit
].Top
->type
!= MATRIX_IDENTITY
) {
1891 needMatrix
= GL_TRUE
;
1892 texMatEnabled
|= (RADEON_TEXGEN_TEXMAT_0_ENABLE
|
1893 RADEON_TEXMAT_0_ENABLE
) << unit
;
1895 if (rmesa
->TexGenEnabled
& (RADEON_TEXMAT_0_ENABLE
<< unit
)) {
1896 /* Need to preconcatenate any active texgen
1897 * obj/eyeplane matrices:
1899 _math_matrix_mul_matrix( &rmesa
->tmpmat
[unit
],
1900 ctx
->TextureMatrixStack
[unit
].Top
,
1901 &rmesa
->TexGenMatrix
[unit
] );
1904 _math_matrix_copy( &rmesa
->tmpmat
[unit
],
1905 ctx
->TextureMatrixStack
[unit
].Top
);
1908 else if (rmesa
->TexGenEnabled
& (RADEON_TEXMAT_0_ENABLE
<< unit
)) {
1909 _math_matrix_copy( &rmesa
->tmpmat
[unit
], &rmesa
->TexGenMatrix
[unit
] );
1910 needMatrix
= GL_TRUE
;
1913 rmesa
->NeedTexMatrix
|= 1 << unit
;
1914 radeonUploadTexMatrix( rmesa
, unit
,
1915 !ctx
->Texture
.Unit
[unit
].TexGenEnabled
);
1920 tpc
= (texMatEnabled
| rmesa
->TexGenEnabled
);
1922 /* TCL_TEX_COMPUTED_x is TCL_TEX_INPUT_x | 0x8 */
1923 vs
&= ~((RADEON_TCL_TEX_COMPUTED_TEX_0
<< RADEON_TCL_TEX_0_OUTPUT_SHIFT
) |
1924 (RADEON_TCL_TEX_COMPUTED_TEX_0
<< RADEON_TCL_TEX_1_OUTPUT_SHIFT
) |
1925 (RADEON_TCL_TEX_COMPUTED_TEX_0
<< RADEON_TCL_TEX_2_OUTPUT_SHIFT
));
1927 vs
|= (((tpc
& RADEON_TEXGEN_TEXMAT_0_ENABLE
) <<
1928 (RADEON_TCL_TEX_0_OUTPUT_SHIFT
+ 3)) |
1929 ((tpc
& RADEON_TEXGEN_TEXMAT_1_ENABLE
) <<
1930 (RADEON_TCL_TEX_1_OUTPUT_SHIFT
+ 2)) |
1931 ((tpc
& RADEON_TEXGEN_TEXMAT_2_ENABLE
) <<
1932 (RADEON_TCL_TEX_2_OUTPUT_SHIFT
+ 1)));
1934 if (tpc
!= rmesa
->hw
.tcl
.cmd
[TCL_TEXTURE_PROC_CTL
] ||
1935 vs
!= rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
]) {
1937 RADEON_STATECHANGE(rmesa
, tcl
);
1938 rmesa
->hw
.tcl
.cmd
[TCL_TEXTURE_PROC_CTL
] = tpc
;
1939 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] = vs
;
1943 GLboolean
r100ValidateBuffers(struct gl_context
*ctx
)
1945 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1946 struct radeon_renderbuffer
*rrb
;
1949 radeon_cs_space_reset_bos(rmesa
->radeon
.cmdbuf
.cs
);
1951 rrb
= radeon_get_colorbuffer(&rmesa
->radeon
);
1953 if (rrb
&& rrb
->bo
) {
1954 radeon_cs_space_add_persistent_bo(rmesa
->radeon
.cmdbuf
.cs
, rrb
->bo
,
1955 0, RADEON_GEM_DOMAIN_VRAM
);
1959 rrb
= radeon_get_depthbuffer(&rmesa
->radeon
);
1961 if (rrb
&& rrb
->bo
) {
1962 radeon_cs_space_add_persistent_bo(rmesa
->radeon
.cmdbuf
.cs
, rrb
->bo
,
1963 0, RADEON_GEM_DOMAIN_VRAM
);
1966 for (i
= 0; i
< ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxTextureImageUnits
; ++i
) {
1969 if (!ctx
->Texture
.Unit
[i
]._Current
)
1972 t
= rmesa
->state
.texture
.unit
[i
].texobj
;
1976 if (t
->image_override
&& t
->bo
)
1977 radeon_cs_space_add_persistent_bo(rmesa
->radeon
.cmdbuf
.cs
, t
->bo
,
1978 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0);
1980 radeon_cs_space_add_persistent_bo(rmesa
->radeon
.cmdbuf
.cs
, t
->mt
->bo
,
1981 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0);
1984 ret
= radeon_cs_space_check_with_bo(rmesa
->radeon
.cmdbuf
.cs
, first_elem(&rmesa
->radeon
.dma
.reserved
)->bo
, RADEON_GEM_DOMAIN_GTT
, 0);
1990 GLboolean
radeonValidateState( struct gl_context
*ctx
)
1992 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1993 GLuint new_state
= rmesa
->radeon
.NewGLState
;
1995 if (new_state
& _NEW_BUFFERS
) {
1996 _mesa_update_framebuffer(ctx
);
1997 /* this updates the DrawBuffer's Width/Height if it's a FBO */
1998 _mesa_update_draw_buffer_bounds(ctx
);
1999 RADEON_STATECHANGE(rmesa
, ctx
);
2002 if (new_state
& _NEW_TEXTURE
) {
2003 radeonUpdateTextureState( ctx
);
2004 new_state
|= rmesa
->radeon
.NewGLState
; /* may add TEXTURE_MATRIX */
2007 /* we need to do a space check here */
2008 if (!r100ValidateBuffers(ctx
))
2011 /* Need an event driven matrix update?
2013 if (new_state
& (_NEW_MODELVIEW
|_NEW_PROJECTION
))
2014 upload_matrix( rmesa
, ctx
->_ModelProjectMatrix
.m
, MODEL_PROJ
);
2016 /* Need these for lighting (shouldn't upload otherwise)
2018 if (new_state
& (_NEW_MODELVIEW
)) {
2019 upload_matrix( rmesa
, ctx
->ModelviewMatrixStack
.Top
->m
, MODEL
);
2020 upload_matrix_t( rmesa
, ctx
->ModelviewMatrixStack
.Top
->inv
, MODEL_IT
);
2023 /* Does this need to be triggered on eg. modelview for
2024 * texgen-derived objplane/eyeplane matrices?
2026 if (new_state
& _NEW_TEXTURE_MATRIX
) {
2027 update_texturematrix( ctx
);
2030 if (new_state
& (_NEW_LIGHT
|_NEW_MODELVIEW
|_MESA_NEW_NEED_EYE_COORDS
)) {
2031 update_light( ctx
);
2034 /* emit all active clip planes if projection matrix changes.
2036 if (new_state
& (_NEW_PROJECTION
)) {
2037 if (ctx
->Transform
.ClipPlanesEnabled
)
2038 radeonUpdateClipPlanes( ctx
);
2042 rmesa
->radeon
.NewGLState
= 0;
2048 static void radeonInvalidateState( struct gl_context
*ctx
, GLuint new_state
)
2050 _swrast_InvalidateState( ctx
, new_state
);
2051 _swsetup_InvalidateState( ctx
, new_state
);
2052 _vbo_InvalidateState( ctx
, new_state
);
2053 _tnl_InvalidateState( ctx
, new_state
);
2054 _ae_invalidate_state( ctx
, new_state
);
2055 R100_CONTEXT(ctx
)->radeon
.NewGLState
|= new_state
;
2059 /* A hack. Need a faster way to find this out.
2061 static GLboolean
check_material( struct gl_context
*ctx
)
2063 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
2066 for (i
= _TNL_ATTRIB_MAT_FRONT_AMBIENT
;
2067 i
< _TNL_ATTRIB_MAT_BACK_INDEXES
;
2069 if (tnl
->vb
.AttribPtr
[i
] &&
2070 tnl
->vb
.AttribPtr
[i
]->stride
)
2077 static void radeonWrapRunPipeline( struct gl_context
*ctx
)
2079 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
2080 GLboolean has_material
;
2083 fprintf(stderr
, "%s, newstate: %x\n", __FUNCTION__
, rmesa
->radeon
.NewGLState
);
2087 if (rmesa
->radeon
.NewGLState
)
2088 if (!radeonValidateState( ctx
))
2089 FALLBACK(rmesa
, RADEON_FALLBACK_TEXTURE
, GL_TRUE
);
2091 has_material
= (ctx
->Light
.Enabled
&& check_material( ctx
));
2094 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_MATERIAL
, GL_TRUE
);
2097 /* Run the pipeline.
2099 _tnl_run_pipeline( ctx
);
2102 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_MATERIAL
, GL_FALSE
);
2106 static void radeonPolygonStipple( struct gl_context
*ctx
, const GLubyte
*mask
)
2108 r100ContextPtr r100
= R100_CONTEXT(ctx
);
2111 radeon_firevertices(&r100
->radeon
);
2113 RADEON_STATECHANGE(r100
, stp
);
2115 /* Must flip pattern upside down.
2117 for ( i
= 31 ; i
>= 0; i
--) {
2118 r100
->hw
.stp
.cmd
[3 + i
] = ((GLuint
*) mask
)[i
];
2123 /* Initialize the driver's state functions.
2124 * Many of the ctx->Driver functions might have been initialized to
2125 * software defaults in the earlier _mesa_init_driver_functions() call.
2127 void radeonInitStateFuncs( struct gl_context
*ctx
)
2129 ctx
->Driver
.UpdateState
= radeonInvalidateState
;
2130 ctx
->Driver
.LightingSpaceChange
= radeonLightingSpaceChange
;
2132 ctx
->Driver
.DrawBuffer
= radeonDrawBuffer
;
2133 ctx
->Driver
.ReadBuffer
= radeonReadBuffer
;
2134 ctx
->Driver
.CopyPixels
= _mesa_meta_CopyPixels
;
2135 ctx
->Driver
.DrawPixels
= _mesa_meta_DrawPixels
;
2136 ctx
->Driver
.ReadPixels
= radeonReadPixels
;
2138 ctx
->Driver
.AlphaFunc
= radeonAlphaFunc
;
2139 ctx
->Driver
.BlendEquationSeparate
= radeonBlendEquationSeparate
;
2140 ctx
->Driver
.BlendFuncSeparate
= radeonBlendFuncSeparate
;
2141 ctx
->Driver
.ClipPlane
= radeonClipPlane
;
2142 ctx
->Driver
.ColorMask
= radeonColorMask
;
2143 ctx
->Driver
.CullFace
= radeonCullFace
;
2144 ctx
->Driver
.DepthFunc
= radeonDepthFunc
;
2145 ctx
->Driver
.DepthMask
= radeonDepthMask
;
2146 ctx
->Driver
.DepthRange
= radeonDepthRange
;
2147 ctx
->Driver
.Enable
= radeonEnable
;
2148 ctx
->Driver
.Fogfv
= radeonFogfv
;
2149 ctx
->Driver
.FrontFace
= radeonFrontFace
;
2150 ctx
->Driver
.Hint
= NULL
;
2151 ctx
->Driver
.LightModelfv
= radeonLightModelfv
;
2152 ctx
->Driver
.Lightfv
= radeonLightfv
;
2153 ctx
->Driver
.LineStipple
= radeonLineStipple
;
2154 ctx
->Driver
.LineWidth
= radeonLineWidth
;
2155 ctx
->Driver
.LogicOpcode
= radeonLogicOpCode
;
2156 ctx
->Driver
.PolygonMode
= radeonPolygonMode
;
2157 ctx
->Driver
.PolygonOffset
= radeonPolygonOffset
;
2158 ctx
->Driver
.PolygonStipple
= radeonPolygonStipple
;
2159 ctx
->Driver
.RenderMode
= radeonRenderMode
;
2160 ctx
->Driver
.Scissor
= radeonScissor
;
2161 ctx
->Driver
.ShadeModel
= radeonShadeModel
;
2162 ctx
->Driver
.StencilFuncSeparate
= radeonStencilFuncSeparate
;
2163 ctx
->Driver
.StencilMaskSeparate
= radeonStencilMaskSeparate
;
2164 ctx
->Driver
.StencilOpSeparate
= radeonStencilOpSeparate
;
2165 ctx
->Driver
.Viewport
= radeonViewport
;
2167 TNL_CONTEXT(ctx
)->Driver
.NotifyMaterialChange
= radeonUpdateMaterial
;
2168 TNL_CONTEXT(ctx
)->Driver
.RunPipeline
= radeonWrapRunPipeline
;