1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_state.c,v 1.8 2002/12/16 16:18:58 dawes Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Gareth Hughes <gareth@valinux.com>
33 * Keith Whitwell <keith@tungstengraphics.com>
38 #include "api_arrayelt.h"
45 #include "swrast/swrast.h"
46 #include "array_cache/acache.h"
48 #include "tnl/t_pipeline.h"
49 #include "main/light.h"
50 #include "swrast_setup/swrast_setup.h"
52 #include "radeon_context.h"
53 #include "radeon_ioctl.h"
54 #include "radeon_state.h"
55 #include "radeon_tcl.h"
56 #include "radeon_tex.h"
57 #include "radeon_swtcl.h"
58 #include "radeon_vtxfmt.h"
60 /* =============================================================
64 static void radeonAlphaFunc( GLcontext
*ctx
, GLenum func
, GLfloat ref
)
66 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
67 int pp_misc
= rmesa
->hw
.ctx
.cmd
[CTX_PP_MISC
];
70 CLAMPED_FLOAT_TO_UBYTE(refByte
, ref
);
72 RADEON_STATECHANGE( rmesa
, ctx
);
74 pp_misc
&= ~(RADEON_ALPHA_TEST_OP_MASK
| RADEON_REF_ALPHA_MASK
);
75 pp_misc
|= (refByte
& RADEON_REF_ALPHA_MASK
);
79 pp_misc
|= RADEON_ALPHA_TEST_FAIL
;
82 pp_misc
|= RADEON_ALPHA_TEST_LESS
;
85 pp_misc
|= RADEON_ALPHA_TEST_EQUAL
;
88 pp_misc
|= RADEON_ALPHA_TEST_LEQUAL
;
91 pp_misc
|= RADEON_ALPHA_TEST_GREATER
;
94 pp_misc
|= RADEON_ALPHA_TEST_NEQUAL
;
97 pp_misc
|= RADEON_ALPHA_TEST_GEQUAL
;
100 pp_misc
|= RADEON_ALPHA_TEST_PASS
;
104 rmesa
->hw
.ctx
.cmd
[CTX_PP_MISC
] = pp_misc
;
107 static void radeonBlendEquationSeparate( GLcontext
*ctx
,
108 GLenum modeRGB
, GLenum modeA
)
110 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
111 GLuint b
= rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] & ~RADEON_COMB_FCN_MASK
;
112 GLboolean fallback
= GL_FALSE
;
114 assert( modeRGB
== modeA
);
119 b
|= RADEON_COMB_FCN_ADD_CLAMP
;
122 case GL_FUNC_SUBTRACT
:
123 b
|= RADEON_COMB_FCN_SUB_CLAMP
;
127 if (ctx
->Color
.BlendEnabled
)
130 b
|= RADEON_COMB_FCN_ADD_CLAMP
;
134 FALLBACK( rmesa
, RADEON_FALLBACK_BLEND_EQ
, fallback
);
136 RADEON_STATECHANGE( rmesa
, ctx
);
137 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] = b
;
138 if ( ctx
->Color
._LogicOpEnabled
) {
139 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_ROP_ENABLE
;
141 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_ROP_ENABLE
;
146 static void radeonBlendFuncSeparate( GLcontext
*ctx
,
147 GLenum sfactorRGB
, GLenum dfactorRGB
,
148 GLenum sfactorA
, GLenum dfactorA
)
150 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
151 GLuint b
= rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] &
152 ~(RADEON_SRC_BLEND_MASK
| RADEON_DST_BLEND_MASK
);
153 GLboolean fallback
= GL_FALSE
;
155 switch ( ctx
->Color
.BlendSrcRGB
) {
157 b
|= RADEON_SRC_BLEND_GL_ZERO
;
160 b
|= RADEON_SRC_BLEND_GL_ONE
;
163 b
|= RADEON_SRC_BLEND_GL_DST_COLOR
;
165 case GL_ONE_MINUS_DST_COLOR
:
166 b
|= RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR
;
169 b
|= RADEON_SRC_BLEND_GL_SRC_COLOR
;
171 case GL_ONE_MINUS_SRC_COLOR
:
172 b
|= RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR
;
175 b
|= RADEON_SRC_BLEND_GL_SRC_ALPHA
;
177 case GL_ONE_MINUS_SRC_ALPHA
:
178 b
|= RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA
;
181 b
|= RADEON_SRC_BLEND_GL_DST_ALPHA
;
183 case GL_ONE_MINUS_DST_ALPHA
:
184 b
|= RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA
;
186 case GL_SRC_ALPHA_SATURATE
:
187 b
|= RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE
;
189 case GL_CONSTANT_COLOR
:
190 case GL_ONE_MINUS_CONSTANT_COLOR
:
191 case GL_CONSTANT_ALPHA
:
192 case GL_ONE_MINUS_CONSTANT_ALPHA
:
193 if (ctx
->Color
.BlendEnabled
)
196 b
|= RADEON_SRC_BLEND_GL_ONE
;
202 switch ( ctx
->Color
.BlendDstRGB
) {
204 b
|= RADEON_DST_BLEND_GL_ZERO
;
207 b
|= RADEON_DST_BLEND_GL_ONE
;
210 b
|= RADEON_DST_BLEND_GL_SRC_COLOR
;
212 case GL_ONE_MINUS_SRC_COLOR
:
213 b
|= RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR
;
216 b
|= RADEON_DST_BLEND_GL_SRC_ALPHA
;
218 case GL_ONE_MINUS_SRC_ALPHA
:
219 b
|= RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA
;
222 b
|= RADEON_DST_BLEND_GL_DST_COLOR
;
224 case GL_ONE_MINUS_DST_COLOR
:
225 b
|= RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR
;
228 b
|= RADEON_DST_BLEND_GL_DST_ALPHA
;
230 case GL_ONE_MINUS_DST_ALPHA
:
231 b
|= RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA
;
233 case GL_CONSTANT_COLOR
:
234 case GL_ONE_MINUS_CONSTANT_COLOR
:
235 case GL_CONSTANT_ALPHA
:
236 case GL_ONE_MINUS_CONSTANT_ALPHA
:
237 if (ctx
->Color
.BlendEnabled
)
240 b
|= RADEON_DST_BLEND_GL_ZERO
;
246 FALLBACK( rmesa
, RADEON_FALLBACK_BLEND_FUNC
, fallback
);
248 RADEON_STATECHANGE( rmesa
, ctx
);
249 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] = b
;
254 /* =============================================================
258 static void radeonDepthFunc( GLcontext
*ctx
, GLenum func
)
260 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
262 RADEON_STATECHANGE( rmesa
, ctx
);
263 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &= ~RADEON_Z_TEST_MASK
;
265 switch ( ctx
->Depth
.Func
) {
267 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_NEVER
;
270 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_LESS
;
273 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_EQUAL
;
276 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_LEQUAL
;
279 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_GREATER
;
282 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_NEQUAL
;
285 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_GEQUAL
;
288 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_ALWAYS
;
294 static void radeonDepthMask( GLcontext
*ctx
, GLboolean flag
)
296 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
297 RADEON_STATECHANGE( rmesa
, ctx
);
299 if ( ctx
->Depth
.Mask
) {
300 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_WRITE_ENABLE
;
302 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &= ~RADEON_Z_WRITE_ENABLE
;
306 static void radeonClearDepth( GLcontext
*ctx
, GLclampd d
)
308 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
309 GLuint format
= (rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &
310 RADEON_DEPTH_FORMAT_MASK
);
313 case RADEON_DEPTH_FORMAT_16BIT_INT_Z
:
314 rmesa
->state
.depth
.clear
= d
* 0x0000ffff;
316 case RADEON_DEPTH_FORMAT_24BIT_INT_Z
:
317 rmesa
->state
.depth
.clear
= d
* 0x00ffffff;
323 /* =============================================================
328 static void radeonFogfv( GLcontext
*ctx
, GLenum pname
, const GLfloat
*param
)
330 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
331 union { int i
; float f
; } c
, d
;
334 c
.i
= rmesa
->hw
.fog
.cmd
[FOG_C
];
335 d
.i
= rmesa
->hw
.fog
.cmd
[FOG_D
];
339 if (!ctx
->Fog
.Enabled
)
341 RADEON_STATECHANGE(rmesa
, tcl
);
342 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~RADEON_TCL_FOG_MASK
;
343 switch (ctx
->Fog
.Mode
) {
345 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_TCL_FOG_LINEAR
;
346 if (ctx
->Fog
.Start
== ctx
->Fog
.End
) {
351 c
.f
= ctx
->Fog
.End
/(ctx
->Fog
.End
-ctx
->Fog
.Start
);
352 d
.f
= 1.0/(ctx
->Fog
.End
-ctx
->Fog
.Start
);
356 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_TCL_FOG_EXP
;
358 d
.f
= ctx
->Fog
.Density
;
361 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_TCL_FOG_EXP2
;
363 d
.f
= -(ctx
->Fog
.Density
* ctx
->Fog
.Density
);
370 switch (ctx
->Fog
.Mode
) {
373 d
.f
= ctx
->Fog
.Density
;
377 d
.f
= -(ctx
->Fog
.Density
* ctx
->Fog
.Density
);
385 if (ctx
->Fog
.Mode
== GL_LINEAR
) {
386 if (ctx
->Fog
.Start
== ctx
->Fog
.End
) {
390 c
.f
= ctx
->Fog
.End
/(ctx
->Fog
.End
-ctx
->Fog
.Start
);
391 d
.f
= 1.0/(ctx
->Fog
.End
-ctx
->Fog
.Start
);
396 RADEON_STATECHANGE( rmesa
, ctx
);
397 UNCLAMPED_FLOAT_TO_RGB_CHAN( col
, ctx
->Fog
.Color
);
398 rmesa
->hw
.ctx
.cmd
[CTX_PP_FOG_COLOR
] =
399 radeonPackColor( 4, col
[0], col
[1], col
[2], 0 );
401 case GL_FOG_COORDINATE_SOURCE_EXT
:
409 if (c
.i
!= rmesa
->hw
.fog
.cmd
[FOG_C
] || d
.i
!= rmesa
->hw
.fog
.cmd
[FOG_D
]) {
410 RADEON_STATECHANGE( rmesa
, fog
);
411 rmesa
->hw
.fog
.cmd
[FOG_C
] = c
.i
;
412 rmesa
->hw
.fog
.cmd
[FOG_D
] = d
.i
;
417 /* =============================================================
422 static GLboolean
intersect_rect( drm_clip_rect_t
*out
,
427 if ( b
->x1
> out
->x1
) out
->x1
= b
->x1
;
428 if ( b
->y1
> out
->y1
) out
->y1
= b
->y1
;
429 if ( b
->x2
< out
->x2
) out
->x2
= b
->x2
;
430 if ( b
->y2
< out
->y2
) out
->y2
= b
->y2
;
431 if ( out
->x1
>= out
->x2
) return GL_FALSE
;
432 if ( out
->y1
>= out
->y2
) return GL_FALSE
;
437 void radeonRecalcScissorRects( radeonContextPtr rmesa
)
439 drm_clip_rect_t
*out
;
442 /* Grow cliprect store?
444 if (rmesa
->state
.scissor
.numAllocedClipRects
< rmesa
->numClipRects
) {
445 while (rmesa
->state
.scissor
.numAllocedClipRects
< rmesa
->numClipRects
) {
446 rmesa
->state
.scissor
.numAllocedClipRects
+= 1; /* zero case */
447 rmesa
->state
.scissor
.numAllocedClipRects
*= 2;
450 if (rmesa
->state
.scissor
.pClipRects
)
451 FREE(rmesa
->state
.scissor
.pClipRects
);
453 rmesa
->state
.scissor
.pClipRects
=
454 MALLOC( rmesa
->state
.scissor
.numAllocedClipRects
*
455 sizeof(drm_clip_rect_t
) );
457 if ( rmesa
->state
.scissor
.pClipRects
== NULL
) {
458 rmesa
->state
.scissor
.numAllocedClipRects
= 0;
463 out
= rmesa
->state
.scissor
.pClipRects
;
464 rmesa
->state
.scissor
.numClipRects
= 0;
466 for ( i
= 0 ; i
< rmesa
->numClipRects
; i
++ ) {
467 if ( intersect_rect( out
,
468 &rmesa
->pClipRects
[i
],
469 &rmesa
->state
.scissor
.rect
) ) {
470 rmesa
->state
.scissor
.numClipRects
++;
477 static void radeonUpdateScissor( GLcontext
*ctx
)
479 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
481 if ( rmesa
->dri
.drawable
) {
482 __DRIdrawablePrivate
*dPriv
= rmesa
->dri
.drawable
;
484 int x
= ctx
->Scissor
.X
;
485 int y
= dPriv
->h
- ctx
->Scissor
.Y
- ctx
->Scissor
.Height
;
486 int w
= ctx
->Scissor
.X
+ ctx
->Scissor
.Width
- 1;
487 int h
= dPriv
->h
- ctx
->Scissor
.Y
- 1;
489 rmesa
->state
.scissor
.rect
.x1
= x
+ dPriv
->x
;
490 rmesa
->state
.scissor
.rect
.y1
= y
+ dPriv
->y
;
491 rmesa
->state
.scissor
.rect
.x2
= w
+ dPriv
->x
+ 1;
492 rmesa
->state
.scissor
.rect
.y2
= h
+ dPriv
->y
+ 1;
494 radeonRecalcScissorRects( rmesa
);
499 static void radeonScissor( GLcontext
*ctx
,
500 GLint x
, GLint y
, GLsizei w
, GLsizei h
)
502 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
504 if ( ctx
->Scissor
.Enabled
) {
505 RADEON_FIREVERTICES( rmesa
); /* don't pipeline cliprect changes */
506 radeonUpdateScissor( ctx
);
512 /* =============================================================
516 static void radeonCullFace( GLcontext
*ctx
, GLenum unused
)
518 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
519 GLuint s
= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
];
520 GLuint t
= rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
];
522 s
|= RADEON_FFACE_SOLID
| RADEON_BFACE_SOLID
;
523 t
&= ~(RADEON_CULL_FRONT
| RADEON_CULL_BACK
);
525 if ( ctx
->Polygon
.CullFlag
) {
526 switch ( ctx
->Polygon
.CullFaceMode
) {
528 s
&= ~RADEON_FFACE_SOLID
;
529 t
|= RADEON_CULL_FRONT
;
532 s
&= ~RADEON_BFACE_SOLID
;
533 t
|= RADEON_CULL_BACK
;
535 case GL_FRONT_AND_BACK
:
536 s
&= ~(RADEON_FFACE_SOLID
| RADEON_BFACE_SOLID
);
537 t
|= (RADEON_CULL_FRONT
| RADEON_CULL_BACK
);
542 if ( rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] != s
) {
543 RADEON_STATECHANGE(rmesa
, set
);
544 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = s
;
547 if ( rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] != t
) {
548 RADEON_STATECHANGE(rmesa
, tcl
);
549 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] = t
;
553 static void radeonFrontFace( GLcontext
*ctx
, GLenum mode
)
555 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
557 RADEON_STATECHANGE( rmesa
, set
);
558 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_FFACE_CULL_DIR_MASK
;
560 RADEON_STATECHANGE( rmesa
, tcl
);
561 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~RADEON_CULL_FRONT_IS_CCW
;
565 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_FFACE_CULL_CW
;
568 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_FFACE_CULL_CCW
;
569 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_CULL_FRONT_IS_CCW
;
575 /* =============================================================
578 static void radeonLineWidth( GLcontext
*ctx
, GLfloat widthf
)
580 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
582 RADEON_STATECHANGE( rmesa
, lin
);
583 RADEON_STATECHANGE( rmesa
, set
);
585 /* Line width is stored in U6.4 format.
587 rmesa
->hw
.lin
.cmd
[LIN_SE_LINE_WIDTH
] = (GLuint
)(widthf
* 16.0);
588 if ( widthf
> 1.0 ) {
589 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_WIDELINE_ENABLE
;
591 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_WIDELINE_ENABLE
;
595 static void radeonLineStipple( GLcontext
*ctx
, GLint factor
, GLushort pattern
)
597 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
599 RADEON_STATECHANGE( rmesa
, lin
);
600 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_PATTERN
] =
601 ((((GLuint
)factor
& 0xff) << 16) | ((GLuint
)pattern
));
605 /* =============================================================
608 static void radeonColorMask( GLcontext
*ctx
,
609 GLboolean r
, GLboolean g
,
610 GLboolean b
, GLboolean a
)
612 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
613 GLuint mask
= radeonPackColor( rmesa
->radeonScreen
->cpp
,
614 ctx
->Color
.ColorMask
[RCOMP
],
615 ctx
->Color
.ColorMask
[GCOMP
],
616 ctx
->Color
.ColorMask
[BCOMP
],
617 ctx
->Color
.ColorMask
[ACOMP
] );
619 if ( rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
] != mask
) {
620 RADEON_STATECHANGE( rmesa
, msk
);
621 rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
] = mask
;
626 /* =============================================================
630 static void radeonPolygonOffset( GLcontext
*ctx
,
631 GLfloat factor
, GLfloat units
)
633 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
634 GLfloat constant
= units
* rmesa
->state
.depth
.scale
;
636 RADEON_STATECHANGE( rmesa
, zbs
);
637 rmesa
->hw
.zbs
.cmd
[ZBS_SE_ZBIAS_FACTOR
] = *(GLuint
*)&factor
;
638 rmesa
->hw
.zbs
.cmd
[ZBS_SE_ZBIAS_CONSTANT
] = *(GLuint
*)&constant
;
641 static void radeonPolygonStipple( GLcontext
*ctx
, const GLubyte
*mask
)
643 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
645 drm_radeon_stipple_t stipple
;
647 /* Must flip pattern upside down.
649 for ( i
= 0 ; i
< 32 ; i
++ ) {
650 rmesa
->state
.stipple
.mask
[31 - i
] = ((GLuint
*) mask
)[i
];
653 /* TODO: push this into cmd mechanism
655 RADEON_FIREVERTICES( rmesa
);
656 LOCK_HARDWARE( rmesa
);
658 /* FIXME: Use window x,y offsets into stipple RAM.
660 stipple
.mask
= rmesa
->state
.stipple
.mask
;
661 drmCommandWrite( rmesa
->dri
.fd
, DRM_RADEON_STIPPLE
,
662 &stipple
, sizeof(drm_radeon_stipple_t
) );
663 UNLOCK_HARDWARE( rmesa
);
666 static void radeonPolygonMode( GLcontext
*ctx
, GLenum face
, GLenum mode
)
668 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
669 GLboolean flag
= (ctx
->_TriangleCaps
& DD_TRI_UNFILLED
) != 0;
671 /* Can't generally do unfilled via tcl, but some good special
674 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_UNFILLED
, flag
);
675 if (rmesa
->TclFallback
) {
676 radeonChooseRenderState( ctx
);
677 radeonChooseVertexState( ctx
);
682 /* =============================================================
683 * Rendering attributes
685 * We really don't want to recalculate all this every time we bind a
686 * texture. These things shouldn't change all that often, so it makes
687 * sense to break them out of the core texture state update routines.
690 /* Examine lighting and texture state to determine if separate specular
693 static void radeonUpdateSpecular( GLcontext
*ctx
)
695 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
696 u_int32_t p
= rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
];
698 RADEON_STATECHANGE( rmesa
, tcl
);
700 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] &= ~RADEON_TCL_COMPUTE_SPECULAR
;
701 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] &= ~RADEON_TCL_COMPUTE_DIFFUSE
;
702 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] &= ~RADEON_TCL_VTX_PK_SPEC
;
703 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] &= ~RADEON_TCL_VTX_PK_DIFFUSE
;
704 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_LIGHTING_ENABLE
;
706 p
&= ~RADEON_SPECULAR_ENABLE
;
708 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_DIFFUSE_SPECULAR_COMBINE
;
711 if (ctx
->Light
.Enabled
&&
712 ctx
->Light
.Model
.ColorControl
== GL_SEPARATE_SPECULAR_COLOR
) {
713 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] |= RADEON_TCL_COMPUTE_SPECULAR
;
714 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] |= RADEON_TCL_COMPUTE_DIFFUSE
;
715 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_SPEC
;
716 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_DIFFUSE
;
717 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_LIGHTING_ENABLE
;
718 p
|= RADEON_SPECULAR_ENABLE
;
719 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &=
720 ~RADEON_DIFFUSE_SPECULAR_COMBINE
;
722 else if (ctx
->Light
.Enabled
) {
723 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] |= RADEON_TCL_COMPUTE_DIFFUSE
;
724 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_DIFFUSE
;
725 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_LIGHTING_ENABLE
;
726 } else if (ctx
->Fog
.ColorSumEnabled
) {
727 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_SPEC
;
728 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_DIFFUSE
;
729 p
|= RADEON_SPECULAR_ENABLE
;
731 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_DIFFUSE
;
734 if (ctx
->Fog
.Enabled
) {
735 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] |= RADEON_TCL_COMPUTE_SPECULAR
;
736 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_SPEC
;
738 /* Bizzare: have to leave lighting enabled to get fog.
740 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_LIGHTING_ENABLE
;
743 if (NEED_SECONDARY_COLOR(ctx
)) {
744 assert( (p
& RADEON_SPECULAR_ENABLE
) != 0 );
746 assert( (p
& RADEON_SPECULAR_ENABLE
) == 0 );
749 if ( rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] != p
) {
750 RADEON_STATECHANGE( rmesa
, ctx
);
751 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] = p
;
754 /* Update vertex/render formats
756 if (rmesa
->TclFallback
) {
757 radeonChooseRenderState( ctx
);
758 radeonChooseVertexState( ctx
);
763 /* =============================================================
768 /* Update on colormaterial, material emmissive/ambient,
769 * lightmodel.globalambient
771 static void update_global_ambient( GLcontext
*ctx
)
773 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
774 float *fcmd
= (float *)RADEON_DB_STATE( glt
);
776 /* Need to do more if both emmissive & ambient are PREMULT:
777 * Hope this is not needed for MULT
779 if ((rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &
780 ((3 << RADEON_EMISSIVE_SOURCE_SHIFT
) |
781 (3 << RADEON_AMBIENT_SOURCE_SHIFT
))) == 0)
783 COPY_3V( &fcmd
[GLT_RED
],
784 ctx
->Light
.Material
.Attrib
[MAT_ATTRIB_FRONT_EMISSION
]);
785 ACC_SCALE_3V( &fcmd
[GLT_RED
],
786 ctx
->Light
.Model
.Ambient
,
787 ctx
->Light
.Material
.Attrib
[MAT_ATTRIB_FRONT_AMBIENT
]);
791 COPY_3V( &fcmd
[GLT_RED
], ctx
->Light
.Model
.Ambient
);
794 RADEON_DB_STATECHANGE(rmesa
, &rmesa
->hw
.glt
);
797 /* Update on change to
801 static void update_light_colors( GLcontext
*ctx
, GLuint p
)
803 struct gl_light
*l
= &ctx
->Light
.Light
[p
];
805 /* fprintf(stderr, "%s\n", __FUNCTION__); */
808 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
809 float *fcmd
= (float *)RADEON_DB_STATE( lit
[p
] );
811 COPY_4V( &fcmd
[LIT_AMBIENT_RED
], l
->Ambient
);
812 COPY_4V( &fcmd
[LIT_DIFFUSE_RED
], l
->Diffuse
);
813 COPY_4V( &fcmd
[LIT_SPECULAR_RED
], l
->Specular
);
815 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.lit
[p
] );
819 /* Also fallback for asym colormaterial mode in twoside lighting...
821 static void check_twoside_fallback( GLcontext
*ctx
)
823 GLboolean fallback
= GL_FALSE
;
826 if (ctx
->Light
.Enabled
&& ctx
->Light
.Model
.TwoSide
) {
827 if (ctx
->Light
.ColorMaterialEnabled
&&
828 (ctx
->Light
.ColorMaterialBitmask
& BACK_MATERIAL_BITS
) !=
829 ((ctx
->Light
.ColorMaterialBitmask
& FRONT_MATERIAL_BITS
)<<1))
832 for (i
= MAT_ATTRIB_FRONT_AMBIENT
; i
< MAT_ATTRIB_FRONT_INDEXES
; i
+=2)
833 if (memcmp( ctx
->Light
.Material
.Attrib
[i
],
834 ctx
->Light
.Material
.Attrib
[i
+1],
835 sizeof(GLfloat
)*4) != 0) {
842 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_LIGHT_TWOSIDE
, fallback
);
846 static void radeonColorMaterial( GLcontext
*ctx
, GLenum face
, GLenum mode
)
848 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
849 GLuint light_model_ctl1
= rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
];
851 light_model_ctl1
&= ~((3 << RADEON_EMISSIVE_SOURCE_SHIFT
) |
852 (3 << RADEON_AMBIENT_SOURCE_SHIFT
) |
853 (3 << RADEON_DIFFUSE_SOURCE_SHIFT
) |
854 (3 << RADEON_SPECULAR_SOURCE_SHIFT
));
856 if (ctx
->Light
.ColorMaterialEnabled
) {
857 GLuint mask
= ctx
->Light
.ColorMaterialBitmask
;
859 if (mask
& MAT_BIT_FRONT_EMISSION
) {
860 light_model_ctl1
|= (RADEON_LM_SOURCE_VERTEX_DIFFUSE
<<
861 RADEON_EMISSIVE_SOURCE_SHIFT
);
864 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<<
865 RADEON_EMISSIVE_SOURCE_SHIFT
);
868 if (mask
& MAT_BIT_FRONT_AMBIENT
) {
869 light_model_ctl1
|= (RADEON_LM_SOURCE_VERTEX_DIFFUSE
<<
870 RADEON_AMBIENT_SOURCE_SHIFT
);
873 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<<
874 RADEON_AMBIENT_SOURCE_SHIFT
);
877 if (mask
& MAT_BIT_FRONT_DIFFUSE
) {
878 light_model_ctl1
|= (RADEON_LM_SOURCE_VERTEX_DIFFUSE
<<
879 RADEON_DIFFUSE_SOURCE_SHIFT
);
882 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<<
883 RADEON_DIFFUSE_SOURCE_SHIFT
);
886 if (mask
& MAT_BIT_FRONT_SPECULAR
) {
887 light_model_ctl1
|= (RADEON_LM_SOURCE_VERTEX_DIFFUSE
<<
888 RADEON_SPECULAR_SOURCE_SHIFT
);
891 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<<
892 RADEON_SPECULAR_SOURCE_SHIFT
);
898 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_EMISSIVE_SOURCE_SHIFT
) |
899 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_AMBIENT_SOURCE_SHIFT
) |
900 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_DIFFUSE_SOURCE_SHIFT
) |
901 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_SPECULAR_SOURCE_SHIFT
);
904 if (light_model_ctl1
!= rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
]) {
905 RADEON_STATECHANGE( rmesa
, tcl
);
906 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] = light_model_ctl1
;
910 void radeonUpdateMaterial( GLcontext
*ctx
)
912 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
913 GLfloat (*mat
)[4] = ctx
->Light
.Material
.Attrib
;
914 GLfloat
*fcmd
= (GLfloat
*)RADEON_DB_STATE( mtl
);
917 if (ctx
->Light
.ColorMaterialEnabled
)
918 mask
&= ~ctx
->Light
.ColorMaterialBitmask
;
920 if (RADEON_DEBUG
& DEBUG_STATE
)
921 fprintf(stderr
, "%s\n", __FUNCTION__
);
924 if (mask
& MAT_BIT_FRONT_EMISSION
) {
925 fcmd
[MTL_EMMISSIVE_RED
] = mat
[MAT_ATTRIB_FRONT_EMISSION
][0];
926 fcmd
[MTL_EMMISSIVE_GREEN
] = mat
[MAT_ATTRIB_FRONT_EMISSION
][1];
927 fcmd
[MTL_EMMISSIVE_BLUE
] = mat
[MAT_ATTRIB_FRONT_EMISSION
][2];
928 fcmd
[MTL_EMMISSIVE_ALPHA
] = mat
[MAT_ATTRIB_FRONT_EMISSION
][3];
930 if (mask
& MAT_BIT_FRONT_AMBIENT
) {
931 fcmd
[MTL_AMBIENT_RED
] = mat
[MAT_ATTRIB_FRONT_AMBIENT
][0];
932 fcmd
[MTL_AMBIENT_GREEN
] = mat
[MAT_ATTRIB_FRONT_AMBIENT
][1];
933 fcmd
[MTL_AMBIENT_BLUE
] = mat
[MAT_ATTRIB_FRONT_AMBIENT
][2];
934 fcmd
[MTL_AMBIENT_ALPHA
] = mat
[MAT_ATTRIB_FRONT_AMBIENT
][3];
936 if (mask
& MAT_BIT_FRONT_DIFFUSE
) {
937 fcmd
[MTL_DIFFUSE_RED
] = mat
[MAT_ATTRIB_FRONT_DIFFUSE
][0];
938 fcmd
[MTL_DIFFUSE_GREEN
] = mat
[MAT_ATTRIB_FRONT_DIFFUSE
][1];
939 fcmd
[MTL_DIFFUSE_BLUE
] = mat
[MAT_ATTRIB_FRONT_DIFFUSE
][2];
940 fcmd
[MTL_DIFFUSE_ALPHA
] = mat
[MAT_ATTRIB_FRONT_DIFFUSE
][3];
942 if (mask
& MAT_BIT_FRONT_SPECULAR
) {
943 fcmd
[MTL_SPECULAR_RED
] = mat
[MAT_ATTRIB_FRONT_SPECULAR
][0];
944 fcmd
[MTL_SPECULAR_GREEN
] = mat
[MAT_ATTRIB_FRONT_SPECULAR
][1];
945 fcmd
[MTL_SPECULAR_BLUE
] = mat
[MAT_ATTRIB_FRONT_SPECULAR
][2];
946 fcmd
[MTL_SPECULAR_ALPHA
] = mat
[MAT_ATTRIB_FRONT_SPECULAR
][3];
948 if (mask
& MAT_BIT_FRONT_SHININESS
) {
949 fcmd
[MTL_SHININESS
] = mat
[MAT_ATTRIB_FRONT_SHININESS
][0];
952 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.mtl
);
954 check_twoside_fallback( ctx
);
955 /* update_global_ambient( ctx );*/
960 * _MESA_NEW_NEED_EYE_COORDS
962 * Uses derived state from mesa:
971 * which are calculated in light.c and are correct for the current
972 * lighting space (model or eye), hence dependencies on _NEW_MODELVIEW
973 * and _MESA_NEW_NEED_EYE_COORDS.
975 static void update_light( GLcontext
*ctx
)
977 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
979 /* Have to check these, or have an automatic shortcircuit mechanism
980 * to remove noop statechanges. (Or just do a better job on the
984 GLuint tmp
= rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
];
986 if (ctx
->_NeedEyeCoords
)
987 tmp
&= ~RADEON_LIGHT_IN_MODELSPACE
;
989 tmp
|= RADEON_LIGHT_IN_MODELSPACE
;
992 /* Leave this test disabled: (unexplained q3 lockup) (even with
995 if (tmp
!= rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
])
997 RADEON_STATECHANGE( rmesa
, tcl
);
998 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] = tmp
;
1003 GLfloat
*fcmd
= (GLfloat
*)RADEON_DB_STATE( eye
);
1004 fcmd
[EYE_X
] = ctx
->_EyeZDir
[0];
1005 fcmd
[EYE_Y
] = ctx
->_EyeZDir
[1];
1006 fcmd
[EYE_Z
] = - ctx
->_EyeZDir
[2];
1007 fcmd
[EYE_RESCALE_FACTOR
] = ctx
->_ModelViewInvScale
;
1008 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.eye
);
1013 if (ctx
->Light
.Enabled
) {
1015 for (p
= 0 ; p
< MAX_LIGHTS
; p
++) {
1016 if (ctx
->Light
.Light
[p
].Enabled
) {
1017 struct gl_light
*l
= &ctx
->Light
.Light
[p
];
1018 GLfloat
*fcmd
= (GLfloat
*)RADEON_DB_STATE( lit
[p
] );
1020 if (l
->EyePosition
[3] == 0.0) {
1021 COPY_3FV( &fcmd
[LIT_POSITION_X
], l
->_VP_inf_norm
);
1022 COPY_3FV( &fcmd
[LIT_DIRECTION_X
], l
->_h_inf_norm
);
1023 fcmd
[LIT_POSITION_W
] = 0;
1024 fcmd
[LIT_DIRECTION_W
] = 0;
1026 COPY_4V( &fcmd
[LIT_POSITION_X
], l
->_Position
);
1027 fcmd
[LIT_DIRECTION_X
] = -l
->_NormDirection
[0];
1028 fcmd
[LIT_DIRECTION_Y
] = -l
->_NormDirection
[1];
1029 fcmd
[LIT_DIRECTION_Z
] = -l
->_NormDirection
[2];
1030 fcmd
[LIT_DIRECTION_W
] = 0;
1033 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.lit
[p
] );
1039 static void radeonLightfv( GLcontext
*ctx
, GLenum light
,
1040 GLenum pname
, const GLfloat
*params
)
1042 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1043 GLint p
= light
- GL_LIGHT0
;
1044 struct gl_light
*l
= &ctx
->Light
.Light
[p
];
1045 GLfloat
*fcmd
= (GLfloat
*)rmesa
->hw
.lit
[p
].cmd
;
1052 update_light_colors( ctx
, p
);
1055 case GL_SPOT_DIRECTION
:
1056 /* picked up in update_light */
1060 /* positions picked up in update_light, but can do flag here */
1062 GLuint idx
= TCL_PER_LIGHT_CTL_0
+ p
/2;
1064 /* FIXME: Set RANGE_ATTEN only when needed */
1066 flag
= RADEON_LIGHT_1_IS_LOCAL
;
1068 flag
= RADEON_LIGHT_0_IS_LOCAL
;
1070 RADEON_STATECHANGE(rmesa
, tcl
);
1071 if (l
->EyePosition
[3] != 0.0F
)
1072 rmesa
->hw
.tcl
.cmd
[idx
] |= flag
;
1074 rmesa
->hw
.tcl
.cmd
[idx
] &= ~flag
;
1078 case GL_SPOT_EXPONENT
:
1079 RADEON_STATECHANGE(rmesa
, lit
[p
]);
1080 fcmd
[LIT_SPOT_EXPONENT
] = params
[0];
1083 case GL_SPOT_CUTOFF
: {
1084 GLuint flag
= (p
&1) ? RADEON_LIGHT_1_IS_SPOT
: RADEON_LIGHT_0_IS_SPOT
;
1085 GLuint idx
= TCL_PER_LIGHT_CTL_0
+ p
/2;
1087 RADEON_STATECHANGE(rmesa
, lit
[p
]);
1088 fcmd
[LIT_SPOT_CUTOFF
] = l
->_CosCutoff
;
1090 RADEON_STATECHANGE(rmesa
, tcl
);
1091 if (l
->SpotCutoff
!= 180.0F
)
1092 rmesa
->hw
.tcl
.cmd
[idx
] |= flag
;
1094 rmesa
->hw
.tcl
.cmd
[idx
] &= ~flag
;
1099 case GL_CONSTANT_ATTENUATION
:
1100 RADEON_STATECHANGE(rmesa
, lit
[p
]);
1101 fcmd
[LIT_ATTEN_CONST
] = params
[0];
1102 if ( params
[0] == 0.0 )
1103 fcmd
[LIT_ATTEN_CONST_INV
] = FLT_MAX
;
1105 fcmd
[LIT_ATTEN_CONST_INV
] = 1.0 / params
[0];
1107 case GL_LINEAR_ATTENUATION
:
1108 RADEON_STATECHANGE(rmesa
, lit
[p
]);
1109 fcmd
[LIT_ATTEN_LINEAR
] = params
[0];
1111 case GL_QUADRATIC_ATTENUATION
:
1112 RADEON_STATECHANGE(rmesa
, lit
[p
]);
1113 fcmd
[LIT_ATTEN_QUADRATIC
] = params
[0];
1119 /* Set RANGE_ATTEN only when needed */
1122 case GL_CONSTANT_ATTENUATION
:
1123 case GL_LINEAR_ATTENUATION
:
1124 case GL_QUADRATIC_ATTENUATION
:
1126 GLuint
*icmd
= (GLuint
*)RADEON_DB_STATE( tcl
);
1127 GLuint idx
= TCL_PER_LIGHT_CTL_0
+ p
/2;
1128 GLuint atten_flag
= ( p
&1 ) ? RADEON_LIGHT_1_ENABLE_RANGE_ATTEN
1129 : RADEON_LIGHT_0_ENABLE_RANGE_ATTEN
;
1130 GLuint atten_const_flag
= ( p
&1 ) ? RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN
1131 : RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN
;
1133 if ( l
->EyePosition
[3] == 0.0F
||
1134 ( ( fcmd
[LIT_ATTEN_CONST
] == 0.0 || fcmd
[LIT_ATTEN_CONST
] == 1.0 ) &&
1135 fcmd
[LIT_ATTEN_QUADRATIC
] == 0.0 && fcmd
[LIT_ATTEN_LINEAR
] == 0.0 ) ) {
1136 /* Disable attenuation */
1137 icmd
[idx
] &= ~atten_flag
;
1139 if ( fcmd
[LIT_ATTEN_QUADRATIC
] == 0.0 && fcmd
[LIT_ATTEN_LINEAR
] == 0.0 ) {
1140 /* Enable only constant portion of attenuation calculation */
1141 icmd
[idx
] |= ( atten_flag
| atten_const_flag
);
1143 /* Enable full attenuation calculation */
1144 icmd
[idx
] &= ~atten_const_flag
;
1145 icmd
[idx
] |= atten_flag
;
1149 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.tcl
);
1160 static void radeonLightModelfv( GLcontext
*ctx
, GLenum pname
,
1161 const GLfloat
*param
)
1163 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1166 case GL_LIGHT_MODEL_AMBIENT
:
1167 update_global_ambient( ctx
);
1170 case GL_LIGHT_MODEL_LOCAL_VIEWER
:
1171 RADEON_STATECHANGE( rmesa
, tcl
);
1172 if (ctx
->Light
.Model
.LocalViewer
)
1173 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_LOCAL_VIEWER
;
1175 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_LOCAL_VIEWER
;
1178 case GL_LIGHT_MODEL_TWO_SIDE
:
1179 RADEON_STATECHANGE( rmesa
, tcl
);
1180 if (ctx
->Light
.Model
.TwoSide
)
1181 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_LIGHT_TWOSIDE
;
1183 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~RADEON_LIGHT_TWOSIDE
;
1185 check_twoside_fallback( ctx
);
1187 if (rmesa
->TclFallback
) {
1188 radeonChooseRenderState( ctx
);
1189 radeonChooseVertexState( ctx
);
1193 case GL_LIGHT_MODEL_COLOR_CONTROL
:
1194 radeonUpdateSpecular(ctx
);
1202 static void radeonShadeModel( GLcontext
*ctx
, GLenum mode
)
1204 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1205 GLuint s
= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
];
1207 s
&= ~(RADEON_DIFFUSE_SHADE_MASK
|
1208 RADEON_ALPHA_SHADE_MASK
|
1209 RADEON_SPECULAR_SHADE_MASK
|
1210 RADEON_FOG_SHADE_MASK
);
1214 s
|= (RADEON_DIFFUSE_SHADE_FLAT
|
1215 RADEON_ALPHA_SHADE_FLAT
|
1216 RADEON_SPECULAR_SHADE_FLAT
|
1217 RADEON_FOG_SHADE_FLAT
);
1220 s
|= (RADEON_DIFFUSE_SHADE_GOURAUD
|
1221 RADEON_ALPHA_SHADE_GOURAUD
|
1222 RADEON_SPECULAR_SHADE_GOURAUD
|
1223 RADEON_FOG_SHADE_GOURAUD
);
1229 if ( rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] != s
) {
1230 RADEON_STATECHANGE( rmesa
, set
);
1231 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = s
;
1236 /* =============================================================
1240 static void radeonClipPlane( GLcontext
*ctx
, GLenum plane
, const GLfloat
*eq
)
1242 GLint p
= (GLint
) plane
- (GLint
) GL_CLIP_PLANE0
;
1243 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1244 GLint
*ip
= (GLint
*)ctx
->Transform
._ClipUserPlane
[p
];
1246 RADEON_STATECHANGE( rmesa
, ucp
[p
] );
1247 rmesa
->hw
.ucp
[p
].cmd
[UCP_X
] = ip
[0];
1248 rmesa
->hw
.ucp
[p
].cmd
[UCP_Y
] = ip
[1];
1249 rmesa
->hw
.ucp
[p
].cmd
[UCP_Z
] = ip
[2];
1250 rmesa
->hw
.ucp
[p
].cmd
[UCP_W
] = ip
[3];
1253 static void radeonUpdateClipPlanes( GLcontext
*ctx
)
1255 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1258 for (p
= 0; p
< ctx
->Const
.MaxClipPlanes
; p
++) {
1259 if (ctx
->Transform
.ClipPlanesEnabled
& (1 << p
)) {
1260 GLint
*ip
= (GLint
*)ctx
->Transform
._ClipUserPlane
[p
];
1262 RADEON_STATECHANGE( rmesa
, ucp
[p
] );
1263 rmesa
->hw
.ucp
[p
].cmd
[UCP_X
] = ip
[0];
1264 rmesa
->hw
.ucp
[p
].cmd
[UCP_Y
] = ip
[1];
1265 rmesa
->hw
.ucp
[p
].cmd
[UCP_Z
] = ip
[2];
1266 rmesa
->hw
.ucp
[p
].cmd
[UCP_W
] = ip
[3];
1272 /* =============================================================
1276 static void radeonStencilFunc( GLcontext
*ctx
, GLenum func
,
1277 GLint ref
, GLuint mask
)
1279 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1280 GLuint refmask
= ((ctx
->Stencil
.Ref
[0] << RADEON_STENCIL_REF_SHIFT
) |
1281 (ctx
->Stencil
.ValueMask
[0] << RADEON_STENCIL_MASK_SHIFT
));
1283 RADEON_STATECHANGE( rmesa
, ctx
);
1284 RADEON_STATECHANGE( rmesa
, msk
);
1286 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &= ~RADEON_STENCIL_TEST_MASK
;
1287 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] &= ~(RADEON_STENCIL_REF_MASK
|
1288 RADEON_STENCIL_VALUE_MASK
);
1290 switch ( ctx
->Stencil
.Function
[0] ) {
1292 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_NEVER
;
1295 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_LESS
;
1298 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_EQUAL
;
1301 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_LEQUAL
;
1304 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_GREATER
;
1307 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_NEQUAL
;
1310 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_GEQUAL
;
1313 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_ALWAYS
;
1317 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] |= refmask
;
1320 static void radeonStencilMask( GLcontext
*ctx
, GLuint mask
)
1322 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1324 RADEON_STATECHANGE( rmesa
, msk
);
1325 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] &= ~RADEON_STENCIL_WRITE_MASK
;
1326 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] |=
1327 (ctx
->Stencil
.WriteMask
[0] << RADEON_STENCIL_WRITEMASK_SHIFT
);
1330 static void radeonStencilOp( GLcontext
*ctx
, GLenum fail
,
1331 GLenum zfail
, GLenum zpass
)
1333 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1335 /* radeon 7200 have stencil bug, DEC and INC_WRAP will actually both do DEC_WRAP,
1336 and DEC_WRAP (and INVERT) will do INVERT. No way to get correct INC_WRAP and DEC,
1337 but DEC_WRAP can be fixed by using DEC and INC_WRAP at least use INC. */
1339 GLuint tempRADEON_STENCIL_FAIL_DEC_WRAP
;
1340 GLuint tempRADEON_STENCIL_FAIL_INC_WRAP
;
1341 GLuint tempRADEON_STENCIL_ZFAIL_DEC_WRAP
;
1342 GLuint tempRADEON_STENCIL_ZFAIL_INC_WRAP
;
1343 GLuint tempRADEON_STENCIL_ZPASS_DEC_WRAP
;
1344 GLuint tempRADEON_STENCIL_ZPASS_INC_WRAP
;
1346 if (rmesa
->radeonScreen
->chipset
& RADEON_CHIPSET_BROKEN_STENCIL
) {
1347 tempRADEON_STENCIL_FAIL_DEC_WRAP
= RADEON_STENCIL_FAIL_DEC
;
1348 tempRADEON_STENCIL_FAIL_INC_WRAP
= RADEON_STENCIL_FAIL_INC
;
1349 tempRADEON_STENCIL_ZFAIL_DEC_WRAP
= RADEON_STENCIL_ZFAIL_DEC
;
1350 tempRADEON_STENCIL_ZFAIL_INC_WRAP
= RADEON_STENCIL_ZFAIL_INC
;
1351 tempRADEON_STENCIL_ZPASS_DEC_WRAP
= RADEON_STENCIL_ZPASS_DEC
;
1352 tempRADEON_STENCIL_ZPASS_INC_WRAP
= RADEON_STENCIL_ZPASS_INC
;
1355 tempRADEON_STENCIL_FAIL_DEC_WRAP
= RADEON_STENCIL_FAIL_DEC_WRAP
;
1356 tempRADEON_STENCIL_FAIL_INC_WRAP
= RADEON_STENCIL_FAIL_INC_WRAP
;
1357 tempRADEON_STENCIL_ZFAIL_DEC_WRAP
= RADEON_STENCIL_ZFAIL_DEC_WRAP
;
1358 tempRADEON_STENCIL_ZFAIL_INC_WRAP
= RADEON_STENCIL_ZFAIL_INC_WRAP
;
1359 tempRADEON_STENCIL_ZPASS_DEC_WRAP
= RADEON_STENCIL_ZPASS_DEC_WRAP
;
1360 tempRADEON_STENCIL_ZPASS_INC_WRAP
= RADEON_STENCIL_ZPASS_INC_WRAP
;
1363 RADEON_STATECHANGE( rmesa
, ctx
);
1364 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &= ~(RADEON_STENCIL_FAIL_MASK
|
1365 RADEON_STENCIL_ZFAIL_MASK
|
1366 RADEON_STENCIL_ZPASS_MASK
);
1368 switch ( ctx
->Stencil
.FailFunc
[0] ) {
1370 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_KEEP
;
1373 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_ZERO
;
1376 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_REPLACE
;
1379 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_INC
;
1382 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_DEC
;
1385 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_FAIL_INC_WRAP
;
1388 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_FAIL_DEC_WRAP
;
1391 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_INVERT
;
1395 switch ( ctx
->Stencil
.ZFailFunc
[0] ) {
1397 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_KEEP
;
1400 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_ZERO
;
1403 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_REPLACE
;
1406 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_INC
;
1409 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_DEC
;
1412 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_ZFAIL_INC_WRAP
;
1415 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_ZFAIL_DEC_WRAP
;
1418 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_INVERT
;
1422 switch ( ctx
->Stencil
.ZPassFunc
[0] ) {
1424 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_KEEP
;
1427 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_ZERO
;
1430 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_REPLACE
;
1433 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_INC
;
1436 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_DEC
;
1439 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_ZPASS_INC_WRAP
;
1442 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_ZPASS_DEC_WRAP
;
1445 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_INVERT
;
1450 static void radeonClearStencil( GLcontext
*ctx
, GLint s
)
1452 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1454 rmesa
->state
.stencil
.clear
=
1455 ((GLuint
) ctx
->Stencil
.Clear
|
1456 (0xff << RADEON_STENCIL_MASK_SHIFT
) |
1457 (ctx
->Stencil
.WriteMask
[0] << RADEON_STENCIL_WRITEMASK_SHIFT
));
1461 /* =============================================================
1462 * Window position and viewport transformation
1466 * To correctly position primitives:
1468 #define SUBPIXEL_X 0.125
1469 #define SUBPIXEL_Y 0.125
1471 void radeonUpdateWindow( GLcontext
*ctx
)
1473 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1474 __DRIdrawablePrivate
*dPriv
= rmesa
->dri
.drawable
;
1475 GLfloat xoffset
= (GLfloat
)dPriv
->x
;
1476 GLfloat yoffset
= (GLfloat
)dPriv
->y
+ dPriv
->h
;
1477 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
1479 GLfloat sx
= v
[MAT_SX
];
1480 GLfloat tx
= v
[MAT_TX
] + xoffset
+ SUBPIXEL_X
;
1481 GLfloat sy
= - v
[MAT_SY
];
1482 GLfloat ty
= (- v
[MAT_TY
]) + yoffset
+ SUBPIXEL_Y
;
1483 GLfloat sz
= v
[MAT_SZ
] * rmesa
->state
.depth
.scale
;
1484 GLfloat tz
= v
[MAT_TZ
] * rmesa
->state
.depth
.scale
;
1485 RADEON_FIREVERTICES( rmesa
);
1486 RADEON_STATECHANGE( rmesa
, vpt
);
1488 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XSCALE
] = *(GLuint
*)&sx
;
1489 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] = *(GLuint
*)&tx
;
1490 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YSCALE
] = *(GLuint
*)&sy
;
1491 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] = *(GLuint
*)&ty
;
1492 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZSCALE
] = *(GLuint
*)&sz
;
1493 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZOFFSET
] = *(GLuint
*)&tz
;
1498 static void radeonViewport( GLcontext
*ctx
, GLint x
, GLint y
,
1499 GLsizei width
, GLsizei height
)
1501 /* update size of Mesa/software ancillary buffers */
1502 _mesa_ResizeBuffersMESA();
1503 /* Don't pipeline viewport changes, conflict with window offset
1504 * setting below. Could apply deltas to rescue pipelined viewport
1505 * values, or keep the originals hanging around.
1507 RADEON_FIREVERTICES( RADEON_CONTEXT(ctx
) );
1508 radeonUpdateWindow( ctx
);
1511 static void radeonDepthRange( GLcontext
*ctx
, GLclampd nearval
,
1514 radeonUpdateWindow( ctx
);
1517 void radeonUpdateViewportOffset( GLcontext
*ctx
)
1519 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1520 __DRIdrawablePrivate
*dPriv
= rmesa
->dri
.drawable
;
1521 GLfloat xoffset
= (GLfloat
)dPriv
->x
;
1522 GLfloat yoffset
= (GLfloat
)dPriv
->y
+ dPriv
->h
;
1523 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
1525 GLfloat tx
= v
[MAT_TX
] + xoffset
;
1526 GLfloat ty
= (- v
[MAT_TY
]) + yoffset
;
1528 if ( rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] != *(GLuint
*)&tx
||
1529 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] != *(GLuint
*)&ty
)
1531 /* Note: this should also modify whatever data the context reset
1534 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] = *(GLuint
*)&tx
;
1535 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] = *(GLuint
*)&ty
;
1537 /* update polygon stipple x/y screen offset */
1540 GLuint m
= rmesa
->hw
.msc
.cmd
[MSC_RE_MISC
];
1542 m
&= ~(RADEON_STIPPLE_X_OFFSET_MASK
|
1543 RADEON_STIPPLE_Y_OFFSET_MASK
);
1545 /* add magic offsets, then invert */
1546 stx
= 31 - ((rmesa
->dri
.drawable
->x
- 1) & RADEON_STIPPLE_COORD_MASK
);
1547 sty
= 31 - ((rmesa
->dri
.drawable
->y
+ rmesa
->dri
.drawable
->h
- 1)
1548 & RADEON_STIPPLE_COORD_MASK
);
1550 m
|= ((stx
<< RADEON_STIPPLE_X_OFFSET_SHIFT
) |
1551 (sty
<< RADEON_STIPPLE_Y_OFFSET_SHIFT
));
1553 if ( rmesa
->hw
.msc
.cmd
[MSC_RE_MISC
] != m
) {
1554 RADEON_STATECHANGE( rmesa
, msc
);
1555 rmesa
->hw
.msc
.cmd
[MSC_RE_MISC
] = m
;
1560 radeonUpdateScissor( ctx
);
1565 /* =============================================================
1569 static void radeonClearColor( GLcontext
*ctx
, const GLfloat color
[4] )
1571 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1573 CLAMPED_FLOAT_TO_UBYTE(c
[0], color
[0]);
1574 CLAMPED_FLOAT_TO_UBYTE(c
[1], color
[1]);
1575 CLAMPED_FLOAT_TO_UBYTE(c
[2], color
[2]);
1576 CLAMPED_FLOAT_TO_UBYTE(c
[3], color
[3]);
1577 rmesa
->state
.color
.clear
= radeonPackColor( rmesa
->radeonScreen
->cpp
,
1578 c
[0], c
[1], c
[2], c
[3] );
1582 static void radeonRenderMode( GLcontext
*ctx
, GLenum mode
)
1584 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1585 FALLBACK( rmesa
, RADEON_FALLBACK_RENDER_MODE
, (mode
!= GL_RENDER
) );
1589 static GLuint radeon_rop_tab
[] = {
1592 RADEON_ROP_AND_REVERSE
,
1594 RADEON_ROP_AND_INVERTED
,
1601 RADEON_ROP_OR_REVERSE
,
1602 RADEON_ROP_COPY_INVERTED
,
1603 RADEON_ROP_OR_INVERTED
,
1608 static void radeonLogicOpCode( GLcontext
*ctx
, GLenum opcode
)
1610 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1611 GLuint rop
= (GLuint
)opcode
- GL_CLEAR
;
1615 RADEON_STATECHANGE( rmesa
, msk
);
1616 rmesa
->hw
.msk
.cmd
[MSK_RB3D_ROPCNTL
] = radeon_rop_tab
[rop
];
1620 void radeonSetCliprects( radeonContextPtr rmesa
, GLenum mode
)
1622 __DRIdrawablePrivate
*dPriv
= rmesa
->dri
.drawable
;
1626 rmesa
->numClipRects
= dPriv
->numClipRects
;
1627 rmesa
->pClipRects
= dPriv
->pClipRects
;
1630 /* Can't ignore 2d windows if we are page flipping.
1632 if ( dPriv
->numBackClipRects
== 0 || rmesa
->doPageFlip
) {
1633 rmesa
->numClipRects
= dPriv
->numClipRects
;
1634 rmesa
->pClipRects
= dPriv
->pClipRects
;
1637 rmesa
->numClipRects
= dPriv
->numBackClipRects
;
1638 rmesa
->pClipRects
= dPriv
->pBackClipRects
;
1642 fprintf(stderr
, "bad mode in radeonSetCliprects\n");
1646 if (rmesa
->state
.scissor
.enabled
)
1647 radeonRecalcScissorRects( rmesa
);
1651 static void radeonDrawBuffer( GLcontext
*ctx
, GLenum mode
)
1653 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1655 if (RADEON_DEBUG
& DEBUG_DRI
)
1656 fprintf(stderr
, "%s %s\n", __FUNCTION__
,
1657 _mesa_lookup_enum_by_nr( mode
));
1659 RADEON_FIREVERTICES(rmesa
); /* don't pipeline cliprect changes */
1662 * _DrawDestMask is easier to cope with than <mode>.
1664 switch ( ctx
->Color
._DrawDestMask
[0] ) {
1665 case DD_FRONT_LEFT_BIT
:
1666 FALLBACK( rmesa
, RADEON_FALLBACK_DRAW_BUFFER
, GL_FALSE
);
1667 radeonSetCliprects( rmesa
, GL_FRONT_LEFT
);
1669 case DD_BACK_LEFT_BIT
:
1670 FALLBACK( rmesa
, RADEON_FALLBACK_DRAW_BUFFER
, GL_FALSE
);
1671 radeonSetCliprects( rmesa
, GL_BACK_LEFT
);
1674 /* GL_NONE or GL_FRONT_AND_BACK or stereo left&right, etc */
1675 FALLBACK( rmesa
, RADEON_FALLBACK_DRAW_BUFFER
, GL_TRUE
);
1679 /* We want to update the s/w rast state too so that r200SetBuffer()
1682 _swrast_DrawBuffer(ctx
, mode
);
1684 RADEON_STATECHANGE( rmesa
, ctx
);
1685 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLOROFFSET
] = ((rmesa
->state
.color
.drawOffset
+
1686 rmesa
->radeonScreen
->fbLocation
)
1687 & RADEON_COLOROFFSET_MASK
);
1688 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] = rmesa
->state
.color
.drawPitch
;
1689 if (rmesa
->sarea
->tiling_enabled
) {
1690 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] |= RADEON_COLOR_TILE_ENABLE
;
1694 static void radeonReadBuffer( GLcontext
*ctx
, GLenum mode
)
1696 /* nothing, until we implement h/w glRead/CopyPixels or CopyTexImage */
1700 /* =============================================================
1701 * State enable/disable
1704 static void radeonEnable( GLcontext
*ctx
, GLenum cap
, GLboolean state
)
1706 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1709 if ( RADEON_DEBUG
& DEBUG_STATE
)
1710 fprintf( stderr
, "%s( %s = %s )\n", __FUNCTION__
,
1711 _mesa_lookup_enum_by_nr( cap
),
1712 state
? "GL_TRUE" : "GL_FALSE" );
1715 /* Fast track this one...
1723 RADEON_STATECHANGE( rmesa
, ctx
);
1725 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_ALPHA_TEST_ENABLE
;
1727 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_ALPHA_TEST_ENABLE
;
1732 RADEON_STATECHANGE( rmesa
, ctx
);
1734 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_ALPHA_BLEND_ENABLE
;
1736 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_ALPHA_BLEND_ENABLE
;
1738 if ( ctx
->Color
._LogicOpEnabled
) {
1739 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_ROP_ENABLE
;
1741 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_ROP_ENABLE
;
1744 /* Catch a possible fallback:
1747 ctx
->Driver
.BlendEquationSeparate( ctx
,
1748 ctx
->Color
.BlendEquationRGB
,
1749 ctx
->Color
.BlendEquationA
);
1750 ctx
->Driver
.BlendFuncSeparate( ctx
, ctx
->Color
.BlendSrcRGB
,
1751 ctx
->Color
.BlendDstRGB
,
1752 ctx
->Color
.BlendSrcA
,
1753 ctx
->Color
.BlendDstA
);
1756 FALLBACK( rmesa
, RADEON_FALLBACK_BLEND_FUNC
, GL_FALSE
);
1757 FALLBACK( rmesa
, RADEON_FALLBACK_BLEND_EQ
, GL_FALSE
);
1761 case GL_CLIP_PLANE0
:
1762 case GL_CLIP_PLANE1
:
1763 case GL_CLIP_PLANE2
:
1764 case GL_CLIP_PLANE3
:
1765 case GL_CLIP_PLANE4
:
1766 case GL_CLIP_PLANE5
:
1767 p
= cap
-GL_CLIP_PLANE0
;
1768 RADEON_STATECHANGE( rmesa
, tcl
);
1770 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= (RADEON_UCP_ENABLE_0
<<p
);
1771 radeonClipPlane( ctx
, cap
, NULL
);
1774 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~(RADEON_UCP_ENABLE_0
<<p
);
1778 case GL_COLOR_MATERIAL
:
1779 radeonColorMaterial( ctx
, 0, 0 );
1780 radeonUpdateMaterial( ctx
);
1784 radeonCullFace( ctx
, 0 );
1788 RADEON_STATECHANGE(rmesa
, ctx
);
1790 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_Z_ENABLE
;
1792 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_Z_ENABLE
;
1797 RADEON_STATECHANGE(rmesa
, ctx
);
1799 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_DITHER_ENABLE
;
1800 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~rmesa
->state
.color
.roundEnable
;
1802 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_DITHER_ENABLE
;
1803 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= rmesa
->state
.color
.roundEnable
;
1808 RADEON_STATECHANGE(rmesa
, ctx
);
1810 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_FOG_ENABLE
;
1811 radeonFogfv( ctx
, GL_FOG_MODE
, 0 );
1813 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_FOG_ENABLE
;
1814 RADEON_STATECHANGE(rmesa
, tcl
);
1815 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~RADEON_TCL_FOG_MASK
;
1817 radeonUpdateSpecular( ctx
); /* for PK_SPEC */
1818 if (rmesa
->TclFallback
)
1819 radeonChooseVertexState( ctx
);
1820 _mesa_allow_light_in_model( ctx
, !state
);
1831 RADEON_STATECHANGE(rmesa
, tcl
);
1832 p
= cap
- GL_LIGHT0
;
1834 flag
= (RADEON_LIGHT_1_ENABLE
|
1835 RADEON_LIGHT_1_ENABLE_AMBIENT
|
1836 RADEON_LIGHT_1_ENABLE_SPECULAR
);
1838 flag
= (RADEON_LIGHT_0_ENABLE
|
1839 RADEON_LIGHT_0_ENABLE_AMBIENT
|
1840 RADEON_LIGHT_0_ENABLE_SPECULAR
);
1843 rmesa
->hw
.tcl
.cmd
[p
/2 + TCL_PER_LIGHT_CTL_0
] |= flag
;
1845 rmesa
->hw
.tcl
.cmd
[p
/2 + TCL_PER_LIGHT_CTL_0
] &= ~flag
;
1849 update_light_colors( ctx
, p
);
1853 RADEON_STATECHANGE(rmesa
, tcl
);
1854 radeonUpdateSpecular(ctx
);
1855 check_twoside_fallback( ctx
);
1858 case GL_LINE_SMOOTH
:
1859 RADEON_STATECHANGE( rmesa
, ctx
);
1861 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_ANTI_ALIAS_LINE
;
1863 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_ANTI_ALIAS_LINE
;
1867 case GL_LINE_STIPPLE
:
1868 RADEON_STATECHANGE( rmesa
, ctx
);
1870 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_PATTERN_ENABLE
;
1872 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_PATTERN_ENABLE
;
1876 case GL_COLOR_LOGIC_OP
:
1877 RADEON_STATECHANGE( rmesa
, ctx
);
1878 if ( ctx
->Color
._LogicOpEnabled
) {
1879 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_ROP_ENABLE
;
1881 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_ROP_ENABLE
;
1886 RADEON_STATECHANGE( rmesa
, tcl
);
1888 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_NORMALIZE_NORMALS
;
1890 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_NORMALIZE_NORMALS
;
1894 case GL_POLYGON_OFFSET_POINT
:
1895 if (rmesa
->dri
.drmMinor
== 1) {
1896 radeonChooseRenderState( ctx
);
1899 RADEON_STATECHANGE( rmesa
, set
);
1901 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_ZBIAS_ENABLE_POINT
;
1903 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_ZBIAS_ENABLE_POINT
;
1908 case GL_POLYGON_OFFSET_LINE
:
1909 if (rmesa
->dri
.drmMinor
== 1) {
1910 radeonChooseRenderState( ctx
);
1913 RADEON_STATECHANGE( rmesa
, set
);
1915 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_ZBIAS_ENABLE_LINE
;
1917 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_ZBIAS_ENABLE_LINE
;
1922 case GL_POLYGON_OFFSET_FILL
:
1923 if (rmesa
->dri
.drmMinor
== 1) {
1924 radeonChooseRenderState( ctx
);
1927 RADEON_STATECHANGE( rmesa
, set
);
1929 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_ZBIAS_ENABLE_TRI
;
1931 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_ZBIAS_ENABLE_TRI
;
1936 case GL_POLYGON_SMOOTH
:
1937 RADEON_STATECHANGE( rmesa
, ctx
);
1939 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_ANTI_ALIAS_POLY
;
1941 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_ANTI_ALIAS_POLY
;
1945 case GL_POLYGON_STIPPLE
:
1946 RADEON_STATECHANGE(rmesa
, ctx
);
1948 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_STIPPLE_ENABLE
;
1950 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_STIPPLE_ENABLE
;
1954 case GL_RESCALE_NORMAL_EXT
: {
1955 GLboolean tmp
= ctx
->_NeedEyeCoords
? state
: !state
;
1956 RADEON_STATECHANGE( rmesa
, tcl
);
1958 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_RESCALE_NORMALS
;
1960 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_RESCALE_NORMALS
;
1965 case GL_SCISSOR_TEST
:
1966 RADEON_FIREVERTICES( rmesa
);
1967 rmesa
->state
.scissor
.enabled
= state
;
1968 radeonUpdateScissor( ctx
);
1971 case GL_STENCIL_TEST
:
1972 if ( rmesa
->state
.stencil
.hwBuffer
) {
1973 RADEON_STATECHANGE( rmesa
, ctx
);
1975 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_STENCIL_ENABLE
;
1977 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_STENCIL_ENABLE
;
1980 FALLBACK( rmesa
, RADEON_FALLBACK_STENCIL
, state
);
1984 case GL_TEXTURE_GEN_Q
:
1985 case GL_TEXTURE_GEN_R
:
1986 case GL_TEXTURE_GEN_S
:
1987 case GL_TEXTURE_GEN_T
:
1988 /* Picked up in radeonUpdateTextureState.
1990 rmesa
->recheck_texgen
[ctx
->Texture
.CurrentUnit
] = GL_TRUE
;
1993 case GL_COLOR_SUM_EXT
:
1994 radeonUpdateSpecular ( ctx
);
2003 static void radeonLightingSpaceChange( GLcontext
*ctx
)
2005 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
2007 RADEON_STATECHANGE( rmesa
, tcl
);
2009 if (RADEON_DEBUG
& DEBUG_STATE
)
2010 fprintf(stderr
, "%s %d BEFORE %x\n", __FUNCTION__
, ctx
->_NeedEyeCoords
,
2011 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
]);
2013 if (ctx
->_NeedEyeCoords
)
2014 tmp
= ctx
->Transform
.RescaleNormals
;
2016 tmp
= !ctx
->Transform
.RescaleNormals
;
2019 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_RESCALE_NORMALS
;
2021 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_RESCALE_NORMALS
;
2024 if (RADEON_DEBUG
& DEBUG_STATE
)
2025 fprintf(stderr
, "%s %d AFTER %x\n", __FUNCTION__
, ctx
->_NeedEyeCoords
,
2026 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
]);
2029 /* =============================================================
2030 * Deferred state management - matrices, textures, other?
2036 static void upload_matrix( radeonContextPtr rmesa
, GLfloat
*src
, int idx
)
2038 float *dest
= ((float *)RADEON_DB_STATE( mat
[idx
] ))+MAT_ELT_0
;
2042 for (i
= 0 ; i
< 4 ; i
++) {
2046 *dest
++ = src
[i
+12];
2049 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.mat
[idx
] );
2052 static void upload_matrix_t( radeonContextPtr rmesa
, GLfloat
*src
, int idx
)
2054 float *dest
= ((float *)RADEON_DB_STATE( mat
[idx
] ))+MAT_ELT_0
;
2055 memcpy(dest
, src
, 16*sizeof(float));
2056 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.mat
[idx
] );
2060 static void update_texturematrix( GLcontext
*ctx
)
2062 radeonContextPtr rmesa
= RADEON_CONTEXT( ctx
);
2063 GLuint tpc
= rmesa
->hw
.tcl
.cmd
[TCL_TEXTURE_PROC_CTL
];
2064 GLuint vs
= rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
];
2067 rmesa
->TexMatEnabled
= 0;
2069 for (unit
= 0 ; unit
< 2; unit
++) {
2070 if (!ctx
->Texture
.Unit
[unit
]._ReallyEnabled
) {
2072 else if (ctx
->TextureMatrixStack
[unit
].Top
->type
!= MATRIX_IDENTITY
) {
2073 GLuint inputshift
= RADEON_TEXGEN_0_INPUT_SHIFT
+ unit
*4;
2075 rmesa
->TexMatEnabled
|= (RADEON_TEXGEN_TEXMAT_0_ENABLE
|
2076 RADEON_TEXMAT_0_ENABLE
) << unit
;
2078 if (rmesa
->TexGenEnabled
& (RADEON_TEXMAT_0_ENABLE
<< unit
)) {
2079 /* Need to preconcatenate any active texgen
2080 * obj/eyeplane matrices:
2082 _math_matrix_mul_matrix( &rmesa
->tmpmat
,
2083 &rmesa
->TexGenMatrix
[unit
],
2084 ctx
->TextureMatrixStack
[unit
].Top
);
2085 upload_matrix( rmesa
, rmesa
->tmpmat
.m
, TEXMAT_0
+unit
);
2088 rmesa
->TexMatEnabled
|=
2089 (RADEON_TEXGEN_INPUT_TEXCOORD_0
+unit
) << inputshift
;
2090 upload_matrix( rmesa
, ctx
->TextureMatrixStack
[unit
].Top
->m
,
2094 else if (rmesa
->TexGenEnabled
& (RADEON_TEXMAT_0_ENABLE
<< unit
)) {
2095 upload_matrix( rmesa
, rmesa
->TexGenMatrix
[unit
].m
,
2101 tpc
= (rmesa
->TexMatEnabled
| rmesa
->TexGenEnabled
);
2103 vs
&= ~((0xf << RADEON_TCL_TEX_0_OUTPUT_SHIFT
) |
2104 (0xf << RADEON_TCL_TEX_1_OUTPUT_SHIFT
));
2106 if (tpc
& RADEON_TEXGEN_TEXMAT_0_ENABLE
)
2107 vs
|= RADEON_TCL_TEX_COMPUTED_TEX_0
<< RADEON_TCL_TEX_0_OUTPUT_SHIFT
;
2109 vs
|= RADEON_TCL_TEX_INPUT_TEX_0
<< RADEON_TCL_TEX_0_OUTPUT_SHIFT
;
2111 if (tpc
& RADEON_TEXGEN_TEXMAT_1_ENABLE
)
2112 vs
|= RADEON_TCL_TEX_COMPUTED_TEX_1
<< RADEON_TCL_TEX_1_OUTPUT_SHIFT
;
2114 vs
|= RADEON_TCL_TEX_INPUT_TEX_1
<< RADEON_TCL_TEX_1_OUTPUT_SHIFT
;
2116 if (tpc
!= rmesa
->hw
.tcl
.cmd
[TCL_TEXTURE_PROC_CTL
] ||
2117 vs
!= rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
]) {
2119 RADEON_STATECHANGE(rmesa
, tcl
);
2120 rmesa
->hw
.tcl
.cmd
[TCL_TEXTURE_PROC_CTL
] = tpc
;
2121 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] = vs
;
2127 void radeonValidateState( GLcontext
*ctx
)
2129 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
2130 GLuint new_state
= rmesa
->NewGLState
;
2132 if (new_state
& _NEW_TEXTURE
) {
2133 radeonUpdateTextureState( ctx
);
2134 new_state
|= rmesa
->NewGLState
; /* may add TEXTURE_MATRIX */
2137 /* Need an event driven matrix update?
2139 if (new_state
& (_NEW_MODELVIEW
|_NEW_PROJECTION
))
2140 upload_matrix( rmesa
, ctx
->_ModelProjectMatrix
.m
, MODEL_PROJ
);
2142 /* Need these for lighting (shouldn't upload otherwise)
2144 if (new_state
& (_NEW_MODELVIEW
)) {
2145 upload_matrix( rmesa
, ctx
->ModelviewMatrixStack
.Top
->m
, MODEL
);
2146 upload_matrix_t( rmesa
, ctx
->ModelviewMatrixStack
.Top
->inv
, MODEL_IT
);
2149 /* Does this need to be triggered on eg. modelview for
2150 * texgen-derived objplane/eyeplane matrices?
2152 if (new_state
& _NEW_TEXTURE_MATRIX
) {
2153 update_texturematrix( ctx
);
2156 if (new_state
& (_NEW_LIGHT
|_NEW_MODELVIEW
|_MESA_NEW_NEED_EYE_COORDS
)) {
2157 update_light( ctx
);
2160 /* emit all active clip planes if projection matrix changes.
2162 if (new_state
& (_NEW_PROJECTION
)) {
2163 if (ctx
->Transform
.ClipPlanesEnabled
)
2164 radeonUpdateClipPlanes( ctx
);
2168 rmesa
->NewGLState
= 0;
2172 static void radeonInvalidateState( GLcontext
*ctx
, GLuint new_state
)
2174 _swrast_InvalidateState( ctx
, new_state
);
2175 _swsetup_InvalidateState( ctx
, new_state
);
2176 _ac_InvalidateState( ctx
, new_state
);
2177 _tnl_InvalidateState( ctx
, new_state
);
2178 _ae_invalidate_state( ctx
, new_state
);
2179 RADEON_CONTEXT(ctx
)->NewGLState
|= new_state
;
2180 radeonVtxfmtInvalidate( ctx
);
2184 /* A hack. Need a faster way to find this out.
2186 static GLboolean
check_material( GLcontext
*ctx
)
2188 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
2191 for (i
= _TNL_ATTRIB_MAT_FRONT_AMBIENT
;
2192 i
< _TNL_ATTRIB_MAT_BACK_INDEXES
;
2194 if (tnl
->vb
.AttribPtr
[i
] &&
2195 tnl
->vb
.AttribPtr
[i
]->stride
)
2202 static void radeonWrapRunPipeline( GLcontext
*ctx
)
2204 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
2205 GLboolean has_material
;
2208 fprintf(stderr
, "%s, newstate: %x\n", __FUNCTION__
, rmesa
->NewGLState
);
2212 if (rmesa
->NewGLState
)
2213 radeonValidateState( ctx
);
2215 has_material
= (ctx
->Light
.Enabled
&& check_material( ctx
));
2218 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_MATERIAL
, GL_TRUE
);
2221 /* Run the pipeline.
2223 _tnl_run_pipeline( ctx
);
2226 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_MATERIAL
, GL_FALSE
);
2231 /* Initialize the driver's state functions.
2233 void radeonInitStateFuncs( GLcontext
*ctx
)
2235 ctx
->Driver
.UpdateState
= radeonInvalidateState
;
2236 ctx
->Driver
.LightingSpaceChange
= radeonLightingSpaceChange
;
2238 ctx
->Driver
.DrawBuffer
= radeonDrawBuffer
;
2239 ctx
->Driver
.ReadBuffer
= radeonReadBuffer
;
2241 ctx
->Driver
.AlphaFunc
= radeonAlphaFunc
;
2242 ctx
->Driver
.BlendEquationSeparate
= radeonBlendEquationSeparate
;
2243 ctx
->Driver
.BlendFuncSeparate
= radeonBlendFuncSeparate
;
2244 ctx
->Driver
.ClearColor
= radeonClearColor
;
2245 ctx
->Driver
.ClearDepth
= radeonClearDepth
;
2246 ctx
->Driver
.ClearIndex
= NULL
;
2247 ctx
->Driver
.ClearStencil
= radeonClearStencil
;
2248 ctx
->Driver
.ClipPlane
= radeonClipPlane
;
2249 ctx
->Driver
.ColorMask
= radeonColorMask
;
2250 ctx
->Driver
.CullFace
= radeonCullFace
;
2251 ctx
->Driver
.DepthFunc
= radeonDepthFunc
;
2252 ctx
->Driver
.DepthMask
= radeonDepthMask
;
2253 ctx
->Driver
.DepthRange
= radeonDepthRange
;
2254 ctx
->Driver
.Enable
= radeonEnable
;
2255 ctx
->Driver
.Fogfv
= radeonFogfv
;
2256 ctx
->Driver
.FrontFace
= radeonFrontFace
;
2257 ctx
->Driver
.Hint
= NULL
;
2258 ctx
->Driver
.IndexMask
= NULL
;
2259 ctx
->Driver
.LightModelfv
= radeonLightModelfv
;
2260 ctx
->Driver
.Lightfv
= radeonLightfv
;
2261 ctx
->Driver
.LineStipple
= radeonLineStipple
;
2262 ctx
->Driver
.LineWidth
= radeonLineWidth
;
2263 ctx
->Driver
.LogicOpcode
= radeonLogicOpCode
;
2264 ctx
->Driver
.PolygonMode
= radeonPolygonMode
;
2266 if (RADEON_CONTEXT(ctx
)->dri
.drmMinor
> 1)
2267 ctx
->Driver
.PolygonOffset
= radeonPolygonOffset
;
2269 ctx
->Driver
.PolygonStipple
= radeonPolygonStipple
;
2270 ctx
->Driver
.RenderMode
= radeonRenderMode
;
2271 ctx
->Driver
.Scissor
= radeonScissor
;
2272 ctx
->Driver
.ShadeModel
= radeonShadeModel
;
2273 ctx
->Driver
.StencilFunc
= radeonStencilFunc
;
2274 ctx
->Driver
.StencilMask
= radeonStencilMask
;
2275 ctx
->Driver
.StencilOp
= radeonStencilOp
;
2276 ctx
->Driver
.Viewport
= radeonViewport
;
2278 /* Pixel path fallbacks
2280 ctx
->Driver
.Accum
= _swrast_Accum
;
2281 ctx
->Driver
.Bitmap
= _swrast_Bitmap
;
2282 ctx
->Driver
.CopyPixels
= _swrast_CopyPixels
;
2283 ctx
->Driver
.DrawPixels
= _swrast_DrawPixels
;
2284 ctx
->Driver
.ReadPixels
= _swrast_ReadPixels
;
2286 /* Swrast hooks for imaging extensions:
2288 ctx
->Driver
.CopyColorTable
= _swrast_CopyColorTable
;
2289 ctx
->Driver
.CopyColorSubTable
= _swrast_CopyColorSubTable
;
2290 ctx
->Driver
.CopyConvolutionFilter1D
= _swrast_CopyConvolutionFilter1D
;
2291 ctx
->Driver
.CopyConvolutionFilter2D
= _swrast_CopyConvolutionFilter2D
;
2293 TNL_CONTEXT(ctx
)->Driver
.NotifyMaterialChange
= radeonUpdateMaterial
;
2294 TNL_CONTEXT(ctx
)->Driver
.RunPipeline
= radeonWrapRunPipeline
;