1 /**************************************************************************
3 Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
7 Permission is hereby granted, free of charge, to any person obtaining
8 a copy of this software and associated documentation files (the
9 "Software"), to deal in the Software without restriction, including
10 without limitation the rights to use, copy, modify, merge, publish,
11 distribute, sublicense, and/or sell copies of the Software, and to
12 permit persons to whom the Software is furnished to do so, subject to
13 the following conditions:
15 The above copyright notice and this permission notice (including the
16 next paragraph) shall be included in all copies or substantial
17 portions of the Software.
19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
23 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
24 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
25 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
31 * Gareth Hughes <gareth@valinux.com>
32 * Keith Whitwell <keith@tungstengraphics.com>
35 #include "main/glheader.h"
36 #include "main/imports.h"
37 #include "main/api_arrayelt.h"
38 #include "main/enums.h"
39 #include "main/light.h"
40 #include "main/state.h"
41 #include "main/context.h"
42 #include "main/framebuffer.h"
46 #include "tnl/t_pipeline.h"
47 #include "swrast_setup/swrast_setup.h"
49 #include "radeon_context.h"
50 #include "radeon_mipmap_tree.h"
51 #include "radeon_ioctl.h"
52 #include "radeon_state.h"
53 #include "radeon_tcl.h"
54 #include "radeon_tex.h"
55 #include "radeon_swtcl.h"
56 #include "drirenderbuffer.h"
58 static void radeonUpdateSpecular( GLcontext
*ctx
);
60 /* =============================================================
64 static void radeonAlphaFunc( GLcontext
*ctx
, GLenum func
, GLfloat ref
)
66 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
67 int pp_misc
= rmesa
->hw
.ctx
.cmd
[CTX_PP_MISC
];
70 CLAMPED_FLOAT_TO_UBYTE(refByte
, ref
);
72 RADEON_STATECHANGE( rmesa
, ctx
);
74 pp_misc
&= ~(RADEON_ALPHA_TEST_OP_MASK
| RADEON_REF_ALPHA_MASK
);
75 pp_misc
|= (refByte
& RADEON_REF_ALPHA_MASK
);
79 pp_misc
|= RADEON_ALPHA_TEST_FAIL
;
82 pp_misc
|= RADEON_ALPHA_TEST_LESS
;
85 pp_misc
|= RADEON_ALPHA_TEST_EQUAL
;
88 pp_misc
|= RADEON_ALPHA_TEST_LEQUAL
;
91 pp_misc
|= RADEON_ALPHA_TEST_GREATER
;
94 pp_misc
|= RADEON_ALPHA_TEST_NEQUAL
;
97 pp_misc
|= RADEON_ALPHA_TEST_GEQUAL
;
100 pp_misc
|= RADEON_ALPHA_TEST_PASS
;
104 rmesa
->hw
.ctx
.cmd
[CTX_PP_MISC
] = pp_misc
;
107 static void radeonBlendEquationSeparate( GLcontext
*ctx
,
108 GLenum modeRGB
, GLenum modeA
)
110 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
111 GLuint b
= rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] & ~RADEON_COMB_FCN_MASK
;
112 GLboolean fallback
= GL_FALSE
;
114 assert( modeRGB
== modeA
);
119 b
|= RADEON_COMB_FCN_ADD_CLAMP
;
122 case GL_FUNC_SUBTRACT
:
123 b
|= RADEON_COMB_FCN_SUB_CLAMP
;
127 if (ctx
->Color
.BlendEnabled
)
130 b
|= RADEON_COMB_FCN_ADD_CLAMP
;
134 FALLBACK( rmesa
, RADEON_FALLBACK_BLEND_EQ
, fallback
);
136 RADEON_STATECHANGE( rmesa
, ctx
);
137 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] = b
;
138 if ( (ctx
->Color
.ColorLogicOpEnabled
|| (ctx
->Color
.BlendEnabled
139 && ctx
->Color
.BlendEquationRGB
== GL_LOGIC_OP
)) ) {
140 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_ROP_ENABLE
;
142 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_ROP_ENABLE
;
147 static void radeonBlendFuncSeparate( GLcontext
*ctx
,
148 GLenum sfactorRGB
, GLenum dfactorRGB
,
149 GLenum sfactorA
, GLenum dfactorA
)
151 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
152 GLuint b
= rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] &
153 ~(RADEON_SRC_BLEND_MASK
| RADEON_DST_BLEND_MASK
);
154 GLboolean fallback
= GL_FALSE
;
156 switch ( ctx
->Color
.BlendSrcRGB
) {
158 b
|= RADEON_SRC_BLEND_GL_ZERO
;
161 b
|= RADEON_SRC_BLEND_GL_ONE
;
164 b
|= RADEON_SRC_BLEND_GL_DST_COLOR
;
166 case GL_ONE_MINUS_DST_COLOR
:
167 b
|= RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR
;
170 b
|= RADEON_SRC_BLEND_GL_SRC_COLOR
;
172 case GL_ONE_MINUS_SRC_COLOR
:
173 b
|= RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR
;
176 b
|= RADEON_SRC_BLEND_GL_SRC_ALPHA
;
178 case GL_ONE_MINUS_SRC_ALPHA
:
179 b
|= RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA
;
182 b
|= RADEON_SRC_BLEND_GL_DST_ALPHA
;
184 case GL_ONE_MINUS_DST_ALPHA
:
185 b
|= RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA
;
187 case GL_SRC_ALPHA_SATURATE
:
188 b
|= RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE
;
190 case GL_CONSTANT_COLOR
:
191 case GL_ONE_MINUS_CONSTANT_COLOR
:
192 case GL_CONSTANT_ALPHA
:
193 case GL_ONE_MINUS_CONSTANT_ALPHA
:
194 if (ctx
->Color
.BlendEnabled
)
197 b
|= RADEON_SRC_BLEND_GL_ONE
;
203 switch ( ctx
->Color
.BlendDstRGB
) {
205 b
|= RADEON_DST_BLEND_GL_ZERO
;
208 b
|= RADEON_DST_BLEND_GL_ONE
;
211 b
|= RADEON_DST_BLEND_GL_SRC_COLOR
;
213 case GL_ONE_MINUS_SRC_COLOR
:
214 b
|= RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR
;
217 b
|= RADEON_DST_BLEND_GL_SRC_ALPHA
;
219 case GL_ONE_MINUS_SRC_ALPHA
:
220 b
|= RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA
;
223 b
|= RADEON_DST_BLEND_GL_DST_COLOR
;
225 case GL_ONE_MINUS_DST_COLOR
:
226 b
|= RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR
;
229 b
|= RADEON_DST_BLEND_GL_DST_ALPHA
;
231 case GL_ONE_MINUS_DST_ALPHA
:
232 b
|= RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA
;
234 case GL_CONSTANT_COLOR
:
235 case GL_ONE_MINUS_CONSTANT_COLOR
:
236 case GL_CONSTANT_ALPHA
:
237 case GL_ONE_MINUS_CONSTANT_ALPHA
:
238 if (ctx
->Color
.BlendEnabled
)
241 b
|= RADEON_DST_BLEND_GL_ZERO
;
247 FALLBACK( rmesa
, RADEON_FALLBACK_BLEND_FUNC
, fallback
);
249 RADEON_STATECHANGE( rmesa
, ctx
);
250 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] = b
;
255 /* =============================================================
259 static void radeonDepthFunc( GLcontext
*ctx
, GLenum func
)
261 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
263 RADEON_STATECHANGE( rmesa
, ctx
);
264 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &= ~RADEON_Z_TEST_MASK
;
266 switch ( ctx
->Depth
.Func
) {
268 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_NEVER
;
271 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_LESS
;
274 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_EQUAL
;
277 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_LEQUAL
;
280 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_GREATER
;
283 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_NEQUAL
;
286 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_GEQUAL
;
289 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_ALWAYS
;
295 static void radeonDepthMask( GLcontext
*ctx
, GLboolean flag
)
297 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
298 RADEON_STATECHANGE( rmesa
, ctx
);
300 if ( ctx
->Depth
.Mask
) {
301 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_WRITE_ENABLE
;
303 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &= ~RADEON_Z_WRITE_ENABLE
;
307 static void radeonClearDepth( GLcontext
*ctx
, GLclampd d
)
309 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
310 GLuint format
= (rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &
311 RADEON_DEPTH_FORMAT_MASK
);
314 case RADEON_DEPTH_FORMAT_16BIT_INT_Z
:
315 rmesa
->radeon
.state
.depth
.clear
= d
* 0x0000ffff;
317 case RADEON_DEPTH_FORMAT_24BIT_INT_Z
:
318 rmesa
->radeon
.state
.depth
.clear
= d
* 0x00ffffff;
324 /* =============================================================
329 static void radeonFogfv( GLcontext
*ctx
, GLenum pname
, const GLfloat
*param
)
331 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
332 union { int i
; float f
; } c
, d
;
337 if (!ctx
->Fog
.Enabled
)
339 RADEON_STATECHANGE(rmesa
, tcl
);
340 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~RADEON_TCL_FOG_MASK
;
341 switch (ctx
->Fog
.Mode
) {
343 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_TCL_FOG_LINEAR
;
346 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_TCL_FOG_EXP
;
349 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_TCL_FOG_EXP2
;
358 if (!ctx
->Fog
.Enabled
)
360 c
.i
= rmesa
->hw
.fog
.cmd
[FOG_C
];
361 d
.i
= rmesa
->hw
.fog
.cmd
[FOG_D
];
362 switch (ctx
->Fog
.Mode
) {
365 /* While this is the opposite sign from the DDK, it makes the fog test
366 * pass, and matches r200.
368 d
.f
= -ctx
->Fog
.Density
;
372 d
.f
= -(ctx
->Fog
.Density
* ctx
->Fog
.Density
);
375 if (ctx
->Fog
.Start
== ctx
->Fog
.End
) {
379 c
.f
= ctx
->Fog
.End
/(ctx
->Fog
.End
-ctx
->Fog
.Start
);
380 /* While this is the opposite sign from the DDK, it makes the fog
381 * test pass, and matches r200.
383 d
.f
= -1.0/(ctx
->Fog
.End
-ctx
->Fog
.Start
);
389 if (c
.i
!= rmesa
->hw
.fog
.cmd
[FOG_C
] || d
.i
!= rmesa
->hw
.fog
.cmd
[FOG_D
]) {
390 RADEON_STATECHANGE( rmesa
, fog
);
391 rmesa
->hw
.fog
.cmd
[FOG_C
] = c
.i
;
392 rmesa
->hw
.fog
.cmd
[FOG_D
] = d
.i
;
396 RADEON_STATECHANGE( rmesa
, ctx
);
397 UNCLAMPED_FLOAT_TO_RGB_CHAN( col
, ctx
->Fog
.Color
);
398 rmesa
->hw
.ctx
.cmd
[CTX_PP_FOG_COLOR
] &= ~RADEON_FOG_COLOR_MASK
;
399 rmesa
->hw
.ctx
.cmd
[CTX_PP_FOG_COLOR
] |=
400 radeonPackColor( 4, col
[0], col
[1], col
[2], 0 );
402 case GL_FOG_COORD_SRC
:
403 radeonUpdateSpecular( ctx
);
410 /* =============================================================
414 static void radeonCullFace( GLcontext
*ctx
, GLenum unused
)
416 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
417 GLuint s
= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
];
418 GLuint t
= rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
];
420 s
|= RADEON_FFACE_SOLID
| RADEON_BFACE_SOLID
;
421 t
&= ~(RADEON_CULL_FRONT
| RADEON_CULL_BACK
);
423 if ( ctx
->Polygon
.CullFlag
) {
424 switch ( ctx
->Polygon
.CullFaceMode
) {
426 s
&= ~RADEON_FFACE_SOLID
;
427 t
|= RADEON_CULL_FRONT
;
430 s
&= ~RADEON_BFACE_SOLID
;
431 t
|= RADEON_CULL_BACK
;
433 case GL_FRONT_AND_BACK
:
434 s
&= ~(RADEON_FFACE_SOLID
| RADEON_BFACE_SOLID
);
435 t
|= (RADEON_CULL_FRONT
| RADEON_CULL_BACK
);
440 if ( rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] != s
) {
441 RADEON_STATECHANGE(rmesa
, set
);
442 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = s
;
445 if ( rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] != t
) {
446 RADEON_STATECHANGE(rmesa
, tcl
);
447 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] = t
;
451 static void radeonFrontFace( GLcontext
*ctx
, GLenum mode
)
453 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
455 RADEON_STATECHANGE( rmesa
, set
);
456 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_FFACE_CULL_DIR_MASK
;
458 RADEON_STATECHANGE( rmesa
, tcl
);
459 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~RADEON_CULL_FRONT_IS_CCW
;
463 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_FFACE_CULL_CW
;
466 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_FFACE_CULL_CCW
;
467 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_CULL_FRONT_IS_CCW
;
473 /* =============================================================
476 static void radeonLineWidth( GLcontext
*ctx
, GLfloat widthf
)
478 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
480 RADEON_STATECHANGE( rmesa
, lin
);
481 RADEON_STATECHANGE( rmesa
, set
);
483 /* Line width is stored in U6.4 format.
485 rmesa
->hw
.lin
.cmd
[LIN_SE_LINE_WIDTH
] = (GLuint
)(widthf
* 16.0);
486 if ( widthf
> 1.0 ) {
487 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_WIDELINE_ENABLE
;
489 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_WIDELINE_ENABLE
;
493 static void radeonLineStipple( GLcontext
*ctx
, GLint factor
, GLushort pattern
)
495 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
497 RADEON_STATECHANGE( rmesa
, lin
);
498 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_PATTERN
] =
499 ((((GLuint
)factor
& 0xff) << 16) | ((GLuint
)pattern
));
503 /* =============================================================
506 static void radeonColorMask( GLcontext
*ctx
,
507 GLboolean r
, GLboolean g
,
508 GLboolean b
, GLboolean a
)
510 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
511 GLuint mask
= radeonPackColor( rmesa
->radeon
.radeonScreen
->cpp
,
512 ctx
->Color
.ColorMask
[RCOMP
],
513 ctx
->Color
.ColorMask
[GCOMP
],
514 ctx
->Color
.ColorMask
[BCOMP
],
515 ctx
->Color
.ColorMask
[ACOMP
] );
517 if ( rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
] != mask
) {
518 RADEON_STATECHANGE( rmesa
, msk
);
519 rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
] = mask
;
524 /* =============================================================
528 static void radeonPolygonOffset( GLcontext
*ctx
,
529 GLfloat factor
, GLfloat units
)
531 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
532 const GLfloat depthScale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
533 float_ui32_type constant
= { units
* depthScale
};
534 float_ui32_type factoru
= { factor
};
536 RADEON_STATECHANGE( rmesa
, zbs
);
537 rmesa
->hw
.zbs
.cmd
[ZBS_SE_ZBIAS_FACTOR
] = factoru
.ui32
;
538 rmesa
->hw
.zbs
.cmd
[ZBS_SE_ZBIAS_CONSTANT
] = constant
.ui32
;
541 static void radeonPolygonStipple( GLcontext
*ctx
, const GLubyte
*mask
)
543 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
545 drm_radeon_stipple_t stipple
;
547 /* Must flip pattern upside down.
549 for ( i
= 0 ; i
< 32 ; i
++ ) {
550 rmesa
->state
.stipple
.mask
[31 - i
] = ((GLuint
*) mask
)[i
];
553 /* TODO: push this into cmd mechanism
555 radeon_firevertices(&rmesa
->radeon
);
556 LOCK_HARDWARE( &rmesa
->radeon
);
558 /* FIXME: Use window x,y offsets into stipple RAM.
560 stipple
.mask
= rmesa
->state
.stipple
.mask
;
561 drmCommandWrite( rmesa
->radeon
.dri
.fd
, DRM_RADEON_STIPPLE
,
562 &stipple
, sizeof(drm_radeon_stipple_t
) );
563 UNLOCK_HARDWARE( &rmesa
->radeon
);
566 static void radeonPolygonMode( GLcontext
*ctx
, GLenum face
, GLenum mode
)
568 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
569 GLboolean flag
= (ctx
->_TriangleCaps
& DD_TRI_UNFILLED
) != 0;
571 /* Can't generally do unfilled via tcl, but some good special
574 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_UNFILLED
, flag
);
575 if (rmesa
->radeon
.TclFallback
) {
576 radeonChooseRenderState( ctx
);
577 radeonChooseVertexState( ctx
);
582 /* =============================================================
583 * Rendering attributes
585 * We really don't want to recalculate all this every time we bind a
586 * texture. These things shouldn't change all that often, so it makes
587 * sense to break them out of the core texture state update routines.
590 /* Examine lighting and texture state to determine if separate specular
593 static void radeonUpdateSpecular( GLcontext
*ctx
)
595 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
596 uint32_t p
= rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
];
599 RADEON_STATECHANGE( rmesa
, tcl
);
601 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] &= ~RADEON_TCL_COMPUTE_SPECULAR
;
602 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] &= ~RADEON_TCL_COMPUTE_DIFFUSE
;
603 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] &= ~RADEON_TCL_VTX_PK_SPEC
;
604 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] &= ~RADEON_TCL_VTX_PK_DIFFUSE
;
605 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_LIGHTING_ENABLE
;
607 p
&= ~RADEON_SPECULAR_ENABLE
;
609 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_DIFFUSE_SPECULAR_COMBINE
;
612 if (ctx
->Light
.Enabled
&&
613 ctx
->Light
.Model
.ColorControl
== GL_SEPARATE_SPECULAR_COLOR
) {
614 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] |= RADEON_TCL_COMPUTE_SPECULAR
;
615 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] |= RADEON_TCL_COMPUTE_DIFFUSE
;
616 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_SPEC
;
617 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_DIFFUSE
;
618 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_LIGHTING_ENABLE
;
619 p
|= RADEON_SPECULAR_ENABLE
;
620 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &=
621 ~RADEON_DIFFUSE_SPECULAR_COMBINE
;
623 else if (ctx
->Light
.Enabled
) {
624 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] |= RADEON_TCL_COMPUTE_DIFFUSE
;
625 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_DIFFUSE
;
626 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_LIGHTING_ENABLE
;
627 } else if (ctx
->Fog
.ColorSumEnabled
) {
628 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_SPEC
;
629 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_DIFFUSE
;
630 p
|= RADEON_SPECULAR_ENABLE
;
632 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_DIFFUSE
;
635 if (ctx
->Fog
.Enabled
) {
636 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_SPEC
;
637 if (ctx
->Fog
.FogCoordinateSource
== GL_FRAGMENT_DEPTH
) {
638 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] |= RADEON_TCL_COMPUTE_SPECULAR
;
639 /* Bizzare: have to leave lighting enabled to get fog. */
640 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_LIGHTING_ENABLE
;
643 /* cannot do tcl fog factor calculation with fog coord source
644 * (send precomputed factors). Cannot use precomputed fog
645 * factors together with tcl spec light (need tcl fallback) */
646 flag
= (rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] &
647 RADEON_TCL_COMPUTE_SPECULAR
) != 0;
651 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_FOGCOORDSPEC
, flag
);
653 if (NEED_SECONDARY_COLOR(ctx
)) {
654 assert( (p
& RADEON_SPECULAR_ENABLE
) != 0 );
656 assert( (p
& RADEON_SPECULAR_ENABLE
) == 0 );
659 if ( rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] != p
) {
660 RADEON_STATECHANGE( rmesa
, ctx
);
661 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] = p
;
664 /* Update vertex/render formats
666 if (rmesa
->radeon
.TclFallback
) {
667 radeonChooseRenderState( ctx
);
668 radeonChooseVertexState( ctx
);
673 /* =============================================================
678 /* Update on colormaterial, material emmissive/ambient,
679 * lightmodel.globalambient
681 static void update_global_ambient( GLcontext
*ctx
)
683 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
684 float *fcmd
= (float *)RADEON_DB_STATE( glt
);
686 /* Need to do more if both emmissive & ambient are PREMULT:
687 * Hope this is not needed for MULT
689 if ((rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &
690 ((3 << RADEON_EMISSIVE_SOURCE_SHIFT
) |
691 (3 << RADEON_AMBIENT_SOURCE_SHIFT
))) == 0)
693 COPY_3V( &fcmd
[GLT_RED
],
694 ctx
->Light
.Material
.Attrib
[MAT_ATTRIB_FRONT_EMISSION
]);
695 ACC_SCALE_3V( &fcmd
[GLT_RED
],
696 ctx
->Light
.Model
.Ambient
,
697 ctx
->Light
.Material
.Attrib
[MAT_ATTRIB_FRONT_AMBIENT
]);
701 COPY_3V( &fcmd
[GLT_RED
], ctx
->Light
.Model
.Ambient
);
704 RADEON_DB_STATECHANGE(rmesa
, &rmesa
->hw
.glt
);
707 /* Update on change to
711 static void update_light_colors( GLcontext
*ctx
, GLuint p
)
713 struct gl_light
*l
= &ctx
->Light
.Light
[p
];
715 /* fprintf(stderr, "%s\n", __FUNCTION__); */
718 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
719 float *fcmd
= (float *)RADEON_DB_STATE( lit
[p
] );
721 COPY_4V( &fcmd
[LIT_AMBIENT_RED
], l
->Ambient
);
722 COPY_4V( &fcmd
[LIT_DIFFUSE_RED
], l
->Diffuse
);
723 COPY_4V( &fcmd
[LIT_SPECULAR_RED
], l
->Specular
);
725 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.lit
[p
] );
729 /* Also fallback for asym colormaterial mode in twoside lighting...
731 static void check_twoside_fallback( GLcontext
*ctx
)
733 GLboolean fallback
= GL_FALSE
;
736 if (ctx
->Light
.Enabled
&& ctx
->Light
.Model
.TwoSide
) {
737 if (ctx
->Light
.ColorMaterialEnabled
&&
738 (ctx
->Light
.ColorMaterialBitmask
& BACK_MATERIAL_BITS
) !=
739 ((ctx
->Light
.ColorMaterialBitmask
& FRONT_MATERIAL_BITS
)<<1))
742 for (i
= MAT_ATTRIB_FRONT_AMBIENT
; i
< MAT_ATTRIB_FRONT_INDEXES
; i
+=2)
743 if (memcmp( ctx
->Light
.Material
.Attrib
[i
],
744 ctx
->Light
.Material
.Attrib
[i
+1],
745 sizeof(GLfloat
)*4) != 0) {
752 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_LIGHT_TWOSIDE
, fallback
);
756 static void radeonColorMaterial( GLcontext
*ctx
, GLenum face
, GLenum mode
)
758 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
759 GLuint light_model_ctl1
= rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
];
761 light_model_ctl1
&= ~((3 << RADEON_EMISSIVE_SOURCE_SHIFT
) |
762 (3 << RADEON_AMBIENT_SOURCE_SHIFT
) |
763 (3 << RADEON_DIFFUSE_SOURCE_SHIFT
) |
764 (3 << RADEON_SPECULAR_SOURCE_SHIFT
));
766 if (ctx
->Light
.ColorMaterialEnabled
) {
767 GLuint mask
= ctx
->Light
.ColorMaterialBitmask
;
769 if (mask
& MAT_BIT_FRONT_EMISSION
) {
770 light_model_ctl1
|= (RADEON_LM_SOURCE_VERTEX_DIFFUSE
<<
771 RADEON_EMISSIVE_SOURCE_SHIFT
);
774 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<<
775 RADEON_EMISSIVE_SOURCE_SHIFT
);
778 if (mask
& MAT_BIT_FRONT_AMBIENT
) {
779 light_model_ctl1
|= (RADEON_LM_SOURCE_VERTEX_DIFFUSE
<<
780 RADEON_AMBIENT_SOURCE_SHIFT
);
783 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<<
784 RADEON_AMBIENT_SOURCE_SHIFT
);
787 if (mask
& MAT_BIT_FRONT_DIFFUSE
) {
788 light_model_ctl1
|= (RADEON_LM_SOURCE_VERTEX_DIFFUSE
<<
789 RADEON_DIFFUSE_SOURCE_SHIFT
);
792 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<<
793 RADEON_DIFFUSE_SOURCE_SHIFT
);
796 if (mask
& MAT_BIT_FRONT_SPECULAR
) {
797 light_model_ctl1
|= (RADEON_LM_SOURCE_VERTEX_DIFFUSE
<<
798 RADEON_SPECULAR_SOURCE_SHIFT
);
801 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<<
802 RADEON_SPECULAR_SOURCE_SHIFT
);
808 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_EMISSIVE_SOURCE_SHIFT
) |
809 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_AMBIENT_SOURCE_SHIFT
) |
810 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_DIFFUSE_SOURCE_SHIFT
) |
811 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_SPECULAR_SOURCE_SHIFT
);
814 if (light_model_ctl1
!= rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
]) {
815 RADEON_STATECHANGE( rmesa
, tcl
);
816 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] = light_model_ctl1
;
820 void radeonUpdateMaterial( GLcontext
*ctx
)
822 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
823 GLfloat (*mat
)[4] = ctx
->Light
.Material
.Attrib
;
824 GLfloat
*fcmd
= (GLfloat
*)RADEON_DB_STATE( mtl
);
827 if (ctx
->Light
.ColorMaterialEnabled
)
828 mask
&= ~ctx
->Light
.ColorMaterialBitmask
;
830 if (RADEON_DEBUG
& DEBUG_STATE
)
831 fprintf(stderr
, "%s\n", __FUNCTION__
);
834 if (mask
& MAT_BIT_FRONT_EMISSION
) {
835 fcmd
[MTL_EMMISSIVE_RED
] = mat
[MAT_ATTRIB_FRONT_EMISSION
][0];
836 fcmd
[MTL_EMMISSIVE_GREEN
] = mat
[MAT_ATTRIB_FRONT_EMISSION
][1];
837 fcmd
[MTL_EMMISSIVE_BLUE
] = mat
[MAT_ATTRIB_FRONT_EMISSION
][2];
838 fcmd
[MTL_EMMISSIVE_ALPHA
] = mat
[MAT_ATTRIB_FRONT_EMISSION
][3];
840 if (mask
& MAT_BIT_FRONT_AMBIENT
) {
841 fcmd
[MTL_AMBIENT_RED
] = mat
[MAT_ATTRIB_FRONT_AMBIENT
][0];
842 fcmd
[MTL_AMBIENT_GREEN
] = mat
[MAT_ATTRIB_FRONT_AMBIENT
][1];
843 fcmd
[MTL_AMBIENT_BLUE
] = mat
[MAT_ATTRIB_FRONT_AMBIENT
][2];
844 fcmd
[MTL_AMBIENT_ALPHA
] = mat
[MAT_ATTRIB_FRONT_AMBIENT
][3];
846 if (mask
& MAT_BIT_FRONT_DIFFUSE
) {
847 fcmd
[MTL_DIFFUSE_RED
] = mat
[MAT_ATTRIB_FRONT_DIFFUSE
][0];
848 fcmd
[MTL_DIFFUSE_GREEN
] = mat
[MAT_ATTRIB_FRONT_DIFFUSE
][1];
849 fcmd
[MTL_DIFFUSE_BLUE
] = mat
[MAT_ATTRIB_FRONT_DIFFUSE
][2];
850 fcmd
[MTL_DIFFUSE_ALPHA
] = mat
[MAT_ATTRIB_FRONT_DIFFUSE
][3];
852 if (mask
& MAT_BIT_FRONT_SPECULAR
) {
853 fcmd
[MTL_SPECULAR_RED
] = mat
[MAT_ATTRIB_FRONT_SPECULAR
][0];
854 fcmd
[MTL_SPECULAR_GREEN
] = mat
[MAT_ATTRIB_FRONT_SPECULAR
][1];
855 fcmd
[MTL_SPECULAR_BLUE
] = mat
[MAT_ATTRIB_FRONT_SPECULAR
][2];
856 fcmd
[MTL_SPECULAR_ALPHA
] = mat
[MAT_ATTRIB_FRONT_SPECULAR
][3];
858 if (mask
& MAT_BIT_FRONT_SHININESS
) {
859 fcmd
[MTL_SHININESS
] = mat
[MAT_ATTRIB_FRONT_SHININESS
][0];
862 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.mtl
);
864 check_twoside_fallback( ctx
);
865 /* update_global_ambient( ctx );*/
870 * _MESA_NEW_NEED_EYE_COORDS
872 * Uses derived state from mesa:
881 * which are calculated in light.c and are correct for the current
882 * lighting space (model or eye), hence dependencies on _NEW_MODELVIEW
883 * and _MESA_NEW_NEED_EYE_COORDS.
885 static void update_light( GLcontext
*ctx
)
887 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
889 /* Have to check these, or have an automatic shortcircuit mechanism
890 * to remove noop statechanges. (Or just do a better job on the
894 GLuint tmp
= rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
];
896 if (ctx
->_NeedEyeCoords
)
897 tmp
&= ~RADEON_LIGHT_IN_MODELSPACE
;
899 tmp
|= RADEON_LIGHT_IN_MODELSPACE
;
902 /* Leave this test disabled: (unexplained q3 lockup) (even with
905 if (tmp
!= rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
])
907 RADEON_STATECHANGE( rmesa
, tcl
);
908 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] = tmp
;
913 GLfloat
*fcmd
= (GLfloat
*)RADEON_DB_STATE( eye
);
914 fcmd
[EYE_X
] = ctx
->_EyeZDir
[0];
915 fcmd
[EYE_Y
] = ctx
->_EyeZDir
[1];
916 fcmd
[EYE_Z
] = - ctx
->_EyeZDir
[2];
917 fcmd
[EYE_RESCALE_FACTOR
] = ctx
->_ModelViewInvScale
;
918 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.eye
);
923 if (ctx
->Light
.Enabled
) {
925 for (p
= 0 ; p
< MAX_LIGHTS
; p
++) {
926 if (ctx
->Light
.Light
[p
].Enabled
) {
927 struct gl_light
*l
= &ctx
->Light
.Light
[p
];
928 GLfloat
*fcmd
= (GLfloat
*)RADEON_DB_STATE( lit
[p
] );
930 if (l
->EyePosition
[3] == 0.0) {
931 COPY_3FV( &fcmd
[LIT_POSITION_X
], l
->_VP_inf_norm
);
932 COPY_3FV( &fcmd
[LIT_DIRECTION_X
], l
->_h_inf_norm
);
933 fcmd
[LIT_POSITION_W
] = 0;
934 fcmd
[LIT_DIRECTION_W
] = 0;
936 COPY_4V( &fcmd
[LIT_POSITION_X
], l
->_Position
);
937 fcmd
[LIT_DIRECTION_X
] = -l
->_NormSpotDirection
[0];
938 fcmd
[LIT_DIRECTION_Y
] = -l
->_NormSpotDirection
[1];
939 fcmd
[LIT_DIRECTION_Z
] = -l
->_NormSpotDirection
[2];
940 fcmd
[LIT_DIRECTION_W
] = 0;
943 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.lit
[p
] );
949 static void radeonLightfv( GLcontext
*ctx
, GLenum light
,
950 GLenum pname
, const GLfloat
*params
)
952 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
953 GLint p
= light
- GL_LIGHT0
;
954 struct gl_light
*l
= &ctx
->Light
.Light
[p
];
955 GLfloat
*fcmd
= (GLfloat
*)rmesa
->hw
.lit
[p
].cmd
;
962 update_light_colors( ctx
, p
);
965 case GL_SPOT_DIRECTION
:
966 /* picked up in update_light */
970 /* positions picked up in update_light, but can do flag here */
972 GLuint idx
= TCL_PER_LIGHT_CTL_0
+ p
/2;
974 /* FIXME: Set RANGE_ATTEN only when needed */
976 flag
= RADEON_LIGHT_1_IS_LOCAL
;
978 flag
= RADEON_LIGHT_0_IS_LOCAL
;
980 RADEON_STATECHANGE(rmesa
, tcl
);
981 if (l
->EyePosition
[3] != 0.0F
)
982 rmesa
->hw
.tcl
.cmd
[idx
] |= flag
;
984 rmesa
->hw
.tcl
.cmd
[idx
] &= ~flag
;
988 case GL_SPOT_EXPONENT
:
989 RADEON_STATECHANGE(rmesa
, lit
[p
]);
990 fcmd
[LIT_SPOT_EXPONENT
] = params
[0];
993 case GL_SPOT_CUTOFF
: {
994 GLuint flag
= (p
&1) ? RADEON_LIGHT_1_IS_SPOT
: RADEON_LIGHT_0_IS_SPOT
;
995 GLuint idx
= TCL_PER_LIGHT_CTL_0
+ p
/2;
997 RADEON_STATECHANGE(rmesa
, lit
[p
]);
998 fcmd
[LIT_SPOT_CUTOFF
] = l
->_CosCutoff
;
1000 RADEON_STATECHANGE(rmesa
, tcl
);
1001 if (l
->SpotCutoff
!= 180.0F
)
1002 rmesa
->hw
.tcl
.cmd
[idx
] |= flag
;
1004 rmesa
->hw
.tcl
.cmd
[idx
] &= ~flag
;
1009 case GL_CONSTANT_ATTENUATION
:
1010 RADEON_STATECHANGE(rmesa
, lit
[p
]);
1011 fcmd
[LIT_ATTEN_CONST
] = params
[0];
1012 if ( params
[0] == 0.0 )
1013 fcmd
[LIT_ATTEN_CONST_INV
] = FLT_MAX
;
1015 fcmd
[LIT_ATTEN_CONST_INV
] = 1.0 / params
[0];
1017 case GL_LINEAR_ATTENUATION
:
1018 RADEON_STATECHANGE(rmesa
, lit
[p
]);
1019 fcmd
[LIT_ATTEN_LINEAR
] = params
[0];
1021 case GL_QUADRATIC_ATTENUATION
:
1022 RADEON_STATECHANGE(rmesa
, lit
[p
]);
1023 fcmd
[LIT_ATTEN_QUADRATIC
] = params
[0];
1029 /* Set RANGE_ATTEN only when needed */
1032 case GL_CONSTANT_ATTENUATION
:
1033 case GL_LINEAR_ATTENUATION
:
1034 case GL_QUADRATIC_ATTENUATION
:
1036 GLuint
*icmd
= (GLuint
*)RADEON_DB_STATE( tcl
);
1037 GLuint idx
= TCL_PER_LIGHT_CTL_0
+ p
/2;
1038 GLuint atten_flag
= ( p
&1 ) ? RADEON_LIGHT_1_ENABLE_RANGE_ATTEN
1039 : RADEON_LIGHT_0_ENABLE_RANGE_ATTEN
;
1040 GLuint atten_const_flag
= ( p
&1 ) ? RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN
1041 : RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN
;
1043 if ( l
->EyePosition
[3] == 0.0F
||
1044 ( ( fcmd
[LIT_ATTEN_CONST
] == 0.0 || fcmd
[LIT_ATTEN_CONST
] == 1.0 ) &&
1045 fcmd
[LIT_ATTEN_QUADRATIC
] == 0.0 && fcmd
[LIT_ATTEN_LINEAR
] == 0.0 ) ) {
1046 /* Disable attenuation */
1047 icmd
[idx
] &= ~atten_flag
;
1049 if ( fcmd
[LIT_ATTEN_QUADRATIC
] == 0.0 && fcmd
[LIT_ATTEN_LINEAR
] == 0.0 ) {
1050 /* Enable only constant portion of attenuation calculation */
1051 icmd
[idx
] |= ( atten_flag
| atten_const_flag
);
1053 /* Enable full attenuation calculation */
1054 icmd
[idx
] &= ~atten_const_flag
;
1055 icmd
[idx
] |= atten_flag
;
1059 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.tcl
);
1070 static void radeonLightModelfv( GLcontext
*ctx
, GLenum pname
,
1071 const GLfloat
*param
)
1073 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1076 case GL_LIGHT_MODEL_AMBIENT
:
1077 update_global_ambient( ctx
);
1080 case GL_LIGHT_MODEL_LOCAL_VIEWER
:
1081 RADEON_STATECHANGE( rmesa
, tcl
);
1082 if (ctx
->Light
.Model
.LocalViewer
)
1083 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_LOCAL_VIEWER
;
1085 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_LOCAL_VIEWER
;
1088 case GL_LIGHT_MODEL_TWO_SIDE
:
1089 RADEON_STATECHANGE( rmesa
, tcl
);
1090 if (ctx
->Light
.Model
.TwoSide
)
1091 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_LIGHT_TWOSIDE
;
1093 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~RADEON_LIGHT_TWOSIDE
;
1095 check_twoside_fallback( ctx
);
1097 if (rmesa
->radeon
.TclFallback
) {
1098 radeonChooseRenderState( ctx
);
1099 radeonChooseVertexState( ctx
);
1103 case GL_LIGHT_MODEL_COLOR_CONTROL
:
1104 radeonUpdateSpecular(ctx
);
1112 static void radeonShadeModel( GLcontext
*ctx
, GLenum mode
)
1114 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1115 GLuint s
= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
];
1117 s
&= ~(RADEON_DIFFUSE_SHADE_MASK
|
1118 RADEON_ALPHA_SHADE_MASK
|
1119 RADEON_SPECULAR_SHADE_MASK
|
1120 RADEON_FOG_SHADE_MASK
);
1124 s
|= (RADEON_DIFFUSE_SHADE_FLAT
|
1125 RADEON_ALPHA_SHADE_FLAT
|
1126 RADEON_SPECULAR_SHADE_FLAT
|
1127 RADEON_FOG_SHADE_FLAT
);
1130 s
|= (RADEON_DIFFUSE_SHADE_GOURAUD
|
1131 RADEON_ALPHA_SHADE_GOURAUD
|
1132 RADEON_SPECULAR_SHADE_GOURAUD
|
1133 RADEON_FOG_SHADE_GOURAUD
);
1139 if ( rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] != s
) {
1140 RADEON_STATECHANGE( rmesa
, set
);
1141 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = s
;
1146 /* =============================================================
1150 static void radeonClipPlane( GLcontext
*ctx
, GLenum plane
, const GLfloat
*eq
)
1152 GLint p
= (GLint
) plane
- (GLint
) GL_CLIP_PLANE0
;
1153 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1154 GLint
*ip
= (GLint
*)ctx
->Transform
._ClipUserPlane
[p
];
1156 RADEON_STATECHANGE( rmesa
, ucp
[p
] );
1157 rmesa
->hw
.ucp
[p
].cmd
[UCP_X
] = ip
[0];
1158 rmesa
->hw
.ucp
[p
].cmd
[UCP_Y
] = ip
[1];
1159 rmesa
->hw
.ucp
[p
].cmd
[UCP_Z
] = ip
[2];
1160 rmesa
->hw
.ucp
[p
].cmd
[UCP_W
] = ip
[3];
1163 static void radeonUpdateClipPlanes( GLcontext
*ctx
)
1165 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1168 for (p
= 0; p
< ctx
->Const
.MaxClipPlanes
; p
++) {
1169 if (ctx
->Transform
.ClipPlanesEnabled
& (1 << p
)) {
1170 GLint
*ip
= (GLint
*)ctx
->Transform
._ClipUserPlane
[p
];
1172 RADEON_STATECHANGE( rmesa
, ucp
[p
] );
1173 rmesa
->hw
.ucp
[p
].cmd
[UCP_X
] = ip
[0];
1174 rmesa
->hw
.ucp
[p
].cmd
[UCP_Y
] = ip
[1];
1175 rmesa
->hw
.ucp
[p
].cmd
[UCP_Z
] = ip
[2];
1176 rmesa
->hw
.ucp
[p
].cmd
[UCP_W
] = ip
[3];
1182 /* =============================================================
1187 radeonStencilFuncSeparate( GLcontext
*ctx
, GLenum face
, GLenum func
,
1188 GLint ref
, GLuint mask
)
1190 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1191 GLuint refmask
= (((ctx
->Stencil
.Ref
[0] & 0xff) << RADEON_STENCIL_REF_SHIFT
) |
1192 ((ctx
->Stencil
.ValueMask
[0] & 0xff) << RADEON_STENCIL_MASK_SHIFT
));
1194 RADEON_STATECHANGE( rmesa
, ctx
);
1195 RADEON_STATECHANGE( rmesa
, msk
);
1197 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &= ~RADEON_STENCIL_TEST_MASK
;
1198 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] &= ~(RADEON_STENCIL_REF_MASK
|
1199 RADEON_STENCIL_VALUE_MASK
);
1201 switch ( ctx
->Stencil
.Function
[0] ) {
1203 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_NEVER
;
1206 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_LESS
;
1209 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_EQUAL
;
1212 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_LEQUAL
;
1215 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_GREATER
;
1218 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_NEQUAL
;
1221 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_GEQUAL
;
1224 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_ALWAYS
;
1228 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] |= refmask
;
1232 radeonStencilMaskSeparate( GLcontext
*ctx
, GLenum face
, GLuint mask
)
1234 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1236 RADEON_STATECHANGE( rmesa
, msk
);
1237 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] &= ~RADEON_STENCIL_WRITE_MASK
;
1238 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] |=
1239 ((ctx
->Stencil
.WriteMask
[0] & 0xff) << RADEON_STENCIL_WRITEMASK_SHIFT
);
1242 static void radeonStencilOpSeparate( GLcontext
*ctx
, GLenum face
, GLenum fail
,
1243 GLenum zfail
, GLenum zpass
)
1245 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1247 /* radeon 7200 have stencil bug, DEC and INC_WRAP will actually both do DEC_WRAP,
1248 and DEC_WRAP (and INVERT) will do INVERT. No way to get correct INC_WRAP and DEC,
1249 but DEC_WRAP can be fixed by using DEC and INC_WRAP at least use INC. */
1251 GLuint tempRADEON_STENCIL_FAIL_DEC_WRAP
;
1252 GLuint tempRADEON_STENCIL_FAIL_INC_WRAP
;
1253 GLuint tempRADEON_STENCIL_ZFAIL_DEC_WRAP
;
1254 GLuint tempRADEON_STENCIL_ZFAIL_INC_WRAP
;
1255 GLuint tempRADEON_STENCIL_ZPASS_DEC_WRAP
;
1256 GLuint tempRADEON_STENCIL_ZPASS_INC_WRAP
;
1258 if (rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_BROKEN_STENCIL
) {
1259 tempRADEON_STENCIL_FAIL_DEC_WRAP
= RADEON_STENCIL_FAIL_DEC
;
1260 tempRADEON_STENCIL_FAIL_INC_WRAP
= RADEON_STENCIL_FAIL_INC
;
1261 tempRADEON_STENCIL_ZFAIL_DEC_WRAP
= RADEON_STENCIL_ZFAIL_DEC
;
1262 tempRADEON_STENCIL_ZFAIL_INC_WRAP
= RADEON_STENCIL_ZFAIL_INC
;
1263 tempRADEON_STENCIL_ZPASS_DEC_WRAP
= RADEON_STENCIL_ZPASS_DEC
;
1264 tempRADEON_STENCIL_ZPASS_INC_WRAP
= RADEON_STENCIL_ZPASS_INC
;
1267 tempRADEON_STENCIL_FAIL_DEC_WRAP
= RADEON_STENCIL_FAIL_DEC_WRAP
;
1268 tempRADEON_STENCIL_FAIL_INC_WRAP
= RADEON_STENCIL_FAIL_INC_WRAP
;
1269 tempRADEON_STENCIL_ZFAIL_DEC_WRAP
= RADEON_STENCIL_ZFAIL_DEC_WRAP
;
1270 tempRADEON_STENCIL_ZFAIL_INC_WRAP
= RADEON_STENCIL_ZFAIL_INC_WRAP
;
1271 tempRADEON_STENCIL_ZPASS_DEC_WRAP
= RADEON_STENCIL_ZPASS_DEC_WRAP
;
1272 tempRADEON_STENCIL_ZPASS_INC_WRAP
= RADEON_STENCIL_ZPASS_INC_WRAP
;
1275 RADEON_STATECHANGE( rmesa
, ctx
);
1276 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &= ~(RADEON_STENCIL_FAIL_MASK
|
1277 RADEON_STENCIL_ZFAIL_MASK
|
1278 RADEON_STENCIL_ZPASS_MASK
);
1280 switch ( ctx
->Stencil
.FailFunc
[0] ) {
1282 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_KEEP
;
1285 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_ZERO
;
1288 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_REPLACE
;
1291 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_INC
;
1294 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_DEC
;
1297 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_FAIL_INC_WRAP
;
1300 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_FAIL_DEC_WRAP
;
1303 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_INVERT
;
1307 switch ( ctx
->Stencil
.ZFailFunc
[0] ) {
1309 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_KEEP
;
1312 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_ZERO
;
1315 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_REPLACE
;
1318 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_INC
;
1321 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_DEC
;
1324 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_ZFAIL_INC_WRAP
;
1327 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_ZFAIL_DEC_WRAP
;
1330 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_INVERT
;
1334 switch ( ctx
->Stencil
.ZPassFunc
[0] ) {
1336 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_KEEP
;
1339 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_ZERO
;
1342 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_REPLACE
;
1345 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_INC
;
1348 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_DEC
;
1351 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_ZPASS_INC_WRAP
;
1354 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_ZPASS_DEC_WRAP
;
1357 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_INVERT
;
1362 static void radeonClearStencil( GLcontext
*ctx
, GLint s
)
1364 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1366 rmesa
->radeon
.state
.stencil
.clear
=
1367 ((GLuint
) (ctx
->Stencil
.Clear
& 0xff) |
1368 (0xff << RADEON_STENCIL_MASK_SHIFT
) |
1369 ((ctx
->Stencil
.WriteMask
[0] & 0xff) << RADEON_STENCIL_WRITEMASK_SHIFT
));
1373 /* =============================================================
1374 * Window position and viewport transformation
1378 * To correctly position primitives:
1380 #define SUBPIXEL_X 0.125
1381 #define SUBPIXEL_Y 0.125
1385 * Called when window size or position changes or viewport or depth range
1386 * state is changed. We update the hardware viewport state here.
1388 void radeonUpdateWindow( GLcontext
*ctx
)
1390 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1391 __DRIdrawablePrivate
*dPriv
= rmesa
->radeon
.dri
.drawable
;
1392 GLfloat xoffset
= dPriv
? (GLfloat
) dPriv
->x
: 0;
1393 GLfloat yoffset
= dPriv
? (GLfloat
) dPriv
->y
+ dPriv
->h
: 0;
1394 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
1395 const GLboolean render_to_fbo
= (ctx
->DrawBuffer
? (ctx
->DrawBuffer
->Name
!= 0) : 0);
1396 const GLfloat depthScale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
1397 GLfloat y_scale
, y_bias
;
1399 if (render_to_fbo
) {
1407 float_ui32_type sx
= { v
[MAT_SX
] };
1408 float_ui32_type tx
= { v
[MAT_TX
] + xoffset
+ SUBPIXEL_X
};
1409 float_ui32_type sy
= { v
[MAT_SY
] * y_scale
};
1410 float_ui32_type ty
= { (v
[MAT_TY
] * y_scale
) + y_bias
+ SUBPIXEL_Y
};
1411 float_ui32_type sz
= { v
[MAT_SZ
] * depthScale
};
1412 float_ui32_type tz
= { v
[MAT_TZ
] * depthScale
};
1414 RADEON_STATECHANGE( rmesa
, vpt
);
1416 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XSCALE
] = sx
.ui32
;
1417 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] = tx
.ui32
;
1418 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YSCALE
] = sy
.ui32
;
1419 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] = ty
.ui32
;
1420 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZSCALE
] = sz
.ui32
;
1421 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZOFFSET
] = tz
.ui32
;
1425 static void radeonViewport( GLcontext
*ctx
, GLint x
, GLint y
,
1426 GLsizei width
, GLsizei height
)
1428 /* Don't pipeline viewport changes, conflict with window offset
1429 * setting below. Could apply deltas to rescue pipelined viewport
1430 * values, or keep the originals hanging around.
1432 radeonUpdateWindow( ctx
);
1434 radeon_viewport(ctx
, x
, y
, width
, height
);
1437 static void radeonDepthRange( GLcontext
*ctx
, GLclampd nearval
,
1440 radeonUpdateWindow( ctx
);
1443 void radeonUpdateViewportOffset( GLcontext
*ctx
)
1445 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1446 __DRIdrawablePrivate
*dPriv
= rmesa
->radeon
.dri
.drawable
;
1447 GLfloat xoffset
= (GLfloat
)dPriv
->x
;
1448 GLfloat yoffset
= (GLfloat
)dPriv
->y
+ dPriv
->h
;
1449 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
1454 tx
.f
= v
[MAT_TX
] + xoffset
+ SUBPIXEL_X
;
1455 ty
.f
= (- v
[MAT_TY
]) + yoffset
+ SUBPIXEL_Y
;
1457 if ( rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] != tx
.ui32
||
1458 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] != ty
.ui32
)
1460 /* Note: this should also modify whatever data the context reset
1463 RADEON_STATECHANGE( rmesa
, vpt
);
1464 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] = tx
.ui32
;
1465 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] = ty
.ui32
;
1467 /* update polygon stipple x/y screen offset */
1470 GLuint m
= rmesa
->hw
.msc
.cmd
[MSC_RE_MISC
];
1472 m
&= ~(RADEON_STIPPLE_X_OFFSET_MASK
|
1473 RADEON_STIPPLE_Y_OFFSET_MASK
);
1475 /* add magic offsets, then invert */
1476 stx
= 31 - ((rmesa
->radeon
.dri
.drawable
->x
- 1) & RADEON_STIPPLE_COORD_MASK
);
1477 sty
= 31 - ((rmesa
->radeon
.dri
.drawable
->y
+ rmesa
->radeon
.dri
.drawable
->h
- 1)
1478 & RADEON_STIPPLE_COORD_MASK
);
1480 m
|= ((stx
<< RADEON_STIPPLE_X_OFFSET_SHIFT
) |
1481 (sty
<< RADEON_STIPPLE_Y_OFFSET_SHIFT
));
1483 if ( rmesa
->hw
.msc
.cmd
[MSC_RE_MISC
] != m
) {
1484 RADEON_STATECHANGE( rmesa
, msc
);
1485 rmesa
->hw
.msc
.cmd
[MSC_RE_MISC
] = m
;
1490 radeonUpdateScissor( ctx
);
1495 /* =============================================================
1499 static void radeonClearColor( GLcontext
*ctx
, const GLfloat color
[4] )
1501 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1503 CLAMPED_FLOAT_TO_UBYTE(c
[0], color
[0]);
1504 CLAMPED_FLOAT_TO_UBYTE(c
[1], color
[1]);
1505 CLAMPED_FLOAT_TO_UBYTE(c
[2], color
[2]);
1506 CLAMPED_FLOAT_TO_UBYTE(c
[3], color
[3]);
1507 rmesa
->radeon
.state
.color
.clear
= radeonPackColor( rmesa
->radeon
.radeonScreen
->cpp
,
1508 c
[0], c
[1], c
[2], c
[3] );
1512 static void radeonRenderMode( GLcontext
*ctx
, GLenum mode
)
1514 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1515 FALLBACK( rmesa
, RADEON_FALLBACK_RENDER_MODE
, (mode
!= GL_RENDER
) );
1519 static GLuint radeon_rop_tab
[] = {
1522 RADEON_ROP_AND_REVERSE
,
1524 RADEON_ROP_AND_INVERTED
,
1531 RADEON_ROP_OR_REVERSE
,
1532 RADEON_ROP_COPY_INVERTED
,
1533 RADEON_ROP_OR_INVERTED
,
1538 static void radeonLogicOpCode( GLcontext
*ctx
, GLenum opcode
)
1540 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1541 GLuint rop
= (GLuint
)opcode
- GL_CLEAR
;
1545 RADEON_STATECHANGE( rmesa
, msk
);
1546 rmesa
->hw
.msk
.cmd
[MSK_RB3D_ROPCNTL
] = radeon_rop_tab
[rop
];
1549 /* =============================================================
1550 * State enable/disable
1553 static void radeonEnable( GLcontext
*ctx
, GLenum cap
, GLboolean state
)
1555 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1558 if ( RADEON_DEBUG
& DEBUG_STATE
)
1559 fprintf( stderr
, "%s( %s = %s )\n", __FUNCTION__
,
1560 _mesa_lookup_enum_by_nr( cap
),
1561 state
? "GL_TRUE" : "GL_FALSE" );
1564 /* Fast track this one...
1572 RADEON_STATECHANGE( rmesa
, ctx
);
1574 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_ALPHA_TEST_ENABLE
;
1576 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_ALPHA_TEST_ENABLE
;
1581 RADEON_STATECHANGE( rmesa
, ctx
);
1583 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_ALPHA_BLEND_ENABLE
;
1585 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_ALPHA_BLEND_ENABLE
;
1587 if ( (ctx
->Color
.ColorLogicOpEnabled
|| (ctx
->Color
.BlendEnabled
1588 && ctx
->Color
.BlendEquationRGB
== GL_LOGIC_OP
)) ) {
1589 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_ROP_ENABLE
;
1591 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_ROP_ENABLE
;
1594 /* Catch a possible fallback:
1597 ctx
->Driver
.BlendEquationSeparate( ctx
,
1598 ctx
->Color
.BlendEquationRGB
,
1599 ctx
->Color
.BlendEquationA
);
1600 ctx
->Driver
.BlendFuncSeparate( ctx
, ctx
->Color
.BlendSrcRGB
,
1601 ctx
->Color
.BlendDstRGB
,
1602 ctx
->Color
.BlendSrcA
,
1603 ctx
->Color
.BlendDstA
);
1606 FALLBACK( rmesa
, RADEON_FALLBACK_BLEND_FUNC
, GL_FALSE
);
1607 FALLBACK( rmesa
, RADEON_FALLBACK_BLEND_EQ
, GL_FALSE
);
1611 case GL_CLIP_PLANE0
:
1612 case GL_CLIP_PLANE1
:
1613 case GL_CLIP_PLANE2
:
1614 case GL_CLIP_PLANE3
:
1615 case GL_CLIP_PLANE4
:
1616 case GL_CLIP_PLANE5
:
1617 p
= cap
-GL_CLIP_PLANE0
;
1618 RADEON_STATECHANGE( rmesa
, tcl
);
1620 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= (RADEON_UCP_ENABLE_0
<<p
);
1621 radeonClipPlane( ctx
, cap
, NULL
);
1624 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~(RADEON_UCP_ENABLE_0
<<p
);
1628 case GL_COLOR_MATERIAL
:
1629 radeonColorMaterial( ctx
, 0, 0 );
1630 radeonUpdateMaterial( ctx
);
1634 radeonCullFace( ctx
, 0 );
1638 RADEON_STATECHANGE(rmesa
, ctx
);
1640 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_Z_ENABLE
;
1642 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_Z_ENABLE
;
1647 RADEON_STATECHANGE(rmesa
, ctx
);
1649 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_DITHER_ENABLE
;
1650 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~rmesa
->radeon
.state
.color
.roundEnable
;
1652 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_DITHER_ENABLE
;
1653 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= rmesa
->radeon
.state
.color
.roundEnable
;
1658 RADEON_STATECHANGE(rmesa
, ctx
);
1660 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_FOG_ENABLE
;
1661 radeonFogfv( ctx
, GL_FOG_MODE
, NULL
);
1663 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_FOG_ENABLE
;
1664 RADEON_STATECHANGE(rmesa
, tcl
);
1665 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~RADEON_TCL_FOG_MASK
;
1667 radeonUpdateSpecular( ctx
); /* for PK_SPEC */
1668 _mesa_allow_light_in_model( ctx
, !state
);
1679 RADEON_STATECHANGE(rmesa
, tcl
);
1680 p
= cap
- GL_LIGHT0
;
1682 flag
= (RADEON_LIGHT_1_ENABLE
|
1683 RADEON_LIGHT_1_ENABLE_AMBIENT
|
1684 RADEON_LIGHT_1_ENABLE_SPECULAR
);
1686 flag
= (RADEON_LIGHT_0_ENABLE
|
1687 RADEON_LIGHT_0_ENABLE_AMBIENT
|
1688 RADEON_LIGHT_0_ENABLE_SPECULAR
);
1691 rmesa
->hw
.tcl
.cmd
[p
/2 + TCL_PER_LIGHT_CTL_0
] |= flag
;
1693 rmesa
->hw
.tcl
.cmd
[p
/2 + TCL_PER_LIGHT_CTL_0
] &= ~flag
;
1697 update_light_colors( ctx
, p
);
1701 RADEON_STATECHANGE(rmesa
, tcl
);
1702 radeonUpdateSpecular(ctx
);
1703 check_twoside_fallback( ctx
);
1706 case GL_LINE_SMOOTH
:
1707 RADEON_STATECHANGE( rmesa
, ctx
);
1709 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_ANTI_ALIAS_LINE
;
1711 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_ANTI_ALIAS_LINE
;
1715 case GL_LINE_STIPPLE
:
1716 RADEON_STATECHANGE( rmesa
, ctx
);
1718 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_PATTERN_ENABLE
;
1720 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_PATTERN_ENABLE
;
1724 case GL_COLOR_LOGIC_OP
:
1725 RADEON_STATECHANGE( rmesa
, ctx
);
1726 if ( (ctx
->Color
.ColorLogicOpEnabled
|| (ctx
->Color
.BlendEnabled
1727 && ctx
->Color
.BlendEquationRGB
== GL_LOGIC_OP
)) ) {
1728 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_ROP_ENABLE
;
1730 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_ROP_ENABLE
;
1735 RADEON_STATECHANGE( rmesa
, tcl
);
1737 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_NORMALIZE_NORMALS
;
1739 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_NORMALIZE_NORMALS
;
1743 case GL_POLYGON_OFFSET_POINT
:
1744 RADEON_STATECHANGE( rmesa
, set
);
1746 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_ZBIAS_ENABLE_POINT
;
1748 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_ZBIAS_ENABLE_POINT
;
1752 case GL_POLYGON_OFFSET_LINE
:
1753 RADEON_STATECHANGE( rmesa
, set
);
1755 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_ZBIAS_ENABLE_LINE
;
1757 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_ZBIAS_ENABLE_LINE
;
1761 case GL_POLYGON_OFFSET_FILL
:
1762 RADEON_STATECHANGE( rmesa
, set
);
1764 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_ZBIAS_ENABLE_TRI
;
1766 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_ZBIAS_ENABLE_TRI
;
1770 case GL_POLYGON_SMOOTH
:
1771 RADEON_STATECHANGE( rmesa
, ctx
);
1773 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_ANTI_ALIAS_POLY
;
1775 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_ANTI_ALIAS_POLY
;
1779 case GL_POLYGON_STIPPLE
:
1780 RADEON_STATECHANGE(rmesa
, ctx
);
1782 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_STIPPLE_ENABLE
;
1784 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_STIPPLE_ENABLE
;
1788 case GL_RESCALE_NORMAL_EXT
: {
1789 GLboolean tmp
= ctx
->_NeedEyeCoords
? state
: !state
;
1790 RADEON_STATECHANGE( rmesa
, tcl
);
1792 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_RESCALE_NORMALS
;
1794 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_RESCALE_NORMALS
;
1799 case GL_SCISSOR_TEST
:
1800 radeon_firevertices(&rmesa
->radeon
);
1801 rmesa
->radeon
.state
.scissor
.enabled
= state
;
1802 radeonUpdateScissor( ctx
);
1805 case GL_STENCIL_TEST
:
1807 GLboolean hw_stencil
= GL_FALSE
;
1808 if (ctx
->DrawBuffer
) {
1809 struct radeon_renderbuffer
*rrbStencil
1810 = radeon_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_STENCIL
);
1811 hw_stencil
= (rrbStencil
&& rrbStencil
->bo
);
1815 RADEON_STATECHANGE( rmesa
, ctx
);
1817 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_STENCIL_ENABLE
;
1819 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_STENCIL_ENABLE
;
1822 FALLBACK( rmesa
, RADEON_FALLBACK_STENCIL
, state
);
1827 case GL_TEXTURE_GEN_Q
:
1828 case GL_TEXTURE_GEN_R
:
1829 case GL_TEXTURE_GEN_S
:
1830 case GL_TEXTURE_GEN_T
:
1831 /* Picked up in radeonUpdateTextureState.
1833 rmesa
->recheck_texgen
[ctx
->Texture
.CurrentUnit
] = GL_TRUE
;
1836 case GL_COLOR_SUM_EXT
:
1837 radeonUpdateSpecular ( ctx
);
1846 static void radeonLightingSpaceChange( GLcontext
*ctx
)
1848 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1850 RADEON_STATECHANGE( rmesa
, tcl
);
1852 if (RADEON_DEBUG
& DEBUG_STATE
)
1853 fprintf(stderr
, "%s %d BEFORE %x\n", __FUNCTION__
, ctx
->_NeedEyeCoords
,
1854 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
]);
1856 if (ctx
->_NeedEyeCoords
)
1857 tmp
= ctx
->Transform
.RescaleNormals
;
1859 tmp
= !ctx
->Transform
.RescaleNormals
;
1862 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_RESCALE_NORMALS
;
1864 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_RESCALE_NORMALS
;
1867 if (RADEON_DEBUG
& DEBUG_STATE
)
1868 fprintf(stderr
, "%s %d AFTER %x\n", __FUNCTION__
, ctx
->_NeedEyeCoords
,
1869 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
]);
1872 /* =============================================================
1873 * Deferred state management - matrices, textures, other?
1877 void radeonUploadTexMatrix( r100ContextPtr rmesa
,
1878 int unit
, GLboolean swapcols
)
1880 /* Here's how this works: on r100, only 3 tex coords can be submitted, so the
1881 vector looks like this probably: (s t r|q 0) (not sure if the last coord
1882 is hardwired to 0, could be 1 too). Interestingly, it actually looks like
1883 texgen generates all 4 coords, at least tests with projtex indicated that.
1884 So: if we need the q coord in the end (solely determined by the texture
1885 target, i.e. 2d / 1d / texrect targets) we swap the third and 4th row.
1886 Additionally, if we don't have texgen but 4 tex coords submitted, we swap
1887 column 3 and 4 (for the 2d / 1d / texrect targets) since the the q coord
1888 will get submitted in the "wrong", i.e. 3rd, slot.
1889 If an app submits 3 coords for 2d targets, we assume it is saving on vertex
1890 size and using the texture matrix to swap the r and q coords around (ut2k3
1891 does exactly that), so we don't need the 3rd / 4th column swap - still need
1892 the 3rd / 4th row swap of course. This will potentially break for apps which
1893 use TexCoord3x just for fun. Additionally, it will never work if an app uses
1894 an "advanced" texture matrix and relies on all 4 texcoord inputs to generate
1895 the maximum needed 3. This seems impossible to do with hw tcl on r100, and
1896 incredibly hard to detect so we can't just fallback in such a case. Assume
1897 it never happens... - rs
1900 int idx
= TEXMAT_0
+ unit
;
1901 float *dest
= ((float *)RADEON_DB_STATE( mat
[idx
] )) + MAT_ELT_0
;
1903 struct gl_texture_unit tUnit
= rmesa
->radeon
.glCtx
->Texture
.Unit
[unit
];
1904 GLfloat
*src
= rmesa
->tmpmat
[unit
].m
;
1906 rmesa
->TexMatColSwap
&= ~(1 << unit
);
1907 if ((tUnit
._ReallyEnabled
& (TEXTURE_3D_BIT
| TEXTURE_CUBE_BIT
)) == 0) {
1909 rmesa
->TexMatColSwap
|= 1 << unit
;
1910 /* attention some elems are swapped 2 times! */
1923 /* those last 4 are probably never used */
1930 for (i
= 0; i
< 2; i
++) {
1934 *dest
++ = src
[i
+12];
1936 for (i
= 3; i
>= 2; i
--) {
1940 *dest
++ = src
[i
+12];
1945 for (i
= 0 ; i
< 4 ; i
++) {
1949 *dest
++ = src
[i
+12];
1953 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.mat
[idx
] );
1957 static void upload_matrix( r100ContextPtr rmesa
, GLfloat
*src
, int idx
)
1959 float *dest
= ((float *)RADEON_DB_STATE( mat
[idx
] ))+MAT_ELT_0
;
1963 for (i
= 0 ; i
< 4 ; i
++) {
1967 *dest
++ = src
[i
+12];
1970 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.mat
[idx
] );
1973 static void upload_matrix_t( r100ContextPtr rmesa
, GLfloat
*src
, int idx
)
1975 float *dest
= ((float *)RADEON_DB_STATE( mat
[idx
] ))+MAT_ELT_0
;
1976 memcpy(dest
, src
, 16*sizeof(float));
1977 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.mat
[idx
] );
1981 static void update_texturematrix( GLcontext
*ctx
)
1983 r100ContextPtr rmesa
= R100_CONTEXT( ctx
);
1984 GLuint tpc
= rmesa
->hw
.tcl
.cmd
[TCL_TEXTURE_PROC_CTL
];
1985 GLuint vs
= rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
];
1987 GLuint texMatEnabled
= 0;
1988 rmesa
->NeedTexMatrix
= 0;
1989 rmesa
->TexMatColSwap
= 0;
1991 for (unit
= 0 ; unit
< ctx
->Const
.MaxTextureUnits
; unit
++) {
1992 if (ctx
->Texture
.Unit
[unit
]._ReallyEnabled
) {
1993 GLboolean needMatrix
= GL_FALSE
;
1994 if (ctx
->TextureMatrixStack
[unit
].Top
->type
!= MATRIX_IDENTITY
) {
1995 needMatrix
= GL_TRUE
;
1996 texMatEnabled
|= (RADEON_TEXGEN_TEXMAT_0_ENABLE
|
1997 RADEON_TEXMAT_0_ENABLE
) << unit
;
1999 if (rmesa
->TexGenEnabled
& (RADEON_TEXMAT_0_ENABLE
<< unit
)) {
2000 /* Need to preconcatenate any active texgen
2001 * obj/eyeplane matrices:
2003 _math_matrix_mul_matrix( &rmesa
->tmpmat
[unit
],
2004 ctx
->TextureMatrixStack
[unit
].Top
,
2005 &rmesa
->TexGenMatrix
[unit
] );
2008 _math_matrix_copy( &rmesa
->tmpmat
[unit
],
2009 ctx
->TextureMatrixStack
[unit
].Top
);
2012 else if (rmesa
->TexGenEnabled
& (RADEON_TEXMAT_0_ENABLE
<< unit
)) {
2013 _math_matrix_copy( &rmesa
->tmpmat
[unit
], &rmesa
->TexGenMatrix
[unit
] );
2014 needMatrix
= GL_TRUE
;
2017 rmesa
->NeedTexMatrix
|= 1 << unit
;
2018 radeonUploadTexMatrix( rmesa
, unit
,
2019 !ctx
->Texture
.Unit
[unit
].TexGenEnabled
);
2024 tpc
= (texMatEnabled
| rmesa
->TexGenEnabled
);
2026 /* TCL_TEX_COMPUTED_x is TCL_TEX_INPUT_x | 0x8 */
2027 vs
&= ~((RADEON_TCL_TEX_COMPUTED_TEX_0
<< RADEON_TCL_TEX_0_OUTPUT_SHIFT
) |
2028 (RADEON_TCL_TEX_COMPUTED_TEX_0
<< RADEON_TCL_TEX_1_OUTPUT_SHIFT
) |
2029 (RADEON_TCL_TEX_COMPUTED_TEX_0
<< RADEON_TCL_TEX_2_OUTPUT_SHIFT
));
2031 vs
|= (((tpc
& RADEON_TEXGEN_TEXMAT_0_ENABLE
) <<
2032 (RADEON_TCL_TEX_0_OUTPUT_SHIFT
+ 3)) |
2033 ((tpc
& RADEON_TEXGEN_TEXMAT_1_ENABLE
) <<
2034 (RADEON_TCL_TEX_1_OUTPUT_SHIFT
+ 2)) |
2035 ((tpc
& RADEON_TEXGEN_TEXMAT_2_ENABLE
) <<
2036 (RADEON_TCL_TEX_2_OUTPUT_SHIFT
+ 1)));
2038 if (tpc
!= rmesa
->hw
.tcl
.cmd
[TCL_TEXTURE_PROC_CTL
] ||
2039 vs
!= rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
]) {
2041 RADEON_STATECHANGE(rmesa
, tcl
);
2042 rmesa
->hw
.tcl
.cmd
[TCL_TEXTURE_PROC_CTL
] = tpc
;
2043 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] = vs
;
2047 static GLboolean
r100ValidateBuffers(GLcontext
*ctx
)
2049 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
2050 struct radeon_renderbuffer
*rrb
;
2053 radeon_validate_reset_bos(&rmesa
->radeon
);
2055 rrb
= radeon_get_colorbuffer(&rmesa
->radeon
);
2057 if (rrb
&& rrb
->bo
) {
2058 radeon_validate_bo(&rmesa
->radeon
, rrb
->bo
,
2059 0, RADEON_GEM_DOMAIN_VRAM
);
2063 rrb
= radeon_get_depthbuffer(&rmesa
->radeon
);
2065 if (rrb
&& rrb
->bo
) {
2066 radeon_validate_bo(&rmesa
->radeon
, rrb
->bo
,
2067 0, RADEON_GEM_DOMAIN_VRAM
);
2070 for (i
= 0; i
< ctx
->Const
.MaxTextureImageUnits
; ++i
) {
2073 if (!ctx
->Texture
.Unit
[i
]._ReallyEnabled
)
2076 t
= radeon_tex_obj(ctx
->Texture
.Unit
[i
]._Current
);
2077 if (t
->image_override
&& t
->bo
)
2078 radeon_validate_bo(&rmesa
->radeon
, t
->bo
,
2079 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0);
2081 radeon_validate_bo(&rmesa
->radeon
, t
->mt
->bo
,
2082 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0);
2085 if (rmesa
->radeon
.dma
.current
)
2086 radeon_validate_bo(&rmesa
->radeon
, rmesa
->radeon
.dma
.current
,
2087 RADEON_GEM_DOMAIN_GTT
, 0);
2089 return radeon_revalidate_bos(ctx
);
2092 GLboolean
radeonValidateState( GLcontext
*ctx
)
2094 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
2095 GLuint new_state
= rmesa
->radeon
.NewGLState
;
2097 if (new_state
& _NEW_BUFFERS
) {
2098 _mesa_update_framebuffer(ctx
);
2099 /* this updates the DrawBuffer's Width/Height if it's a FBO */
2100 _mesa_update_draw_buffer_bounds(ctx
);
2101 RADEON_STATECHANGE(rmesa
, ctx
);
2104 if (new_state
& _NEW_TEXTURE
) {
2105 radeonUpdateTextureState( ctx
);
2106 new_state
|= rmesa
->radeon
.NewGLState
; /* may add TEXTURE_MATRIX */
2109 /* we need to do a space check here */
2110 if (!r100ValidateBuffers(ctx
))
2113 /* Need an event driven matrix update?
2115 if (new_state
& (_NEW_MODELVIEW
|_NEW_PROJECTION
))
2116 upload_matrix( rmesa
, ctx
->_ModelProjectMatrix
.m
, MODEL_PROJ
);
2118 /* Need these for lighting (shouldn't upload otherwise)
2120 if (new_state
& (_NEW_MODELVIEW
)) {
2121 upload_matrix( rmesa
, ctx
->ModelviewMatrixStack
.Top
->m
, MODEL
);
2122 upload_matrix_t( rmesa
, ctx
->ModelviewMatrixStack
.Top
->inv
, MODEL_IT
);
2125 /* Does this need to be triggered on eg. modelview for
2126 * texgen-derived objplane/eyeplane matrices?
2128 if (new_state
& _NEW_TEXTURE_MATRIX
) {
2129 update_texturematrix( ctx
);
2132 if (new_state
& (_NEW_LIGHT
|_NEW_MODELVIEW
|_MESA_NEW_NEED_EYE_COORDS
)) {
2133 update_light( ctx
);
2136 /* emit all active clip planes if projection matrix changes.
2138 if (new_state
& (_NEW_PROJECTION
)) {
2139 if (ctx
->Transform
.ClipPlanesEnabled
)
2140 radeonUpdateClipPlanes( ctx
);
2144 rmesa
->radeon
.NewGLState
= 0;
2150 static void radeonInvalidateState( GLcontext
*ctx
, GLuint new_state
)
2152 _swrast_InvalidateState( ctx
, new_state
);
2153 _swsetup_InvalidateState( ctx
, new_state
);
2154 _vbo_InvalidateState( ctx
, new_state
);
2155 _tnl_InvalidateState( ctx
, new_state
);
2156 _ae_invalidate_state( ctx
, new_state
);
2157 R100_CONTEXT(ctx
)->radeon
.NewGLState
|= new_state
;
2161 /* A hack. Need a faster way to find this out.
2163 static GLboolean
check_material( GLcontext
*ctx
)
2165 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
2168 for (i
= _TNL_ATTRIB_MAT_FRONT_AMBIENT
;
2169 i
< _TNL_ATTRIB_MAT_BACK_INDEXES
;
2171 if (tnl
->vb
.AttribPtr
[i
] &&
2172 tnl
->vb
.AttribPtr
[i
]->stride
)
2179 static void radeonWrapRunPipeline( GLcontext
*ctx
)
2181 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
2182 GLboolean has_material
;
2185 fprintf(stderr
, "%s, newstate: %x\n", __FUNCTION__
, rmesa
->radeon
.NewGLState
);
2189 if (rmesa
->radeon
.NewGLState
)
2190 if (!radeonValidateState( ctx
))
2191 FALLBACK(rmesa
, RADEON_FALLBACK_TEXTURE
, GL_TRUE
);
2193 has_material
= (ctx
->Light
.Enabled
&& check_material( ctx
));
2196 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_MATERIAL
, GL_TRUE
);
2199 /* Run the pipeline.
2201 _tnl_run_pipeline( ctx
);
2204 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_MATERIAL
, GL_FALSE
);
2209 /* Initialize the driver's state functions.
2210 * Many of the ctx->Driver functions might have been initialized to
2211 * software defaults in the earlier _mesa_init_driver_functions() call.
2213 void radeonInitStateFuncs( GLcontext
*ctx
)
2215 ctx
->Driver
.UpdateState
= radeonInvalidateState
;
2216 ctx
->Driver
.LightingSpaceChange
= radeonLightingSpaceChange
;
2218 ctx
->Driver
.DrawBuffer
= radeonDrawBuffer
;
2219 ctx
->Driver
.ReadBuffer
= radeonReadBuffer
;
2221 ctx
->Driver
.AlphaFunc
= radeonAlphaFunc
;
2222 ctx
->Driver
.BlendEquationSeparate
= radeonBlendEquationSeparate
;
2223 ctx
->Driver
.BlendFuncSeparate
= radeonBlendFuncSeparate
;
2224 ctx
->Driver
.ClearColor
= radeonClearColor
;
2225 ctx
->Driver
.ClearDepth
= radeonClearDepth
;
2226 ctx
->Driver
.ClearIndex
= NULL
;
2227 ctx
->Driver
.ClearStencil
= radeonClearStencil
;
2228 ctx
->Driver
.ClipPlane
= radeonClipPlane
;
2229 ctx
->Driver
.ColorMask
= radeonColorMask
;
2230 ctx
->Driver
.CullFace
= radeonCullFace
;
2231 ctx
->Driver
.DepthFunc
= radeonDepthFunc
;
2232 ctx
->Driver
.DepthMask
= radeonDepthMask
;
2233 ctx
->Driver
.DepthRange
= radeonDepthRange
;
2234 ctx
->Driver
.Enable
= radeonEnable
;
2235 ctx
->Driver
.Fogfv
= radeonFogfv
;
2236 ctx
->Driver
.FrontFace
= radeonFrontFace
;
2237 ctx
->Driver
.Hint
= NULL
;
2238 ctx
->Driver
.IndexMask
= NULL
;
2239 ctx
->Driver
.LightModelfv
= radeonLightModelfv
;
2240 ctx
->Driver
.Lightfv
= radeonLightfv
;
2241 ctx
->Driver
.LineStipple
= radeonLineStipple
;
2242 ctx
->Driver
.LineWidth
= radeonLineWidth
;
2243 ctx
->Driver
.LogicOpcode
= radeonLogicOpCode
;
2244 ctx
->Driver
.PolygonMode
= radeonPolygonMode
;
2245 ctx
->Driver
.PolygonOffset
= radeonPolygonOffset
;
2246 ctx
->Driver
.PolygonStipple
= radeonPolygonStipple
;
2247 ctx
->Driver
.RenderMode
= radeonRenderMode
;
2248 ctx
->Driver
.Scissor
= radeonScissor
;
2249 ctx
->Driver
.ShadeModel
= radeonShadeModel
;
2250 ctx
->Driver
.StencilFuncSeparate
= radeonStencilFuncSeparate
;
2251 ctx
->Driver
.StencilMaskSeparate
= radeonStencilMaskSeparate
;
2252 ctx
->Driver
.StencilOpSeparate
= radeonStencilOpSeparate
;
2253 ctx
->Driver
.Viewport
= radeonViewport
;
2255 TNL_CONTEXT(ctx
)->Driver
.NotifyMaterialChange
= radeonUpdateMaterial
;
2256 TNL_CONTEXT(ctx
)->Driver
.RunPipeline
= radeonWrapRunPipeline
;