1 /**************************************************************************
3 Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
7 Permission is hereby granted, free of charge, to any person obtaining
8 a copy of this software and associated documentation files (the
9 "Software"), to deal in the Software without restriction, including
10 without limitation the rights to use, copy, modify, merge, publish,
11 distribute, sublicense, and/or sell copies of the Software, and to
12 permit persons to whom the Software is furnished to do so, subject to
13 the following conditions:
15 The above copyright notice and this permission notice (including the
16 next paragraph) shall be included in all copies or substantial
17 portions of the Software.
19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
23 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
24 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
25 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
31 * Gareth Hughes <gareth@valinux.com>
32 * Keith Whitwell <keith@tungstengraphics.com>
35 #include "main/glheader.h"
36 #include "main/imports.h"
37 #include "main/api_arrayelt.h"
38 #include "main/enums.h"
39 #include "main/light.h"
40 #include "main/context.h"
41 #include "main/framebuffer.h"
42 #include "main/simple_list.h"
46 #include "tnl/t_pipeline.h"
47 #include "swrast_setup/swrast_setup.h"
48 #include "drivers/common/meta.h"
50 #include "radeon_context.h"
51 #include "radeon_mipmap_tree.h"
52 #include "radeon_ioctl.h"
53 #include "radeon_state.h"
54 #include "radeon_tcl.h"
55 #include "radeon_tex.h"
56 #include "radeon_swtcl.h"
58 static void radeonUpdateSpecular( GLcontext
*ctx
);
60 /* =============================================================
64 static void radeonAlphaFunc( GLcontext
*ctx
, GLenum func
, GLfloat ref
)
66 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
67 int pp_misc
= rmesa
->hw
.ctx
.cmd
[CTX_PP_MISC
];
70 CLAMPED_FLOAT_TO_UBYTE(refByte
, ref
);
72 RADEON_STATECHANGE( rmesa
, ctx
);
74 pp_misc
&= ~(RADEON_ALPHA_TEST_OP_MASK
| RADEON_REF_ALPHA_MASK
);
75 pp_misc
|= (refByte
& RADEON_REF_ALPHA_MASK
);
79 pp_misc
|= RADEON_ALPHA_TEST_FAIL
;
82 pp_misc
|= RADEON_ALPHA_TEST_LESS
;
85 pp_misc
|= RADEON_ALPHA_TEST_EQUAL
;
88 pp_misc
|= RADEON_ALPHA_TEST_LEQUAL
;
91 pp_misc
|= RADEON_ALPHA_TEST_GREATER
;
94 pp_misc
|= RADEON_ALPHA_TEST_NEQUAL
;
97 pp_misc
|= RADEON_ALPHA_TEST_GEQUAL
;
100 pp_misc
|= RADEON_ALPHA_TEST_PASS
;
104 rmesa
->hw
.ctx
.cmd
[CTX_PP_MISC
] = pp_misc
;
107 static void radeonBlendEquationSeparate( GLcontext
*ctx
,
108 GLenum modeRGB
, GLenum modeA
)
110 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
111 GLuint b
= rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] & ~RADEON_COMB_FCN_MASK
;
112 GLboolean fallback
= GL_FALSE
;
114 assert( modeRGB
== modeA
);
119 b
|= RADEON_COMB_FCN_ADD_CLAMP
;
122 case GL_FUNC_SUBTRACT
:
123 b
|= RADEON_COMB_FCN_SUB_CLAMP
;
127 if (ctx
->Color
.BlendEnabled
)
130 b
|= RADEON_COMB_FCN_ADD_CLAMP
;
134 FALLBACK( rmesa
, RADEON_FALLBACK_BLEND_EQ
, fallback
);
136 RADEON_STATECHANGE( rmesa
, ctx
);
137 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] = b
;
138 if ( (ctx
->Color
.ColorLogicOpEnabled
|| (ctx
->Color
.BlendEnabled
139 && ctx
->Color
.BlendEquationRGB
== GL_LOGIC_OP
)) ) {
140 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_ROP_ENABLE
;
142 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_ROP_ENABLE
;
147 static void radeonBlendFuncSeparate( GLcontext
*ctx
,
148 GLenum sfactorRGB
, GLenum dfactorRGB
,
149 GLenum sfactorA
, GLenum dfactorA
)
151 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
152 GLuint b
= rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] &
153 ~(RADEON_SRC_BLEND_MASK
| RADEON_DST_BLEND_MASK
);
154 GLboolean fallback
= GL_FALSE
;
156 switch ( ctx
->Color
.BlendSrcRGB
) {
158 b
|= RADEON_SRC_BLEND_GL_ZERO
;
161 b
|= RADEON_SRC_BLEND_GL_ONE
;
164 b
|= RADEON_SRC_BLEND_GL_DST_COLOR
;
166 case GL_ONE_MINUS_DST_COLOR
:
167 b
|= RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR
;
170 b
|= RADEON_SRC_BLEND_GL_SRC_COLOR
;
172 case GL_ONE_MINUS_SRC_COLOR
:
173 b
|= RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR
;
176 b
|= RADEON_SRC_BLEND_GL_SRC_ALPHA
;
178 case GL_ONE_MINUS_SRC_ALPHA
:
179 b
|= RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA
;
182 b
|= RADEON_SRC_BLEND_GL_DST_ALPHA
;
184 case GL_ONE_MINUS_DST_ALPHA
:
185 b
|= RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA
;
187 case GL_SRC_ALPHA_SATURATE
:
188 b
|= RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE
;
190 case GL_CONSTANT_COLOR
:
191 case GL_ONE_MINUS_CONSTANT_COLOR
:
192 case GL_CONSTANT_ALPHA
:
193 case GL_ONE_MINUS_CONSTANT_ALPHA
:
194 if (ctx
->Color
.BlendEnabled
)
197 b
|= RADEON_SRC_BLEND_GL_ONE
;
203 switch ( ctx
->Color
.BlendDstRGB
) {
205 b
|= RADEON_DST_BLEND_GL_ZERO
;
208 b
|= RADEON_DST_BLEND_GL_ONE
;
211 b
|= RADEON_DST_BLEND_GL_SRC_COLOR
;
213 case GL_ONE_MINUS_SRC_COLOR
:
214 b
|= RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR
;
217 b
|= RADEON_DST_BLEND_GL_SRC_ALPHA
;
219 case GL_ONE_MINUS_SRC_ALPHA
:
220 b
|= RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA
;
223 b
|= RADEON_DST_BLEND_GL_DST_COLOR
;
225 case GL_ONE_MINUS_DST_COLOR
:
226 b
|= RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR
;
229 b
|= RADEON_DST_BLEND_GL_DST_ALPHA
;
231 case GL_ONE_MINUS_DST_ALPHA
:
232 b
|= RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA
;
234 case GL_CONSTANT_COLOR
:
235 case GL_ONE_MINUS_CONSTANT_COLOR
:
236 case GL_CONSTANT_ALPHA
:
237 case GL_ONE_MINUS_CONSTANT_ALPHA
:
238 if (ctx
->Color
.BlendEnabled
)
241 b
|= RADEON_DST_BLEND_GL_ZERO
;
247 FALLBACK( rmesa
, RADEON_FALLBACK_BLEND_FUNC
, fallback
);
249 RADEON_STATECHANGE( rmesa
, ctx
);
250 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] = b
;
255 /* =============================================================
259 static void radeonDepthFunc( GLcontext
*ctx
, GLenum func
)
261 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
263 RADEON_STATECHANGE( rmesa
, ctx
);
264 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &= ~RADEON_Z_TEST_MASK
;
266 switch ( ctx
->Depth
.Func
) {
268 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_NEVER
;
271 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_LESS
;
274 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_EQUAL
;
277 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_LEQUAL
;
280 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_GREATER
;
283 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_NEQUAL
;
286 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_GEQUAL
;
289 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_TEST_ALWAYS
;
295 static void radeonDepthMask( GLcontext
*ctx
, GLboolean flag
)
297 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
298 RADEON_STATECHANGE( rmesa
, ctx
);
300 if ( ctx
->Depth
.Mask
) {
301 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_WRITE_ENABLE
;
303 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &= ~RADEON_Z_WRITE_ENABLE
;
307 static void radeonClearDepth( GLcontext
*ctx
, GLclampd d
)
309 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
310 GLuint format
= (rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &
311 RADEON_DEPTH_FORMAT_MASK
);
314 case RADEON_DEPTH_FORMAT_16BIT_INT_Z
:
315 rmesa
->radeon
.state
.depth
.clear
= d
* 0x0000ffff;
317 case RADEON_DEPTH_FORMAT_24BIT_INT_Z
:
318 rmesa
->radeon
.state
.depth
.clear
= d
* 0x00ffffff;
324 /* =============================================================
329 static void radeonFogfv( GLcontext
*ctx
, GLenum pname
, const GLfloat
*param
)
331 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
332 union { int i
; float f
; } c
, d
;
337 if (!ctx
->Fog
.Enabled
)
339 RADEON_STATECHANGE(rmesa
, tcl
);
340 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~RADEON_TCL_FOG_MASK
;
341 switch (ctx
->Fog
.Mode
) {
343 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_TCL_FOG_LINEAR
;
346 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_TCL_FOG_EXP
;
349 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_TCL_FOG_EXP2
;
358 if (!ctx
->Fog
.Enabled
)
360 c
.i
= rmesa
->hw
.fog
.cmd
[FOG_C
];
361 d
.i
= rmesa
->hw
.fog
.cmd
[FOG_D
];
362 switch (ctx
->Fog
.Mode
) {
365 /* While this is the opposite sign from the DDK, it makes the fog test
366 * pass, and matches r200.
368 d
.f
= -ctx
->Fog
.Density
;
372 d
.f
= -(ctx
->Fog
.Density
* ctx
->Fog
.Density
);
375 if (ctx
->Fog
.Start
== ctx
->Fog
.End
) {
379 c
.f
= ctx
->Fog
.End
/(ctx
->Fog
.End
-ctx
->Fog
.Start
);
380 /* While this is the opposite sign from the DDK, it makes the fog
381 * test pass, and matches r200.
383 d
.f
= -1.0/(ctx
->Fog
.End
-ctx
->Fog
.Start
);
389 if (c
.i
!= rmesa
->hw
.fog
.cmd
[FOG_C
] || d
.i
!= rmesa
->hw
.fog
.cmd
[FOG_D
]) {
390 RADEON_STATECHANGE( rmesa
, fog
);
391 rmesa
->hw
.fog
.cmd
[FOG_C
] = c
.i
;
392 rmesa
->hw
.fog
.cmd
[FOG_D
] = d
.i
;
396 RADEON_STATECHANGE( rmesa
, ctx
);
397 UNCLAMPED_FLOAT_TO_RGB_CHAN( col
, ctx
->Fog
.Color
);
398 rmesa
->hw
.ctx
.cmd
[CTX_PP_FOG_COLOR
] &= ~RADEON_FOG_COLOR_MASK
;
399 rmesa
->hw
.ctx
.cmd
[CTX_PP_FOG_COLOR
] |=
400 radeonPackColor( 4, col
[0], col
[1], col
[2], 0 );
402 case GL_FOG_COORD_SRC
:
403 radeonUpdateSpecular( ctx
);
410 /* =============================================================
414 static void radeonCullFace( GLcontext
*ctx
, GLenum unused
)
416 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
417 GLuint s
= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
];
418 GLuint t
= rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
];
420 s
|= RADEON_FFACE_SOLID
| RADEON_BFACE_SOLID
;
421 t
&= ~(RADEON_CULL_FRONT
| RADEON_CULL_BACK
);
423 if ( ctx
->Polygon
.CullFlag
) {
424 switch ( ctx
->Polygon
.CullFaceMode
) {
426 s
&= ~RADEON_FFACE_SOLID
;
427 t
|= RADEON_CULL_FRONT
;
430 s
&= ~RADEON_BFACE_SOLID
;
431 t
|= RADEON_CULL_BACK
;
433 case GL_FRONT_AND_BACK
:
434 s
&= ~(RADEON_FFACE_SOLID
| RADEON_BFACE_SOLID
);
435 t
|= (RADEON_CULL_FRONT
| RADEON_CULL_BACK
);
440 if ( rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] != s
) {
441 RADEON_STATECHANGE(rmesa
, set
);
442 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = s
;
445 if ( rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] != t
) {
446 RADEON_STATECHANGE(rmesa
, tcl
);
447 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] = t
;
451 static void radeonFrontFace( GLcontext
*ctx
, GLenum mode
)
453 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
455 RADEON_STATECHANGE( rmesa
, set
);
456 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_FFACE_CULL_DIR_MASK
;
458 RADEON_STATECHANGE( rmesa
, tcl
);
459 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~RADEON_CULL_FRONT_IS_CCW
;
461 /* Winding is inverted when rendering to FBO */
462 if (ctx
->DrawBuffer
&& ctx
->DrawBuffer
->Name
)
463 mode
= (mode
== GL_CW
) ? GL_CCW
: GL_CW
;
467 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_FFACE_CULL_CW
;
470 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_FFACE_CULL_CCW
;
471 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_CULL_FRONT_IS_CCW
;
477 /* =============================================================
480 static void radeonLineWidth( GLcontext
*ctx
, GLfloat widthf
)
482 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
484 RADEON_STATECHANGE( rmesa
, lin
);
485 RADEON_STATECHANGE( rmesa
, set
);
487 /* Line width is stored in U6.4 format.
489 rmesa
->hw
.lin
.cmd
[LIN_SE_LINE_WIDTH
] = (GLuint
)(widthf
* 16.0);
490 if ( widthf
> 1.0 ) {
491 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_WIDELINE_ENABLE
;
493 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_WIDELINE_ENABLE
;
497 static void radeonLineStipple( GLcontext
*ctx
, GLint factor
, GLushort pattern
)
499 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
501 RADEON_STATECHANGE( rmesa
, lin
);
502 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_PATTERN
] =
503 ((((GLuint
)factor
& 0xff) << 16) | ((GLuint
)pattern
));
507 /* =============================================================
510 static void radeonColorMask( GLcontext
*ctx
,
511 GLboolean r
, GLboolean g
,
512 GLboolean b
, GLboolean a
)
514 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
515 struct radeon_renderbuffer
*rrb
;
518 rrb
= radeon_get_colorbuffer(&rmesa
->radeon
);
522 mask
= radeonPackColor( rrb
->cpp
,
523 ctx
->Color
.ColorMask
[0][RCOMP
],
524 ctx
->Color
.ColorMask
[0][GCOMP
],
525 ctx
->Color
.ColorMask
[0][BCOMP
],
526 ctx
->Color
.ColorMask
[0][ACOMP
] );
528 if ( rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
] != mask
) {
529 RADEON_STATECHANGE( rmesa
, msk
);
530 rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
] = mask
;
535 /* =============================================================
539 static void radeonPolygonOffset( GLcontext
*ctx
,
540 GLfloat factor
, GLfloat units
)
542 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
543 const GLfloat depthScale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
544 float_ui32_type constant
= { units
* depthScale
};
545 float_ui32_type factoru
= { factor
};
547 RADEON_STATECHANGE( rmesa
, zbs
);
548 rmesa
->hw
.zbs
.cmd
[ZBS_SE_ZBIAS_FACTOR
] = factoru
.ui32
;
549 rmesa
->hw
.zbs
.cmd
[ZBS_SE_ZBIAS_CONSTANT
] = constant
.ui32
;
552 static void radeonPolygonStipplePreKMS( GLcontext
*ctx
, const GLubyte
*mask
)
554 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
556 drm_radeon_stipple_t stipple
;
558 /* Must flip pattern upside down.
560 for ( i
= 0 ; i
< 32 ; i
++ ) {
561 rmesa
->state
.stipple
.mask
[31 - i
] = ((GLuint
*) mask
)[i
];
564 /* TODO: push this into cmd mechanism
566 radeon_firevertices(&rmesa
->radeon
);
567 LOCK_HARDWARE( &rmesa
->radeon
);
569 /* FIXME: Use window x,y offsets into stipple RAM.
571 stipple
.mask
= rmesa
->state
.stipple
.mask
;
572 drmCommandWrite( rmesa
->radeon
.dri
.fd
, DRM_RADEON_STIPPLE
,
573 &stipple
, sizeof(drm_radeon_stipple_t
) );
574 UNLOCK_HARDWARE( &rmesa
->radeon
);
577 static void radeonPolygonMode( GLcontext
*ctx
, GLenum face
, GLenum mode
)
579 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
580 GLboolean flag
= (ctx
->_TriangleCaps
& DD_TRI_UNFILLED
) != 0;
582 /* Can't generally do unfilled via tcl, but some good special
585 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_UNFILLED
, flag
);
586 if (rmesa
->radeon
.TclFallback
) {
587 radeonChooseRenderState( ctx
);
588 radeonChooseVertexState( ctx
);
593 /* =============================================================
594 * Rendering attributes
596 * We really don't want to recalculate all this every time we bind a
597 * texture. These things shouldn't change all that often, so it makes
598 * sense to break them out of the core texture state update routines.
601 /* Examine lighting and texture state to determine if separate specular
604 static void radeonUpdateSpecular( GLcontext
*ctx
)
606 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
607 uint32_t p
= rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
];
610 RADEON_STATECHANGE( rmesa
, tcl
);
612 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] &= ~RADEON_TCL_COMPUTE_SPECULAR
;
613 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] &= ~RADEON_TCL_COMPUTE_DIFFUSE
;
614 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] &= ~RADEON_TCL_VTX_PK_SPEC
;
615 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] &= ~RADEON_TCL_VTX_PK_DIFFUSE
;
616 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_LIGHTING_ENABLE
;
618 p
&= ~RADEON_SPECULAR_ENABLE
;
620 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_DIFFUSE_SPECULAR_COMBINE
;
623 if (ctx
->Light
.Enabled
&&
624 ctx
->Light
.Model
.ColorControl
== GL_SEPARATE_SPECULAR_COLOR
) {
625 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] |= RADEON_TCL_COMPUTE_SPECULAR
;
626 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] |= RADEON_TCL_COMPUTE_DIFFUSE
;
627 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_SPEC
;
628 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_DIFFUSE
;
629 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_LIGHTING_ENABLE
;
630 p
|= RADEON_SPECULAR_ENABLE
;
631 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &=
632 ~RADEON_DIFFUSE_SPECULAR_COMBINE
;
634 else if (ctx
->Light
.Enabled
) {
635 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] |= RADEON_TCL_COMPUTE_DIFFUSE
;
636 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_DIFFUSE
;
637 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_LIGHTING_ENABLE
;
638 } else if (ctx
->Fog
.ColorSumEnabled
) {
639 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_SPEC
;
640 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_DIFFUSE
;
641 p
|= RADEON_SPECULAR_ENABLE
;
643 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_DIFFUSE
;
646 if (ctx
->Fog
.Enabled
) {
647 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_PK_SPEC
;
648 if (ctx
->Fog
.FogCoordinateSource
== GL_FRAGMENT_DEPTH
) {
649 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] |= RADEON_TCL_COMPUTE_SPECULAR
;
650 /* Bizzare: have to leave lighting enabled to get fog. */
651 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_LIGHTING_ENABLE
;
654 /* cannot do tcl fog factor calculation with fog coord source
655 * (send precomputed factors). Cannot use precomputed fog
656 * factors together with tcl spec light (need tcl fallback) */
657 flag
= (rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] &
658 RADEON_TCL_COMPUTE_SPECULAR
) != 0;
662 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_FOGCOORDSPEC
, flag
);
664 if (NEED_SECONDARY_COLOR(ctx
)) {
665 assert( (p
& RADEON_SPECULAR_ENABLE
) != 0 );
667 assert( (p
& RADEON_SPECULAR_ENABLE
) == 0 );
670 if ( rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] != p
) {
671 RADEON_STATECHANGE( rmesa
, ctx
);
672 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] = p
;
675 /* Update vertex/render formats
677 if (rmesa
->radeon
.TclFallback
) {
678 radeonChooseRenderState( ctx
);
679 radeonChooseVertexState( ctx
);
684 /* =============================================================
689 /* Update on colormaterial, material emmissive/ambient,
690 * lightmodel.globalambient
692 static void update_global_ambient( GLcontext
*ctx
)
694 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
695 float *fcmd
= (float *)RADEON_DB_STATE( glt
);
697 /* Need to do more if both emmissive & ambient are PREMULT:
698 * Hope this is not needed for MULT
700 if ((rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &
701 ((3 << RADEON_EMISSIVE_SOURCE_SHIFT
) |
702 (3 << RADEON_AMBIENT_SOURCE_SHIFT
))) == 0)
704 COPY_3V( &fcmd
[GLT_RED
],
705 ctx
->Light
.Material
.Attrib
[MAT_ATTRIB_FRONT_EMISSION
]);
706 ACC_SCALE_3V( &fcmd
[GLT_RED
],
707 ctx
->Light
.Model
.Ambient
,
708 ctx
->Light
.Material
.Attrib
[MAT_ATTRIB_FRONT_AMBIENT
]);
712 COPY_3V( &fcmd
[GLT_RED
], ctx
->Light
.Model
.Ambient
);
715 RADEON_DB_STATECHANGE(rmesa
, &rmesa
->hw
.glt
);
718 /* Update on change to
722 static void update_light_colors( GLcontext
*ctx
, GLuint p
)
724 struct gl_light
*l
= &ctx
->Light
.Light
[p
];
726 /* fprintf(stderr, "%s\n", __FUNCTION__); */
729 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
730 float *fcmd
= (float *)RADEON_DB_STATE( lit
[p
] );
732 COPY_4V( &fcmd
[LIT_AMBIENT_RED
], l
->Ambient
);
733 COPY_4V( &fcmd
[LIT_DIFFUSE_RED
], l
->Diffuse
);
734 COPY_4V( &fcmd
[LIT_SPECULAR_RED
], l
->Specular
);
736 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.lit
[p
] );
740 /* Also fallback for asym colormaterial mode in twoside lighting...
742 static void check_twoside_fallback( GLcontext
*ctx
)
744 GLboolean fallback
= GL_FALSE
;
747 if (ctx
->Light
.Enabled
&& ctx
->Light
.Model
.TwoSide
) {
748 if (ctx
->Light
.ColorMaterialEnabled
&&
749 (ctx
->Light
.ColorMaterialBitmask
& BACK_MATERIAL_BITS
) !=
750 ((ctx
->Light
.ColorMaterialBitmask
& FRONT_MATERIAL_BITS
)<<1))
753 for (i
= MAT_ATTRIB_FRONT_AMBIENT
; i
< MAT_ATTRIB_FRONT_INDEXES
; i
+=2)
754 if (memcmp( ctx
->Light
.Material
.Attrib
[i
],
755 ctx
->Light
.Material
.Attrib
[i
+1],
756 sizeof(GLfloat
)*4) != 0) {
763 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_LIGHT_TWOSIDE
, fallback
);
767 static void radeonColorMaterial( GLcontext
*ctx
, GLenum face
, GLenum mode
)
769 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
770 GLuint light_model_ctl1
= rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
];
772 light_model_ctl1
&= ~((3 << RADEON_EMISSIVE_SOURCE_SHIFT
) |
773 (3 << RADEON_AMBIENT_SOURCE_SHIFT
) |
774 (3 << RADEON_DIFFUSE_SOURCE_SHIFT
) |
775 (3 << RADEON_SPECULAR_SOURCE_SHIFT
));
777 if (ctx
->Light
.ColorMaterialEnabled
) {
778 GLuint mask
= ctx
->Light
.ColorMaterialBitmask
;
780 if (mask
& MAT_BIT_FRONT_EMISSION
) {
781 light_model_ctl1
|= (RADEON_LM_SOURCE_VERTEX_DIFFUSE
<<
782 RADEON_EMISSIVE_SOURCE_SHIFT
);
785 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<<
786 RADEON_EMISSIVE_SOURCE_SHIFT
);
789 if (mask
& MAT_BIT_FRONT_AMBIENT
) {
790 light_model_ctl1
|= (RADEON_LM_SOURCE_VERTEX_DIFFUSE
<<
791 RADEON_AMBIENT_SOURCE_SHIFT
);
794 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<<
795 RADEON_AMBIENT_SOURCE_SHIFT
);
798 if (mask
& MAT_BIT_FRONT_DIFFUSE
) {
799 light_model_ctl1
|= (RADEON_LM_SOURCE_VERTEX_DIFFUSE
<<
800 RADEON_DIFFUSE_SOURCE_SHIFT
);
803 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<<
804 RADEON_DIFFUSE_SOURCE_SHIFT
);
807 if (mask
& MAT_BIT_FRONT_SPECULAR
) {
808 light_model_ctl1
|= (RADEON_LM_SOURCE_VERTEX_DIFFUSE
<<
809 RADEON_SPECULAR_SOURCE_SHIFT
);
812 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<<
813 RADEON_SPECULAR_SOURCE_SHIFT
);
819 light_model_ctl1
|= (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_EMISSIVE_SOURCE_SHIFT
) |
820 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_AMBIENT_SOURCE_SHIFT
) |
821 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_DIFFUSE_SOURCE_SHIFT
) |
822 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_SPECULAR_SOURCE_SHIFT
);
825 if (light_model_ctl1
!= rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
]) {
826 RADEON_STATECHANGE( rmesa
, tcl
);
827 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] = light_model_ctl1
;
831 void radeonUpdateMaterial( GLcontext
*ctx
)
833 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
834 GLfloat (*mat
)[4] = ctx
->Light
.Material
.Attrib
;
835 GLfloat
*fcmd
= (GLfloat
*)RADEON_DB_STATE( mtl
);
838 if (ctx
->Light
.ColorMaterialEnabled
)
839 mask
&= ~ctx
->Light
.ColorMaterialBitmask
;
841 if (RADEON_DEBUG
& RADEON_STATE
)
842 fprintf(stderr
, "%s\n", __FUNCTION__
);
845 if (mask
& MAT_BIT_FRONT_EMISSION
) {
846 fcmd
[MTL_EMMISSIVE_RED
] = mat
[MAT_ATTRIB_FRONT_EMISSION
][0];
847 fcmd
[MTL_EMMISSIVE_GREEN
] = mat
[MAT_ATTRIB_FRONT_EMISSION
][1];
848 fcmd
[MTL_EMMISSIVE_BLUE
] = mat
[MAT_ATTRIB_FRONT_EMISSION
][2];
849 fcmd
[MTL_EMMISSIVE_ALPHA
] = mat
[MAT_ATTRIB_FRONT_EMISSION
][3];
851 if (mask
& MAT_BIT_FRONT_AMBIENT
) {
852 fcmd
[MTL_AMBIENT_RED
] = mat
[MAT_ATTRIB_FRONT_AMBIENT
][0];
853 fcmd
[MTL_AMBIENT_GREEN
] = mat
[MAT_ATTRIB_FRONT_AMBIENT
][1];
854 fcmd
[MTL_AMBIENT_BLUE
] = mat
[MAT_ATTRIB_FRONT_AMBIENT
][2];
855 fcmd
[MTL_AMBIENT_ALPHA
] = mat
[MAT_ATTRIB_FRONT_AMBIENT
][3];
857 if (mask
& MAT_BIT_FRONT_DIFFUSE
) {
858 fcmd
[MTL_DIFFUSE_RED
] = mat
[MAT_ATTRIB_FRONT_DIFFUSE
][0];
859 fcmd
[MTL_DIFFUSE_GREEN
] = mat
[MAT_ATTRIB_FRONT_DIFFUSE
][1];
860 fcmd
[MTL_DIFFUSE_BLUE
] = mat
[MAT_ATTRIB_FRONT_DIFFUSE
][2];
861 fcmd
[MTL_DIFFUSE_ALPHA
] = mat
[MAT_ATTRIB_FRONT_DIFFUSE
][3];
863 if (mask
& MAT_BIT_FRONT_SPECULAR
) {
864 fcmd
[MTL_SPECULAR_RED
] = mat
[MAT_ATTRIB_FRONT_SPECULAR
][0];
865 fcmd
[MTL_SPECULAR_GREEN
] = mat
[MAT_ATTRIB_FRONT_SPECULAR
][1];
866 fcmd
[MTL_SPECULAR_BLUE
] = mat
[MAT_ATTRIB_FRONT_SPECULAR
][2];
867 fcmd
[MTL_SPECULAR_ALPHA
] = mat
[MAT_ATTRIB_FRONT_SPECULAR
][3];
869 if (mask
& MAT_BIT_FRONT_SHININESS
) {
870 fcmd
[MTL_SHININESS
] = mat
[MAT_ATTRIB_FRONT_SHININESS
][0];
873 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.mtl
);
875 check_twoside_fallback( ctx
);
876 /* update_global_ambient( ctx );*/
881 * _MESA_NEW_NEED_EYE_COORDS
883 * Uses derived state from mesa:
892 * which are calculated in light.c and are correct for the current
893 * lighting space (model or eye), hence dependencies on _NEW_MODELVIEW
894 * and _MESA_NEW_NEED_EYE_COORDS.
896 static void update_light( GLcontext
*ctx
)
898 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
900 /* Have to check these, or have an automatic shortcircuit mechanism
901 * to remove noop statechanges. (Or just do a better job on the
905 GLuint tmp
= rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
];
907 if (ctx
->_NeedEyeCoords
)
908 tmp
&= ~RADEON_LIGHT_IN_MODELSPACE
;
910 tmp
|= RADEON_LIGHT_IN_MODELSPACE
;
913 /* Leave this test disabled: (unexplained q3 lockup) (even with
916 if (tmp
!= rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
])
918 RADEON_STATECHANGE( rmesa
, tcl
);
919 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] = tmp
;
924 GLfloat
*fcmd
= (GLfloat
*)RADEON_DB_STATE( eye
);
925 fcmd
[EYE_X
] = ctx
->_EyeZDir
[0];
926 fcmd
[EYE_Y
] = ctx
->_EyeZDir
[1];
927 fcmd
[EYE_Z
] = - ctx
->_EyeZDir
[2];
928 fcmd
[EYE_RESCALE_FACTOR
] = ctx
->_ModelViewInvScale
;
929 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.eye
);
934 if (ctx
->Light
.Enabled
) {
936 for (p
= 0 ; p
< MAX_LIGHTS
; p
++) {
937 if (ctx
->Light
.Light
[p
].Enabled
) {
938 struct gl_light
*l
= &ctx
->Light
.Light
[p
];
939 GLfloat
*fcmd
= (GLfloat
*)RADEON_DB_STATE( lit
[p
] );
941 if (l
->EyePosition
[3] == 0.0) {
942 COPY_3FV( &fcmd
[LIT_POSITION_X
], l
->_VP_inf_norm
);
943 COPY_3FV( &fcmd
[LIT_DIRECTION_X
], l
->_h_inf_norm
);
944 fcmd
[LIT_POSITION_W
] = 0;
945 fcmd
[LIT_DIRECTION_W
] = 0;
947 COPY_4V( &fcmd
[LIT_POSITION_X
], l
->_Position
);
948 fcmd
[LIT_DIRECTION_X
] = -l
->_NormSpotDirection
[0];
949 fcmd
[LIT_DIRECTION_Y
] = -l
->_NormSpotDirection
[1];
950 fcmd
[LIT_DIRECTION_Z
] = -l
->_NormSpotDirection
[2];
951 fcmd
[LIT_DIRECTION_W
] = 0;
954 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.lit
[p
] );
960 static void radeonLightfv( GLcontext
*ctx
, GLenum light
,
961 GLenum pname
, const GLfloat
*params
)
963 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
964 GLint p
= light
- GL_LIGHT0
;
965 struct gl_light
*l
= &ctx
->Light
.Light
[p
];
966 GLfloat
*fcmd
= (GLfloat
*)rmesa
->hw
.lit
[p
].cmd
;
973 update_light_colors( ctx
, p
);
976 case GL_SPOT_DIRECTION
:
977 /* picked up in update_light */
981 /* positions picked up in update_light, but can do flag here */
983 GLuint idx
= TCL_PER_LIGHT_CTL_0
+ p
/2;
985 /* FIXME: Set RANGE_ATTEN only when needed */
987 flag
= RADEON_LIGHT_1_IS_LOCAL
;
989 flag
= RADEON_LIGHT_0_IS_LOCAL
;
991 RADEON_STATECHANGE(rmesa
, tcl
);
992 if (l
->EyePosition
[3] != 0.0F
)
993 rmesa
->hw
.tcl
.cmd
[idx
] |= flag
;
995 rmesa
->hw
.tcl
.cmd
[idx
] &= ~flag
;
999 case GL_SPOT_EXPONENT
:
1000 RADEON_STATECHANGE(rmesa
, lit
[p
]);
1001 fcmd
[LIT_SPOT_EXPONENT
] = params
[0];
1004 case GL_SPOT_CUTOFF
: {
1005 GLuint flag
= (p
&1) ? RADEON_LIGHT_1_IS_SPOT
: RADEON_LIGHT_0_IS_SPOT
;
1006 GLuint idx
= TCL_PER_LIGHT_CTL_0
+ p
/2;
1008 RADEON_STATECHANGE(rmesa
, lit
[p
]);
1009 fcmd
[LIT_SPOT_CUTOFF
] = l
->_CosCutoff
;
1011 RADEON_STATECHANGE(rmesa
, tcl
);
1012 if (l
->SpotCutoff
!= 180.0F
)
1013 rmesa
->hw
.tcl
.cmd
[idx
] |= flag
;
1015 rmesa
->hw
.tcl
.cmd
[idx
] &= ~flag
;
1020 case GL_CONSTANT_ATTENUATION
:
1021 RADEON_STATECHANGE(rmesa
, lit
[p
]);
1022 fcmd
[LIT_ATTEN_CONST
] = params
[0];
1023 if ( params
[0] == 0.0 )
1024 fcmd
[LIT_ATTEN_CONST_INV
] = FLT_MAX
;
1026 fcmd
[LIT_ATTEN_CONST_INV
] = 1.0 / params
[0];
1028 case GL_LINEAR_ATTENUATION
:
1029 RADEON_STATECHANGE(rmesa
, lit
[p
]);
1030 fcmd
[LIT_ATTEN_LINEAR
] = params
[0];
1032 case GL_QUADRATIC_ATTENUATION
:
1033 RADEON_STATECHANGE(rmesa
, lit
[p
]);
1034 fcmd
[LIT_ATTEN_QUADRATIC
] = params
[0];
1040 /* Set RANGE_ATTEN only when needed */
1043 case GL_CONSTANT_ATTENUATION
:
1044 case GL_LINEAR_ATTENUATION
:
1045 case GL_QUADRATIC_ATTENUATION
:
1047 GLuint
*icmd
= (GLuint
*)RADEON_DB_STATE( tcl
);
1048 GLuint idx
= TCL_PER_LIGHT_CTL_0
+ p
/2;
1049 GLuint atten_flag
= ( p
&1 ) ? RADEON_LIGHT_1_ENABLE_RANGE_ATTEN
1050 : RADEON_LIGHT_0_ENABLE_RANGE_ATTEN
;
1051 GLuint atten_const_flag
= ( p
&1 ) ? RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN
1052 : RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN
;
1054 if ( l
->EyePosition
[3] == 0.0F
||
1055 ( ( fcmd
[LIT_ATTEN_CONST
] == 0.0 || fcmd
[LIT_ATTEN_CONST
] == 1.0 ) &&
1056 fcmd
[LIT_ATTEN_QUADRATIC
] == 0.0 && fcmd
[LIT_ATTEN_LINEAR
] == 0.0 ) ) {
1057 /* Disable attenuation */
1058 icmd
[idx
] &= ~atten_flag
;
1060 if ( fcmd
[LIT_ATTEN_QUADRATIC
] == 0.0 && fcmd
[LIT_ATTEN_LINEAR
] == 0.0 ) {
1061 /* Enable only constant portion of attenuation calculation */
1062 icmd
[idx
] |= ( atten_flag
| atten_const_flag
);
1064 /* Enable full attenuation calculation */
1065 icmd
[idx
] &= ~atten_const_flag
;
1066 icmd
[idx
] |= atten_flag
;
1070 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.tcl
);
1081 static void radeonLightModelfv( GLcontext
*ctx
, GLenum pname
,
1082 const GLfloat
*param
)
1084 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1087 case GL_LIGHT_MODEL_AMBIENT
:
1088 update_global_ambient( ctx
);
1091 case GL_LIGHT_MODEL_LOCAL_VIEWER
:
1092 RADEON_STATECHANGE( rmesa
, tcl
);
1093 if (ctx
->Light
.Model
.LocalViewer
)
1094 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_LOCAL_VIEWER
;
1096 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_LOCAL_VIEWER
;
1099 case GL_LIGHT_MODEL_TWO_SIDE
:
1100 RADEON_STATECHANGE( rmesa
, tcl
);
1101 if (ctx
->Light
.Model
.TwoSide
)
1102 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= RADEON_LIGHT_TWOSIDE
;
1104 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~RADEON_LIGHT_TWOSIDE
;
1106 check_twoside_fallback( ctx
);
1108 if (rmesa
->radeon
.TclFallback
) {
1109 radeonChooseRenderState( ctx
);
1110 radeonChooseVertexState( ctx
);
1114 case GL_LIGHT_MODEL_COLOR_CONTROL
:
1115 radeonUpdateSpecular(ctx
);
1123 static void radeonShadeModel( GLcontext
*ctx
, GLenum mode
)
1125 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1126 GLuint s
= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
];
1128 s
&= ~(RADEON_DIFFUSE_SHADE_MASK
|
1129 RADEON_ALPHA_SHADE_MASK
|
1130 RADEON_SPECULAR_SHADE_MASK
|
1131 RADEON_FOG_SHADE_MASK
);
1135 s
|= (RADEON_DIFFUSE_SHADE_FLAT
|
1136 RADEON_ALPHA_SHADE_FLAT
|
1137 RADEON_SPECULAR_SHADE_FLAT
|
1138 RADEON_FOG_SHADE_FLAT
);
1141 s
|= (RADEON_DIFFUSE_SHADE_GOURAUD
|
1142 RADEON_ALPHA_SHADE_GOURAUD
|
1143 RADEON_SPECULAR_SHADE_GOURAUD
|
1144 RADEON_FOG_SHADE_GOURAUD
);
1150 if ( rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] != s
) {
1151 RADEON_STATECHANGE( rmesa
, set
);
1152 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = s
;
1157 /* =============================================================
1161 static void radeonClipPlane( GLcontext
*ctx
, GLenum plane
, const GLfloat
*eq
)
1163 GLint p
= (GLint
) plane
- (GLint
) GL_CLIP_PLANE0
;
1164 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1165 GLint
*ip
= (GLint
*)ctx
->Transform
._ClipUserPlane
[p
];
1167 RADEON_STATECHANGE( rmesa
, ucp
[p
] );
1168 rmesa
->hw
.ucp
[p
].cmd
[UCP_X
] = ip
[0];
1169 rmesa
->hw
.ucp
[p
].cmd
[UCP_Y
] = ip
[1];
1170 rmesa
->hw
.ucp
[p
].cmd
[UCP_Z
] = ip
[2];
1171 rmesa
->hw
.ucp
[p
].cmd
[UCP_W
] = ip
[3];
1174 static void radeonUpdateClipPlanes( GLcontext
*ctx
)
1176 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1179 for (p
= 0; p
< ctx
->Const
.MaxClipPlanes
; p
++) {
1180 if (ctx
->Transform
.ClipPlanesEnabled
& (1 << p
)) {
1181 GLint
*ip
= (GLint
*)ctx
->Transform
._ClipUserPlane
[p
];
1183 RADEON_STATECHANGE( rmesa
, ucp
[p
] );
1184 rmesa
->hw
.ucp
[p
].cmd
[UCP_X
] = ip
[0];
1185 rmesa
->hw
.ucp
[p
].cmd
[UCP_Y
] = ip
[1];
1186 rmesa
->hw
.ucp
[p
].cmd
[UCP_Z
] = ip
[2];
1187 rmesa
->hw
.ucp
[p
].cmd
[UCP_W
] = ip
[3];
1193 /* =============================================================
1198 radeonStencilFuncSeparate( GLcontext
*ctx
, GLenum face
, GLenum func
,
1199 GLint ref
, GLuint mask
)
1201 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1202 GLuint refmask
= (((ctx
->Stencil
.Ref
[0] & 0xff) << RADEON_STENCIL_REF_SHIFT
) |
1203 ((ctx
->Stencil
.ValueMask
[0] & 0xff) << RADEON_STENCIL_MASK_SHIFT
));
1205 RADEON_STATECHANGE( rmesa
, ctx
);
1206 RADEON_STATECHANGE( rmesa
, msk
);
1208 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &= ~RADEON_STENCIL_TEST_MASK
;
1209 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] &= ~(RADEON_STENCIL_REF_MASK
|
1210 RADEON_STENCIL_VALUE_MASK
);
1212 switch ( ctx
->Stencil
.Function
[0] ) {
1214 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_NEVER
;
1217 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_LESS
;
1220 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_EQUAL
;
1223 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_LEQUAL
;
1226 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_GREATER
;
1229 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_NEQUAL
;
1232 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_GEQUAL
;
1235 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_TEST_ALWAYS
;
1239 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] |= refmask
;
1243 radeonStencilMaskSeparate( GLcontext
*ctx
, GLenum face
, GLuint mask
)
1245 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1247 RADEON_STATECHANGE( rmesa
, msk
);
1248 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] &= ~RADEON_STENCIL_WRITE_MASK
;
1249 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] |=
1250 ((ctx
->Stencil
.WriteMask
[0] & 0xff) << RADEON_STENCIL_WRITEMASK_SHIFT
);
1253 static void radeonStencilOpSeparate( GLcontext
*ctx
, GLenum face
, GLenum fail
,
1254 GLenum zfail
, GLenum zpass
)
1256 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1258 /* radeon 7200 have stencil bug, DEC and INC_WRAP will actually both do DEC_WRAP,
1259 and DEC_WRAP (and INVERT) will do INVERT. No way to get correct INC_WRAP and DEC,
1260 but DEC_WRAP can be fixed by using DEC and INC_WRAP at least use INC. */
1262 GLuint tempRADEON_STENCIL_FAIL_DEC_WRAP
;
1263 GLuint tempRADEON_STENCIL_FAIL_INC_WRAP
;
1264 GLuint tempRADEON_STENCIL_ZFAIL_DEC_WRAP
;
1265 GLuint tempRADEON_STENCIL_ZFAIL_INC_WRAP
;
1266 GLuint tempRADEON_STENCIL_ZPASS_DEC_WRAP
;
1267 GLuint tempRADEON_STENCIL_ZPASS_INC_WRAP
;
1269 if (rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_BROKEN_STENCIL
) {
1270 tempRADEON_STENCIL_FAIL_DEC_WRAP
= RADEON_STENCIL_FAIL_DEC
;
1271 tempRADEON_STENCIL_FAIL_INC_WRAP
= RADEON_STENCIL_FAIL_INC
;
1272 tempRADEON_STENCIL_ZFAIL_DEC_WRAP
= RADEON_STENCIL_ZFAIL_DEC
;
1273 tempRADEON_STENCIL_ZFAIL_INC_WRAP
= RADEON_STENCIL_ZFAIL_INC
;
1274 tempRADEON_STENCIL_ZPASS_DEC_WRAP
= RADEON_STENCIL_ZPASS_DEC
;
1275 tempRADEON_STENCIL_ZPASS_INC_WRAP
= RADEON_STENCIL_ZPASS_INC
;
1278 tempRADEON_STENCIL_FAIL_DEC_WRAP
= RADEON_STENCIL_FAIL_DEC_WRAP
;
1279 tempRADEON_STENCIL_FAIL_INC_WRAP
= RADEON_STENCIL_FAIL_INC_WRAP
;
1280 tempRADEON_STENCIL_ZFAIL_DEC_WRAP
= RADEON_STENCIL_ZFAIL_DEC_WRAP
;
1281 tempRADEON_STENCIL_ZFAIL_INC_WRAP
= RADEON_STENCIL_ZFAIL_INC_WRAP
;
1282 tempRADEON_STENCIL_ZPASS_DEC_WRAP
= RADEON_STENCIL_ZPASS_DEC_WRAP
;
1283 tempRADEON_STENCIL_ZPASS_INC_WRAP
= RADEON_STENCIL_ZPASS_INC_WRAP
;
1286 RADEON_STATECHANGE( rmesa
, ctx
);
1287 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] &= ~(RADEON_STENCIL_FAIL_MASK
|
1288 RADEON_STENCIL_ZFAIL_MASK
|
1289 RADEON_STENCIL_ZPASS_MASK
);
1291 switch ( ctx
->Stencil
.FailFunc
[0] ) {
1293 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_KEEP
;
1296 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_ZERO
;
1299 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_REPLACE
;
1302 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_INC
;
1305 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_DEC
;
1308 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_FAIL_INC_WRAP
;
1311 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_FAIL_DEC_WRAP
;
1314 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_FAIL_INVERT
;
1318 switch ( ctx
->Stencil
.ZFailFunc
[0] ) {
1320 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_KEEP
;
1323 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_ZERO
;
1326 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_REPLACE
;
1329 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_INC
;
1332 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_DEC
;
1335 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_ZFAIL_INC_WRAP
;
1338 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_ZFAIL_DEC_WRAP
;
1341 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZFAIL_INVERT
;
1345 switch ( ctx
->Stencil
.ZPassFunc
[0] ) {
1347 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_KEEP
;
1350 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_ZERO
;
1353 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_REPLACE
;
1356 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_INC
;
1359 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_DEC
;
1362 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_ZPASS_INC_WRAP
;
1365 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= tempRADEON_STENCIL_ZPASS_DEC_WRAP
;
1368 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_STENCIL_ZPASS_INVERT
;
1373 static void radeonClearStencil( GLcontext
*ctx
, GLint s
)
1375 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1377 rmesa
->radeon
.state
.stencil
.clear
=
1378 ((GLuint
) (ctx
->Stencil
.Clear
& 0xff) |
1379 (0xff << RADEON_STENCIL_MASK_SHIFT
) |
1380 ((ctx
->Stencil
.WriteMask
[0] & 0xff) << RADEON_STENCIL_WRITEMASK_SHIFT
));
1384 /* =============================================================
1385 * Window position and viewport transformation
1389 * To correctly position primitives:
1391 #define SUBPIXEL_X 0.125
1392 #define SUBPIXEL_Y 0.125
1396 * Called when window size or position changes or viewport or depth range
1397 * state is changed. We update the hardware viewport state here.
1399 void radeonUpdateWindow( GLcontext
*ctx
)
1401 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1402 __DRIdrawable
*dPriv
= radeon_get_drawable(&rmesa
->radeon
);
1403 GLfloat xoffset
= dPriv
? (GLfloat
) dPriv
->x
: 0;
1404 GLfloat yoffset
= dPriv
? (GLfloat
) dPriv
->y
+ dPriv
->h
: 0;
1405 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
1406 const GLboolean render_to_fbo
= (ctx
->DrawBuffer
? (ctx
->DrawBuffer
->Name
!= 0) : 0);
1407 const GLfloat depthScale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
1408 GLfloat y_scale
, y_bias
;
1410 if (render_to_fbo
) {
1418 float_ui32_type sx
= { v
[MAT_SX
] };
1419 float_ui32_type tx
= { v
[MAT_TX
] + xoffset
+ SUBPIXEL_X
};
1420 float_ui32_type sy
= { v
[MAT_SY
] * y_scale
};
1421 float_ui32_type ty
= { (v
[MAT_TY
] * y_scale
) + y_bias
+ SUBPIXEL_Y
};
1422 float_ui32_type sz
= { v
[MAT_SZ
] * depthScale
};
1423 float_ui32_type tz
= { v
[MAT_TZ
] * depthScale
};
1425 RADEON_STATECHANGE( rmesa
, vpt
);
1427 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XSCALE
] = sx
.ui32
;
1428 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] = tx
.ui32
;
1429 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YSCALE
] = sy
.ui32
;
1430 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] = ty
.ui32
;
1431 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZSCALE
] = sz
.ui32
;
1432 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZOFFSET
] = tz
.ui32
;
1436 static void radeonViewport( GLcontext
*ctx
, GLint x
, GLint y
,
1437 GLsizei width
, GLsizei height
)
1439 /* Don't pipeline viewport changes, conflict with window offset
1440 * setting below. Could apply deltas to rescue pipelined viewport
1441 * values, or keep the originals hanging around.
1443 radeonUpdateWindow( ctx
);
1445 radeon_viewport(ctx
, x
, y
, width
, height
);
1448 static void radeonDepthRange( GLcontext
*ctx
, GLclampd nearval
,
1451 radeonUpdateWindow( ctx
);
1454 void radeonUpdateViewportOffset( GLcontext
*ctx
)
1456 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1457 __DRIdrawable
*dPriv
= radeon_get_drawable(&rmesa
->radeon
);
1458 GLfloat xoffset
= (GLfloat
)dPriv
->x
;
1459 GLfloat yoffset
= (GLfloat
)dPriv
->y
+ dPriv
->h
;
1460 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
1465 tx
.f
= v
[MAT_TX
] + xoffset
+ SUBPIXEL_X
;
1466 ty
.f
= (- v
[MAT_TY
]) + yoffset
+ SUBPIXEL_Y
;
1468 if ( rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] != tx
.ui32
||
1469 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] != ty
.ui32
)
1471 /* Note: this should also modify whatever data the context reset
1474 RADEON_STATECHANGE( rmesa
, vpt
);
1475 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] = tx
.ui32
;
1476 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] = ty
.ui32
;
1478 /* update polygon stipple x/y screen offset */
1481 GLuint m
= rmesa
->hw
.msc
.cmd
[MSC_RE_MISC
];
1483 m
&= ~(RADEON_STIPPLE_X_OFFSET_MASK
|
1484 RADEON_STIPPLE_Y_OFFSET_MASK
);
1486 /* add magic offsets, then invert */
1487 stx
= 31 - ((dPriv
->x
- 1) & RADEON_STIPPLE_COORD_MASK
);
1488 sty
= 31 - ((dPriv
->y
+ dPriv
->h
- 1)
1489 & RADEON_STIPPLE_COORD_MASK
);
1491 m
|= ((stx
<< RADEON_STIPPLE_X_OFFSET_SHIFT
) |
1492 (sty
<< RADEON_STIPPLE_Y_OFFSET_SHIFT
));
1494 if ( rmesa
->hw
.msc
.cmd
[MSC_RE_MISC
] != m
) {
1495 RADEON_STATECHANGE( rmesa
, msc
);
1496 rmesa
->hw
.msc
.cmd
[MSC_RE_MISC
] = m
;
1501 radeonUpdateScissor( ctx
);
1506 /* =============================================================
1510 static void radeonClearColor( GLcontext
*ctx
, const GLfloat color
[4] )
1512 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1514 struct radeon_renderbuffer
*rrb
;
1516 rrb
= radeon_get_colorbuffer(&rmesa
->radeon
);
1520 CLAMPED_FLOAT_TO_UBYTE(c
[0], color
[0]);
1521 CLAMPED_FLOAT_TO_UBYTE(c
[1], color
[1]);
1522 CLAMPED_FLOAT_TO_UBYTE(c
[2], color
[2]);
1523 CLAMPED_FLOAT_TO_UBYTE(c
[3], color
[3]);
1524 rmesa
->radeon
.state
.color
.clear
= radeonPackColor( rrb
->cpp
,
1525 c
[0], c
[1], c
[2], c
[3] );
1529 static void radeonRenderMode( GLcontext
*ctx
, GLenum mode
)
1531 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1532 FALLBACK( rmesa
, RADEON_FALLBACK_RENDER_MODE
, (mode
!= GL_RENDER
) );
1536 static GLuint radeon_rop_tab
[] = {
1539 RADEON_ROP_AND_REVERSE
,
1541 RADEON_ROP_AND_INVERTED
,
1548 RADEON_ROP_OR_REVERSE
,
1549 RADEON_ROP_COPY_INVERTED
,
1550 RADEON_ROP_OR_INVERTED
,
1555 static void radeonLogicOpCode( GLcontext
*ctx
, GLenum opcode
)
1557 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1558 GLuint rop
= (GLuint
)opcode
- GL_CLEAR
;
1562 RADEON_STATECHANGE( rmesa
, msk
);
1563 rmesa
->hw
.msk
.cmd
[MSK_RB3D_ROPCNTL
] = radeon_rop_tab
[rop
];
1566 /* =============================================================
1567 * State enable/disable
1570 static void radeonEnable( GLcontext
*ctx
, GLenum cap
, GLboolean state
)
1572 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1575 if ( RADEON_DEBUG
& RADEON_STATE
)
1576 fprintf( stderr
, "%s( %s = %s )\n", __FUNCTION__
,
1577 _mesa_lookup_enum_by_nr( cap
),
1578 state
? "GL_TRUE" : "GL_FALSE" );
1581 /* Fast track this one...
1589 RADEON_STATECHANGE( rmesa
, ctx
);
1591 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_ALPHA_TEST_ENABLE
;
1593 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_ALPHA_TEST_ENABLE
;
1598 RADEON_STATECHANGE( rmesa
, ctx
);
1600 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_ALPHA_BLEND_ENABLE
;
1602 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_ALPHA_BLEND_ENABLE
;
1604 if ( (ctx
->Color
.ColorLogicOpEnabled
|| (ctx
->Color
.BlendEnabled
1605 && ctx
->Color
.BlendEquationRGB
== GL_LOGIC_OP
)) ) {
1606 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_ROP_ENABLE
;
1608 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_ROP_ENABLE
;
1611 /* Catch a possible fallback:
1614 ctx
->Driver
.BlendEquationSeparate( ctx
,
1615 ctx
->Color
.BlendEquationRGB
,
1616 ctx
->Color
.BlendEquationA
);
1617 ctx
->Driver
.BlendFuncSeparate( ctx
, ctx
->Color
.BlendSrcRGB
,
1618 ctx
->Color
.BlendDstRGB
,
1619 ctx
->Color
.BlendSrcA
,
1620 ctx
->Color
.BlendDstA
);
1623 FALLBACK( rmesa
, RADEON_FALLBACK_BLEND_FUNC
, GL_FALSE
);
1624 FALLBACK( rmesa
, RADEON_FALLBACK_BLEND_EQ
, GL_FALSE
);
1628 case GL_CLIP_PLANE0
:
1629 case GL_CLIP_PLANE1
:
1630 case GL_CLIP_PLANE2
:
1631 case GL_CLIP_PLANE3
:
1632 case GL_CLIP_PLANE4
:
1633 case GL_CLIP_PLANE5
:
1634 p
= cap
-GL_CLIP_PLANE0
;
1635 RADEON_STATECHANGE( rmesa
, tcl
);
1637 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] |= (RADEON_UCP_ENABLE_0
<<p
);
1638 radeonClipPlane( ctx
, cap
, NULL
);
1641 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~(RADEON_UCP_ENABLE_0
<<p
);
1645 case GL_COLOR_MATERIAL
:
1646 radeonColorMaterial( ctx
, 0, 0 );
1647 radeonUpdateMaterial( ctx
);
1651 radeonCullFace( ctx
, 0 );
1655 RADEON_STATECHANGE(rmesa
, ctx
);
1657 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_Z_ENABLE
;
1659 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_Z_ENABLE
;
1664 RADEON_STATECHANGE(rmesa
, ctx
);
1666 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_DITHER_ENABLE
;
1667 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~rmesa
->radeon
.state
.color
.roundEnable
;
1669 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_DITHER_ENABLE
;
1670 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= rmesa
->radeon
.state
.color
.roundEnable
;
1675 RADEON_STATECHANGE(rmesa
, ctx
);
1677 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_FOG_ENABLE
;
1678 radeonFogfv( ctx
, GL_FOG_MODE
, NULL
);
1680 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_FOG_ENABLE
;
1681 RADEON_STATECHANGE(rmesa
, tcl
);
1682 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] &= ~RADEON_TCL_FOG_MASK
;
1684 radeonUpdateSpecular( ctx
); /* for PK_SPEC */
1685 _mesa_allow_light_in_model( ctx
, !state
);
1696 RADEON_STATECHANGE(rmesa
, tcl
);
1697 p
= cap
- GL_LIGHT0
;
1699 flag
= (RADEON_LIGHT_1_ENABLE
|
1700 RADEON_LIGHT_1_ENABLE_AMBIENT
|
1701 RADEON_LIGHT_1_ENABLE_SPECULAR
);
1703 flag
= (RADEON_LIGHT_0_ENABLE
|
1704 RADEON_LIGHT_0_ENABLE_AMBIENT
|
1705 RADEON_LIGHT_0_ENABLE_SPECULAR
);
1708 rmesa
->hw
.tcl
.cmd
[p
/2 + TCL_PER_LIGHT_CTL_0
] |= flag
;
1710 rmesa
->hw
.tcl
.cmd
[p
/2 + TCL_PER_LIGHT_CTL_0
] &= ~flag
;
1714 update_light_colors( ctx
, p
);
1718 RADEON_STATECHANGE(rmesa
, tcl
);
1719 radeonUpdateSpecular(ctx
);
1720 check_twoside_fallback( ctx
);
1723 case GL_LINE_SMOOTH
:
1724 RADEON_STATECHANGE( rmesa
, ctx
);
1726 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_ANTI_ALIAS_LINE
;
1728 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_ANTI_ALIAS_LINE
;
1732 case GL_LINE_STIPPLE
:
1733 RADEON_STATECHANGE( rmesa
, ctx
);
1735 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_PATTERN_ENABLE
;
1737 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_PATTERN_ENABLE
;
1741 case GL_COLOR_LOGIC_OP
:
1742 RADEON_STATECHANGE( rmesa
, ctx
);
1743 if ( (ctx
->Color
.ColorLogicOpEnabled
|| (ctx
->Color
.BlendEnabled
1744 && ctx
->Color
.BlendEquationRGB
== GL_LOGIC_OP
)) ) {
1745 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_ROP_ENABLE
;
1747 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_ROP_ENABLE
;
1752 RADEON_STATECHANGE( rmesa
, tcl
);
1754 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_NORMALIZE_NORMALS
;
1756 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_NORMALIZE_NORMALS
;
1760 case GL_POLYGON_OFFSET_POINT
:
1761 RADEON_STATECHANGE( rmesa
, set
);
1763 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_ZBIAS_ENABLE_POINT
;
1765 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_ZBIAS_ENABLE_POINT
;
1769 case GL_POLYGON_OFFSET_LINE
:
1770 RADEON_STATECHANGE( rmesa
, set
);
1772 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_ZBIAS_ENABLE_LINE
;
1774 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_ZBIAS_ENABLE_LINE
;
1778 case GL_POLYGON_OFFSET_FILL
:
1779 RADEON_STATECHANGE( rmesa
, set
);
1781 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] |= RADEON_ZBIAS_ENABLE_TRI
;
1783 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] &= ~RADEON_ZBIAS_ENABLE_TRI
;
1787 case GL_POLYGON_SMOOTH
:
1788 RADEON_STATECHANGE( rmesa
, ctx
);
1790 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_ANTI_ALIAS_POLY
;
1792 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_ANTI_ALIAS_POLY
;
1796 case GL_POLYGON_STIPPLE
:
1797 RADEON_STATECHANGE(rmesa
, ctx
);
1799 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |= RADEON_STIPPLE_ENABLE
;
1801 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~RADEON_STIPPLE_ENABLE
;
1805 case GL_RESCALE_NORMAL_EXT
: {
1806 GLboolean tmp
= ctx
->_NeedEyeCoords
? state
: !state
;
1807 RADEON_STATECHANGE( rmesa
, tcl
);
1809 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_RESCALE_NORMALS
;
1811 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_RESCALE_NORMALS
;
1816 case GL_SCISSOR_TEST
:
1817 radeon_firevertices(&rmesa
->radeon
);
1818 rmesa
->radeon
.state
.scissor
.enabled
= state
;
1819 radeonUpdateScissor( ctx
);
1822 case GL_STENCIL_TEST
:
1824 GLboolean hw_stencil
= GL_FALSE
;
1825 if (ctx
->DrawBuffer
) {
1826 struct radeon_renderbuffer
*rrbStencil
1827 = radeon_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_STENCIL
);
1828 hw_stencil
= (rrbStencil
&& rrbStencil
->bo
);
1832 RADEON_STATECHANGE( rmesa
, ctx
);
1834 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_STENCIL_ENABLE
;
1836 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] &= ~RADEON_STENCIL_ENABLE
;
1839 FALLBACK( rmesa
, RADEON_FALLBACK_STENCIL
, state
);
1844 case GL_TEXTURE_GEN_Q
:
1845 case GL_TEXTURE_GEN_R
:
1846 case GL_TEXTURE_GEN_S
:
1847 case GL_TEXTURE_GEN_T
:
1848 /* Picked up in radeonUpdateTextureState.
1850 rmesa
->recheck_texgen
[ctx
->Texture
.CurrentUnit
] = GL_TRUE
;
1853 case GL_COLOR_SUM_EXT
:
1854 radeonUpdateSpecular ( ctx
);
1863 static void radeonLightingSpaceChange( GLcontext
*ctx
)
1865 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1867 RADEON_STATECHANGE( rmesa
, tcl
);
1869 if (RADEON_DEBUG
& RADEON_STATE
)
1870 fprintf(stderr
, "%s %d BEFORE %x\n", __FUNCTION__
, ctx
->_NeedEyeCoords
,
1871 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
]);
1873 if (ctx
->_NeedEyeCoords
)
1874 tmp
= ctx
->Transform
.RescaleNormals
;
1876 tmp
= !ctx
->Transform
.RescaleNormals
;
1879 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] |= RADEON_RESCALE_NORMALS
;
1881 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] &= ~RADEON_RESCALE_NORMALS
;
1884 if (RADEON_DEBUG
& RADEON_STATE
)
1885 fprintf(stderr
, "%s %d AFTER %x\n", __FUNCTION__
, ctx
->_NeedEyeCoords
,
1886 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
]);
1889 /* =============================================================
1890 * Deferred state management - matrices, textures, other?
1894 void radeonUploadTexMatrix( r100ContextPtr rmesa
,
1895 int unit
, GLboolean swapcols
)
1897 /* Here's how this works: on r100, only 3 tex coords can be submitted, so the
1898 vector looks like this probably: (s t r|q 0) (not sure if the last coord
1899 is hardwired to 0, could be 1 too). Interestingly, it actually looks like
1900 texgen generates all 4 coords, at least tests with projtex indicated that.
1901 So: if we need the q coord in the end (solely determined by the texture
1902 target, i.e. 2d / 1d / texrect targets) we swap the third and 4th row.
1903 Additionally, if we don't have texgen but 4 tex coords submitted, we swap
1904 column 3 and 4 (for the 2d / 1d / texrect targets) since the q coord
1905 will get submitted in the "wrong", i.e. 3rd, slot.
1906 If an app submits 3 coords for 2d targets, we assume it is saving on vertex
1907 size and using the texture matrix to swap the r and q coords around (ut2k3
1908 does exactly that), so we don't need the 3rd / 4th column swap - still need
1909 the 3rd / 4th row swap of course. This will potentially break for apps which
1910 use TexCoord3x just for fun. Additionally, it will never work if an app uses
1911 an "advanced" texture matrix and relies on all 4 texcoord inputs to generate
1912 the maximum needed 3. This seems impossible to do with hw tcl on r100, and
1913 incredibly hard to detect so we can't just fallback in such a case. Assume
1914 it never happens... - rs
1917 int idx
= TEXMAT_0
+ unit
;
1918 float *dest
= ((float *)RADEON_DB_STATE( mat
[idx
] )) + MAT_ELT_0
;
1920 struct gl_texture_unit tUnit
= rmesa
->radeon
.glCtx
->Texture
.Unit
[unit
];
1921 GLfloat
*src
= rmesa
->tmpmat
[unit
].m
;
1923 rmesa
->TexMatColSwap
&= ~(1 << unit
);
1924 if ((tUnit
._ReallyEnabled
& (TEXTURE_3D_BIT
| TEXTURE_CUBE_BIT
)) == 0) {
1926 rmesa
->TexMatColSwap
|= 1 << unit
;
1927 /* attention some elems are swapped 2 times! */
1940 /* those last 4 are probably never used */
1947 for (i
= 0; i
< 2; i
++) {
1951 *dest
++ = src
[i
+12];
1953 for (i
= 3; i
>= 2; i
--) {
1957 *dest
++ = src
[i
+12];
1962 for (i
= 0 ; i
< 4 ; i
++) {
1966 *dest
++ = src
[i
+12];
1970 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.mat
[idx
] );
1974 static void upload_matrix( r100ContextPtr rmesa
, GLfloat
*src
, int idx
)
1976 float *dest
= ((float *)RADEON_DB_STATE( mat
[idx
] ))+MAT_ELT_0
;
1980 for (i
= 0 ; i
< 4 ; i
++) {
1984 *dest
++ = src
[i
+12];
1987 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.mat
[idx
] );
1990 static void upload_matrix_t( r100ContextPtr rmesa
, GLfloat
*src
, int idx
)
1992 float *dest
= ((float *)RADEON_DB_STATE( mat
[idx
] ))+MAT_ELT_0
;
1993 memcpy(dest
, src
, 16*sizeof(float));
1994 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.mat
[idx
] );
1998 static void update_texturematrix( GLcontext
*ctx
)
2000 r100ContextPtr rmesa
= R100_CONTEXT( ctx
);
2001 GLuint tpc
= rmesa
->hw
.tcl
.cmd
[TCL_TEXTURE_PROC_CTL
];
2002 GLuint vs
= rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
];
2004 GLuint texMatEnabled
= 0;
2005 rmesa
->NeedTexMatrix
= 0;
2006 rmesa
->TexMatColSwap
= 0;
2008 for (unit
= 0 ; unit
< ctx
->Const
.MaxTextureUnits
; unit
++) {
2009 if (ctx
->Texture
.Unit
[unit
]._ReallyEnabled
) {
2010 GLboolean needMatrix
= GL_FALSE
;
2011 if (ctx
->TextureMatrixStack
[unit
].Top
->type
!= MATRIX_IDENTITY
) {
2012 needMatrix
= GL_TRUE
;
2013 texMatEnabled
|= (RADEON_TEXGEN_TEXMAT_0_ENABLE
|
2014 RADEON_TEXMAT_0_ENABLE
) << unit
;
2016 if (rmesa
->TexGenEnabled
& (RADEON_TEXMAT_0_ENABLE
<< unit
)) {
2017 /* Need to preconcatenate any active texgen
2018 * obj/eyeplane matrices:
2020 _math_matrix_mul_matrix( &rmesa
->tmpmat
[unit
],
2021 ctx
->TextureMatrixStack
[unit
].Top
,
2022 &rmesa
->TexGenMatrix
[unit
] );
2025 _math_matrix_copy( &rmesa
->tmpmat
[unit
],
2026 ctx
->TextureMatrixStack
[unit
].Top
);
2029 else if (rmesa
->TexGenEnabled
& (RADEON_TEXMAT_0_ENABLE
<< unit
)) {
2030 _math_matrix_copy( &rmesa
->tmpmat
[unit
], &rmesa
->TexGenMatrix
[unit
] );
2031 needMatrix
= GL_TRUE
;
2034 rmesa
->NeedTexMatrix
|= 1 << unit
;
2035 radeonUploadTexMatrix( rmesa
, unit
,
2036 !ctx
->Texture
.Unit
[unit
].TexGenEnabled
);
2041 tpc
= (texMatEnabled
| rmesa
->TexGenEnabled
);
2043 /* TCL_TEX_COMPUTED_x is TCL_TEX_INPUT_x | 0x8 */
2044 vs
&= ~((RADEON_TCL_TEX_COMPUTED_TEX_0
<< RADEON_TCL_TEX_0_OUTPUT_SHIFT
) |
2045 (RADEON_TCL_TEX_COMPUTED_TEX_0
<< RADEON_TCL_TEX_1_OUTPUT_SHIFT
) |
2046 (RADEON_TCL_TEX_COMPUTED_TEX_0
<< RADEON_TCL_TEX_2_OUTPUT_SHIFT
));
2048 vs
|= (((tpc
& RADEON_TEXGEN_TEXMAT_0_ENABLE
) <<
2049 (RADEON_TCL_TEX_0_OUTPUT_SHIFT
+ 3)) |
2050 ((tpc
& RADEON_TEXGEN_TEXMAT_1_ENABLE
) <<
2051 (RADEON_TCL_TEX_1_OUTPUT_SHIFT
+ 2)) |
2052 ((tpc
& RADEON_TEXGEN_TEXMAT_2_ENABLE
) <<
2053 (RADEON_TCL_TEX_2_OUTPUT_SHIFT
+ 1)));
2055 if (tpc
!= rmesa
->hw
.tcl
.cmd
[TCL_TEXTURE_PROC_CTL
] ||
2056 vs
!= rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
]) {
2058 RADEON_STATECHANGE(rmesa
, tcl
);
2059 rmesa
->hw
.tcl
.cmd
[TCL_TEXTURE_PROC_CTL
] = tpc
;
2060 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] = vs
;
2064 static GLboolean
r100ValidateBuffers(GLcontext
*ctx
)
2066 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
2067 struct radeon_renderbuffer
*rrb
;
2070 radeon_cs_space_reset_bos(rmesa
->radeon
.cmdbuf
.cs
);
2072 rrb
= radeon_get_colorbuffer(&rmesa
->radeon
);
2074 if (rrb
&& rrb
->bo
) {
2075 radeon_cs_space_add_persistent_bo(rmesa
->radeon
.cmdbuf
.cs
, rrb
->bo
,
2076 0, RADEON_GEM_DOMAIN_VRAM
);
2080 rrb
= radeon_get_depthbuffer(&rmesa
->radeon
);
2082 if (rrb
&& rrb
->bo
) {
2083 radeon_cs_space_add_persistent_bo(rmesa
->radeon
.cmdbuf
.cs
, rrb
->bo
,
2084 0, RADEON_GEM_DOMAIN_VRAM
);
2087 for (i
= 0; i
< ctx
->Const
.MaxTextureImageUnits
; ++i
) {
2090 if (!ctx
->Texture
.Unit
[i
]._ReallyEnabled
)
2093 t
= rmesa
->state
.texture
.unit
[i
].texobj
;
2094 if (t
->image_override
&& t
->bo
)
2095 radeon_cs_space_add_persistent_bo(rmesa
->radeon
.cmdbuf
.cs
, t
->bo
,
2096 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0);
2098 radeon_cs_space_add_persistent_bo(rmesa
->radeon
.cmdbuf
.cs
, t
->mt
->bo
,
2099 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0);
2102 ret
= radeon_cs_space_check_with_bo(rmesa
->radeon
.cmdbuf
.cs
, first_elem(&rmesa
->radeon
.dma
.reserved
)->bo
, RADEON_GEM_DOMAIN_GTT
, 0);
2108 GLboolean
radeonValidateState( GLcontext
*ctx
)
2110 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
2111 GLuint new_state
= rmesa
->radeon
.NewGLState
;
2113 if (new_state
& _NEW_BUFFERS
) {
2114 _mesa_update_framebuffer(ctx
);
2115 /* this updates the DrawBuffer's Width/Height if it's a FBO */
2116 _mesa_update_draw_buffer_bounds(ctx
);
2117 RADEON_STATECHANGE(rmesa
, ctx
);
2120 if (new_state
& _NEW_TEXTURE
) {
2121 radeonUpdateTextureState( ctx
);
2122 new_state
|= rmesa
->radeon
.NewGLState
; /* may add TEXTURE_MATRIX */
2125 /* we need to do a space check here */
2126 if (!r100ValidateBuffers(ctx
))
2129 /* Need an event driven matrix update?
2131 if (new_state
& (_NEW_MODELVIEW
|_NEW_PROJECTION
))
2132 upload_matrix( rmesa
, ctx
->_ModelProjectMatrix
.m
, MODEL_PROJ
);
2134 /* Need these for lighting (shouldn't upload otherwise)
2136 if (new_state
& (_NEW_MODELVIEW
)) {
2137 upload_matrix( rmesa
, ctx
->ModelviewMatrixStack
.Top
->m
, MODEL
);
2138 upload_matrix_t( rmesa
, ctx
->ModelviewMatrixStack
.Top
->inv
, MODEL_IT
);
2141 /* Does this need to be triggered on eg. modelview for
2142 * texgen-derived objplane/eyeplane matrices?
2144 if (new_state
& _NEW_TEXTURE_MATRIX
) {
2145 update_texturematrix( ctx
);
2148 if (new_state
& (_NEW_LIGHT
|_NEW_MODELVIEW
|_MESA_NEW_NEED_EYE_COORDS
)) {
2149 update_light( ctx
);
2152 /* emit all active clip planes if projection matrix changes.
2154 if (new_state
& (_NEW_PROJECTION
)) {
2155 if (ctx
->Transform
.ClipPlanesEnabled
)
2156 radeonUpdateClipPlanes( ctx
);
2160 rmesa
->radeon
.NewGLState
= 0;
2166 static void radeonInvalidateState( GLcontext
*ctx
, GLuint new_state
)
2168 _swrast_InvalidateState( ctx
, new_state
);
2169 _swsetup_InvalidateState( ctx
, new_state
);
2170 _vbo_InvalidateState( ctx
, new_state
);
2171 _tnl_InvalidateState( ctx
, new_state
);
2172 _ae_invalidate_state( ctx
, new_state
);
2173 R100_CONTEXT(ctx
)->radeon
.NewGLState
|= new_state
;
2177 /* A hack. Need a faster way to find this out.
2179 static GLboolean
check_material( GLcontext
*ctx
)
2181 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
2184 for (i
= _TNL_ATTRIB_MAT_FRONT_AMBIENT
;
2185 i
< _TNL_ATTRIB_MAT_BACK_INDEXES
;
2187 if (tnl
->vb
.AttribPtr
[i
] &&
2188 tnl
->vb
.AttribPtr
[i
]->stride
)
2195 static void radeonWrapRunPipeline( GLcontext
*ctx
)
2197 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
2198 GLboolean has_material
;
2201 fprintf(stderr
, "%s, newstate: %x\n", __FUNCTION__
, rmesa
->radeon
.NewGLState
);
2205 if (rmesa
->radeon
.NewGLState
)
2206 if (!radeonValidateState( ctx
))
2207 FALLBACK(rmesa
, RADEON_FALLBACK_TEXTURE
, GL_TRUE
);
2209 has_material
= (ctx
->Light
.Enabled
&& check_material( ctx
));
2212 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_MATERIAL
, GL_TRUE
);
2215 /* Run the pipeline.
2217 _tnl_run_pipeline( ctx
);
2220 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_MATERIAL
, GL_FALSE
);
2224 static void radeonPolygonStipple( GLcontext
*ctx
, const GLubyte
*mask
)
2226 r100ContextPtr r100
= R100_CONTEXT(ctx
);
2229 radeon_firevertices(&r100
->radeon
);
2231 RADEON_STATECHANGE(r100
, stp
);
2233 /* Must flip pattern upside down.
2235 for ( i
= 31 ; i
>= 0; i
--) {
2236 r100
->hw
.stp
.cmd
[3 + i
] = ((GLuint
*) mask
)[i
];
2241 /* Initialize the driver's state functions.
2242 * Many of the ctx->Driver functions might have been initialized to
2243 * software defaults in the earlier _mesa_init_driver_functions() call.
2245 void radeonInitStateFuncs( GLcontext
*ctx
, GLboolean dri2
)
2247 ctx
->Driver
.UpdateState
= radeonInvalidateState
;
2248 ctx
->Driver
.LightingSpaceChange
= radeonLightingSpaceChange
;
2250 ctx
->Driver
.DrawBuffer
= radeonDrawBuffer
;
2251 ctx
->Driver
.ReadBuffer
= radeonReadBuffer
;
2252 ctx
->Driver
.CopyPixels
= _mesa_meta_CopyPixels
;
2253 ctx
->Driver
.DrawPixels
= _mesa_meta_DrawPixels
;
2255 ctx
->Driver
.ReadPixels
= radeonReadPixels
;
2257 ctx
->Driver
.AlphaFunc
= radeonAlphaFunc
;
2258 ctx
->Driver
.BlendEquationSeparate
= radeonBlendEquationSeparate
;
2259 ctx
->Driver
.BlendFuncSeparate
= radeonBlendFuncSeparate
;
2260 ctx
->Driver
.ClearColor
= radeonClearColor
;
2261 ctx
->Driver
.ClearDepth
= radeonClearDepth
;
2262 ctx
->Driver
.ClearStencil
= radeonClearStencil
;
2263 ctx
->Driver
.ClipPlane
= radeonClipPlane
;
2264 ctx
->Driver
.ColorMask
= radeonColorMask
;
2265 ctx
->Driver
.CullFace
= radeonCullFace
;
2266 ctx
->Driver
.DepthFunc
= radeonDepthFunc
;
2267 ctx
->Driver
.DepthMask
= radeonDepthMask
;
2268 ctx
->Driver
.DepthRange
= radeonDepthRange
;
2269 ctx
->Driver
.Enable
= radeonEnable
;
2270 ctx
->Driver
.Fogfv
= radeonFogfv
;
2271 ctx
->Driver
.FrontFace
= radeonFrontFace
;
2272 ctx
->Driver
.Hint
= NULL
;
2273 ctx
->Driver
.LightModelfv
= radeonLightModelfv
;
2274 ctx
->Driver
.Lightfv
= radeonLightfv
;
2275 ctx
->Driver
.LineStipple
= radeonLineStipple
;
2276 ctx
->Driver
.LineWidth
= radeonLineWidth
;
2277 ctx
->Driver
.LogicOpcode
= radeonLogicOpCode
;
2278 ctx
->Driver
.PolygonMode
= radeonPolygonMode
;
2279 ctx
->Driver
.PolygonOffset
= radeonPolygonOffset
;
2281 ctx
->Driver
.PolygonStipple
= radeonPolygonStipple
;
2283 ctx
->Driver
.PolygonStipple
= radeonPolygonStipplePreKMS
;
2284 ctx
->Driver
.RenderMode
= radeonRenderMode
;
2285 ctx
->Driver
.Scissor
= radeonScissor
;
2286 ctx
->Driver
.ShadeModel
= radeonShadeModel
;
2287 ctx
->Driver
.StencilFuncSeparate
= radeonStencilFuncSeparate
;
2288 ctx
->Driver
.StencilMaskSeparate
= radeonStencilMaskSeparate
;
2289 ctx
->Driver
.StencilOpSeparate
= radeonStencilOpSeparate
;
2290 ctx
->Driver
.Viewport
= radeonViewport
;
2292 TNL_CONTEXT(ctx
)->Driver
.NotifyMaterialChange
= radeonUpdateMaterial
;
2293 TNL_CONTEXT(ctx
)->Driver
.RunPipeline
= radeonWrapRunPipeline
;