src/mesa/drivers/dri/radeon/radeon_state_init.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c,v 1.3 2003/02/22 06:21:11 dawes Exp $ */
   2 /*
   3  * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
   4  *
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * on the rights to use, copy, modify, merge, publish, distribute, sub
  11  * license, and/or sell copies of the Software, and to permit persons to whom
  12  * the Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  24  * OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Gareth Hughes <gareth@valinux.com>
  28  *    Keith Whitwell <keith@tungstengraphics.com>
  29  */
  30
  31 #include "glheader.h"
  32 #include "imports.h"
  33 #include "api_arrayelt.h"
  34
  35 #include "swrast/swrast.h"
  36 #include "array_cache/acache.h"
  37 #include "tnl/tnl.h"
  38 #include "tnl/t_pipeline.h"
  39 #include "swrast_setup/swrast_setup.h"
  40
  41 #include "radeon_context.h"
  42 #include "radeon_ioctl.h"
  43 #include "radeon_state.h"
  44 #include "radeon_tcl.h"
  45 #include "radeon_tex.h"
  46 #include "radeon_swtcl.h"
  47 #include "radeon_vtxfmt.h"
  48
  49 #include "xmlpool.h"
  50
  51 /* =============================================================
  52  * State initialization
  53  */
  54
  55 void radeonPrintDirty( radeonContextPtr rmesa, const char *msg )
  56 {
  57    struct radeon_state_atom *l;
  58
  59    fprintf(stderr, msg);
  60    fprintf(stderr, ": ");
  61
  62    foreach(l, &rmesa->hw.atomlist) {
  63       if (l->dirty || rmesa->hw.all_dirty)
  64          fprintf(stderr, "%s, ", l->name);
  65    }
  66
  67    fprintf(stderr, "\n");
  68 }
  69
  70 static int cmdpkt( int id )
  71 {
  72    drm_radeon_cmd_header_t h;
  73    h.i = 0;
  74    h.packet.cmd_type = RADEON_CMD_PACKET;
  75    h.packet.packet_id = id;
  76    return h.i;
  77 }
  78
  79 static int cmdvec( int offset, int stride, int count )
  80 {
  81    drm_radeon_cmd_header_t h;
  82    h.i = 0;
  83    h.vectors.cmd_type = RADEON_CMD_VECTORS;
  84    h.vectors.offset = offset;
  85    h.vectors.stride = stride;
  86    h.vectors.count = count;
  87    return h.i;
  88 }
  89
  90 static int cmdscl( int offset, int stride, int count )
  91 {
  92    drm_radeon_cmd_header_t h;
  93    h.i = 0;
  94    h.scalars.cmd_type = RADEON_CMD_SCALARS;
  95    h.scalars.offset = offset;
  96    h.scalars.stride = stride;
  97    h.scalars.count = count;
  98    return h.i;
  99 }
 100
 101 #define CHECK( NM, FLAG )                       \
 102 static GLboolean check_##NM( GLcontext *ctx )   \
 103 {                                               \
 104    return FLAG;                                 \
 105 }
 106
 107 #define TCL_CHECK( NM, FLAG )                           \
 108 static GLboolean check_##NM( GLcontext *ctx )           \
 109 {                                                       \
 110    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);        \
 111    return !rmesa->TclFallback && (FLAG);                \
 112 }
 113
 114
 115 CHECK( always, GL_TRUE )
 116 CHECK( never, GL_FALSE )
 117 CHECK( tex0, ctx->Texture.Unit[0]._ReallyEnabled )
 118 CHECK( tex1, ctx->Texture.Unit[1]._ReallyEnabled )
 119 /* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */
 120 CHECK( tex2, ctx->Texture._EnabledUnits )
 121 CHECK( cube0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_CUBE_BIT))
 122 CHECK( cube1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_CUBE_BIT))
 123 CHECK( cube2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_CUBE_BIT))
 124 CHECK( fog, ctx->Fog.Enabled )
 125 TCL_CHECK( tcl, GL_TRUE )
 126 TCL_CHECK( tcl_tex0, ctx->Texture.Unit[0]._ReallyEnabled )
 127 TCL_CHECK( tcl_tex1, ctx->Texture.Unit[1]._ReallyEnabled )
 128 TCL_CHECK( tcl_tex2, ctx->Texture.Unit[2]._ReallyEnabled )
 129 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
 130 TCL_CHECK( tcl_eyespace_or_lighting, ctx->_NeedEyeCoords || ctx->Light.Enabled )
 131 TCL_CHECK( tcl_lit0, ctx->Light.Enabled && ctx->Light.Light[0].Enabled )
 132 TCL_CHECK( tcl_lit1, ctx->Light.Enabled && ctx->Light.Light[1].Enabled )
 133 TCL_CHECK( tcl_lit2, ctx->Light.Enabled && ctx->Light.Light[2].Enabled )
 134 TCL_CHECK( tcl_lit3, ctx->Light.Enabled && ctx->Light.Light[3].Enabled )
 135 TCL_CHECK( tcl_lit4, ctx->Light.Enabled && ctx->Light.Light[4].Enabled )
 136 TCL_CHECK( tcl_lit5, ctx->Light.Enabled && ctx->Light.Light[5].Enabled )
 137 TCL_CHECK( tcl_lit6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled )
 138 TCL_CHECK( tcl_lit7, ctx->Light.Enabled && ctx->Light.Light[7].Enabled )
 139 TCL_CHECK( tcl_ucp0, (ctx->Transform.ClipPlanesEnabled & 0x1) )
 140 TCL_CHECK( tcl_ucp1, (ctx->Transform.ClipPlanesEnabled & 0x2) )
 141 TCL_CHECK( tcl_ucp2, (ctx->Transform.ClipPlanesEnabled & 0x4) )
 142 TCL_CHECK( tcl_ucp3, (ctx->Transform.ClipPlanesEnabled & 0x8) )
 143 TCL_CHECK( tcl_ucp4, (ctx->Transform.ClipPlanesEnabled & 0x10) )
 144 TCL_CHECK( tcl_ucp5, (ctx->Transform.ClipPlanesEnabled & 0x20) )
 145 TCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || ctx->Fog.Enabled )
 146
 147 CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT))
 148 CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT))
 149 CHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT))
 150
 151
 152
 153 /* Initialize the context's hardware state.
 154  */
 155 void radeonInitState( radeonContextPtr rmesa )
 156 {
 157    GLcontext *ctx = rmesa->glCtx;
 158    GLuint color_fmt, depth_fmt, i;
 159    GLint drawPitch, drawOffset;
 160
 161    switch ( rmesa->radeonScreen->cpp ) {
 162    case 2:
 163       color_fmt = RADEON_COLOR_FORMAT_RGB565;
 164       break;
 165    case 4:
 166       color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
 167       break;
 168    default:
 169       fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" );
 170       exit( -1 );
 171    }
 172
 173    rmesa->state.color.clear = 0x00000000;
 174
 175    switch ( ctx->Visual.depthBits ) {
 176    case 16:
 177       rmesa->state.depth.clear = 0x0000ffff;
 178       rmesa->state.depth.scale = 1.0 / (GLfloat)0xffff;
 179       depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
 180       rmesa->state.stencil.clear = 0x00000000;
 181       break;
 182    case 24:
 183       rmesa->state.depth.clear = 0x00ffffff;
 184       rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff;
 185       depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
 186       rmesa->state.stencil.clear = 0xffff0000;
 187       break;
 188    default:
 189       fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
 190                ctx->Visual.depthBits );
 191       exit( -1 );
 192    }
 193
 194    /* Only have hw stencil when depth buffer is 24 bits deep */
 195    rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
 196                                      ctx->Visual.depthBits == 24 );
 197
 198    rmesa->Fallback = 0;
 199
 200    if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) {
 201       drawOffset = rmesa->radeonScreen->backOffset;
 202       drawPitch  = rmesa->radeonScreen->backPitch;
 203    } else {
 204       drawOffset = rmesa->radeonScreen->frontOffset;
 205       drawPitch  = rmesa->radeonScreen->frontPitch;
 206    }
 207
 208    rmesa->hw.max_state_size = 0;
 209
 210 #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG )                          \
 211    do {                                                         \
 212       rmesa->hw.ATOM.cmd_size = SZ;                             \
 213       rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int));     \
 214       rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \
 215       rmesa->hw.ATOM.name = NM;                                 \
 216       rmesa->hw.ATOM.is_tcl = FLAG;                                     \
 217       rmesa->hw.ATOM.check = check_##CHK;                               \
 218       rmesa->hw.ATOM.dirty = GL_TRUE;                           \
 219       rmesa->hw.max_state_size += SZ * sizeof(int);             \
 220    } while (0)
 221
 222
 223    /* Allocate state buffers:
 224     */
 225    ALLOC_STATE( ctx, always, CTX_STATE_SIZE, "CTX/context", 0 );
 226    ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
 227    ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
 228    ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
 229    ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
 230    ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
 231    ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
 232    ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 );
 233    ALLOC_STATE( mtl, tcl_lighting, MTL_STATE_SIZE, "MTL/material", 1 );
 234    ALLOC_STATE( grd, always, GRD_STATE_SIZE, "GRD/guard-band", 1 );
 235    ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 );
 236    ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 );
 237    ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 );
 238    ALLOC_STATE( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0 );
 239    ALLOC_STATE( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0 );
 240    ALLOC_STATE( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0 );
 241    if (rmesa->radeonScreen->drmSupportsCubeMapsR100)
 242    {
 243       ALLOC_STATE( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0 );
 244       ALLOC_STATE( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/cube-1", 0 );
 245       ALLOC_STATE( cube[2], cube2, CUBE_STATE_SIZE, "CUBE/cube-2", 0 );
 246    }
 247    else
 248    {
 249       ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/cube-0", 0 );
 250       ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/cube-1", 0 );
 251       ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/cube-2", 0 );
 252    }
 253    ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 );
 254    ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 );
 255    ALLOC_STATE( mat[2], tcl_eyespace_or_lighting, MAT_STATE_SIZE, "MAT/it-modelview", 1 );
 256    ALLOC_STATE( mat[3], tcl_tex0, MAT_STATE_SIZE, "MAT/texmat0", 1 );
 257    ALLOC_STATE( mat[4], tcl_tex1, MAT_STATE_SIZE, "MAT/texmat1", 1 );
 258    ALLOC_STATE( mat[5], tcl_tex2, MAT_STATE_SIZE, "MAT/texmat2", 1 );
 259    ALLOC_STATE( ucp[0], tcl_ucp0, UCP_STATE_SIZE, "UCP/userclip-0", 1 );
 260    ALLOC_STATE( ucp[1], tcl_ucp1, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
 261    ALLOC_STATE( ucp[2], tcl_ucp2, UCP_STATE_SIZE, "UCP/userclip-2", 1 );
 262    ALLOC_STATE( ucp[3], tcl_ucp3, UCP_STATE_SIZE, "UCP/userclip-3", 1 );
 263    ALLOC_STATE( ucp[4], tcl_ucp4, UCP_STATE_SIZE, "UCP/userclip-4", 1 );
 264    ALLOC_STATE( ucp[5], tcl_ucp5, UCP_STATE_SIZE, "UCP/userclip-5", 1 );
 265    ALLOC_STATE( lit[0], tcl_lit0, LIT_STATE_SIZE, "LIT/light-0", 1 );
 266    ALLOC_STATE( lit[1], tcl_lit1, LIT_STATE_SIZE, "LIT/light-1", 1 );
 267    ALLOC_STATE( lit[2], tcl_lit2, LIT_STATE_SIZE, "LIT/light-2", 1 );
 268    ALLOC_STATE( lit[3], tcl_lit3, LIT_STATE_SIZE, "LIT/light-3", 1 );
 269    ALLOC_STATE( lit[4], tcl_lit4, LIT_STATE_SIZE, "LIT/light-4", 1 );
 270    ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 );
 271    ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 );
 272    ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 );
 273    ALLOC_STATE( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0 );
 274    ALLOC_STATE( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0 );
 275    ALLOC_STATE( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0 );
 276
 277    radeonSetUpAtomList( rmesa );
 278
 279    /* Fill in the packet headers:
 280     */
 281    rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(RADEON_EMIT_PP_MISC);
 282    rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(RADEON_EMIT_PP_CNTL);
 283    rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH);
 284    rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN);
 285    rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH);
 286    rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK);
 287    rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE);
 288    rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(RADEON_EMIT_SE_CNTL);
 289    rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(RADEON_EMIT_SE_CNTL_STATUS);
 290    rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(RADEON_EMIT_RE_MISC);
 291    rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_0);
 292    rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_0);
 293    rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_1);
 294    rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_1);
 295    rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_2);
 296    rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_2);
 297    rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(RADEON_EMIT_PP_CUBIC_FACES_0);
 298    rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(RADEON_EMIT_PP_CUBIC_OFFSETS_T0);
 299    rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(RADEON_EMIT_PP_CUBIC_FACES_1);
 300    rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(RADEON_EMIT_PP_CUBIC_OFFSETS_T1);
 301    rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(RADEON_EMIT_PP_CUBIC_FACES_2);
 302    rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(RADEON_EMIT_PP_CUBIC_OFFSETS_T2);
 303    rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR);
 304    rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
 305    rmesa->hw.mtl.cmd[MTL_CMD_0] =
 306       cmdpkt(RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED);
 307    rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_0);
 308    rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_1);
 309    rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_2);
 310    rmesa->hw.grd.cmd[GRD_CMD_0] =
 311       cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
 312    rmesa->hw.fog.cmd[FOG_CMD_0] =
 313       cmdvec( RADEON_VS_FOG_PARAM_ADDR, 1, 4 );
 314    rmesa->hw.glt.cmd[GLT_CMD_0] =
 315       cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
 316    rmesa->hw.eye.cmd[EYE_CMD_0] =
 317       cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 );
 318
 319    for (i = 0 ; i < 6; i++) {
 320       rmesa->hw.mat[i].cmd[MAT_CMD_0] =
 321          cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16);
 322    }
 323
 324    for (i = 0 ; i < 8; i++) {
 325       rmesa->hw.lit[i].cmd[LIT_CMD_0] =
 326          cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
 327       rmesa->hw.lit[i].cmd[LIT_CMD_1] =
 328          cmdscl( RADEON_SS_LIGHT_DCD_ADDR + i, 8, 6 );
 329    }
 330
 331    for (i = 0 ; i < 6; i++) {
 332       rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
 333          cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 );
 334    }
 335
 336    rmesa->last_ReallyEnabled = -1;
 337
 338    /* Initial Harware state:
 339     */
 340    rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS |
 341                                      RADEON_CHROMA_FUNC_FAIL |
 342                                      RADEON_CHROMA_KEY_NEAREST |
 343                                      RADEON_SHADOW_FUNC_EQUAL |
 344                                      RADEON_SHADOW_PASS_1 /*|
 345                                      RADEON_RIGHT_HAND_CUBE_OGL */);
 346
 347    rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX |
 348                                           /* this bit unused for vertex fog */
 349                                           RADEON_FOG_USE_DEPTH);
 350
 351    rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
 352
 353    rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP |
 354                                             RADEON_SRC_BLEND_GL_ONE |
 355                                             RADEON_DST_BLEND_GL_ZERO );
 356
 357    rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
 358       rmesa->radeonScreen->depthOffset + rmesa->radeonScreen->fbLocation;
 359
 360    rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
 361       ((rmesa->radeonScreen->depthPitch &
 362         RADEON_DEPTHPITCH_MASK) |
 363        RADEON_DEPTH_ENDIAN_NO_SWAP);
 364
 365    if (rmesa->using_hyperz)
 366        rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= RADEON_DEPTH_HYPERZ;
 367
 368    rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
 369                                                RADEON_Z_TEST_LESS |
 370                                                RADEON_STENCIL_TEST_ALWAYS |
 371                                                RADEON_STENCIL_FAIL_KEEP |
 372                                                RADEON_STENCIL_ZPASS_KEEP |
 373                                                RADEON_STENCIL_ZFAIL_KEEP |
 374                                                RADEON_Z_WRITE_ENABLE);
 375
 376    if (rmesa->using_hyperz) {
 377        rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
 378                                                    RADEON_Z_DECOMPRESSION_ENABLE;
 379       if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 380          /* works for q3, but slight rendering errors with glxgears ? */
 381 /*       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
 382          /* need this otherwise get lots of lockups with q3 ??? */
 383          rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY;
 384       }
 385    }
 386
 387    rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
 388                                      RADEON_ANTI_ALIAS_NONE);
 389
 390    rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
 391                                        color_fmt |
 392                                        RADEON_ZBLOCK16);
 393
 394    switch ( driQueryOptioni( &rmesa->optionCache, "dither_mode" ) ) {
 395    case DRI_CONF_DITHER_XERRORDIFFRESET:
 396       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
 397       break;
 398    case DRI_CONF_DITHER_ORDERED:
 399       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
 400       break;
 401    }
 402    if ( driQueryOptioni( &rmesa->optionCache, "round_mode" ) ==
 403         DRI_CONF_ROUND_ROUND )
 404       rmesa->state.color.roundEnable = RADEON_ROUND_ENABLE;
 405    else
 406       rmesa->state.color.roundEnable = 0;
 407    if ( driQueryOptioni (&rmesa->optionCache, "color_reduction" ) ==
 408         DRI_CONF_COLOR_REDUCTION_DITHER )
 409       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
 410    else
 411       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable;
 412
 413    rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset +
 414                                                rmesa->radeonScreen->fbLocation)
 415                                               & RADEON_COLOROFFSET_MASK);
 416
 417    rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch &
 418                                               RADEON_COLORPITCH_MASK) |
 419                                              RADEON_COLOR_ENDIAN_NO_SWAP);
 420
 421
 422    /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
 423    if (rmesa->sarea->tiling_enabled) {
 424       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
 425    }
 426
 427    rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW |
 428                                      RADEON_BFACE_SOLID |
 429                                      RADEON_FFACE_SOLID |
 430 /*                           RADEON_BADVTX_CULL_DISABLE | */
 431                                      RADEON_FLAT_SHADE_VTX_LAST |
 432                                      RADEON_DIFFUSE_SHADE_GOURAUD |
 433                                      RADEON_ALPHA_SHADE_GOURAUD |
 434                                      RADEON_SPECULAR_SHADE_GOURAUD |
 435                                      RADEON_FOG_SHADE_GOURAUD |
 436                                      RADEON_VPORT_XY_XFORM_ENABLE |
 437                                      RADEON_VPORT_Z_XFORM_ENABLE |
 438                                      RADEON_VTX_PIX_CENTER_OGL |
 439                                      RADEON_ROUND_MODE_TRUNC |
 440                                      RADEON_ROUND_PREC_8TH_PIX);
 441
 442    rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] =
 443 #ifdef MESA_BIG_ENDIAN
 444                                             RADEON_VC_32BIT_SWAP;
 445 #else
 446                                             RADEON_VC_NO_SWAP;
 447 #endif
 448
 449    if (!(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
 450      rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS;
 451    }
 452
 453    rmesa->hw.set.cmd[SET_SE_COORDFMT] = (
 454       RADEON_VTX_W0_IS_NOT_1_OVER_W0 |
 455       RADEON_TEX1_W_ROUTING_USE_Q1);
 456
 457
 458    rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
 459
 460    rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
 461       ((0 << RADEON_LINE_CURRENT_PTR_SHIFT) |
 462        (1 << RADEON_LINE_CURRENT_COUNT_SHIFT));
 463
 464    rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
 465
 466    rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
 467       ((0x00 << RADEON_STENCIL_REF_SHIFT) |
 468        (0xff << RADEON_STENCIL_MASK_SHIFT) |
 469        (0xff << RADEON_STENCIL_WRITEMASK_SHIFT));
 470
 471    rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY;
 472    rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
 473
 474    rmesa->hw.msc.cmd[MSC_RE_MISC] =
 475       ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT) |
 476        (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT) |
 477        RADEON_STIPPLE_BIG_BIT_ORDER);
 478
 479    rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE]  = 0x00000000;
 480    rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
 481    rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE]  = 0x00000000;
 482    rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
 483    rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE]  = 0x00000000;
 484    rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
 485
 486    for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
 487       rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL;
 488       rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
 489           (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
 490            RADEON_TXFORMAT_PERSPECTIVE_ENABLE |
 491            (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */
 492            (2 << RADEON_TXFORMAT_WIDTH_SHIFT) |
 493            (2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
 494
 495       /* Initialize the texture offset to the start of the card texture heap */
 496       rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
 497           rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
 498
 499       rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
 500       rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =
 501           (RADEON_COLOR_ARG_A_ZERO |
 502            RADEON_COLOR_ARG_B_ZERO |
 503            RADEON_COLOR_ARG_C_CURRENT_COLOR |
 504            RADEON_BLEND_CTL_ADD |
 505            RADEON_SCALE_1X |
 506            RADEON_CLAMP_TX);
 507       rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] =
 508           (RADEON_ALPHA_ARG_A_ZERO |
 509            RADEON_ALPHA_ARG_B_ZERO |
 510            RADEON_ALPHA_ARG_C_CURRENT_ALPHA |
 511            RADEON_BLEND_CTL_ADD |
 512            RADEON_SCALE_1X |
 513            RADEON_CLAMP_TX);
 514       rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0;
 515
 516       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
 517       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] =
 518           rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
 519       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_1] =
 520           rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
 521       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_2] =
 522           rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
 523       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_3] =
 524           rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
 525       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_4] =
 526           rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
 527    }
 528
 529    /* Can only add ST1 at the time of doing some multitex but can keep
 530     * it after that.  Errors if DIFFUSE is missing.
 531     */
 532    rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] =
 533       (RADEON_TCL_VTX_Z0 |
 534        RADEON_TCL_VTX_W0 |
 535        RADEON_TCL_VTX_PK_DIFFUSE
 536          );     /* need to keep this uptodate */
 537
 538    rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] =
 539       ( RADEON_TCL_COMPUTE_XYZW         |
 540         (RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) |
 541         (RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) |
 542         (RADEON_TCL_TEX_INPUT_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT));
 543
 544
 545    /* XXX */
 546    rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] =
 547       ((MODEL << RADEON_MODELVIEW_0_SHIFT) |
 548        (MODEL_IT << RADEON_IT_MODELVIEW_0_SHIFT));
 549
 550    rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] =
 551       ((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) |
 552        (TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) |
 553        (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT) |
 554        (TEXMAT_2 << RADEON_TEXMAT_2_SHIFT));
 555
 556    rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
 557       (RADEON_UCP_IN_CLIP_SPACE |
 558        RADEON_CULL_FRONT_IS_CCW);
 559
 560    rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0;
 561
 562    rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] =
 563       (RADEON_SPECULAR_LIGHTS |
 564        RADEON_DIFFUSE_SPECULAR_COMBINE |
 565        RADEON_LOCAL_LIGHT_VEC_GL |
 566        (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) |
 567        (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) |
 568        (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
 569        (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT));
 570
 571    for (i = 0 ; i < 8; i++) {
 572       struct gl_light *l = &ctx->Light.Light[i];
 573       GLenum p = GL_LIGHT0 + i;
 574       *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
 575
 576       ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
 577       ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
 578       ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
 579       ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
 580       ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
 581       ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
 582       ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
 583       ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
 584                            &l->ConstantAttenuation );
 585       ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
 586                            &l->LinearAttenuation );
 587       ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
 588                      &l->QuadraticAttenuation );
 589       *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
 590    }
 591
 592    ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
 593                              ctx->Light.Model.Ambient );
 594
 595    TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
 596
 597    for (i = 0 ; i < 6; i++) {
 598       ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
 599    }
 600
 601    ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
 602    ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
 603    ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
 604    ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
 605    ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
 606    ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
 607
 608    rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
 609    rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
 610    rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
 611    rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
 612
 613    rmesa->hw.eye.cmd[EYE_X] = 0;
 614    rmesa->hw.eye.cmd[EYE_Y] = 0;
 615    rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
 616    rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
 617
 618    rmesa->hw.all_dirty = GL_TRUE;
 619 }