src/mesa/drivers/dri/radeon/radeon_state_init.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c,v 1.3 2003/02/22 06:21:11 dawes Exp $ */
   2 /*
   3  * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
   4  *
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * on the rights to use, copy, modify, merge, publish, distribute, sub
  11  * license, and/or sell copies of the Software, and to permit persons to whom
  12  * the Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  24  * OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Gareth Hughes <gareth@valinux.com>
  28  *    Keith Whitwell <keith@tungstengraphics.com>
  29  */
  30
  31 #include "glheader.h"
  32 #include "imports.h"
  33 #include "api_arrayelt.h"
  34
  35 #include "swrast/swrast.h"
  36 #include "array_cache/acache.h"
  37 #include "tnl/tnl.h"
  38 #include "tnl/t_pipeline.h"
  39 #include "swrast_setup/swrast_setup.h"
  40
  41 #include "radeon_context.h"
  42 #include "radeon_ioctl.h"
  43 #include "radeon_state.h"
  44 #include "radeon_tcl.h"
  45 #include "radeon_tex.h"
  46 #include "radeon_swtcl.h"
  47 #include "radeon_vtxfmt.h"
  48
  49 #include "xmlpool.h"
  50
  51 /* =============================================================
  52  * State initialization
  53  */
  54
  55 void radeonPrintDirty( radeonContextPtr rmesa, const char *msg )
  56 {
  57    struct radeon_state_atom *l;
  58
  59    fprintf(stderr, msg);
  60    fprintf(stderr, ": ");
  61
  62    foreach(l, &(rmesa->hw.dirty)) {
  63       fprintf(stderr, "%s, ", l->name);
  64    }
  65
  66    fprintf(stderr, "\n");
  67 }
  68
  69 static int cmdpkt( int id )
  70 {
  71    drm_radeon_cmd_header_t h;
  72    h.i = 0;
  73    h.packet.cmd_type = RADEON_CMD_PACKET;
  74    h.packet.packet_id = id;
  75    return h.i;
  76 }
  77
  78 static int cmdvec( int offset, int stride, int count )
  79 {
  80    drm_radeon_cmd_header_t h;
  81    h.i = 0;
  82    h.vectors.cmd_type = RADEON_CMD_VECTORS;
  83    h.vectors.offset = offset;
  84    h.vectors.stride = stride;
  85    h.vectors.count = count;
  86    return h.i;
  87 }
  88
  89 static int cmdscl( int offset, int stride, int count )
  90 {
  91    drm_radeon_cmd_header_t h;
  92    h.i = 0;
  93    h.scalars.cmd_type = RADEON_CMD_SCALARS;
  94    h.scalars.offset = offset;
  95    h.scalars.stride = stride;
  96    h.scalars.count = count;
  97    return h.i;
  98 }
  99
 100 #define CHECK( NM, FLAG )                       \
 101 static GLboolean check_##NM( GLcontext *ctx )   \
 102 {                                               \
 103    return FLAG;                                 \
 104 }
 105
 106 #define TCL_CHECK( NM, FLAG )                           \
 107 static GLboolean check_##NM( GLcontext *ctx )           \
 108 {                                                       \
 109    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);        \
 110    return !rmesa->TclFallback && (FLAG);                \
 111 }
 112
 113
 114 CHECK( always, GL_TRUE )
 115 CHECK( tex0, ctx->Texture.Unit[0]._ReallyEnabled )
 116 CHECK( tex1, ctx->Texture.Unit[1]._ReallyEnabled )
 117 CHECK( fog, ctx->Fog.Enabled )
 118 TCL_CHECK( tcl, GL_TRUE )
 119 TCL_CHECK( tcl_tex0, ctx->Texture.Unit[0]._ReallyEnabled )
 120 TCL_CHECK( tcl_tex1, ctx->Texture.Unit[1]._ReallyEnabled )
 121 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
 122 TCL_CHECK( tcl_eyespace_or_lighting, ctx->_NeedEyeCoords || ctx->Light.Enabled )
 123 TCL_CHECK( tcl_lit0, ctx->Light.Enabled && ctx->Light.Light[0].Enabled )
 124 TCL_CHECK( tcl_lit1, ctx->Light.Enabled && ctx->Light.Light[1].Enabled )
 125 TCL_CHECK( tcl_lit2, ctx->Light.Enabled && ctx->Light.Light[2].Enabled )
 126 TCL_CHECK( tcl_lit3, ctx->Light.Enabled && ctx->Light.Light[3].Enabled )
 127 TCL_CHECK( tcl_lit4, ctx->Light.Enabled && ctx->Light.Light[4].Enabled )
 128 TCL_CHECK( tcl_lit5, ctx->Light.Enabled && ctx->Light.Light[5].Enabled )
 129 TCL_CHECK( tcl_lit6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled )
 130 TCL_CHECK( tcl_lit7, ctx->Light.Enabled && ctx->Light.Light[7].Enabled )
 131 TCL_CHECK( tcl_ucp0, (ctx->Transform.ClipPlanesEnabled & 0x1) )
 132 TCL_CHECK( tcl_ucp1, (ctx->Transform.ClipPlanesEnabled & 0x2) )
 133 TCL_CHECK( tcl_ucp2, (ctx->Transform.ClipPlanesEnabled & 0x4) )
 134 TCL_CHECK( tcl_ucp3, (ctx->Transform.ClipPlanesEnabled & 0x8) )
 135 TCL_CHECK( tcl_ucp4, (ctx->Transform.ClipPlanesEnabled & 0x10) )
 136 TCL_CHECK( tcl_ucp5, (ctx->Transform.ClipPlanesEnabled & 0x20) )
 137 TCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || ctx->Fog.Enabled )
 138
 139 CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT))
 140 CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT))
 141
 142
 143
 144 /* Initialize the context's hardware state.
 145  */
 146 void radeonInitState( radeonContextPtr rmesa )
 147 {
 148    GLcontext *ctx = rmesa->glCtx;
 149    GLuint color_fmt, depth_fmt, i;
 150
 151    switch ( rmesa->radeonScreen->cpp ) {
 152    case 2:
 153       color_fmt = RADEON_COLOR_FORMAT_RGB565;
 154       break;
 155    case 4:
 156       color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
 157       break;
 158    default:
 159       fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" );
 160       exit( -1 );
 161    }
 162
 163    rmesa->state.color.clear = 0x00000000;
 164
 165    switch ( ctx->Visual.depthBits ) {
 166    case 16:
 167       rmesa->state.depth.clear = 0x0000ffff;
 168       rmesa->state.depth.scale = 1.0 / (GLfloat)0xffff;
 169       depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
 170       rmesa->state.stencil.clear = 0x00000000;
 171       break;
 172    case 24:
 173       rmesa->state.depth.clear = 0x00ffffff;
 174       rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff;
 175       depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
 176       rmesa->state.stencil.clear = 0xff000000;
 177       break;
 178    default:
 179       fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
 180                ctx->Visual.depthBits );
 181       exit( -1 );
 182    }
 183
 184    /* Only have hw stencil when depth buffer is 24 bits deep */
 185    rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
 186                                      ctx->Visual.depthBits == 24 );
 187
 188    rmesa->Fallback = 0;
 189
 190    if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) {
 191       rmesa->state.color.drawOffset = rmesa->radeonScreen->backOffset;
 192       rmesa->state.color.drawPitch  = rmesa->radeonScreen->backPitch;
 193    } else {
 194       rmesa->state.color.drawOffset = rmesa->radeonScreen->frontOffset;
 195       rmesa->state.color.drawPitch  = rmesa->radeonScreen->frontPitch;
 196    }
 197    rmesa->state.pixel.readOffset = rmesa->state.color.drawOffset;
 198    rmesa->state.pixel.readPitch  = rmesa->state.color.drawPitch;
 199
 200    /* Initialize lists:
 201     */
 202    make_empty_list(&(rmesa->hw.dirty));
 203    make_empty_list(&(rmesa->hw.clean));
 204
 205    rmesa->hw.max_state_size = 0;
 206
 207 #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG )                          \
 208    do {                                                         \
 209       rmesa->hw.ATOM.cmd_size = SZ;                             \
 210       rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int));     \
 211       rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \
 212       rmesa->hw.ATOM.name = NM;                                 \
 213       rmesa->hw.ATOM.is_tcl = FLAG;                                     \
 214       rmesa->hw.ATOM.check = check_##CHK;                               \
 215       insert_at_head(&(rmesa->hw.dirty), &(rmesa->hw.ATOM));    \
 216       rmesa->hw.max_state_size += SZ * sizeof(int);             \
 217    } while (0)
 218
 219
 220    /* Allocate state buffers:
 221     */
 222    ALLOC_STATE( ctx, always, CTX_STATE_SIZE, "CTX/context", 0 );
 223    ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
 224    ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
 225    ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
 226    ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
 227    ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
 228    ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
 229    ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 );
 230    ALLOC_STATE( mtl, tcl_lighting, MTL_STATE_SIZE, "MTL/material", 1 );
 231    ALLOC_STATE( grd, always, GRD_STATE_SIZE, "GRD/guard-band", 1 );
 232    ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 );
 233    ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 );
 234    ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 );
 235    ALLOC_STATE( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0 );
 236    ALLOC_STATE( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0 );
 237    ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 );
 238    ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 );
 239    ALLOC_STATE( mat[2], tcl_eyespace_or_lighting, MAT_STATE_SIZE, "MAT/it-modelview", 1 );
 240    ALLOC_STATE( mat[3], tcl_tex0, MAT_STATE_SIZE, "MAT/texmat0", 1 );
 241    ALLOC_STATE( mat[4], tcl_tex1, MAT_STATE_SIZE, "MAT/texmat1", 1 );
 242    ALLOC_STATE( ucp[0], tcl_ucp0, UCP_STATE_SIZE, "UCP/userclip-0", 1 );
 243    ALLOC_STATE( ucp[1], tcl_ucp1, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
 244    ALLOC_STATE( ucp[2], tcl_ucp2, UCP_STATE_SIZE, "UCP/userclip-2", 1 );
 245    ALLOC_STATE( ucp[3], tcl_ucp3, UCP_STATE_SIZE, "UCP/userclip-3", 1 );
 246    ALLOC_STATE( ucp[4], tcl_ucp4, UCP_STATE_SIZE, "UCP/userclip-4", 1 );
 247    ALLOC_STATE( ucp[5], tcl_ucp5, UCP_STATE_SIZE, "UCP/userclip-5", 1 );
 248    ALLOC_STATE( lit[0], tcl_lit0, LIT_STATE_SIZE, "LIT/light-0", 1 );
 249    ALLOC_STATE( lit[1], tcl_lit1, LIT_STATE_SIZE, "LIT/light-1", 1 );
 250    ALLOC_STATE( lit[2], tcl_lit2, LIT_STATE_SIZE, "LIT/light-2", 1 );
 251    ALLOC_STATE( lit[3], tcl_lit3, LIT_STATE_SIZE, "LIT/light-3", 1 );
 252    ALLOC_STATE( lit[4], tcl_lit4, LIT_STATE_SIZE, "LIT/light-4", 1 );
 253    ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 );
 254    ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 );
 255    ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 );
 256    ALLOC_STATE( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0 );
 257    ALLOC_STATE( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0 );
 258
 259
 260    /* Fill in the packet headers:
 261     */
 262    rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(RADEON_EMIT_PP_MISC);
 263    rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(RADEON_EMIT_PP_CNTL);
 264    rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH);
 265    rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN);
 266    rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH);
 267    rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK);
 268    rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE);
 269    rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(RADEON_EMIT_SE_CNTL);
 270    rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(RADEON_EMIT_SE_CNTL_STATUS);
 271    rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(RADEON_EMIT_RE_MISC);
 272    rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_0);
 273    rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_0);
 274    rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_1);
 275    rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_1);
 276    rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR);
 277    rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
 278    rmesa->hw.mtl.cmd[MTL_CMD_0] =
 279       cmdpkt(RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED);
 280    rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_0);
 281    rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_1);
 282    rmesa->hw.grd.cmd[GRD_CMD_0] =
 283       cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
 284    rmesa->hw.fog.cmd[FOG_CMD_0] =
 285       cmdvec( RADEON_VS_FOG_PARAM_ADDR, 1, 4 );
 286    rmesa->hw.glt.cmd[GLT_CMD_0] =
 287       cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
 288    rmesa->hw.eye.cmd[EYE_CMD_0] =
 289       cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 );
 290
 291    for (i = 0 ; i < 5; i++) {
 292       rmesa->hw.mat[i].cmd[MAT_CMD_0] =
 293          cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16);
 294    }
 295
 296    for (i = 0 ; i < 8; i++) {
 297       rmesa->hw.lit[i].cmd[LIT_CMD_0] =
 298          cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
 299       rmesa->hw.lit[i].cmd[LIT_CMD_1] =
 300          cmdscl( RADEON_SS_LIGHT_DCD_ADDR + i, 8, 6 );
 301    }
 302
 303    for (i = 0 ; i < 6; i++) {
 304       rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
 305          cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 );
 306    }
 307
 308    rmesa->last_ReallyEnabled = -1;
 309
 310    /* Initial Harware state:
 311     */
 312    rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS |
 313                                      RADEON_CHROMA_FUNC_FAIL |
 314                                      RADEON_CHROMA_KEY_NEAREST |
 315                                      RADEON_SHADOW_FUNC_EQUAL |
 316                                      RADEON_SHADOW_PASS_1 |
 317                                      RADEON_RIGHT_HAND_CUBE_OGL);
 318
 319    rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX |
 320                                           RADEON_FOG_USE_DEPTH);
 321
 322    rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
 323
 324    rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP |
 325                                             RADEON_SRC_BLEND_GL_ONE |
 326                                             RADEON_DST_BLEND_GL_ZERO );
 327
 328    rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
 329       rmesa->radeonScreen->depthOffset + rmesa->radeonScreen->fbLocation;
 330
 331    rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
 332       ((rmesa->radeonScreen->depthPitch &
 333         RADEON_DEPTHPITCH_MASK) |
 334        RADEON_DEPTH_ENDIAN_NO_SWAP);
 335
 336    rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
 337                                                RADEON_Z_TEST_LESS |
 338                                                RADEON_STENCIL_TEST_ALWAYS |
 339                                                RADEON_STENCIL_FAIL_KEEP |
 340                                                RADEON_STENCIL_ZPASS_KEEP |
 341                                                RADEON_STENCIL_ZFAIL_KEEP |
 342                                                RADEON_Z_WRITE_ENABLE);
 343
 344    rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
 345                                      RADEON_ANTI_ALIAS_NONE);
 346
 347    rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
 348                                        color_fmt |
 349                                        (1<<15));
 350
 351    switch ( driQueryOptioni( &rmesa->optionCache, "dither_mode" ) ) {
 352    case DRI_CONF_DITHER_XERRORDIFFRESET:
 353       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
 354       break;
 355    case DRI_CONF_DITHER_ORDERED:
 356       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
 357       break;
 358    }
 359    if ( driQueryOptioni( &rmesa->optionCache, "round_mode" ) ==
 360         DRI_CONF_ROUND_ROUND )
 361       rmesa->state.color.roundEnable = RADEON_ROUND_ENABLE;
 362    else
 363       rmesa->state.color.roundEnable = 0;
 364    if ( driQueryOptioni (&rmesa->optionCache, "color_reduction" ) ==
 365         DRI_CONF_COLOR_REDUCTION_DITHER )
 366       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
 367    else
 368       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable;
 369
 370    rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset +
 371                                                rmesa->radeonScreen->fbLocation)
 372                                               & RADEON_COLOROFFSET_MASK);
 373
 374    rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch &
 375                                               RADEON_COLORPITCH_MASK) |
 376                                              RADEON_COLOR_ENDIAN_NO_SWAP);
 377
 378    rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW |
 379                                      RADEON_BFACE_SOLID |
 380                                      RADEON_FFACE_SOLID |
 381 /*                           RADEON_BADVTX_CULL_DISABLE | */
 382                                      RADEON_FLAT_SHADE_VTX_LAST |
 383                                      RADEON_DIFFUSE_SHADE_GOURAUD |
 384                                      RADEON_ALPHA_SHADE_GOURAUD |
 385                                      RADEON_SPECULAR_SHADE_GOURAUD |
 386                                      RADEON_FOG_SHADE_GOURAUD |
 387                                      RADEON_VPORT_XY_XFORM_ENABLE |
 388                                      RADEON_VPORT_Z_XFORM_ENABLE |
 389                                      RADEON_VTX_PIX_CENTER_OGL |
 390                                      RADEON_ROUND_MODE_TRUNC |
 391                                      RADEON_ROUND_PREC_8TH_PIX);
 392
 393    rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] =
 394 #ifdef MESA_BIG_ENDIAN
 395                                             RADEON_VC_32BIT_SWAP;
 396 #else
 397                                             RADEON_VC_NO_SWAP;
 398 #endif
 399
 400    if (!(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)) {
 401      rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS;
 402    }
 403
 404    rmesa->hw.set.cmd[SET_SE_COORDFMT] = (
 405       RADEON_VTX_W0_IS_NOT_1_OVER_W0 |
 406       RADEON_TEX1_W_ROUTING_USE_Q1);
 407
 408
 409    rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
 410
 411    rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
 412       ((0 << RADEON_LINE_CURRENT_PTR_SHIFT) |
 413        (1 << RADEON_LINE_CURRENT_COUNT_SHIFT));
 414
 415    rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
 416
 417    rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
 418       ((0x00 << RADEON_STENCIL_REF_SHIFT) |
 419        (0xff << RADEON_STENCIL_MASK_SHIFT) |
 420        (0xff << RADEON_STENCIL_WRITEMASK_SHIFT));
 421
 422    rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY;
 423    rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
 424
 425    rmesa->hw.msc.cmd[MSC_RE_MISC] =
 426       ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT) |
 427        (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT) |
 428        RADEON_STIPPLE_BIG_BIT_ORDER);
 429
 430    rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE]  = 0x00000000;
 431    rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
 432    rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE]  = 0x00000000;
 433    rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
 434    rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE]  = 0x00000000;
 435    rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
 436
 437    for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
 438       rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL;
 439       rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
 440           (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
 441            RADEON_TXFORMAT_PERSPECTIVE_ENABLE |
 442            (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */
 443            (2 << RADEON_TXFORMAT_WIDTH_SHIFT) |
 444            (2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
 445
 446       /* Initialize the texture offset to the start of the card texture heap */
 447       rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
 448           rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
 449
 450       rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
 451       rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =
 452           (RADEON_COLOR_ARG_A_ZERO |
 453            RADEON_COLOR_ARG_B_ZERO |
 454            RADEON_COLOR_ARG_C_CURRENT_COLOR |
 455            RADEON_BLEND_CTL_ADD |
 456            RADEON_SCALE_1X |
 457            RADEON_CLAMP_TX);
 458       rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] =
 459           (RADEON_ALPHA_ARG_A_ZERO |
 460            RADEON_ALPHA_ARG_B_ZERO |
 461            RADEON_ALPHA_ARG_C_CURRENT_ALPHA |
 462            RADEON_BLEND_CTL_ADD |
 463            RADEON_SCALE_1X |
 464            RADEON_CLAMP_TX);
 465       rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0;
 466    }
 467
 468    /* Can only add ST1 at the time of doing some multitex but can keep
 469     * it after that.  Errors if DIFFUSE is missing.
 470     */
 471    rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] =
 472       (RADEON_TCL_VTX_Z0 |
 473        RADEON_TCL_VTX_W0 |
 474        RADEON_TCL_VTX_PK_DIFFUSE
 475          );     /* need to keep this uptodate */
 476
 477    rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] =
 478       ( RADEON_TCL_COMPUTE_XYZW         |
 479         (RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) |
 480         (RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) |
 481         (RADEON_TCL_TEX_INPUT_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT));
 482
 483
 484    /* XXX */
 485    rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] =
 486       ((MODEL << RADEON_MODELVIEW_0_SHIFT) |
 487        (MODEL_IT << RADEON_IT_MODELVIEW_0_SHIFT));
 488
 489    rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] =
 490       ((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) |
 491        (TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) |
 492        (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT));
 493
 494    rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
 495       (RADEON_UCP_IN_CLIP_SPACE |
 496        RADEON_CULL_FRONT_IS_CCW);
 497
 498    rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0;
 499
 500    rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] =
 501       (RADEON_SPECULAR_LIGHTS |
 502        RADEON_DIFFUSE_SPECULAR_COMBINE |
 503        RADEON_LOCAL_LIGHT_VEC_GL |
 504        (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) |
 505        (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) |
 506        (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
 507        (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT));
 508
 509    for (i = 0 ; i < 8; i++) {
 510       struct gl_light *l = &ctx->Light.Light[i];
 511       GLenum p = GL_LIGHT0 + i;
 512       *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
 513
 514       ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
 515       ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
 516       ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
 517       ctx->Driver.Lightfv( ctx, p, GL_POSITION, 0 );
 518       ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, 0 );
 519       ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
 520       ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
 521       ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
 522                            &l->ConstantAttenuation );
 523       ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
 524                            &l->LinearAttenuation );
 525       ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
 526                      &l->QuadraticAttenuation );
 527       *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
 528    }
 529
 530    ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
 531                              ctx->Light.Model.Ambient );
 532
 533    TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
 534
 535    for (i = 0 ; i < 6; i++) {
 536       ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
 537    }
 538
 539    ctx->Driver.Fogfv( ctx, GL_FOG_MODE, 0 );
 540    ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
 541    ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
 542    ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
 543    ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
 544    ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, 0 );
 545
 546    rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
 547    rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
 548    rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
 549    rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
 550
 551    rmesa->hw.eye.cmd[EYE_X] = 0;
 552    rmesa->hw.eye.cmd[EYE_Y] = 0;
 553    rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
 554    rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
 555 }