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radeon: remove debugging
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_state_init.c
1 /*
2 * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23 * OTHER DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Gareth Hughes <gareth@valinux.com>
27 * Keith Whitwell <keith@tungstengraphics.com>
28 */
29
30 #include "main/glheader.h"
31 #include "main/imports.h"
32 #include "main/api_arrayelt.h"
33
34 #include "swrast/swrast.h"
35 #include "vbo/vbo.h"
36 #include "tnl/tnl.h"
37 #include "tnl/t_pipeline.h"
38 #include "swrast_setup/swrast_setup.h"
39
40 #include "radeon_context.h"
41 #include "radeon_mipmap_tree.h"
42 #include "radeon_ioctl.h"
43 #include "radeon_state.h"
44 #include "radeon_tcl.h"
45 #include "radeon_tex.h"
46 #include "radeon_swtcl.h"
47
48 #include "../r200/r200_reg.h"
49
50 #include "xmlpool.h"
51
52 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
53 * 1.3 cmdbuffers allow all previous state to be updated as well as
54 * the tcl scalar and vector areas.
55 */
56 static struct {
57 int start;
58 int len;
59 const char *name;
60 } packet[RADEON_MAX_STATE_PACKETS] = {
61 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
62 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
63 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
64 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
65 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
66 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
67 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
68 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
69 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
70 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
71 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
72 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
73 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
74 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
75 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
76 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
77 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
78 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
79 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
80 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
81 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
82 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
83 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
84 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
85 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
86 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
87 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
88 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
89 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
90 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
91 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
92 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
93 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
94 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
95 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
96 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
97 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
98 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
99 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
100 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
101 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
102 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
103 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
104 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
105 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
106 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
107 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
108 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
109 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
110 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
111 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
112 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
113 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
114 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
115 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
116 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
117 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
118 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
119 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
120 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
121 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
122 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
123 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
124 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
125 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
126 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
127 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
128 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
129 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
130 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
131 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
132 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
133 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
134 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
135 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
136 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
137 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
138 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
139 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
140 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
141 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
142 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
143 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
144 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
145 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
146 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
147 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
148 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
149 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
150 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
151 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
152 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
153 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
154 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
155 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
156 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
157 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
158 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
159 };
160
161 /* =============================================================
162 * State initialization
163 */
164
165 void radeonPrintDirty( r100ContextPtr rmesa, const char *msg )
166 {
167 struct radeon_state_atom *l;
168
169 fprintf(stderr, msg);
170 fprintf(stderr, ": ");
171
172 foreach(l, &rmesa->radeon.hw.atomlist) {
173 if (l->dirty || rmesa->radeon.hw.all_dirty)
174 fprintf(stderr, "%s, ", l->name);
175 }
176
177 fprintf(stderr, "\n");
178 }
179
180 static int cmdpkt( r100ContextPtr rmesa, int id )
181 {
182 drm_radeon_cmd_header_t h;
183
184 if (rmesa->radeon.radeonScreen->kernel_mm) {
185 return CP_PACKET0(packet[id].start, packet[id].len - 1);
186 } else {
187 h.i = 0;
188 h.packet.cmd_type = RADEON_CMD_PACKET;
189 h.packet.packet_id = id;
190 }
191 return h.i;
192 }
193
194 static int cmdvec( int offset, int stride, int count )
195 {
196 drm_radeon_cmd_header_t h;
197 h.i = 0;
198 h.vectors.cmd_type = RADEON_CMD_VECTORS;
199 h.vectors.offset = offset;
200 h.vectors.stride = stride;
201 h.vectors.count = count;
202 return h.i;
203 }
204
205 static int cmdscl( int offset, int stride, int count )
206 {
207 drm_radeon_cmd_header_t h;
208 h.i = 0;
209 h.scalars.cmd_type = RADEON_CMD_SCALARS;
210 h.scalars.offset = offset;
211 h.scalars.stride = stride;
212 h.scalars.count = count;
213 return h.i;
214 }
215
216 #define CHECK( NM, FLAG ) \
217 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
218 { \
219 return FLAG ? atom->cmd_size : 0; \
220 }
221
222 #define TCL_CHECK( NM, FLAG ) \
223 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
224 { \
225 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
226 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \
227 }
228
229
230 CHECK( always, GL_TRUE )
231 CHECK( never, GL_FALSE )
232 CHECK( tex0, ctx->Texture.Unit[0]._ReallyEnabled )
233 CHECK( tex1, ctx->Texture.Unit[1]._ReallyEnabled )
234 /* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */
235 CHECK( tex2, ctx->Texture._EnabledUnits )
236 CHECK( cube0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_CUBE_BIT))
237 CHECK( cube1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_CUBE_BIT))
238 CHECK( cube2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_CUBE_BIT))
239 CHECK( fog, ctx->Fog.Enabled )
240 TCL_CHECK( tcl, GL_TRUE )
241 TCL_CHECK( tcl_tex0, ctx->Texture.Unit[0]._ReallyEnabled )
242 TCL_CHECK( tcl_tex1, ctx->Texture.Unit[1]._ReallyEnabled )
243 TCL_CHECK( tcl_tex2, ctx->Texture.Unit[2]._ReallyEnabled )
244 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
245 TCL_CHECK( tcl_eyespace_or_lighting, ctx->_NeedEyeCoords || ctx->Light.Enabled )
246 TCL_CHECK( tcl_lit0, ctx->Light.Enabled && ctx->Light.Light[0].Enabled )
247 TCL_CHECK( tcl_lit1, ctx->Light.Enabled && ctx->Light.Light[1].Enabled )
248 TCL_CHECK( tcl_lit2, ctx->Light.Enabled && ctx->Light.Light[2].Enabled )
249 TCL_CHECK( tcl_lit3, ctx->Light.Enabled && ctx->Light.Light[3].Enabled )
250 TCL_CHECK( tcl_lit4, ctx->Light.Enabled && ctx->Light.Light[4].Enabled )
251 TCL_CHECK( tcl_lit5, ctx->Light.Enabled && ctx->Light.Light[5].Enabled )
252 TCL_CHECK( tcl_lit6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled )
253 TCL_CHECK( tcl_lit7, ctx->Light.Enabled && ctx->Light.Light[7].Enabled )
254 TCL_CHECK( tcl_ucp0, (ctx->Transform.ClipPlanesEnabled & 0x1) )
255 TCL_CHECK( tcl_ucp1, (ctx->Transform.ClipPlanesEnabled & 0x2) )
256 TCL_CHECK( tcl_ucp2, (ctx->Transform.ClipPlanesEnabled & 0x4) )
257 TCL_CHECK( tcl_ucp3, (ctx->Transform.ClipPlanesEnabled & 0x8) )
258 TCL_CHECK( tcl_ucp4, (ctx->Transform.ClipPlanesEnabled & 0x10) )
259 TCL_CHECK( tcl_ucp5, (ctx->Transform.ClipPlanesEnabled & 0x20) )
260 TCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || ctx->Fog.Enabled )
261
262 CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT))
263 CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT))
264 CHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT))
265
266 #define OUT_VEC(hdr, data) do { \
267 drm_radeon_cmd_header_t h; \
268 h.i = hdr; \
269 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
270 OUT_BATCH(0); \
271 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
272 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
273 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
274 OUT_BATCH_TABLE((data), h.vectors.count); \
275 } while(0)
276
277 #define OUT_SCL(hdr, data) do { \
278 drm_radeon_cmd_header_t h; \
279 h.i = hdr; \
280 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
281 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
282 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
283 OUT_BATCH_TABLE((data), h.scalars.count); \
284 } while(0)
285
286 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
287 {
288 r100ContextPtr r100 = R100_CONTEXT(ctx);
289 BATCH_LOCALS(&r100->radeon);
290 uint32_t dwords = atom->cmd_size;
291
292 dwords += 2;
293 BEGIN_BATCH_NO_AUTOSTATE(dwords);
294 OUT_SCL(atom->cmd[0], atom->cmd+1);
295 END_BATCH();
296 }
297
298
299 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
300 {
301 r100ContextPtr r100 = R100_CONTEXT(ctx);
302 BATCH_LOCALS(&r100->radeon);
303 uint32_t dwords = atom->cmd_size;
304
305 dwords += 4;
306 BEGIN_BATCH_NO_AUTOSTATE(dwords);
307 OUT_VEC(atom->cmd[0], atom->cmd+1);
308 END_BATCH();
309 }
310
311
312 static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
313 {
314 r100ContextPtr r100 = R100_CONTEXT(ctx);
315 BATCH_LOCALS(&r100->radeon);
316 uint32_t dwords = atom->cmd_size;
317
318 dwords += 6;
319 BEGIN_BATCH_NO_AUTOSTATE(dwords);
320 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
321 OUT_SCL(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
322 END_BATCH();
323 }
324
325 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
326 {
327 r100ContextPtr r100 = R100_CONTEXT(ctx);
328 BATCH_LOCALS(&r100->radeon);
329 struct radeon_renderbuffer *rrb;
330 uint32_t cbpitch;
331 uint32_t zbpitch, depth_fmt;
332 uint32_t dwords = atom->cmd_size;
333
334 /* output the first 7 bytes of context */
335 BEGIN_BATCH_NO_AUTOSTATE(dwords + 4);
336 OUT_BATCH_TABLE(atom->cmd, 5);
337
338 rrb = radeon_get_depthbuffer(&r100->radeon);
339 if (!rrb) {
340 OUT_BATCH(0);
341 OUT_BATCH(0);
342 } else {
343 zbpitch = (rrb->pitch / rrb->cpp);
344 if (r100->using_hyperz)
345 zbpitch |= RADEON_DEPTH_HYPERZ;
346
347 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
348 OUT_BATCH(zbpitch);
349 if (rrb->cpp == 4)
350 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
351 else
352 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
353 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
354 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
355 }
356
357 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
358 OUT_BATCH(atom->cmd[CTX_CMD_1]);
359 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
360
361 rrb = radeon_get_colorbuffer(&r100->radeon);
362 if (!rrb || !rrb->bo) {
363 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
364 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
365 } else {
366 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
367 if (rrb->cpp == 4)
368 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
369 else
370 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
371
372 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
373 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
374 }
375
376 OUT_BATCH(atom->cmd[CTX_CMD_2]);
377
378 if (!rrb || !rrb->bo) {
379 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
380 } else {
381 cbpitch = (rrb->pitch / rrb->cpp);
382 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
383 cbpitch |= RADEON_COLOR_TILE_ENABLE;
384 OUT_BATCH(cbpitch);
385 }
386
387 END_BATCH();
388 }
389
390 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
391 {
392 r100ContextPtr r100 = R100_CONTEXT(ctx);
393 BATCH_LOCALS(&r100->radeon);
394 struct radeon_renderbuffer *rrb, *drb;
395 uint32_t cbpitch = 0;
396 uint32_t zbpitch = 0;
397 uint32_t dwords = atom->cmd_size;
398 uint32_t depth_fmt;
399
400 rrb = radeon_get_colorbuffer(&r100->radeon);
401 if (!rrb || !rrb->bo) {
402 fprintf(stderr, "no rrb\n");
403 return;
404 }
405
406 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
407 if (rrb->cpp == 4)
408 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
409 else
410 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
411
412 cbpitch = (rrb->pitch / rrb->cpp);
413 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
414 cbpitch |= R200_COLOR_TILE_ENABLE;
415
416 drb = radeon_get_depthbuffer(&r100->radeon);
417 if (drb) {
418 zbpitch = (drb->pitch / drb->cpp);
419 if (drb->cpp == 4)
420 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
421 else
422 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
423 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
424 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
425
426 }
427
428 /* output the first 7 bytes of context */
429 if (drb)
430 dwords += 4;
431 if (rrb)
432 dwords += 4;
433 BEGIN_BATCH_NO_AUTOSTATE(dwords);
434
435 /* In the CS case we need to split this up */
436 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
437 OUT_BATCH_TABLE((atom->cmd + 1), 4);
438
439 if (drb) {
440 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
441 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
442
443 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
444 OUT_BATCH(zbpitch);
445 }
446
447 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
448 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
449 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
450 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
451 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
452
453 if (rrb) {
454 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
455 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
456 }
457
458 if (rrb) {
459 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
460 OUT_BATCH(cbpitch);
461 }
462
463 // if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
464 // OUT_BATCH_TABLE((atom->cmd + 14), 4);
465 // }
466
467 END_BATCH();
468 }
469
470 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
471 {
472 r100ContextPtr r100 = R100_CONTEXT(ctx);
473 BATCH_LOCALS(&r100->radeon);
474 uint32_t dwords = atom->cmd_size;
475 int i = atom->idx, j;
476 radeonTexObj *t = r100->state.texture.unit[i].texobj;
477 radeon_mipmap_level *lvl;
478
479 if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT))
480 return;
481
482 if (!t)
483 return;
484
485 if (!t->mt)
486 return;
487
488 BEGIN_BATCH_NO_AUTOSTATE(dwords + 10);
489 OUT_BATCH_TABLE(atom->cmd, 3);
490 lvl = &t->mt->levels[0];
491 for (j = 0; j < 5; j++) {
492 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
493 RADEON_GEM_DOMAIN_VRAM, 0, 0);
494 }
495 END_BATCH();
496 }
497
498 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
499 {
500 r100ContextPtr r100 = R100_CONTEXT(ctx);
501 BATCH_LOCALS(&r100->radeon);
502 uint32_t dwords = atom->cmd_size;
503 int i = atom->idx;
504 radeonTexObj *t = r100->state.texture.unit[i].texobj;
505 radeon_mipmap_level *lvl;
506
507 if (t && t->mt && !t->image_override)
508 dwords += 2;
509 BEGIN_BATCH_NO_AUTOSTATE(dwords);
510 OUT_BATCH_TABLE(atom->cmd, 3);
511 if (t && t->mt && !t->image_override) {
512 if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
513 lvl = &t->mt->levels[0];
514 OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
515 RADEON_GEM_DOMAIN_VRAM, 0, 0);
516 } else {
517 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
518 RADEON_GEM_DOMAIN_VRAM, 0, 0);
519 }
520 } else if (!t) {
521 /* workaround for old CS mechanism */
522 OUT_BATCH(r100->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
523 // OUT_BATCH(r100->radeon.radeonScreen);
524 } else if (t->image_override)
525 OUT_BATCH(t->override_offset);
526
527 OUT_BATCH_TABLE((atom->cmd+4), 5);
528 END_BATCH();
529 }
530
531 /* Initialize the context's hardware state.
532 */
533 void radeonInitState( r100ContextPtr rmesa )
534 {
535 GLcontext *ctx = rmesa->radeon.glCtx;
536 GLuint i;
537
538 rmesa->radeon.state.color.clear = 0x00000000;
539
540 switch ( ctx->Visual.depthBits ) {
541 case 16:
542 rmesa->radeon.state.depth.clear = 0x0000ffff;
543 rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff;
544 rmesa->radeon.state.stencil.clear = 0x00000000;
545 break;
546 case 24:
547 rmesa->radeon.state.depth.clear = 0x00ffffff;
548 rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff;
549 rmesa->radeon.state.stencil.clear = 0xffff0000;
550 break;
551 default:
552 fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
553 ctx->Visual.depthBits );
554 exit( -1 );
555 }
556
557 /* Only have hw stencil when depth buffer is 24 bits deep */
558 rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
559 ctx->Visual.depthBits == 24 );
560
561 rmesa->radeon.Fallback = 0;
562
563
564 rmesa->radeon.hw.max_state_size = 0;
565
566 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \
567 do { \
568 rmesa->hw.ATOM.cmd_size = SZ; \
569 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
570 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
571 rmesa->hw.ATOM.name = NM; \
572 rmesa->hw.ATOM.is_tcl = FLAG; \
573 rmesa->hw.ATOM.check = check_##CHK; \
574 rmesa->hw.ATOM.dirty = GL_TRUE; \
575 rmesa->hw.ATOM.idx = IDX; \
576 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
577 } while (0)
578
579 #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \
580 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0)
581
582 /* Allocate state buffers:
583 */
584 ALLOC_STATE( ctx, always, CTX_STATE_SIZE, "CTX/context", 0 );
585 if (rmesa->radeon.radeonScreen->kernel_mm)
586 rmesa->hw.ctx.emit = ctx_emit_cs;
587 else
588 rmesa->hw.ctx.emit = ctx_emit;
589 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
590 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
591 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
592 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
593 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
594 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
595 ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 );
596 ALLOC_STATE( mtl, tcl_lighting, MTL_STATE_SIZE, "MTL/material", 1 );
597 ALLOC_STATE( grd, always, GRD_STATE_SIZE, "GRD/guard-band", 1 );
598 ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 );
599 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 );
600 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 );
601 ALLOC_STATE_IDX( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0, 0);
602 ALLOC_STATE_IDX( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0, 1);
603 ALLOC_STATE_IDX( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0, 2 );
604
605 for (i = 0; i < 3; i++)
606 rmesa->hw.tex[i].emit = tex_emit;
607 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
608 {
609 ALLOC_STATE_IDX( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 );
610 ALLOC_STATE_IDX( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 );
611 ALLOC_STATE_IDX( cube[2], cube2, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 );
612 for (i = 0; i < 3; i++)
613 rmesa->hw.cube[i].emit = cube_emit;
614 }
615 else
616 {
617 ALLOC_STATE_IDX( cube[0], never, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 );
618 ALLOC_STATE_IDX( cube[1], never, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 );
619 ALLOC_STATE_IDX( cube[2], never, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 );
620 }
621 ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 );
622 ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 );
623 ALLOC_STATE( mat[2], tcl_eyespace_or_lighting, MAT_STATE_SIZE, "MAT/it-modelview", 1 );
624 ALLOC_STATE( mat[3], tcl_tex0, MAT_STATE_SIZE, "MAT/texmat0", 1 );
625 ALLOC_STATE( mat[4], tcl_tex1, MAT_STATE_SIZE, "MAT/texmat1", 1 );
626 ALLOC_STATE( mat[5], tcl_tex2, MAT_STATE_SIZE, "MAT/texmat2", 1 );
627 ALLOC_STATE( ucp[0], tcl_ucp0, UCP_STATE_SIZE, "UCP/userclip-0", 1 );
628 ALLOC_STATE( ucp[1], tcl_ucp1, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
629 ALLOC_STATE( ucp[2], tcl_ucp2, UCP_STATE_SIZE, "UCP/userclip-2", 1 );
630 ALLOC_STATE( ucp[3], tcl_ucp3, UCP_STATE_SIZE, "UCP/userclip-3", 1 );
631 ALLOC_STATE( ucp[4], tcl_ucp4, UCP_STATE_SIZE, "UCP/userclip-4", 1 );
632 ALLOC_STATE( ucp[5], tcl_ucp5, UCP_STATE_SIZE, "UCP/userclip-5", 1 );
633 ALLOC_STATE( lit[0], tcl_lit0, LIT_STATE_SIZE, "LIT/light-0", 1 );
634 ALLOC_STATE( lit[1], tcl_lit1, LIT_STATE_SIZE, "LIT/light-1", 1 );
635 ALLOC_STATE( lit[2], tcl_lit2, LIT_STATE_SIZE, "LIT/light-2", 1 );
636 ALLOC_STATE( lit[3], tcl_lit3, LIT_STATE_SIZE, "LIT/light-3", 1 );
637 ALLOC_STATE( lit[4], tcl_lit4, LIT_STATE_SIZE, "LIT/light-4", 1 );
638 ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 );
639 ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 );
640 ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 );
641 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 );
642 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 );
643 ALLOC_STATE_IDX( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0, 2 );
644
645 radeonSetUpAtomList( rmesa );
646
647 /* Fill in the packet headers:
648 */
649 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
650 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
651 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
652 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
653 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
654 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
655 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
656 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
657 rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL_STATUS);
658 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
659 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_0);
660 rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_0);
661 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_1);
662 rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_1);
663 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_2);
664 rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_2);
665 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_0);
666 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T0);
667 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_1);
668 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T1);
669 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_2);
670 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T2);
671 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
672 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
673 rmesa->hw.mtl.cmd[MTL_CMD_0] =
674 cmdpkt(rmesa, RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED);
675 rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_0);
676 rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_1);
677 rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_2);
678 rmesa->hw.grd.cmd[GRD_CMD_0] =
679 cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
680 rmesa->hw.fog.cmd[FOG_CMD_0] =
681 cmdvec( RADEON_VS_FOG_PARAM_ADDR, 1, 4 );
682 rmesa->hw.glt.cmd[GLT_CMD_0] =
683 cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
684 rmesa->hw.eye.cmd[EYE_CMD_0] =
685 cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 );
686
687 for (i = 0 ; i < 6; i++) {
688 rmesa->hw.mat[i].cmd[MAT_CMD_0] =
689 cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16);
690 }
691
692 for (i = 0 ; i < 8; i++) {
693 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
694 cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
695 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
696 cmdscl( RADEON_SS_LIGHT_DCD_ADDR + i, 8, 6 );
697 }
698
699 for (i = 0 ; i < 6; i++) {
700 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
701 cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 );
702 }
703
704 if (rmesa->radeon.radeonScreen->kernel_mm) {
705 rmesa->hw.grd.emit = scl_emit;
706 rmesa->hw.fog.emit = vec_emit;
707 rmesa->hw.glt.emit = vec_emit;
708 rmesa->hw.eye.emit = vec_emit;
709
710 for (i = 0; i <= 6; i++)
711 rmesa->hw.mat[i].emit = vec_emit;
712
713 for (i = 0; i < 8; i++)
714 rmesa->hw.lit[i].emit = lit_emit;
715
716 for (i = 0; i < 6; i++)
717 rmesa->hw.ucp[i].emit = vec_emit;
718 }
719
720 rmesa->last_ReallyEnabled = -1;
721
722 /* Initial Harware state:
723 */
724 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS |
725 RADEON_CHROMA_FUNC_FAIL |
726 RADEON_CHROMA_KEY_NEAREST |
727 RADEON_SHADOW_FUNC_EQUAL |
728 RADEON_SHADOW_PASS_1 /*|
729 RADEON_RIGHT_HAND_CUBE_OGL */);
730
731 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX |
732 /* this bit unused for vertex fog */
733 RADEON_FOG_USE_DEPTH);
734
735 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
736
737 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP |
738 RADEON_SRC_BLEND_GL_ONE |
739 RADEON_DST_BLEND_GL_ZERO );
740
741 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (RADEON_Z_TEST_LESS |
742 RADEON_STENCIL_TEST_ALWAYS |
743 RADEON_STENCIL_FAIL_KEEP |
744 RADEON_STENCIL_ZPASS_KEEP |
745 RADEON_STENCIL_ZFAIL_KEEP |
746 RADEON_Z_WRITE_ENABLE);
747
748 if (rmesa->using_hyperz) {
749 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
750 RADEON_Z_DECOMPRESSION_ENABLE;
751 if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
752 /* works for q3, but slight rendering errors with glxgears ? */
753 /* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
754 /* need this otherwise get lots of lockups with q3 ??? */
755 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY;
756 }
757 }
758
759 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
760 RADEON_ANTI_ALIAS_NONE);
761
762 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
763 RADEON_ZBLOCK16);
764
765 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
766 case DRI_CONF_DITHER_XERRORDIFFRESET:
767 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
768 break;
769 case DRI_CONF_DITHER_ORDERED:
770 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
771 break;
772 }
773 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
774 DRI_CONF_ROUND_ROUND )
775 rmesa->radeon.state.color.roundEnable = RADEON_ROUND_ENABLE;
776 else
777 rmesa->radeon.state.color.roundEnable = 0;
778 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
779 DRI_CONF_COLOR_REDUCTION_DITHER )
780 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
781 else
782 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
783
784
785 rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW |
786 RADEON_BFACE_SOLID |
787 RADEON_FFACE_SOLID |
788 /* RADEON_BADVTX_CULL_DISABLE | */
789 RADEON_FLAT_SHADE_VTX_LAST |
790 RADEON_DIFFUSE_SHADE_GOURAUD |
791 RADEON_ALPHA_SHADE_GOURAUD |
792 RADEON_SPECULAR_SHADE_GOURAUD |
793 RADEON_FOG_SHADE_GOURAUD |
794 RADEON_VPORT_XY_XFORM_ENABLE |
795 RADEON_VPORT_Z_XFORM_ENABLE |
796 RADEON_VTX_PIX_CENTER_OGL |
797 RADEON_ROUND_MODE_TRUNC |
798 RADEON_ROUND_PREC_8TH_PIX);
799
800 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] =
801 #ifdef MESA_BIG_ENDIAN
802 RADEON_VC_32BIT_SWAP;
803 #else
804 RADEON_VC_NO_SWAP;
805 #endif
806
807 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
808 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS;
809 }
810
811 rmesa->hw.set.cmd[SET_SE_COORDFMT] = (
812 RADEON_VTX_W0_IS_NOT_1_OVER_W0 |
813 RADEON_TEX1_W_ROUTING_USE_Q1);
814
815
816 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
817
818 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
819 ((0 << RADEON_LINE_CURRENT_PTR_SHIFT) |
820 (1 << RADEON_LINE_CURRENT_COUNT_SHIFT));
821
822 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
823
824 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
825 ((0x00 << RADEON_STENCIL_REF_SHIFT) |
826 (0xff << RADEON_STENCIL_MASK_SHIFT) |
827 (0xff << RADEON_STENCIL_WRITEMASK_SHIFT));
828
829 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY;
830 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
831
832 rmesa->hw.msc.cmd[MSC_RE_MISC] =
833 ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT) |
834 (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT) |
835 RADEON_STIPPLE_BIG_BIT_ORDER);
836
837 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
838 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
839 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
840 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
841 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
842 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
843
844 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
845 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL;
846 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
847 (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
848 RADEON_TXFORMAT_PERSPECTIVE_ENABLE |
849 (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */
850 (2 << RADEON_TXFORMAT_WIDTH_SHIFT) |
851 (2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
852
853 /* Initialize the texture offset to the start of the card texture heap */
854 // rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
855 // rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
856
857 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
858 rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =
859 (RADEON_COLOR_ARG_A_ZERO |
860 RADEON_COLOR_ARG_B_ZERO |
861 RADEON_COLOR_ARG_C_CURRENT_COLOR |
862 RADEON_BLEND_CTL_ADD |
863 RADEON_SCALE_1X |
864 RADEON_CLAMP_TX);
865 rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] =
866 (RADEON_ALPHA_ARG_A_ZERO |
867 RADEON_ALPHA_ARG_B_ZERO |
868 RADEON_ALPHA_ARG_C_CURRENT_ALPHA |
869 RADEON_BLEND_CTL_ADD |
870 RADEON_SCALE_1X |
871 RADEON_CLAMP_TX);
872 rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0;
873
874 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
875 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] =
876 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
877 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_1] =
878 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
879 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_2] =
880 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
881 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_3] =
882 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
883 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_4] =
884 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
885 }
886
887 /* Can only add ST1 at the time of doing some multitex but can keep
888 * it after that. Errors if DIFFUSE is missing.
889 */
890 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] =
891 (RADEON_TCL_VTX_Z0 |
892 RADEON_TCL_VTX_W0 |
893 RADEON_TCL_VTX_PK_DIFFUSE
894 ); /* need to keep this uptodate */
895
896 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] =
897 ( RADEON_TCL_COMPUTE_XYZW |
898 (RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) |
899 (RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) |
900 (RADEON_TCL_TEX_INPUT_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT));
901
902
903 /* XXX */
904 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] =
905 ((MODEL << RADEON_MODELVIEW_0_SHIFT) |
906 (MODEL_IT << RADEON_IT_MODELVIEW_0_SHIFT));
907
908 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] =
909 ((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) |
910 (TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) |
911 (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT) |
912 (TEXMAT_2 << RADEON_TEXMAT_2_SHIFT));
913
914 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
915 (RADEON_UCP_IN_CLIP_SPACE |
916 RADEON_CULL_FRONT_IS_CCW);
917
918 rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0;
919
920 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] =
921 (RADEON_SPECULAR_LIGHTS |
922 RADEON_DIFFUSE_SPECULAR_COMBINE |
923 RADEON_LOCAL_LIGHT_VEC_GL |
924 (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) |
925 (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) |
926 (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
927 (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT));
928
929 for (i = 0 ; i < 8; i++) {
930 struct gl_light *l = &ctx->Light.Light[i];
931 GLenum p = GL_LIGHT0 + i;
932 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
933
934 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
935 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
936 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
937 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
938 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
939 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
940 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
941 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
942 &l->ConstantAttenuation );
943 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
944 &l->LinearAttenuation );
945 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
946 &l->QuadraticAttenuation );
947 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
948 }
949
950 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
951 ctx->Light.Model.Ambient );
952
953 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
954
955 for (i = 0 ; i < 6; i++) {
956 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
957 }
958
959 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
960 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
961 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
962 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
963 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
964 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
965
966 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
967 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
968 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
969 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
970
971 rmesa->hw.eye.cmd[EYE_X] = 0;
972 rmesa->hw.eye.cmd[EYE_Y] = 0;
973 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
974 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
975
976 rmesa->radeon.hw.all_dirty = GL_TRUE;
977
978 rcommonInitCmdBuf(&rmesa->radeon);
979 }